From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Sebastian Brzezinka <sebastian.brzezinka@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/7] drm/i915: Disable compression tricks on JSL
Date: Thu, 28 Nov 2024 14:34:52 +0200 [thread overview]
Message-ID: <Z0hjbLJSjVBQxTxY@intel.com> (raw)
In-Reply-To: <o3albuqlbexbhczvhi7lnh4klyaccdbo34rbtaj52mp4ox4ecj@kjggr3melenq>
On Wed, Nov 27, 2024 at 03:56:27PM +0000, Sebastian Brzezinka wrote:
>
> Hi Ville
>
> I found your patch looking at issue VLK-65591, seems like for some reason
> cannot apply this workaround on JasperLake and end up with an error:
>
> ```
> <3> [463.126159] i915 0000:00:02.0: [drm] ERROR GT0: engine workaround lost on application! (reg[7000]=0x0, relevant bits were 0x0 vs expected 0x8000)
>
> ```
>
> When the workaround is verified, 15th bit is not set. Is it possible that
> this workaround is not available ? I would be grateful for any tips.
I suppose it's possible the spec is wrong and the bit doesn't exist, or
perhaps it's only present on some steppings. Shrug.
I'm not seeing any problems being reported in CI however, so I'm a bit
confused where these are happening?
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-11-28 12:34 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-18 14:44 [PATCH 0/7] drm/i915: 10bpc/fp16 + CCS support Ville Syrjala
2024-09-18 14:44 ` [PATCH 1/7] drm/i915: Set clear color block size to 0x0 Ville Syrjala
2024-09-23 14:58 ` Imre Deak
2024-09-18 14:44 ` [PATCH 2/7] drm/i915: Disable compression tricks on JSL Ville Syrjala
2024-10-04 13:22 ` Juha-Pekka Heikkila
2024-10-04 17:54 ` Ville Syrjälä
2024-11-27 15:56 ` Sebastian Brzezinka
2024-11-28 12:34 ` Ville Syrjälä [this message]
2024-11-28 13:20 ` Sebastian Brzezinka
2024-09-18 14:44 ` [PATCH 3/7] drm/i915: Enable 10bpc + CCS on TGL+ Ville Syrjala
2024-10-04 13:35 ` Juha-Pekka Heikkila
2024-10-04 18:03 ` Ville Syrjälä
2024-10-08 9:01 ` Juha-Pekka Heikkila
2024-11-25 6:55 ` Xi Ruoyao
2024-11-27 5:57 ` Ville Syrjälä
2024-11-27 6:58 ` Xi Ruoyao
2024-09-18 14:44 ` [PATCH 4/7] drm/i915: Enable 10bpc + CCS on ICL Ville Syrjala
2024-10-04 13:36 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 5/7] drm/i915: Enable fp16 + CCS on TGL+ Ville Syrjala
2024-10-04 13:50 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 6/7] drm/i915: Drop GEN12_MC_CCS check from skl_plane_max_width() Ville Syrjala
2024-10-04 13:52 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 7/7] drm/i915: s/gen12/tgl/ in the universal plane code Ville Syrjala
2024-10-04 13:54 ` Juha-Pekka Heikkila
2024-09-18 15:50 ` ✗ Fi.CI.SPARSE: warning for drm/i915: 10bpc/fp16 + CCS support Patchwork
2024-09-18 15:59 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-19 5:19 ` ✗ Fi.CI.IGT: failure " Patchwork
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