Re: [PATCH 10/16] drm/xe/xe3p_lpg: Update LRC sizes

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Feb 02, 2026 at 06:43:16PM -0300, Gustavo Sousa wrote:
> Like with previous generations, the engine context images for of both
> RCS and CCS in Xe3p_LPG contain a common layout at the end for the
> context related to the "Compute Pipeline".
> 
> The size of the memory area written to such section varies; it depends
> on the type of preemption has taken place during the execution and type
> of command streamer instruction that was used on the pipeline. For
> Xe3p_LPG, the maximum possible size, including NOOPs for cache line
> alignment, is 4368 dwords, which would be the case of a mid-thread
> preemption during the execution of a COMPUTE_WALKER_2 instruction.

Double checking:

CW_INTERNAL_STATE_2: 22 dwords each * 128 instances = 2816 dwords
CFE_SS_RESTORE:  2 dwords
COMPUTE_WALKER_2:  64 dwords * 24 instances = 1536

2816 + 2 + 1536 = 4354 rounded up to cacheline (16 dword) alignment is
4368 which matches what you calculated.

I didn't carefully re-count all the non-computepipeline dwords again,
but eyeballing the list there aren't any major differences in that part
that would meaningfully change the size of the LRC once we round up to
page size, so replacing the old Xe2/Xe3 compute pipeline (~1128 dwords)
with the new Xe3p 4368 value gives me a rounded up value of 7 pages and
5 pages for the RCS and CCS respectively, which is what you have here.
So your numbers look good to me.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Hopefully in future platforms they'll make these numbers easier to
verify in the bspec without requiring us to carefully count up hundreds
of instructions by hand...


Matt

> 
> The maximum size has increased in such a way that we need to update
> xe_gt_lrc_size() to match the new sizing requirement. When we add that
> to the engine-specific parts, we have:
> 
>   - RCS context image: 6672 dwords = 26688 bytes -> 7 pages
>   - CCS context image: 5024 dwords = 20096 bytes -> 5 pages
> 
> Bspec: 65182, 55793, 73590
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_lrc.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index e58eb8b9db78..38f648b98868 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -113,13 +113,17 @@ size_t xe_gt_lrc_hang_replay_size(struct xe_gt *gt, enum xe_engine_class class)
>  	/* Engine context image */
>  	switch (class) {
>  	case XE_ENGINE_CLASS_RENDER:
> -		if (GRAPHICS_VER(xe) >= 20)
> +		if (GRAPHICS_VERx100(xe) >= 3510)
> +			size += 7 * SZ_4K;
> +		else if (GRAPHICS_VER(xe) >= 20)
>  			size += 3 * SZ_4K;
>  		else
>  			size += 13 * SZ_4K;
>  		break;
>  	case XE_ENGINE_CLASS_COMPUTE:
> -		if (GRAPHICS_VER(xe) >= 20)
> +		if (GRAPHICS_VERx100(xe) >= 3510)
> +			size += 5 * SZ_4K;
> +		else if (GRAPHICS_VER(xe) >= 20)
>  			size += 2 * SZ_4K;
>  		else
>  			size += 13 * SZ_4K;
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation