Re: [PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Feb 02, 2026 at 02:11:04PM -0800, Matt Roper wrote:
> On Mon, Feb 02, 2026 at 06:43:07PM -0300, Gustavo Sousa wrote:
> > From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> > 
> > Add graphics IP versions 35.10. Since there will be features enabled
> > that are not present in graphics_xe2, already create a new
> > graphics_xe3p, although currently it only enables the same features as
> > graphics_xe2.
> > 
> > Here is a list of fields, associated Bspec references and eventual
> > comments:
> > 
> >  .va_bits (Bspec 74198)
> >  .vm_max_level (Bspec 59507)
> >     The spec says "The PPGTT is always a 5-level structure even when the
> >     virtual address space is less than 57 bits."
> >  .vram_flags
> >    - ~XE_VRAM_FLAGS_NEED64K
> >      That limitation that does not exist for Xe3p_LPG.
> 
> These three aren't part of the graphics descriptor anymore, so they're
> not relevant to this patch.
> 
> >  .hw_engine_mask (Bspec 60149)
> >  .tile_gsm_size (Bspec 52961)
> >     This is queried directly from the hardware.
> 
> I don't think this flag has ever existed, outside of some temporary
> development patches that never moved forward.
> 
> >  .has_asid (Bspec 71132)
> >  .has_atomic_enable_pte_bit (Bspec 59510, 74675)
> >  .has_flat_ccs (Bspec 65255)
> 
> This one also isn't part of the graphics descriptor anymore.
> 
> >  .has_indirect_ring_state (Bspec 67296)
> >  .has_range_tlb_inval (Bspec 71126)
> >  .has_usm (Bspec 59651)
> > 
> 
> We should probably add a reference for has_64bit_timestamp (bspec 60318)
> since it's set in XE2_GFX_FEATURES.
> 
> Is there any reason not to go ahead and squash in
> multi_queue_engine_class_mask from patch #12 here?
> 
> 
> Matt
> 
> > Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_pci.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index b5e8935fff1d..edca562462fa 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -106,6 +106,10 @@ static const struct xe_graphics_desc graphics_xe2 = {
> >  	XE2_GFX_FEATURES,
> >  };
> >  
> > +static const struct xe_graphics_desc graphics_xe3p = {

One more comment: we may want to name this "graphics_xe3p_lpg" to help
distinguish it from graphics_xe3p_xpc below.


Matt

> > +	XE2_GFX_FEATURES,
> > +};
> > +
> >  static const struct xe_graphics_desc graphics_xe3p_xpc = {
> >  	XE2_GFX_FEATURES,
> >  	.has_indirect_ring_state = 1,
> > @@ -148,6 +152,7 @@ static const struct xe_ip graphics_ips[] = {
> >  	{ 3003, "Xe3_LPG", &graphics_xe2 },
> >  	{ 3004, "Xe3_LPG", &graphics_xe2 },
> >  	{ 3005, "Xe3_LPG", &graphics_xe2 },
> > +	{ 3510, "Xe3p_LPG", &graphics_xe3p },
> >  	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
> >  };
> >  
> > 
> > -- 
> > 2.52.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation