Re: [PATCH 04/16] drm/xe/xe3p_lpg: Add new PAT table

[Matt Atwood <matthew.s.atwood@intel.com>]

On Mon, Feb 02, 2026 at 06:43:10PM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> PAT programming for Xe3p_LPG is more similar to Xe2 and Xe3 than it is
> to Xe3p_XPC.  Compared to Xe2/Xe3 we have:
> 
> * There's a slight update to the PAT table, where two new indices (18
>   and 19) are added to expose a new "WB - Transient App" L3 caching
>   mode.
> 
> * The PTA_MODE entry must be programmed differently according to the
>   media type, and both differ from Xe2.
> 
> There are no changes to the underlying registers, so the Xe2 ops can be
> re-used for Xe3p.
> 
> Bspec: 71582, 74160
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pat.c | 55 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 54 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 5776ea67fe02..3ba89e80be1f 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -123,7 +123,8 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
>   *   - no_promote:  0=promotable, 1=no promote
>   *   - comp_en:     0=disable, 1=enable
>   *   - l3clos:      L3 class of service (0-3)
> - *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
> + *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"),
> + *                  2=XA ("WB - Transient App" for Xe3p), 3=UC
>   *   - l4_policy:   0=WB, 1=WT, 3=UC
>   *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
>   *
> @@ -252,6 +253,44 @@ static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
>  	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
>  };
>  
> +static const struct xe_pat_table_entry xe3p_primary_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 3);
> +static const struct xe_pat_table_entry xe3p_media_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 2);
> +
> +static const struct xe_pat_table_entry xe3p_lpg_pat_table[] = {
> +	[ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
> +	[ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
> +	[ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
> +	[ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
> +	[ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
> +	[ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
> +	[ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
> +	[ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
> +	[ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
> +	[ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
> +	[10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
> +	[11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
> +	[12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
> +	[13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
> +	[14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
> +	[15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
> +	[16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
> +	/* 17 is reserved; leave set to all 0's */
> +	[18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
> +	[19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
> +	[20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
> +	[21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
> +	[22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
> +	[23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
> +	[24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
> +	[25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
> +	[26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
> +	[27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
> +	[28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
> +	[29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
> +	[30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
> +	[31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
> +};
> +
>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>  {
>  	WARN_ON(pat_index >= xe->pat.n_entries);
> @@ -537,6 +576,20 @@ void xe_pat_init_early(struct xe_device *xe)
>  		xe->pat.idx[XE_CACHE_NONE] = 3;
>  		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
>  		xe->pat.idx[XE_CACHE_WB] = 2;
> +	} else if (GRAPHICS_VER(xe) == 35) {
> +		xe->pat.ops = &xe2_pat_ops;
> +		xe->pat.table = xe3p_lpg_pat_table;
> +		xe->pat.pat_ats = &xe2_pat_ats;
> +		if (!IS_DGFX(xe)) {
> +			xe->pat.pat_primary_pta = &xe3p_primary_pat_pta;
> +			xe->pat.pat_media_pta = &xe3p_media_pat_pta;
> +		}
> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_lpg_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 15;
> +		xe->pat.idx[XE_CACHE_WB] = 2;
> +		xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12;
> +		xe->pat.idx[XE_CACHE_WB_COMPRESSION] = 16;
>  	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>  		xe->pat.ops = &xe2_pat_ops;
>  		if (GRAPHICS_VER(xe) == 30) {
> 
> -- 
> 2.52.0
>