Re: [PATCH 08/11] drm/i915/display: Add PHY_CMN1_CONTROL register definitions

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
> sending.
>
> Bspec: 68962
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 960f7f778fb81..94b6384cdf019 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -278,6 +278,9 @@
>   #define PHY_CX0_TX_CONTROL(tx, control)	(0x400 + ((tx) - 1) * 0x200 + (control))
>   #define   CONTROL2_DISABLE_SINGLE_TX	REG_BIT(6)
>   
> +#define PHY_CMN1_CONTROL(tx, control)	(0x800 + ((tx) - 1) * 0x200 + (control))
> +#define   CONTROL0_MAC_TRANSMIT_LFPS	REG_BIT(1)
> +
>   /* C20 Registers */
>   #define PHY_C20_WR_ADDRESS_L		0xC02
>   #define PHY_C20_WR_ADDRESS_H		0xC03