From: "Shankar, Uma" <uma.shankar@intel.com>
To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
Date: Sun, 18 Oct 2020 20:47:27 +0000 [thread overview]
Message-ID: <7137c1244ee3409da343a6c4a1de38ee@intel.com> (raw)
In-Reply-To: <20201015105259.27934-2-ankit.k.nautiyal@intel.com>
> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
>
> From: Swati Sharma <swati2.sharma@intel.com>
>
> The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific Data block) to have
Typo in HFVSDB
> fields related to newly defined methods of FRL (Fixed Rate Link) levels, number
> of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM
> etc.
>
> This patch adds the new HFVSDB fields that are required for HDMI2.1.
>
> Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index
> b27a0e2169c8..1cc5c2c73282 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -229,6 +229,36 @@ struct detailed_timing {
> DRM_EDID_YCBCR420_DC_36 | \
> DRM_EDID_YCBCR420_DC_30)
>
> +/* HDMI 2.1 additional fields */
> +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
> +#define DRM_EDID_FAPA_START_LOCATION (1 << 0)
> +#define DRM_EDID_ALLM (1 << 1)
> +#define DRM_EDID_FVA (1 << 2)
> +
> +/* Deep Color specific */
> +#define DRM_EDID_DC_30BIT_420 (1 << 0)
> +#define DRM_EDID_DC_36BIT_420 (1 << 1)
> +#define DRM_EDID_DC_48BIT_420 (1 << 2)
> +
> +/* VRR specific */
> +#define DRM_EDID_CNMVRR (1 << 3)
> +#define DRM_EDID_CINEMA_VRR (1 << 4)
> +#define DRM_EDID_MDELTA (1 << 5)
> +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
> +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
> +#define DRM_EDID_VRR_MIN_MASK 0x3f
> +
> +/* DSC specific */
> +#define DRM_EDID_DSC_10BPC (1 << 0)
> +#define DRM_EDID_DSC_12BPC (1 << 1)
> +#define DRM_EDID_DSC_16BPC (1 << 2)
> +#define DRM_EDID_DSC_ALL_BPP (1 << 3)
> +#define DRM_EDID_DSC_NATIVE_420 (1 << 6)
> +#define DRM_EDID_DSC_1P2 (1 << 7)
> +#define DRM_EDID_DSC_MAX_FRL_RATE 0xf
This should be set as mask and made it as 0xf0
> +#define DRM_EDID_DSC_MAX_SLICES 0xf
> +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
> +
> /* ELD Header Block */
> #define DRM_ELD_HEADER_BLOCK_SIZE 4
>
> --
> 2.17.1
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next prev parent reply other threads:[~2020-10-18 20:47 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-15 10:52 [Intel-gfx] [RFC 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma [this message]
2020-11-01 5:31 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma
2020-11-01 5:41 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-18 21:33 ` Shankar, Uma
2020-11-01 5:53 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal
2020-10-18 21:41 ` Shankar, Uma
2020-11-01 5:56 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal
2020-10-18 22:14 ` Shankar, Uma
2020-11-01 6:01 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 06/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal
2020-10-18 22:21 ` Shankar, Uma
2020-11-01 6:06 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 07/13] drm/dp_helper: Add support for link status and link recovery Ankit Nautiyal
2020-10-18 22:37 ` Shankar, Uma
2020-11-01 6:18 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 08/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal
2020-10-18 22:49 ` Shankar, Uma
2020-11-01 6:26 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block Ankit Nautiyal
2020-10-18 23:01 ` Shankar, Uma
2020-11-01 6:52 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal
2020-10-18 23:19 ` Shankar, Uma
2020-11-01 7:00 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal
2020-10-18 23:32 ` Shankar, Uma
2020-10-18 23:34 ` Shankar, Uma
2020-11-01 7:14 ` Nautiyal, Ankit K
2020-11-01 7:13 ` Nautiyal, Ankit K
2020-10-15 10:52 ` [Intel-gfx] [RFC 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] [RFC 13/13] drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal
2020-10-15 11:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev3) Patchwork
2020-10-15 11:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-15 12:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-15 13:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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