* [PATCH 00/16] drm/i915/de: Register polling cleanup
@ 2025-11-10 17:27 Ville Syrjala
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
` (19 more replies)
0 siblings, 20 replies; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the register polling stuff:
- rename the current wait stuff to
intel_de_wait_{,for_set,for_clear}_ms()
- introduce intel_de_wait_{,for_set,for_clear}_us()
- nuke intel_de_wait_custom()
- change the wakelock stuff to use _fw() instead of
hand rolling yet another level of register accessors
- a few other minor cleanups
After this it should be fairly easy to switch over to
poll_timeout_us().
Ville Syrjälä (16):
drm/i915/de: Implement register waits one way
drm/i915/de: Have intel_de_wait() hand out the final register value
drm/i915/de: Include units in intel_de_wait*() function names
drm/i915/de: Introduce intel_de_wait_us()
drm/i915/de: Use intel_de_wait_us()
drm/i915/de: Use intel_de_wait_ms() for the obvious cases
drm/i915/de: Nuke intel_de_wait_custom()
drm/i915/de: Introduce intel_de_wait_for_{set,clear}_us()
drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()
drm/1915/dpio: Stop using intel_de_wait_fw_ms()
drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw()
drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms()
drm/i915/de: Replace __intel_de_wait_for_register_nowl() with
intel_de_wait_fw_us_atomic()
drm/i915/power: Use the intel_de_wait_ms() out value
drm/i915/dpio: Use the intel_de_wait_ms() out value
drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 35 +++---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--
drivers/gpu/drm/i915/display/intel_crt.c | 16 +--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 98 ++++++++--------
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++---
drivers/gpu/drm/i915/display/intel_de.h | 107 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_power.c | 14 +--
.../i915/display/intel_display_power_well.c | 42 +++----
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 25 ++--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 +--
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 10 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 +++--
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
drivers/gpu/drm/i915/display/intel_flipq.c | 8 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++----
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 57 +++++-----
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-
.../gpu/drm/i915/display/intel_pch_display.c | 12 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 10 +-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 18 +--
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
drivers/gpu/drm/i915/display/intel_sbi.c | 6 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +-
drivers/gpu/drm/i915/display/intel_tc.c | 8 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 6 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 54 ++++-----
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +-
.../drm/xe/compat-i915-headers/intel_uncore.h | 31 ++---
34 files changed, 369 insertions(+), 402 deletions(-)
--
2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/16] drm/i915/de: Implement register waits one way
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:52 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value Ville Syrjala
` (18 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we use a messy mix of intel_wait_for_register*()
and __intel_wait_for_register*() to implement various
register polling functions. Make the mess a bit more understandable
by always using the __intel_wait_for_register*() stuff.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 17 +++-------
| 31 ++++++-------------
2 files changed, 14 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 9ecdcf6b73e4..ea9973dbbffc 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -104,15 +104,6 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
return val;
}
-static inline int
-__intel_de_wait_for_register_nowl(struct intel_display *display,
- i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout_ms)
-{
- return intel_wait_for_register(__to_uncore(display), reg, mask,
- value, timeout_ms);
-}
-
static inline int
__intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
i915_reg_t reg,
@@ -131,8 +122,8 @@ intel_de_wait(struct intel_display *display, i915_reg_t reg,
intel_dmc_wl_get(display, reg);
- ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
- timeout_ms);
+ ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
+ value, 2, timeout_ms, NULL);
intel_dmc_wl_put(display, reg);
@@ -147,8 +138,8 @@ intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
intel_dmc_wl_get(display, reg);
- ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
- value, timeout_ms, out_value);
+ ret = __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
+ value, 2, timeout_ms, out_value);
intel_dmc_wl_put(display, reg);
--git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index d012f02bc84f..d93ddacdf743 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -91,27 +91,6 @@ static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);
}
-static inline int intel_wait_for_register(struct intel_uncore *uncore,
- i915_reg_t i915_reg, u32 mask,
- u32 value, unsigned int timeout)
-{
- struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
-
- return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
- timeout * USEC_PER_MSEC, NULL, false);
-}
-
-static inline int intel_wait_for_register_fw(struct intel_uncore *uncore,
- i915_reg_t i915_reg, u32 mask,
- u32 value, unsigned int timeout,
- u32 *out_value)
-{
- struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
-
- return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
- timeout * USEC_PER_MSEC, out_value, false);
-}
-
static inline int
__intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
u32 mask, u32 value, unsigned int fast_timeout_us,
@@ -133,6 +112,16 @@ __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
out_value, atomic);
}
+static inline int
+__intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t i915_reg,
+ u32 mask, u32 value, unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms, u32 *out_value)
+{
+ return __intel_wait_for_register(uncore, i915_reg, mask, value,
+ fast_timeout_us, slow_timeout_ms,
+ out_value);
+}
+
static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
i915_reg_t i915_reg)
{
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:14 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names Ville Syrjala
` (17 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We currently have a bunch of places that want the final register
value after register polling. Currently those places are mostly
using intel_de_wait_custom(). That is not a function that we
want to keep around as it pretty much prevents conversion to
poll_timeout_us().
Have intel_de_wait() also return the final register value so
that some of the current users can be converted over to the
simpler interface.
Done with cocci:
@@
@@
int intel_de_wait(...
+ ,u32 *out_value
)
{
...
__intel_wait_for_register(...,
- NULL
+ out_value
)
...
}
@@
@@
intel_de_wait(...
+ ,NULL
)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 8 ++++----
drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index ea9973dbbffc..a4ad20030c09 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -116,14 +116,14 @@ __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
static inline int
intel_de_wait(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout_ms)
+ u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
{
int ret;
intel_dmc_wl_get(display, reg);
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
- value, 2, timeout_ms, NULL);
+ value, 2, timeout_ms, out_value);
intel_dmc_wl_put(display, reg);
@@ -169,14 +169,14 @@ static inline int
intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, mask, timeout_ms);
+ return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
}
static inline int
intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, 0, timeout_ms);
+ return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index eab7019f2252..afa5d8964f0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1446,7 +1446,7 @@ static void assert_chv_phy_status(struct intel_display *display)
* so the power state can take a while to actually change.
*/
if (intel_de_wait(display, DISPLAY_PHY_STATUS,
- phy_status_mask, phy_status, 10))
+ phy_status_mask, phy_status, 10, NULL))
drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index bd757db85927..27bb2199659f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -784,7 +784,7 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
/* Wait for encryption confirmation */
if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
stream_enc_status, enable ? stream_enc_status : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
@@ -824,7 +824,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 5df6347a420d..378f0836b5a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
break;
}
- if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+ if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000, NULL))
drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
encoder->base.base.id, encoder->base.name,
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
2025-11-10 17:27 ` [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:21 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us() Ville Syrjala
` (16 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_de_wait*() take the timeout in milliseconds. Incldue
that information in the function name to make life less
confusing. And I'll also be introducing microsecond variants
of these later.
Done with cocci:
@@
@@
(
static int
- intel_de_wait
+ intel_de_wait_ms
(...)
{
...
}
|
static int
- intel_de_wait_fw
+ intel_de_wait_fw_ms
(...)
{
...
}
|
static int
- intel_de_wait_for_set
+ intel_de_wait_for_set_ms
(...)
{
...
}
|
static int
- intel_de_wait_for_clear
+ intel_de_wait_for_clear_ms
(...)
{
...
}
)
@@
@@
(
- intel_de_wait
+ intel_de_wait_ms
|
- intel_de_wait_fw
+ intel_de_wait_fw_ms
|
- intel_de_wait_for_set
+ intel_de_wait_for_set_ms
|
- intel_de_wait_for_clear
+ intel_de_wait_for_clear_ms
)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 20 +++----
drivers/gpu/drm/i915/display/intel_crt.c | 16 +++---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 36 ++++++-------
drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
drivers/gpu/drm/i915/display/intel_de.h | 22 ++++----
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_power.c | 4 +-
.../i915/display/intel_display_power_well.c | 38 ++++++-------
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 ++---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++--
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
drivers/gpu/drm/i915/display/intel_flipq.c | 8 +--
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 44 ++++++++-------
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +--
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +--
.../gpu/drm/i915/display/intel_pch_display.c | 12 ++---
drivers/gpu/drm/i915/display/intel_pmdemand.c | 12 ++---
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++--
drivers/gpu/drm/i915/display/intel_sbi.c | 6 ++-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +--
drivers/gpu/drm/i915/display/intel_tc.c | 8 +--
drivers/gpu/drm/i915/display/intel_vrr.c | 6 +--
drivers/gpu/drm/i915/display/vlv_dsi.c | 54 +++++++++----------
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +--
30 files changed, 207 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index f444c5b7a27b..008d339d5c21 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -56,7 +56,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* the HW state readout code will complain that the expected
* IPS_CTL value is not the one we read.
*/
- if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
+ if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
drm_err(display->drm,
"Timed out waiting for IPS enable\n");
}
@@ -78,7 +78,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
* 42ms timeout value leads to occasional timeouts so use 100ms
* instead.
*/
- if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
+ if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
drm_err(display->drm,
"Timed out waiting for IPS disable\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 70d4c1bc70fc..6a11b3bb219b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1048,8 +1048,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
TRANSCONF_ENABLE);
/* wait for transcoder to be enabled */
- if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
- TRANSCONF_STATE_ENABLE, 10))
+ if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),
+ TRANSCONF_STATE_ENABLE, 10))
drm_err(display->drm,
"DSI transcoder not enabled\n");
}
@@ -1317,8 +1317,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
TRANSCONF_ENABLE, 0);
/* wait for transcoder to be disabled */
- if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
- TRANSCONF_STATE_ENABLE, 50))
+ if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),
+ TRANSCONF_STATE_ENABLE, 50))
drm_err(display->drm,
"DSI trancoder not disabled\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4d03cfefc72c..c0d798b1cf46 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1114,7 +1114,7 @@ static void skl_dpll0_enable(struct intel_display *display, int vco)
intel_de_rmw(display, LCPLL1_CTL,
0, LCPLL_PLL_ENABLE);
- if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
+ if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drm_err(display->drm, "DPLL0 not locked\n");
display->cdclk.hw.vco = vco;
@@ -1128,7 +1128,7 @@ static void skl_dpll0_disable(struct intel_display *display)
intel_de_rmw(display, LCPLL1_CTL,
LCPLL_PLL_ENABLE, 0);
- if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
+ if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drm_err(display->drm, "Couldn't disable DPLL0\n");
display->cdclk.hw.vco = 0;
@@ -1835,8 +1835,8 @@ static void bxt_de_pll_disable(struct intel_display *display)
intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_de_wait_for_clear(display,
- BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ if (intel_de_wait_for_clear_ms(display,
+ BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
display->cdclk.hw.vco = 0;
@@ -1852,8 +1852,8 @@ static void bxt_de_pll_enable(struct intel_display *display, int vco)
intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
/* Timeout 200us */
- if (intel_de_wait_for_set(display,
- BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ if (intel_de_wait_for_set_ms(display,
+ BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(display->drm, "timeout waiting for DE PLL lock\n");
display->cdclk.hw.vco = vco;
@@ -1865,7 +1865,7 @@ static void icl_cdclk_pll_disable(struct intel_display *display)
BXT_DE_PLL_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
display->cdclk.hw.vco = 0;
@@ -1883,7 +1883,7 @@ static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
/* Timeout 200us */
- if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
display->cdclk.hw.vco = vco;
@@ -1903,8 +1903,8 @@ static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
/* Timeout 200us */
- if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
- BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
val &= ~BXT_DE_PLL_FREQ_REQ;
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 31e68047f217..82e89cdbe5a5 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -498,10 +498,10 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(display,
- crt->adpa_reg,
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
- 1000))
+ if (intel_de_wait_for_clear_ms(display,
+ crt->adpa_reg,
+ ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
+ 1000))
drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
@@ -553,8 +553,8 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(display, crt->adpa_reg,
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
+ if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,
+ ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
intel_de_write(display, crt->adpa_reg, save_adpa);
@@ -604,8 +604,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
- CRT_HOTPLUG_FORCE_DETECT, 1000))
+ if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display),
+ CRT_HOTPLUG_FORCE_DETECT, 1000))
drm_dbg_kms(display->drm,
"timed out waiting for FORCE_DETECT to go off");
}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1551d30ec584..7870823235c7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -145,9 +145,9 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_M2P_TRANSACTION_RESET,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_RESET,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_err_once(display->drm,
"Failed to bring PHY %c to idle.\n",
phy_name(phy));
@@ -213,9 +213,9 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
int ack;
u32 val;
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_M2P_TRANSACTION_PENDING,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
@@ -284,9 +284,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
int ack;
u32 val;
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_M2P_TRANSACTION_PENDING,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
@@ -300,9 +300,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_M2P_TRANSACTION_PENDING,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
@@ -2813,9 +2813,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_M2P_TRANSACTION_PENDING,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
phy_name(phy));
@@ -2924,9 +2924,9 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status,
- XELPDP_PORT_RESET_END_TIMEOUT_MS))
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status,
+ XELPDP_PORT_RESET_END_TIMEOUT_MS))
drm_warn(display->drm,
"PHY %c failed to bring out of lane reset\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 733ef4559131..33fca83c22b3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -210,8 +210,8 @@ void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
}
static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
- if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port),
- DDI_BUF_IS_IDLE, 10))
+ if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port),
+ DDI_BUF_IS_IDLE, 10))
drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",
port_name(port));
}
@@ -235,8 +235,8 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
}
static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
- if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port),
- DDI_BUF_IS_IDLE, 10))
+ if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port),
+ DDI_BUF_IS_IDLE, 10))
drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",
port_name(port));
}
@@ -2307,8 +2307,8 @@ void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
- if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_ACT_SENT, 1))
+ if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_ACT_SENT, 1))
drm_err(display->drm, "Timed out waiting for ACT sent\n");
}
@@ -2383,11 +2383,11 @@ int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
return 0;
if (enabled)
- ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
+ ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
else
- ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
+ ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
if (ret) {
drm_err(display->drm,
@@ -3868,9 +3868,9 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
if (port == PORT_A && DISPLAY_VER(display) < 12)
return;
- if (intel_de_wait_for_set(display,
- dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_IDLE_DONE, 2))
+ if (intel_de_wait_for_set_ms(display,
+ dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_IDLE_DONE, 2))
drm_err(display->drm,
"Timed out waiting for DP idle patterns\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index a4ad20030c09..d449180d1d22 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -115,8 +115,9 @@ __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
}
static inline int
-intel_de_wait(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
+intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout_ms,
+ u32 *out_value)
{
int ret;
@@ -131,8 +132,9 @@ intel_de_wait(struct intel_display *display, i915_reg_t reg,
}
static inline int
-intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
+intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout_ms,
+ u32 *out_value)
{
int ret;
@@ -166,17 +168,17 @@ intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
}
static inline int
-intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
- u32 mask, unsigned int timeout_ms)
+intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
+ u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
+ return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
}
static inline int
-intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
- u32 mask, unsigned int timeout_ms)
+intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
+ u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
+ return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25986bd8fbdd..6bca186608ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -359,8 +359,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
/* Wait for the Pipe State to go off */
- if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder),
- TRANSCONF_STATE_ENABLE, 100))
+ if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),
+ TRANSCONF_STATE_ENABLE, 100))
drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 74fcd9cfe911..2b86a634c1f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1305,7 +1305,7 @@ static void hsw_disable_lcpll(struct intel_display *display,
intel_de_write(display, LCPLL_CTL, val);
intel_de_posting_read(display, LCPLL_CTL);
- if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
+ if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
drm_err(display->drm, "LCPLL still locked\n");
val = hsw_read_dcomp(display);
@@ -1362,7 +1362,7 @@ static void hsw_restore_lcpll(struct intel_display *display)
val &= ~LCPLL_PLL_DISABLE;
intel_de_write(display, LCPLL_CTL, val);
- if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
+ if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
drm_err(display->drm, "LCPLL not locked yet\n");
if (val & LCPLL_CD_SOURCE_FCLK) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index afa5d8964f0d..8593d2daeaa6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -293,8 +293,8 @@ static void hsw_wait_for_power_well_enable(struct intel_display *display,
}
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
- if (intel_de_wait_for_set(display, regs->driver,
- HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {
+ if (intel_de_wait_for_set_ms(display, regs->driver,
+ HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {
drm_dbg_kms(display->drm, "%s power well enable timeout\n",
intel_power_well_name(power_well));
@@ -338,9 +338,9 @@ static void hsw_wait_for_power_well_disable(struct intel_display *display,
*/
reqs = hsw_power_well_requesters(display, regs, pw_idx);
- ret = intel_de_wait_for_clear(display, regs->driver,
- HSW_PWR_WELL_CTL_STATE(pw_idx),
- reqs ? 0 : 1);
+ ret = intel_de_wait_for_clear_ms(display, regs->driver,
+ HSW_PWR_WELL_CTL_STATE(pw_idx),
+ reqs ? 0 : 1);
if (!ret)
return;
@@ -359,8 +359,8 @@ static void gen9_wait_for_power_well_fuses(struct intel_display *display,
{
/* Timeout 5us for PG#0, for other PGs 1us */
drm_WARN_ON(display->drm,
- intel_de_wait_for_set(display, SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(pg), 1));
+ intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
static void hsw_power_well_enable(struct intel_display *display,
@@ -1445,8 +1445,8 @@ static void assert_chv_phy_status(struct intel_display *display)
* The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change.
*/
- if (intel_de_wait(display, DISPLAY_PHY_STATUS,
- phy_status_mask, phy_status, 10, NULL))
+ if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
+ phy_status_mask, phy_status, 10, NULL))
drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
@@ -1476,8 +1476,8 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
vlv_set_power_well(display, power_well, true);
/* Poll for phypwrgood signal */
- if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
- PHY_POWERGOOD(phy), 1))
+ if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,
+ PHY_POWERGOOD(phy), 1))
drm_err(display->drm, "Display PHY %d is not power up\n",
phy);
@@ -1867,8 +1867,8 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
* bit.
*/
if (DISPLAY_VER(display) >= 35) {
- if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
- XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
+ if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+ XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
drm_warn(display->drm,
"Timeout waiting for PHY %c AUX channel power to be up\n",
phy_name(phy));
@@ -1888,8 +1888,8 @@ static void xelpdp_aux_power_well_disable(struct intel_display *display,
0);
if (DISPLAY_VER(display) >= 35) {
- if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
- XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
+ if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+ XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
drm_warn(display->drm,
"Timeout waiting for PHY %c AUX channel to powerdown\n",
phy_name(phy));
@@ -1913,8 +1913,8 @@ static void xe2lpd_pica_power_well_enable(struct intel_display *display,
intel_de_write(display, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_REQUEST);
- if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL,
- XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
drm_dbg_kms(display->drm, "pica power well enable timeout\n");
drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");
@@ -1926,8 +1926,8 @@ static void xe2lpd_pica_power_well_disable(struct intel_display *display,
{
intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);
- if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL,
- XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
drm_dbg_kms(display->drm, "pica power well disable timeout\n");
drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 27bb2199659f..14ed0ea22dd3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -782,9 +782,9 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
return -EINVAL;
/* Wait for encryption confirmation */
- if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
- stream_enc_status, enable ? stream_enc_status : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
+ if (intel_de_wait_ms(display, HDCP_STATUS(display, cpu_transcoder, port),
+ stream_enc_status, enable ? stream_enc_status : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
@@ -821,10 +821,10 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
return ret;
/* Wait for encryption confirmation */
- if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
- STREAM_ENCRYPTION_STATUS,
- enable ? STREAM_ENCRYPTION_STATUS : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
+ if (intel_de_wait_ms(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 378f0836b5a5..4d1b6e2b93dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -390,7 +390,7 @@ static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
static void bxt_phy_wait_grc_done(struct intel_display *display,
enum dpio_phy phy)
{
- if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
+ if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
}
@@ -427,8 +427,8 @@ static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
* The flag should get set in 100us according to the HW team, but
* use 1ms due to occasional timeouts observed with that.
*/
- if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
- PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL))
+ if (intel_de_wait_fw_ms(display, BXT_PORT_CL1CM_DW0(phy),
+ PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL))
drm_err(display->drm, "timeout during PHY%d power on\n",
phy);
@@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
break;
}
- if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000, NULL))
+ if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, NULL))
drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
encoder->base.base.id, encoder->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2e1f67be8eda..4f1db8493a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -2019,7 +2019,7 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
intel_de_posting_read(display, DPLL(display, pipe));
udelay(150);
- if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
+ if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
drm_err(display->drm, "DPLL %d failed to lock\n", pipe);
}
@@ -2165,7 +2165,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
/* Check PLL is locked */
- if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
+ if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
drm_err(display->drm, "PLL %d failed to lock\n", pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 92c433f7b7e2..683bc61c03c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1395,7 +1395,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
/* the enable bit is always bit 31 */
intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
- if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
+ if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id), 5))
drm_err(display->drm, "DPLL %d not locked\n", id);
}
@@ -3921,7 +3921,7 @@ static void icl_pll_power_enable(struct intel_display *display,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
+ if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE, 1))
drm_err(display->drm, "PLL %d Power not enabled\n",
pll->info->id);
}
@@ -3933,7 +3933,7 @@ static void icl_pll_enable(struct intel_display *display,
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
/* Timeout is actually 600us. */
- if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
+ if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
@@ -4046,7 +4046,7 @@ static void icl_pll_disable(struct intel_display *display,
intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
/* Timeout is actually 1us. */
- if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
+ if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
drm_err(display->drm, "PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
@@ -4057,7 +4057,7 @@ static void icl_pll_disable(struct intel_display *display,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
+ if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_POWER_STATE, 1))
drm_err(display->drm, "PLL %d Power not disabled\n",
pll->info->id);
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a1e3083022ee..437d2fda20a7 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -328,8 +328,8 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
intel_de_write(display, FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
- if (intel_de_wait_for_clear(display, FBC_STATUS,
- FBC_STAT_COMPRESSING, 10)) {
+ if (intel_de_wait_for_clear_ms(display, FBC_STATUS,
+ FBC_STAT_COMPRESSING, 10)) {
drm_dbg_kms(display->drm, "FBC idle timed out\n");
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
index f162614a925d..1e9550cb66a3 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.c
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -163,10 +163,10 @@ static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
PIPEDMC_FQ_CTRL_PREEMPT, preempt ? PIPEDMC_FQ_CTRL_PREEMPT : 0);
if (preempt &&
- intel_de_wait_for_clear(display,
- PIPEDMC_FQ_STATUS(crtc->pipe),
- PIPEDMC_FQ_STATUS_BUSY,
- intel_flipq_preempt_timeout_ms(display)))
+ intel_de_wait_for_clear_ms(display,
+ PIPEDMC_FQ_STATUS(crtc->pipe),
+ PIPEDMC_FQ_STATUS_BUSY,
+ intel_flipq_preempt_timeout_ms(display)))
drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",
crtc->base.base.id, crtc->base.name);
}
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 82f3a40ecac7..795012d7c24c 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -449,7 +449,7 @@ gmbus_wait_idle(struct intel_display *display)
add_wait_queue(&display->gmbus.wait_queue, &wait);
intel_de_write_fw(display, GMBUS4(display), irq_enable);
- ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);
+ ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);
intel_de_write_fw(display, GMBUS4(display), 0);
remove_wait_queue(&display->gmbus.wait_queue, &wait);
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d01733b6460e..78c34466e402 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -428,7 +428,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
static int intel_write_sha_text(struct intel_display *display, u32 sha_text)
{
intel_de_write(display, HDCP_SHA_TEXT, sha_text);
- if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
+ if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
drm_err(display->drm, "Timed out waiting for SHA1 ready\n");
return -ETIMEDOUT;
}
@@ -707,8 +707,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector,
/* Tell the HW we're done with the hash and wait for it to ACK */
intel_de_write(display, HDCP_REP_CTL,
rep_ctl | HDCP_SHA1_COMPLETE_HASH);
- if (intel_de_wait_for_set(display, HDCP_REP_CTL,
- HDCP_SHA1_COMPLETE, 1)) {
+ if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
+ HDCP_SHA1_COMPLETE, 1)) {
drm_err(display->drm, "Timed out waiting for SHA1 complete\n");
return -ETIMEDOUT;
}
@@ -856,9 +856,9 @@ static int intel_hdcp_auth(struct intel_connector *connector)
HDCP_CONF_CAPTURE_AN);
/* Wait for An to be acquired */
- if (intel_de_wait_for_set(display,
- HDCP_STATUS(display, cpu_transcoder, port),
- HDCP_STATUS_AN_READY, 1)) {
+ if (intel_de_wait_for_set_ms(display,
+ HDCP_STATUS(display, cpu_transcoder, port),
+ HDCP_STATUS_AN_READY, 1)) {
drm_err(display->drm, "Timed out waiting for An\n");
return -ETIMEDOUT;
}
@@ -953,10 +953,10 @@ static int intel_hdcp_auth(struct intel_connector *connector)
}
/* Wait for encryption confirmation */
- if (intel_de_wait_for_set(display,
- HDCP_STATUS(display, cpu_transcoder, port),
- HDCP_STATUS_ENC,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ if (intel_de_wait_for_set_ms(display,
+ HDCP_STATUS(display, cpu_transcoder, port),
+ HDCP_STATUS_ENC,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(display->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -1013,9 +1013,9 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
hdcp->hdcp_encrypted = false;
intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0);
- if (intel_de_wait_for_clear(display,
- HDCP_STATUS(display, cpu_transcoder, port),
- ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display,
+ HDCP_STATUS(display, cpu_transcoder, port),
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(display->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1940,11 +1940,10 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
0, CTL_LINK_ENCRYPTION_REQ);
- ret = intel_de_wait_for_set(display,
- HDCP2_STATUS(display, cpu_transcoder,
- port),
- LINK_ENCRYPTION_STATUS,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ ret = intel_de_wait_for_set_ms(display,
+ HDCP2_STATUS(display, cpu_transcoder, port),
+ LINK_ENCRYPTION_STATUS,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
dig_port->hdcp.auth_status = true;
return ret;
@@ -1966,11 +1965,10 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
CTL_LINK_ENCRYPTION_REQ, 0);
- ret = intel_de_wait_for_clear(display,
- HDCP2_STATUS(display, cpu_transcoder,
- port),
- LINK_ENCRYPTION_STATUS,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ ret = intel_de_wait_for_clear_ms(display,
+ HDCP2_STATUS(display, cpu_transcoder, port),
+ LINK_ENCRYPTION_STATUS,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(display->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5c637341b210..908faf17f93d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1598,8 +1598,8 @@ bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);
/* Wait for Ri prime match */
- ret = intel_de_wait_for_set(display, HDCP_STATUS(display, cpu_transcoder, port),
- HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1);
+ ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display, cpu_transcoder, port),
+ HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1);
if (ret) {
drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index b2413b385dc8..6bd42691de8f 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1067,9 +1067,9 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
int ack;
u32 val;
- if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
- XELPDP_PORT_P2P_TRANSACTION_PENDING,
- XELPDP_MSGBUS_TIMEOUT_MS)) {
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+ XELPDP_PORT_P2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_MS)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 48f4d8ed4f15..89aeb4fb340e 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -329,7 +329,7 @@ static void intel_enable_lvds(struct intel_atomic_state *state,
intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON);
intel_de_posting_read(display, lvds_encoder->reg);
- if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON, 5000))
+ if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, 5000))
drm_err(display->drm,
"timed out waiting for panel to power on\n");
@@ -345,7 +345,7 @@ static void intel_disable_lvds(struct intel_atomic_state *state,
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0);
- if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_ON, 1000))
+ if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, 1000))
drm_err(display->drm,
"timed out waiting for panel to power off\n");
@@ -384,7 +384,7 @@ static void intel_lvds_shutdown(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
- if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
+ if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
drm_err(display->drm,
"timed out waiting for panel power cycle delay\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 3456c794e0e7..16619f7be5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -305,7 +305,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
}
intel_de_write(display, reg, val | TRANS_ENABLE);
- if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
+ if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE, 100))
drm_err(display->drm, "failed to enable transcoder %c\n",
pipe_name(pipe));
}
@@ -326,7 +326,7 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
reg = PCH_TRANSCONF(pipe);
intel_de_rmw(display, reg, TRANS_ENABLE, 0);
/* wait for PCH transcoder off, transcoder state */
- if (intel_de_wait_for_clear(display, reg, TRANS_STATE_ENABLE, 50))
+ if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE, 50))
drm_err(display->drm, "failed to disable transcoder %c\n",
pipe_name(pipe));
@@ -572,8 +572,8 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
val |= TRANS_INTERLACE_PROGRESSIVE;
intel_de_write(display, LPT_TRANSCONF, val);
- if (intel_de_wait_for_set(display, LPT_TRANSCONF,
- TRANS_STATE_ENABLE, 100))
+ if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
+ TRANS_STATE_ENABLE, 100))
drm_err(display->drm, "Failed to enable PCH transcoder\n");
}
@@ -581,8 +581,8 @@ static void lpt_disable_pch_transcoder(struct intel_display *display)
{
intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);
/* wait for PCH transcoder off, transcoder state */
- if (intel_de_wait_for_clear(display, LPT_TRANSCONF,
- TRANS_STATE_ENABLE, 50))
+ if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
+ TRANS_STATE_ENABLE, 50))
drm_err(display->drm, "Failed to disable PCH transcoder\n");
/* Workaround: clear timing override bit. */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 22d8f720ae7d..3cc89048b027 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -390,12 +390,12 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)
{
- return !(intel_de_wait_for_clear(display,
- XELPDP_INITIATE_PMDEMAND_REQUEST(1),
- XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
- intel_de_wait_for_clear(display,
- GEN12_DCPR_STATUS_1,
- XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
+ return !(intel_de_wait_for_clear_ms(display,
+ XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
+ intel_de_wait_for_clear_ms(display,
+ GEN12_DCPR_STATUS_1,
+ XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
}
void
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 00b06771ae2d..00ac652809cc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2277,8 +2277,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
}
/* Wait till PSR is idle */
- if (intel_de_wait_for_clear(display, psr_status,
- psr_status_mask, 2000))
+ if (intel_de_wait_for_clear_ms(display, psr_status,
+ psr_status_mask, 2000))
drm_err(display->drm, "Timed out waiting PSR idle state\n");
}
@@ -3166,7 +3166,7 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
return true;
}
- return intel_de_wait_for_clear(display,
+ return intel_de_wait_for_clear_ms(display,
EDP_PSR2_STATUS(display, cpu_transcoder),
EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
PSR_IDLE_TIMEOUT_MS);
@@ -3186,7 +3186,7 @@ _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
return true;
}
- return intel_de_wait_for_clear(display,
+ return intel_de_wait_for_clear_ms(display,
psr_status_reg(display, cpu_transcoder),
EDP_PSR_STATUS_STATE_MASK,
PSR_IDLE_TIMEOUT_MS);
@@ -3264,7 +3264,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
mutex_unlock(&intel_dp->psr.lock);
- err = intel_de_wait_for_clear(display, reg, mask, 50);
+ err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
if (err)
drm_err(display->drm,
"Timed out waiting for PSR Idle for re-enable\n");
diff --git a/drivers/gpu/drm/i915/display/intel_sbi.c b/drivers/gpu/drm/i915/display/intel_sbi.c
index dfcff924f0ed..b636a0060d39 100644
--- a/drivers/gpu/drm/i915/display/intel_sbi.c
+++ b/drivers/gpu/drm/i915/display/intel_sbi.c
@@ -21,7 +21,8 @@ static int intel_sbi_rw(struct intel_display *display, u16 reg,
lockdep_assert_held(&display->sbi.lock);
- if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, NULL)) {
+ if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
+ SBI_STATUS_MASK, SBI_STATUS_READY, 100, NULL)) {
drm_err(display->drm, "timeout waiting for SBI to become ready\n");
return -EBUSY;
}
@@ -37,7 +38,8 @@ static int intel_sbi_rw(struct intel_display *display, u16 reg,
cmd |= SBI_CTL_OP_WR;
intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);
- if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, &cmd)) {
+ if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
+ SBI_STATUS_MASK, SBI_STATUS_READY, 100, &cmd)) {
drm_err(display->drm, "timeout waiting for SBI to complete read\n");
return -ETIMEDOUT;
}
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 4f028e6a91cd..295030742294 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -42,8 +42,8 @@ void intel_snps_phy_wait_for_calibration(struct intel_display *display)
* which phy was affected and skip setup of the corresponding
* output later.
*/
- if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),
- DG2_PHY_DP_TX_ACK_MASK, 25))
+ if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
+ DG2_PHY_DP_TX_ACK_MASK, 25))
display->snps.phy_failed_calibration |= BIT(phy);
}
}
@@ -1863,7 +1863,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
* is locked at new settings. This register bit is sampling PHY
* dp_mpllb_state interface signal.
*/
- if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5))
+ if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));
/*
@@ -1903,7 +1903,7 @@ void intel_mpllb_disable(struct intel_encoder *encoder)
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
* (dp_txX_ack) that the new transmitter setting request is completed.
*/
- if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5))
+ if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));
/*
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 7e17ca018748..1e21fd02685d 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -1076,8 +1076,8 @@ xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)
{
/* check if mailbox is running busy */
- if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
- TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
+ if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
+ TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
drm_dbg_kms(display->drm,
"Timeout waiting for TCSS mailbox run/busy bit to clear\n");
return;
@@ -1089,8 +1089,8 @@ static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enabl
TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1));
/* wait to clear mailbox running busy bit before continuing */
- if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
- TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
+ if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
+ TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
drm_dbg_kms(display->drm,
"Timeout after writing data to mailbox. Mailbox run/busy bit did not clear\n");
return;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00cbc126fb36..b92c42fde937 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -716,9 +716,9 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
- if (intel_de_wait_for_clear(display,
- TRANS_VRR_STATUS(display, cpu_transcoder),
- VRR_STATUS_VRR_EN_LIVE, 1000))
+ if (intel_de_wait_for_clear_ms(display,
+ TRANS_VRR_STATUS(display, cpu_transcoder),
+ VRR_STATUS_VRR_EN_LIVE, 1000))
drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 444682995658..19bdd8662359 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -94,8 +94,8 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
- if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
- mask, 100))
+ if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port),
+ mask, 100))
drm_err(display->drm, "DPI FIFOs are not empty\n");
}
@@ -162,8 +162,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* note: this is never true for reads */
if (packet.payload_length) {
- if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
- data_mask, 50))
+ if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
+ data_mask, 50))
drm_err(display->drm,
"Timeout waiting for HS/LP DATA FIFO !full\n");
@@ -176,8 +176,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
GEN_READ_DATA_AVAIL);
}
- if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
- ctrl_mask, 50)) {
+ if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
+ ctrl_mask, 50)) {
drm_err(display->drm,
"Timeout waiting for HS/LP CTRL FIFO !full\n");
}
@@ -188,8 +188,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* ->rx_len is set only for reads */
if (msg->rx_len) {
data_mask = GEN_READ_DATA_AVAIL;
- if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
- data_mask, 50))
+ if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),
+ data_mask, 50))
drm_err(display->drm,
"Timeout waiting for read data.\n");
@@ -246,7 +246,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
mask = SPL_PKT_SENT_INTERRUPT;
- if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))
+ if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), mask, 100))
drm_err(display->drm,
"Video mode command 0x%08x send failed.\n", cmd);
@@ -352,8 +352,8 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
/* Wait for Pwr ACK */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
- GLK_MIPIIO_PORT_POWERED, 20))
+ if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
+ GLK_MIPIIO_PORT_POWERED, 20))
drm_err(display->drm, "MIPIO port is powergated\n");
}
@@ -374,8 +374,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
- GLK_PHY_STATUS_PORT_READY, 20))
+ if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
+ GLK_PHY_STATUS_PORT_READY, 20))
drm_err(display->drm, "PHY is not ON\n");
}
@@ -394,8 +394,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
/* Wait for ULPS active */
- if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
- GLK_ULPS_NOT_ACTIVE, 20))
+ if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
+ GLK_ULPS_NOT_ACTIVE, 20))
drm_err(display->drm, "ULPS not active\n");
/* Exit ULPS */
@@ -413,16 +413,16 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for Stop state */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
- GLK_DATA_LANE_STOP_STATE, 20))
+ if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
+ GLK_DATA_LANE_STOP_STATE, 20))
drm_err(display->drm,
"Date lane not in STOP state\n");
}
/* Wait for AFE LATCH */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
- AFE_LATCHOUT, 20))
+ if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port),
+ AFE_LATCHOUT, 20))
drm_err(display->drm,
"D-PHY not entering LP-11 state\n");
}
@@ -519,15 +519,15 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
- GLK_PHY_STATUS_PORT_READY, 20))
+ if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
+ GLK_PHY_STATUS_PORT_READY, 20))
drm_err(display->drm, "PHY is not turning OFF\n");
}
/* Wait for Pwr ACK bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
- GLK_MIPIIO_PORT_POWERED, 20))
+ if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
+ GLK_MIPIIO_PORT_POWERED, 20))
drm_err(display->drm,
"MIPI IO Port is not powergated\n");
}
@@ -544,8 +544,8 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
- GLK_PHY_STATUS_PORT_READY, 20))
+ if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
+ GLK_PHY_STATUS_PORT_READY, 20))
drm_err(display->drm, "PHY is not turning OFF\n");
}
@@ -595,8 +595,8 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
* Port A only. MIPI Port C has no similar bit for checking.
*/
if ((display->platform.broxton || port == PORT_A) &&
- intel_de_wait_for_clear(display, port_ctrl,
- AFE_LATCHOUT, 30))
+ intel_de_wait_for_clear_ms(display, port_ctrl,
+ AFE_LATCHOUT, 30))
drm_err(display->drm, "DSI LP not going Low\n");
/* Disable MIPI PHY transparent latch */
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index f078b9cda96c..a2da6285890b 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -319,8 +319,8 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder)
* PLL lock should deassert within 200us.
* Wait up to 1ms before timing out.
*/
- if (intel_de_wait_for_clear(display, BXT_DSI_PLL_ENABLE,
- BXT_DSI_PLL_LOCKED, 1))
+ if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,
+ BXT_DSI_PLL_LOCKED, 1))
drm_err(display->drm,
"Timeout waiting for PLL lock deassertion\n");
}
@@ -568,8 +568,8 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);
/* Timeout and fail if PLL not locked */
- if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE,
- BXT_DSI_PLL_LOCKED, 1)) {
+ if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,
+ BXT_DSI_PLL_LOCKED, 1)) {
drm_err(display->drm,
"Timed out waiting for DSI PLL to lock\n");
return;
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (2 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:24 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 05/16] drm/i915/de: Use intel_de_wait_us() Ville Syrjala
` (15 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Introduce intel_de_wait_us() as the microsecond based
counterpart to the millisecond based intel_de_wait_ms().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index d449180d1d22..43a4160f760a 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -114,6 +114,23 @@ __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
value, fast_timeout_us, 0, NULL);
}
+static inline int
+intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout_us,
+ u32 *out_value)
+{
+ int ret;
+
+ intel_dmc_wl_get(display, reg);
+
+ ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
+ value, timeout_us, 0, out_value);
+
+ intel_dmc_wl_put(display, reg);
+
+ return ret;
+}
+
static inline int
intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 05/16] drm/i915/de: Use intel_de_wait_us()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (3 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:28 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases Ville Syrjala
` (14 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert some of the intel_de_wait_custom() users over to
intel_de_wait_us(). We'll eventually want to eliminate
intel_de_wait_custom() as it's a hinderance towards using
poll_timeout_us().
This includes all the obvious cases where we only specify
a microsecond timeout to intel_de_wait_custom().
Done with cocci (with manual formatting fixes):
@@
expression display, reg, mask, value, timeout_us, out_value;
@@
- intel_de_wait_custom(display, reg, mask, value, timeout_us, 0, out_value)
+ intel_de_wait_us(display, reg, mask, value, timeout_us, out_value)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 27 +++++------
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 48 +++++++++----------
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +---
.../drm/i915/display/intel_display_power.c | 11 ++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 +++----
drivers/gpu/drm/i915/display/intel_lt_phy.c | 19 ++++----
.../gpu/drm/i915/display/intel_pch_refclk.c | 11 ++---
8 files changed, 67 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6a11b3bb219b..151266ffd582 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -148,9 +148,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
- LPTX_IN_PROGRESS, 0,
- 20, 0, NULL);
+ ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
+ LPTX_IN_PROGRESS, 0, 20, NULL);
if (ret)
drm_err(display->drm, "LPTX bit not cleared\n");
}
@@ -534,9 +533,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
- ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
- DDI_BUF_IS_IDLE, 0,
- 500, 0, NULL);
+ ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
+ DDI_BUF_IS_IDLE, 0, 500, NULL);
if (ret)
drm_err(display->drm, "DDI port:%c buffer idle\n",
port_name(port));
@@ -857,9 +855,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
- ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),
- LINK_READY, LINK_READY,
- 2500, 0, NULL);
+ ret = intel_de_wait_us(display,
+ DSI_TRANS_FUNC_CONF(dsi_trans),
+ LINK_READY, LINK_READY, 2500, NULL);
if (ret)
drm_err(display->drm, "DSI link not ready\n");
}
@@ -1358,9 +1356,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
tmp &= ~LINK_ULPS_TYPE_LP11;
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
- ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
- LINK_IN_ULPS, LINK_IN_ULPS,
- 10, 0, NULL);
+ ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
+ LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
if (ret)
drm_err(display->drm, "DSI link not in ULPS\n");
}
@@ -1395,9 +1392,9 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
- ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
- DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,
- 8, 0, NULL);
+ ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
+ DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
+ NULL);
if (ret)
drm_err(display->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c0d798b1cf46..f7daebccb10f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -902,9 +902,8 @@ static void bdw_set_cdclk(struct intel_display *display,
* According to the spec, it should be enough to poll for this 1 us.
* However, extensive testing shows that this can take longer.
*/
- ret = intel_de_wait_custom(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
- 100, 0, NULL);
+ ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
+ LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
if (ret)
drm_err(display->drm, "Switching to FCLK failed\n");
@@ -914,9 +913,8 @@ static void bdw_set_cdclk(struct intel_display *display,
intel_de_rmw(display, LCPLL_CTL,
LCPLL_CD_SOURCE_FCLK, 0);
- ret = intel_de_wait_custom(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE, 0,
- 1, 0, NULL);
+ ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
+ 0, 1, NULL);
if (ret)
drm_err(display->drm, "Switching back to LCPLL failed\n");
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7870823235c7..af97bd42495b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2888,10 +2888,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
- XELPDP_PORT_BUF_SOC_PHY_READY,
- XELPDP_PORT_BUF_SOC_PHY_READY,
- XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, NULL))
drm_warn(display->drm,
"PHY %c failed to bring out of SOC reset\n",
phy_name(phy));
@@ -2899,9 +2899,9 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
lane_pipe_reset);
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status, lane_phy_current_status,
- XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status, lane_phy_current_status,
+ XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
drm_warn(display->drm,
"PHY %c failed to bring out of lane reset\n",
phy_name(phy));
@@ -2910,10 +2910,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
- intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
- intel_cx0_get_pclk_refclk_ack(lane_mask),
- XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
+ intel_cx0_get_pclk_refclk_ack(lane_mask),
+ XELPDP_REFCLK_ENABLE_TIMEOUT_US, NULL))
drm_warn(display->drm,
"PHY %c failed to request refclk\n",
phy_name(phy));
@@ -3064,10 +3064,10 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
- intel_cx0_get_pclk_pll_ack(maxpclk_lane),
- XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_pll_ack(maxpclk_lane),
+ XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
drm_warn(display->drm, "Port %c PLL not locked\n",
phy_name(phy));
@@ -3188,10 +3188,8 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- XELPDP_TBT_CLOCK_ACK,
- XELPDP_TBT_CLOCK_ACK,
- 100, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK, 100, NULL))
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -3302,10 +3300,10 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
- intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
- XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
+ XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
drm_warn(display->drm, "Port %c PLL not unlocked\n",
phy_name(phy));
@@ -3350,8 +3348,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 33fca83c22b3..3b2d2b51ebc6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2577,9 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
intel_de_rmw(display, reg, 0, set_bits);
- ret = intel_de_wait_custom(display, reg,
- wait_bits, wait_bits,
- 100, 0, NULL);
+ ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
if (ret) {
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
@@ -3079,9 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder)
intel_de_rmw(display, reg, clr_bits, 0);
- ret = intel_de_wait_custom(display, reg,
- wait_bits, 0,
- 100, 0, NULL);
+ ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
if (ret)
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2b86a634c1f5..cc701f8277b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1292,9 +1292,9 @@ static void hsw_disable_lcpll(struct intel_display *display,
val |= LCPLL_CD_SOURCE_FCLK;
intel_de_write(display, LCPLL_CTL, val);
- ret = intel_de_wait_custom(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
- 1, 0, NULL);
+ ret = intel_de_wait_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE,
+ LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
if (ret)
drm_err(display->drm, "Switching to FCLK failed\n");
@@ -1368,9 +1368,8 @@ static void hsw_restore_lcpll(struct intel_display *display)
if (val & LCPLL_CD_SOURCE_FCLK) {
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
- ret = intel_de_wait_custom(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE, 0,
- 1, 0, NULL);
+ ret = intel_de_wait_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE, 0, 1, NULL);
if (ret)
drm_err(display->drm,
"Switching back to LCPLL failed\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 683bc61c03c1..1cc1a862c50b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
0, PORT_PLL_POWER_ENABLE);
- ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_POWER_STATE, PORT_PLL_POWER_STATE,
- 200, 0, NULL);
+ ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_POWER_STATE,
+ PORT_PLL_POWER_STATE, 200, NULL);
if (ret)
drm_err(display->drm,
"Power state not set for PLL:%d\n", port);
@@ -2122,9 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_LOCK, PORT_PLL_LOCK,
- 200, 0, NULL);
+ ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
if (ret)
drm_err(display->drm, "PLL %d not locked\n", port);
@@ -2158,9 +2157,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
PORT_PLL_POWER_ENABLE, 0);
- ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_POWER_STATE, 0,
- 200, 0, NULL);
+ ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_POWER_STATE, 0, 200, NULL);
if (ret)
drm_err(display->drm,
"Power state not reset for PLL:%d\n", port);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6bd42691de8f..243fca1c6a2d 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1982,9 +1982,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), 0,
- XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0), 0,
+ XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
@@ -2089,10 +2089,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
lane_pipe_reset);
/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status,
- lane_phy_current_status,
- XE3PLPD_RESET_START_LATENCY_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status, lane_phy_current_status,
+ XE3PLPD_RESET_START_LATENCY_US, NULL))
drm_warn(display->drm, "PHY %c failed to reset lane\n",
phy_name(phy));
@@ -2113,9 +2112,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), 0,
- XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
+ if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0), 0,
+ XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index cca880c7eed4..ebf2d1c34b3e 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -21,17 +21,16 @@ static void lpt_fdi_reset_mphy(struct intel_display *display)
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
- ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
- FDI_MPHY_IOSFSB_RESET_STATUS, FDI_MPHY_IOSFSB_RESET_STATUS,
- 100, 0, NULL);
+ ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
+ FDI_MPHY_IOSFSB_RESET_STATUS,
+ FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
if (ret)
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
- ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
- FDI_MPHY_IOSFSB_RESET_STATUS, 0,
- 100, 0, NULL);
+ ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
+ FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
if (ret)
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
}
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (4 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 05/16] drm/i915/de: Use intel_de_wait_us() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:32 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom() Ville Syrjala
` (13 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace some users of intel_de_wait_custom() with intel_de_wait_ms().
This includes the cases where we pass in the default 2 microsecond
fast timeout, which is also what intel_de_wait_ms() uses so there
are no functional changes here.
Done with cocci (with manual formatting fixes):
@@
expression display, reg, mask, value, timeout_ms, out_value;
@@
- intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value)
+ intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 15 ++++-----
drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 5 ++-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 32 +++++++++----------
drivers/gpu/drm/i915/display/intel_pmdemand.c | 6 ++--
5 files changed, 30 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index af97bd42495b..55fd95994ea7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -164,11 +164,10 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- if (intel_de_wait_custom(display,
- XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
- XELPDP_PORT_P2M_RESPONSE_READY,
- XELPDP_PORT_P2M_RESPONSE_READY,
- 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
+ if (intel_de_wait_ms(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_MSGBUS_TIMEOUT_MS, val)) {
drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
phy_name(phy), *val);
@@ -2827,9 +2826,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (intel_de_wait_custom(display, buf_ctl2_reg,
- intel_cx0_get_powerdown_update(lane_mask), 0,
- 2, XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
+ if (intel_de_wait_ms(display, buf_ctl2_reg,
+ intel_cx0_get_powerdown_update(lane_mask), 0,
+ XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
drm_warn(display->drm,
"PHY %c failed to bring out of lane reset\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2e7dbaf511b9..809799f63e32 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -62,9 +62,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
u32 status;
int ret;
- ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY,
- 0,
- 2, timeout_ms, &status);
+ ret = intel_de_wait_ms(display, ch_ctl,
+ DP_AUX_CH_CTL_SEND_BUSY, 0,
+ timeout_ms, &status);
if (ret == -ETIMEDOUT)
drm_err(display->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 78c34466e402..5e1a96223a9c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -410,9 +410,8 @@ static int intel_hdcp_load_keys(struct intel_display *display)
}
/* Wait for the keys to load (500us) */
- ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
- HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
- 2, 1, &val);
+ ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE,
+ HDCP_KEY_LOAD_DONE, 1, &val);
if (ret)
return ret;
else if (!(val & HDCP_KEY_LOAD_STATUS))
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 243fca1c6a2d..ac6f61107528 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1201,10 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0),
XELPDP_LANE_PCLK_PLL_REQUEST(0));
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0),
- XELPDP_LANE_PCLK_PLL_ACK(0),
- 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+ if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
phy_name(phy));
@@ -1215,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_pipe_reset | lane_phy_pulse_status, 0);
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status, 0,
- 2, XE3PLPD_RESET_END_LATENCY_MS, NULL))
+ if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status, 0,
+ XE3PLPD_RESET_END_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
phy_name(phy));
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_pulse_status, lane_phy_pulse_status,
- 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
+ if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_pulse_status, lane_phy_pulse_status,
+ XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
@@ -2002,10 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0));
/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
- if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0),
- XELPDP_LANE_PCLK_PLL_ACK(0),
- 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+ if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
phy_name(phy));
@@ -2031,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
rate_update, MB_WRITE_COMMITTED);
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
- if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_pulse_status, lane_phy_pulse_status,
- 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
+ if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_pulse_status, lane_phy_pulse_status,
+ XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 3cc89048b027..dc44a7a169c1 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -462,9 +462,9 @@ static void intel_pmdemand_poll(struct intel_display *display)
u32 status;
int ret;
- ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
- XELPDP_PMDEMAND_REQ_ENABLE, 0,
- 2, timeout_ms, &status);
+ ret = intel_de_wait_ms(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ XELPDP_PMDEMAND_REQ_ENABLE, 0,
+ timeout_ms, &status);
if (ret == -ETIMEDOUT)
drm_err(display->drm,
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (5 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:33 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us() Ville Syrjala
` (12 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_de_wait_custom() is finally unused. Get rid of it
before people start abusing it more.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 43a4160f760a..2566079f695e 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -165,25 +165,6 @@ intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
return ret;
}
-static inline int
-intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value,
- unsigned int fast_timeout_us,
- unsigned int slow_timeout_ms, u32 *out_value)
-{
- int ret;
-
- intel_dmc_wl_get(display, reg);
-
- ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
- value,
- fast_timeout_us, slow_timeout_ms, out_value);
-
- intel_dmc_wl_put(display, reg);
-
- return ret;
-}
-
static inline int
intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (6 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:35 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us() Ville Syrjala
` (11 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add intel_de_wait_for_set_us() and intel_de_wait_for_clear_us()
as the microsecond counterparts to intel_de_wait_for_set_ms()
and intel_de_wait_for_clear_ms().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 2566079f695e..a82da6443af9 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -165,6 +165,20 @@ intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
return ret;
}
+static inline int
+intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
+ u32 mask, unsigned int timeout_us)
+{
+ return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
+}
+
+static inline int
+intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
+ u32 mask, unsigned int timeout_us)
+{
+ return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
+}
+
static inline int
intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (7 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:38 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_us() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Ville Syrjala
` (10 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_de_wait_for_{set,clear}_us() instead of
intel_de_wait_us() where appropriate.
Done with cocci (with manual formatting fixes):
@@
identifier func !~ "intel_de_wait_for";
expression display, reg, mask, timeout_us;
@@
func(...)
{
<...
(
- intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL)
+ intel_de_wait_for_set_us(display, reg, mask, timeout_us)
|
- intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL)
+ intel_de_wait_for_clear_us(display, reg, mask, timeout_us)
)
...>
}
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 29 +++++++++----------
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
.../drm/i915/display/intel_display_power.c | 9 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 +++++-----
drivers/gpu/drm/i915/display/intel_lt_phy.c | 18 ++++++------
.../gpu/drm/i915/display/intel_pch_refclk.c | 9 +++---
8 files changed, 57 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 151266ffd582..9230792960f2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -148,8 +148,9 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
- LPTX_IN_PROGRESS, 0, 20, NULL);
+ ret = intel_de_wait_for_clear_us(display,
+ DSI_LP_MSG(dsi_trans),
+ LPTX_IN_PROGRESS, 20);
if (ret)
drm_err(display->drm, "LPTX bit not cleared\n");
}
@@ -533,8 +534,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
- ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
- DDI_BUF_IS_IDLE, 0, 500, NULL);
+ ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
+ DDI_BUF_IS_IDLE, 500);
if (ret)
drm_err(display->drm, "DDI port:%c buffer idle\n",
port_name(port));
@@ -855,9 +856,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
- ret = intel_de_wait_us(display,
- DSI_TRANS_FUNC_CONF(dsi_trans),
- LINK_READY, LINK_READY, 2500, NULL);
+ ret = intel_de_wait_for_set_us(display,
+ DSI_TRANS_FUNC_CONF(dsi_trans),
+ LINK_READY, 2500);
if (ret)
drm_err(display->drm, "DSI link not ready\n");
}
@@ -1356,8 +1357,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
tmp &= ~LINK_ULPS_TYPE_LP11;
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
- ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
- LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
+ ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),
+ LINK_IN_ULPS, 10);
if (ret)
drm_err(display->drm, "DSI link not in ULPS\n");
}
@@ -1392,9 +1393,8 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
- ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
- DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
- NULL);
+ ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
+ DDI_BUF_IS_IDLE, 8);
if (ret)
drm_err(display->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7daebccb10f..37801c744b05 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -902,8 +902,8 @@ static void bdw_set_cdclk(struct intel_display *display,
* According to the spec, it should be enough to poll for this 1 us.
* However, extensive testing shows that this can take longer.
*/
- ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
- LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
+ ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE, 100);
if (ret)
drm_err(display->drm, "Switching to FCLK failed\n");
@@ -913,8 +913,8 @@ static void bdw_set_cdclk(struct intel_display *display,
intel_de_rmw(display, LCPLL_CTL,
LCPLL_CD_SOURCE_FCLK, 0);
- ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
- 0, 1, NULL);
+ ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE, 1);
if (ret)
drm_err(display->drm, "Switching back to LCPLL failed\n");
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 55fd95994ea7..68e9009d2556 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2887,10 +2887,9 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
- XELPDP_PORT_BUF_SOC_PHY_READY,
- XELPDP_PORT_BUF_SOC_PHY_READY,
- XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, NULL))
+ if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL1(display, port),
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US))
drm_warn(display->drm,
"PHY %c failed to bring out of SOC reset\n",
phy_name(phy));
@@ -2898,9 +2897,9 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
lane_pipe_reset);
- if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status, lane_phy_current_status,
- XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
+ if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status,
+ XELPDP_PORT_RESET_START_TIMEOUT_US))
drm_warn(display->drm,
"PHY %c failed to bring out of lane reset\n",
phy_name(phy));
@@ -3187,8 +3186,8 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK, 100, NULL))
+ if (intel_de_wait_for_set_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ XELPDP_TBT_CLOCK_ACK, 100))
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -3299,10 +3298,10 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
- intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
- XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
+ if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
+ XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US))
drm_warn(display->drm, "Port %c PLL not unlocked\n",
phy_name(phy));
@@ -3347,8 +3346,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
- XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
+ if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ XELPDP_TBT_CLOCK_ACK, 10))
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3b2d2b51ebc6..002ccd47856d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2577,7 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
intel_de_rmw(display, reg, 0, set_bits);
- ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
+ ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);
if (ret) {
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
@@ -3077,7 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder)
intel_de_rmw(display, reg, clr_bits, 0);
- ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
+ ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);
if (ret)
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cc701f8277b6..2a4cc1dcc293 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1292,9 +1292,8 @@ static void hsw_disable_lcpll(struct intel_display *display,
val |= LCPLL_CD_SOURCE_FCLK;
intel_de_write(display, LCPLL_CTL, val);
- ret = intel_de_wait_us(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE,
- LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
+ ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE, 1);
if (ret)
drm_err(display->drm, "Switching to FCLK failed\n");
@@ -1368,8 +1367,8 @@ static void hsw_restore_lcpll(struct intel_display *display)
if (val & LCPLL_CD_SOURCE_FCLK) {
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
- ret = intel_de_wait_us(display, LCPLL_CTL,
- LCPLL_CD_SOURCE_FCLK_DONE, 0, 1, NULL);
+ ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
+ LCPLL_CD_SOURCE_FCLK_DONE, 1);
if (ret)
drm_err(display->drm,
"Switching back to LCPLL failed\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1cc1a862c50b..9c7cf03cf022 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
0, PORT_PLL_POWER_ENABLE);
- ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_POWER_STATE,
- PORT_PLL_POWER_STATE, 200, NULL);
+ ret = intel_de_wait_for_set_us(display,
+ BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_POWER_STATE, 200);
if (ret)
drm_err(display->drm,
"Power state not set for PLL:%d\n", port);
@@ -2122,8 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
+ ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_LOCK, 200);
if (ret)
drm_err(display->drm, "PLL %d not locked\n", port);
@@ -2157,8 +2157,9 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
PORT_PLL_POWER_ENABLE, 0);
- ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
- PORT_PLL_POWER_STATE, 0, 200, NULL);
+ ret = intel_de_wait_for_clear_us(display,
+ BXT_PORT_PLL_ENABLE(port),
+ PORT_PLL_POWER_STATE, 200);
if (ret)
drm_err(display->drm,
"Power state not reset for PLL:%d\n", port);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index ac6f61107528..ac6ff183bc97 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1981,9 +1981,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
- if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), 0,
- XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
+ if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
@@ -2087,9 +2087,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
lane_pipe_reset);
/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
- if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status, lane_phy_current_status,
- XE3PLPD_RESET_START_LATENCY_US, NULL))
+ if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status,
+ XE3PLPD_RESET_START_LATENCY_US))
drm_warn(display->drm, "PHY %c failed to reset lane\n",
phy_name(phy));
@@ -2110,9 +2110,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
- if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), 0,
- XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
+ if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index ebf2d1c34b3e..9a89bb6dcf65 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -21,16 +21,15 @@ static void lpt_fdi_reset_mphy(struct intel_display *display)
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
- ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
- FDI_MPHY_IOSFSB_RESET_STATUS,
- FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
+ ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2,
+ FDI_MPHY_IOSFSB_RESET_STATUS, 100);
if (ret)
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
- ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
- FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
+ ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2,
+ FDI_MPHY_IOSFSB_RESET_STATUS, 100);
if (ret)
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
}
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (8 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:39 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_ms() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms() Ville Syrjala
` (9 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_de_wait_for_{set,clear}_ms() instead of
intel_de_wait_ms() where appropriate.
Done with cocci (with manual formatting fixes):
@@
identifier func !~ "intel_de_wait_for";
expression display, reg, mask, timeout_ms;
@@
func(...)
{
<...
(
- intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL)
+ intel_de_wait_for_set_ms(display, reg, mask, timeout_ms)
|
- intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL)
+ intel_de_wait_for_clear_ms(display, reg, mask, timeout_ms)
)
...>
}
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++--
drivers/gpu/drm/i915/display/intel_lt_phy.c | 30 ++++++++++----------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 68e9009d2556..d98b4cf6b60e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2826,9 +2826,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (intel_de_wait_ms(display, buf_ctl2_reg,
- intel_cx0_get_powerdown_update(lane_mask), 0,
- XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
+ if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg,
+ intel_cx0_get_powerdown_update(lane_mask),
+ XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS))
drm_warn(display->drm,
"PHY %c failed to bring out of lane reset\n",
phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index ac6ff183bc97..bebd7488aab9 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1201,9 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0),
XELPDP_LANE_PCLK_PLL_REQUEST(0));
- if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
- XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+ if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNON_LATENCY_MS))
drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
phy_name(phy));
@@ -1214,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_pipe_reset | lane_phy_pulse_status, 0);
- if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_current_status, 0,
- XE3PLPD_RESET_END_LATENCY_MS, NULL))
+ if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_current_status,
+ XE3PLPD_RESET_END_LATENCY_MS))
drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
phy_name(phy));
- if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_pulse_status, lane_phy_pulse_status,
- XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
+ if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_pulse_status,
+ XE3PLPD_RATE_CALIB_DONE_LATENCY_MS))
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
@@ -2001,9 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_REQUEST(0));
/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
- if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
- XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
- XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+ if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
+ XELPDP_LANE_PCLK_PLL_ACK(0),
+ XE3PLPD_MACCLK_TURNON_LATENCY_MS))
drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
phy_name(phy));
@@ -2029,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
rate_update, MB_WRITE_COMMITTED);
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
- if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
- lane_phy_pulse_status, lane_phy_pulse_status,
- XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
+ if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
+ lane_phy_pulse_status,
+ XE3PLPD_RATE_CALIB_DONE_LATENCY_MS))
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (9 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:41 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw() Ville Syrjala
` (8 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
_bxt_dpio_phy_init() doesn't us the _fw() register accessors
for anything else, so stop using them for the register polling
as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 4d1b6e2b93dc..7b7a0461da36 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -427,8 +427,8 @@ static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
* The flag should get set in 100us according to the HW team, but
* use 1ms due to occasional timeouts observed with that.
*/
- if (intel_de_wait_fw_ms(display, BXT_PORT_CL1CM_DW0(phy),
- PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL))
+ if (intel_de_wait_ms(display, BXT_PORT_CL1CM_DW0(phy),
+ PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL))
drm_err(display->drm, "timeout during PHY%d power on\n",
phy);
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (10 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:44 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms() Ville Syrjala
` (7 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have the lower level intel_de_*_fw() stuff, so use
that instead of hand rolling something custom for the DMC
wakelock stuff.
As the wakelock stuff exists only on platforms supported
by the xe driver this doesn't even result in any functional
changes since xe doesn't have uncore.lock nor unclaimed
register access detection.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 21 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 11 +++++------
2 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index a82da6443af9..345b27ada04f 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -83,13 +83,6 @@ intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
intel_dmc_wl_put(display, reg);
}
-static inline u32
-__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
- u32 clear, u32 set)
-{
- return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
-}
-
static inline u32
intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
{
@@ -97,7 +90,7 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
intel_dmc_wl_get(display, reg);
- val = __intel_de_rmw_nowl(display, reg, clear, set);
+ val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
intel_dmc_wl_put(display, reg);
@@ -219,6 +212,18 @@ intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
intel_uncore_write_fw(__to_uncore(display), reg, val);
}
+static inline u32
+intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
+{
+ u32 old, val;
+
+ old = intel_de_read_fw(display, reg);
+ val = (old & ~clear) | set;
+ intel_de_write_fw(display, reg, val);
+
+ return old;
+}
+
static inline u32
intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index b3bb89ba34f9..869beb6f280d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -179,7 +179,7 @@ static void intel_dmc_wl_work(struct work_struct *work)
if (refcount_read(&wl->refcount))
goto out_unlock;
- __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
+ intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL,
DMC_WAKELOCK_CTL_ACK, 0,
@@ -207,8 +207,7 @@ static void __intel_dmc_wl_take(struct intel_display *display)
if (wl->taken)
return;
- __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0,
- DMC_WAKELOCK_CTL_REQ);
+ intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, 0, DMC_WAKELOCK_CTL_REQ);
/*
* We need to use the atomic variant of the waiting routine
@@ -360,7 +359,7 @@ void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)
* wakelock, because we're just enabling it, so call the
* non-locking version directly here.
*/
- __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);
+ intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);
wl->enabled = true;
@@ -402,7 +401,7 @@ void intel_dmc_wl_disable(struct intel_display *display)
goto out_unlock;
/* Disable wakelock in DMC */
- __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);
+ intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);
wl->enabled = false;
@@ -414,7 +413,7 @@ void intel_dmc_wl_disable(struct intel_display *display)
*
* TODO: Get the correct expectation from the hardware team.
*/
- __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
+ intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
wl->taken = false;
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (11 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:45 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic() Ville Syrjala
` (6 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The low level _fw() register accessors aren't supposed to
grab the wakelock. Stop doing so in intel_de_wait_fw_ms().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 345b27ada04f..655867ea76b8 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -146,16 +146,8 @@ intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
u32 *out_value)
{
- int ret;
-
- intel_dmc_wl_get(display, reg);
-
- ret = __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
- value, 2, timeout_ms, out_value);
-
- intel_dmc_wl_put(display, reg);
-
- return ret;
+ return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
+ value, 2, timeout_ms, out_value);
}
static inline int
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic()
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (12 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:46 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value Ville Syrjala
` (5 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Nuke the remaining _nowl() stuff from the wakelock code in the
form of __intel_de_wait_for_register_nowl(), and replace it with
intel_de_wait_fw_us_atomic() that uses the low level _fw() register
accessors on line with the rest of the code.
No change in behaviour since wakelocks are only supported on xe,
and xe doesn't have uncore.lock nor unclaimed register detection
stuff.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 19 +++++++++----------
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 14 +++++++-------
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 655867ea76b8..a7ce3b875e06 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -97,16 +97,6 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
return val;
}
-static inline int
-__intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
- i915_reg_t reg,
- u32 mask, u32 value,
- unsigned int fast_timeout_us)
-{
- return __intel_wait_for_register(__to_uncore(display), reg, mask,
- value, fast_timeout_us, 0, NULL);
-}
-
static inline int
intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout_us,
@@ -150,6 +140,15 @@ intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
value, 2, timeout_ms, out_value);
}
+static inline int
+intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout_us,
+ u32 *out_value)
+{
+ return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
+ value, timeout_us, 0, out_value);
+}
+
static inline int
intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_us)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 869beb6f280d..73a3101514f3 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -181,9 +181,9 @@ static void intel_dmc_wl_work(struct work_struct *work)
intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
- if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL,
- DMC_WAKELOCK_CTL_ACK, 0,
- DMC_WAKELOCK_CTL_TIMEOUT_US)) {
+ if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
+ DMC_WAKELOCK_CTL_ACK, 0,
+ DMC_WAKELOCK_CTL_TIMEOUT_US, NULL)) {
WARN_RATELIMIT(1, "DMC wakelock release timed out");
goto out_unlock;
}
@@ -213,10 +213,10 @@ static void __intel_dmc_wl_take(struct intel_display *display)
* We need to use the atomic variant of the waiting routine
* because the DMC wakelock is also taken in atomic context.
*/
- if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL,
- DMC_WAKELOCK_CTL_ACK,
- DMC_WAKELOCK_CTL_ACK,
- DMC_WAKELOCK_CTL_TIMEOUT_US)) {
+ if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
+ DMC_WAKELOCK_CTL_ACK,
+ DMC_WAKELOCK_CTL_ACK,
+ DMC_WAKELOCK_CTL_TIMEOUT_US, NULL)) {
WARN_RATELIMIT(1, "DMC wakelock ack timed out");
return;
}
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (13 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic() Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:48 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 16/16] drm/i915/dpio: " Ville Syrjala
` (4 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Utilize the 'out_value' output parameter of intel_de_wait_ms()
isntead of re-readiong the PHY_CONTROL register after polling
has finished.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power_well.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8593d2daeaa6..f4f7e73acc87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1358,6 +1358,7 @@ static void assert_chv_phy_status(struct intel_display *display)
u32 phy_control = display->power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
+ u32 val;
/*
* The BIOS can leave the PHY is some weird state
@@ -1446,11 +1447,10 @@ static void assert_chv_phy_status(struct intel_display *display)
* so the power state can take a while to actually change.
*/
if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
- phy_status_mask, phy_status, 10, NULL))
+ phy_status_mask, phy_status, 10, &val))
drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
- intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, display->power.chv_phy_control);
+ val & phy_status_mask, phy_status, display->power.chv_phy_control);
}
#undef BITS_SET
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 16/16] drm/i915/dpio: Use the intel_de_wait_ms() out value
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (14 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value Ville Syrjala
@ 2025-11-10 17:27 ` Ville Syrjala
2025-11-11 4:50 ` Kandpal, Suraj
2025-11-10 21:24 ` ✓ i915.CI.BAT: success for drm/i915/de: Register polling cleanup Patchwork
` (3 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2025-11-10 17:27 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Utilize the 'out_value' output parameter of intel_de_wait_ms()
isntead of re-readiong the DPLL/DPIO_PHY_STATUS register after
polling has finished.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 7b7a0461da36..8027bab2951b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1173,6 +1173,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
struct intel_display *display = to_intel_display(encoder);
u32 port_mask;
i915_reg_t dpll_reg;
+ u32 val;
switch (encoder->port) {
default:
@@ -1193,10 +1194,9 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
break;
}
- if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, NULL))
+ if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, &val))
drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
encoder->base.base.id, encoder->base.name,
- intel_de_read(display, dpll_reg) & port_mask,
- expected_mask);
+ val & port_mask, expected_mask);
}
--
2.49.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/de: Register polling cleanup
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (15 preceding siblings ...)
2025-11-10 17:27 ` [PATCH 16/16] drm/i915/dpio: " Ville Syrjala
@ 2025-11-10 21:24 ` Patchwork
2025-11-11 3:41 ` ✗ i915.CI.Full: failure " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2025-11-10 21:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3593 bytes --]
== Series Details ==
Series: drm/i915/de: Register polling cleanup
URL : https://patchwork.freedesktop.org/series/157342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_17525 -> Patchwork_157342v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/index.html
Participating hosts (45 -> 44)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_157342v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live:
- bat-dg2-8: [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-dg2-8/igt@i915_selftest@live.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-dg2-8/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-mtlp-9: [DMESG-WARN][5] ([i915#13494]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-mtlp-9/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-mtlp-9/igt@i915_module_load@load.html
* igt@i915_selftest@live:
- bat-adlp-11: [DMESG-WARN][7] ([i915#14872]) -> [PASS][8] +1 other test pass
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-adlp-11/igt@i915_selftest@live.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-adlp-11/igt@i915_selftest@live.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-atsm-1: [DMESG-FAIL][9] ([i915#12061] / [i915#14204]) -> [DMESG-FAIL][10] ([i915#12061] / [i915#13929])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-atsm-1/igt@i915_selftest@live.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-atsm-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@mman:
- bat-atsm-1: [DMESG-FAIL][11] ([i915#14204]) -> [DMESG-FAIL][12] ([i915#13929])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/bat-atsm-1/igt@i915_selftest@live@mman.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/bat-atsm-1/igt@i915_selftest@live@mman.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
[i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
[i915#14872]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14872
Build changes
-------------
* Linux: CI_DRM_17525 -> Patchwork_157342v1
CI-20190529: 20190529
CI_DRM_17525: a9792b1ab75123e4aceaba953a89809e745919c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8617: 8617
Patchwork_157342v1: a9792b1ab75123e4aceaba953a89809e745919c6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/index.html
[-- Attachment #2: Type: text/html, Size: 4707 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915/de: Register polling cleanup
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (16 preceding siblings ...)
2025-11-10 21:24 ` ✓ i915.CI.BAT: success for drm/i915/de: Register polling cleanup Patchwork
@ 2025-11-11 3:41 ` Patchwork
2025-11-11 8:01 ` [PATCH 00/16] " Jani Nikula
2025-11-11 19:09 ` Ville Syrjälä
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2025-11-11 3:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 154215 bytes --]
== Series Details ==
Series: drm/i915/de: Register polling cleanup
URL : https://patchwork.freedesktop.org/series/157342/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_17525_full -> Patchwork_157342v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_157342v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_157342v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_157342v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][1] -> [FAIL][2] +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-tglu-7/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
Known issues
------------
Here are the changes found in Patchwork_157342v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg1: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@crc32:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#6230])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@api_intel_bb@crc32.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#11078])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_buddy@drm_buddy:
- shard-glk: NOTRUN -> [DMESG-WARN][6] ([i915#15095]) +1 other test dmesg-warn
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@drm_buddy@drm_buddy.html
* igt@gem_basic@multigpu-create-close:
- shard-tglu: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@large-ctrl-surf-copy:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#13008])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@gem_ccs@large-ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#9323])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#14544] / [i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#8555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#8555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@legacy-engines-hang:
- shard-snb: NOTRUN -> [SKIP][16] ([i915#1099])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hang.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#280])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#4036])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#6344])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-concurrent16:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#14544] / [i915#3281])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_exec_reloc@basic-concurrent16.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#3281])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#3281]) +5 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_exec_reloc@basic-wc-read:
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#3281]) +5 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@gem_exec_reloc@basic-wc-read.html
* igt@gem_exec_reloc@basic-write-read:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3281])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg1: NOTRUN -> [SKIP][27] ([i915#4812]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#7276])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_schedule@smoketest@vcs0:
- shard-rkl: [PASS][29] -> [DMESG-WARN][30] ([i915#12964]) +9 other tests dmesg-warn
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_exec_schedule@smoketest@vcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_exec_schedule@smoketest@vcs0.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#4860]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#4613] / [i915#7582])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][33] ([i915#4613]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
- shard-glk: NOTRUN -> [SKIP][34] ([i915#4613]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-tglu-1: NOTRUN -> [SKIP][35] ([i915#4613]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: NOTRUN -> [TIMEOUT][36] ([i915#5493]) +1 other test timeout
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#4613]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_mmap@bad-object:
- shard-dg1: NOTRUN -> [SKIP][38] ([i915#4083]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@basic:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4077]) +7 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@basic-copy:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4077]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_mmap_gtt@basic-copy.html
* igt@gem_mmap_wc@coherency:
- shard-mtlp: NOTRUN -> [SKIP][41] ([i915#4083])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_mmap_wc@coherency.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#4083])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@reads:
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#14544] / [i915#3282])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3282])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_partial_pwrite_pread@write.html
* igt@gem_pread@exhaustion:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#3282]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3282]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_pread@snoop.html
* igt@gem_pwrite@basic-self:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#3282])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_pwrite@basic-self.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4270]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-rkl: NOTRUN -> [TIMEOUT][49] ([i915#12917] / [i915#12964])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-rkl: [PASS][50] -> [TIMEOUT][51] ([i915#12917] / [i915#12964])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-8/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#4270]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-rkl: NOTRUN -> [SKIP][53] ([i915#4270])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#5190] / [i915#8428]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#8428])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_softpin@evict-snoop:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#4885])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@access-control:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#3297])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglu-1: NOTRUN -> [SKIP][60] ([i915#3297] / [i915#3323])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#3297])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#3297]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@suspend-resume:
- shard-rkl: [PASS][63] -> [INCOMPLETE][64] ([i915#13356])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_workarounds@suspend-resume.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_workarounds@suspend-resume.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-rkl: [PASS][65] -> [ABORT][66] ([i915#15152])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-8/igt@gem_workarounds@suspend-resume-fd.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-4/igt@gem_workarounds@suspend-resume-fd.html
- shard-glk: NOTRUN -> [INCOMPLETE][67] ([i915#13356] / [i915#14586])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk6/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-mtlp: NOTRUN -> [SKIP][68] +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#2856])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#14544] / [i915#2527])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-start-out:
- shard-tglu-1: NOTRUN -> [SKIP][71] ([i915#2527] / [i915#2856])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#2527]) +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#2527]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-dg1: ([PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97]) -> ([PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [SKIP][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121]) ([i915#14785])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@i915_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-12/igt@i915_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-18/igt@i915_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-12/igt@i915_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-18/igt@i915_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-19/igt@i915_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@i915_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-18/igt@i915_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-16/igt@i915_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@i915_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-17/igt@i915_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-13/igt@i915_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-16/igt@i915_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-16/igt@i915_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-12/igt@i915_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@i915_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@i915_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-19/igt@i915_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@i915_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-13/igt@i915_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-17/igt@i915_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-13/igt@i915_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-19/igt@i915_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-17/igt@i915_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@i915_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@i915_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@i915_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-13/igt@i915_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-13/igt@i915_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-13/igt@i915_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-13/igt@i915_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-14/igt@i915_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-14/igt@i915_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-15/igt@i915_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-15/igt@i915_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-15/igt@i915_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@i915_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@i915_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@i915_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@i915_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@i915_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@i915_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-18/igt@i915_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-18/igt@i915_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-18/igt@i915_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-19/igt@i915_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-19/igt@i915_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-19/igt@i915_module_load@load.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#14544] / [i915#8399])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglu-1: NOTRUN -> [WARN][123] ([i915#13790] / [i915#2681]) +1 other test warn
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@system-suspend:
- shard-rkl: [PASS][124] -> [ABORT][125] ([i915#15060])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-8/igt@i915_pm_rpm@system-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-4/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#11681])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#11681])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@i915_pm_rps@thresholds-park.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#7984])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@i915_power@sanity.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#4215])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_async_flips@async-flip-suspend-resume:
- shard-glk10: NOTRUN -> [INCOMPLETE][130] ([i915#12761]) +1 other test incomplete
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk10/igt@kms_async_flips@async-flip-suspend-resume.html
- shard-rkl: [PASS][131] -> [INCOMPLETE][132] ([i915#12761]) +1 other test incomplete
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_async_flips@async-flip-suspend-resume.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#9531])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-tglu: [PASS][134] -> [FAIL][135] ([i915#14857]) +1 other test fail
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-tglu-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-tglu-1: NOTRUN -> [SKIP][136] ([i915#1769] / [i915#3555])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#5286]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][138] ([i915#5286])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#4538] / [i915#5286]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-tglu-1: NOTRUN -> [SKIP][140] ([i915#5286])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][141] +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][142] ([i915#3638]) +2 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#4538] / [i915#5190]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#3638]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][145] +9 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#4538]) +1 other test skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#6095]) +19 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-c-edp-1.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][148] ([i915#6095]) +46 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][149] ([i915#6095]) +19 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#10307] / [i915#6095]) +154 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-11/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#14098] / [i915#6095]) +58 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
- shard-rkl: [PASS][152] -> [SKIP][153] ([i915#14544]) +35 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#12805])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#12805])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][156] ([i915#6095]) +9 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#6095]) +11 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-7/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#12313])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][159] ([i915#12313])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg1: NOTRUN -> [SKIP][161] ([i915#12313])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#6095]) +168 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#13783]) +3 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#11151] / [i915#7828]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#11151] / [i915#7828])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#11151] / [i915#14544] / [i915#7828]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-tglu-1: NOTRUN -> [SKIP][167] ([i915#11151] / [i915#7828]) +1 other test skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#11151] / [i915#7828]) +6 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#11151] / [i915#7828])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#11151] / [i915#7828]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_color@ctm-signed:
- shard-rkl: [PASS][171] -> [SKIP][172] ([i915#12655] / [i915#14544])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_color@ctm-signed.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_color@ctm-signed.html
* igt@kms_content_protection@atomic:
- shard-dg1: NOTRUN -> [SKIP][173] ([i915#7116] / [i915#9424])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_content_protection@atomic.html
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#7118] / [i915#9424])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][175] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#3299])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [FAIL][177] ([i915#7173])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-11/igt@kms_content_protection@lic-type-0@pipe-a-dp-3.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#13049])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][179] ([i915#13566]) +2 other tests fail
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][180] ([i915#3555])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#13049])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x128:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#14544]) +22 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-128x128.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#13049])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#13049]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#13046] / [i915#5354])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#4103])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: NOTRUN -> [FAIL][187] ([i915#2346])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3804])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#3555]) +4 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#13749])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#13748])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#3840] / [i915#9053])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#3840] / [i915#9053])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk10: NOTRUN -> [INCOMPLETE][194] ([i915#9878])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk10/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-tglu-1: NOTRUN -> [SKIP][195] ([i915#2065] / [i915#4854])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#1839])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#3637] / [i915#9934]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-tglu: NOTRUN -> [SKIP][198] ([i915#9934])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#9934]) +3 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-glk: NOTRUN -> [INCOMPLETE][200] ([i915#12745] / [i915#4839])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [INCOMPLETE][201] ([i915#4839])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#9934]) +3 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][203] ([i915#3637] / [i915#9934]) +1 other test skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#14544] / [i915#9934]) +1 other test skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#8381])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-rkl: [PASS][206] -> [SKIP][207] ([i915#14544] / [i915#3637]) +5 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_flip@flip-vs-panning-interruptible.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_flip@flip-vs-panning-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-glk: NOTRUN -> [INCOMPLETE][208] ([i915#12745] / [i915#4839] / [i915#6113])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk1/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-dg2: [PASS][209] -> [INCOMPLETE][210] ([i915#12314] / [i915#12745] / [i915#4839] / [i915#6113])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-3/igt@kms_flip@flip-vs-suspend-interruptible.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
- shard-glk: NOTRUN -> [INCOMPLETE][211] ([i915#12745])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk1/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp3:
- shard-dg2: NOTRUN -> [INCOMPLETE][212] ([i915#12314] / [i915#6113])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_flip@flip-vs-suspend-interruptible@c-dp3.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][213] ([i915#2672] / [i915#3555])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][214] ([i915#2587] / [i915#2672])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#2587] / [i915#2672] / [i915#3555])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#2672] / [i915#3555])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][217] ([i915#2672] / [i915#3555])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][218] ([i915#2672])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#14544] / [i915#3555]) +1 other test skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#2672] / [i915#3555])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#2672]) +4 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][222] ([i915#2587] / [i915#2672]) +1 other test skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-mtlp: NOTRUN -> [SKIP][223] ([i915#2672] / [i915#3555] / [i915#8813])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][224] ([i915#2672] / [i915#8813])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-rkl: [PASS][225] -> [SKIP][226] ([i915#14544] / [i915#1849] / [i915#5354]) +5 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][227] ([i915#1825]) +4 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
- shard-tglu: NOTRUN -> [SKIP][228] +12 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-glk10: NOTRUN -> [SKIP][229] +52 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][230] +24 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#8708]) +5 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#8708]) +2 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][233] ([i915#14544] / [i915#1849] / [i915#5354]) +7 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move:
- shard-tglu-1: NOTRUN -> [SKIP][234] +9 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][235] ([i915#15102] / [i915#3458]) +13 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#15102] / [i915#3458]) +3 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][237] ([i915#15104])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][238] ([i915#15102])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][239] ([i915#8708]) +2 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglu-1: NOTRUN -> [SKIP][240] ([i915#15102]) +5 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#5354]) +3 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][242] ([i915#1825]) +17 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-tglu: NOTRUN -> [SKIP][243] ([i915#15102]) +6 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][244] ([i915#15102] / [i915#3023]) +11 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: [PASS][245] -> [SKIP][246] ([i915#3555] / [i915#8228])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-11/igt@kms_hdr@bpc-switch.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-7/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][247] ([i915#3555] / [i915#8228])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8228])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_hdr@static-toggle.html
- shard-dg1: NOTRUN -> [SKIP][249] ([i915#3555] / [i915#8228])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-dg1: NOTRUN -> [SKIP][250] ([i915#12394])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#13688])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][252] ([i915#10656])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- shard-rkl: [PASS][253] -> [SKIP][254] ([i915#11190] / [i915#14544]) +1 other test skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_pipe_crc_basic@hang-read-crc.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- shard-dg2: NOTRUN -> [ABORT][255] ([i915#15070] / [i915#15132]) +1 other test abort
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_plane@plane-position-hole:
- shard-rkl: [PASS][256] -> [SKIP][257] ([i915#14544] / [i915#8825]) +1 other test skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane@plane-position-hole.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane@plane-position-hole.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][258] ([i915#10647] / [i915#12169]) +1 other test fail
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk6/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb:
- shard-snb: NOTRUN -> [SKIP][259] +4 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-snb7/igt@kms_plane_alpha_blend@alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][260] ([i915#10647]) +3 other tests fail
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html
* igt@kms_plane_alpha_blend@constant-alpha-min:
- shard-rkl: [PASS][261] -> [SKIP][262] ([i915#14544] / [i915#7294])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_alpha_blend@constant-alpha-min.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_alpha_blend@constant-alpha-min.html
* igt@kms_plane_lowres@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#3555] / [i915#8821])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][264] ([i915#13958])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-tglu: NOTRUN -> [SKIP][265] ([i915#13958])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-tglu-1: NOTRUN -> [SKIP][266] ([i915#13958])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][267] ([i915#12247]) +4 other tests skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
- shard-rkl: NOTRUN -> [SKIP][268] ([i915#14544] / [i915#8152])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format:
- shard-rkl: [PASS][269] -> [SKIP][270] ([i915#14544] / [i915#8152])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a:
- shard-rkl: [PASS][271] -> [SKIP][272] ([i915#12247] / [i915#14544]) +2 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b:
- shard-rkl: [PASS][273] -> [SKIP][274] ([i915#12247] / [i915#14544] / [i915#8152]) +2 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#12247]) +4 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
- shard-dg1: NOTRUN -> [SKIP][276] ([i915#12247]) +4 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation:
- shard-glk: NOTRUN -> [SKIP][277] +270 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format:
- shard-dg1: [PASS][278] -> [DMESG-WARN][279] ([i915#4423]) +6 other tests dmesg-warn
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@planes-scaler-unity-scaling:
- shard-rkl: [PASS][280] -> [SKIP][281] ([i915#14544] / [i915#3555] / [i915#8152])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_scaling@planes-scaler-unity-scaling.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@planes-scaler-unity-scaling.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75:
- shard-rkl: NOTRUN -> [SKIP][282] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][283] ([i915#12247] / [i915#14544]) +1 other test skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b:
- shard-rkl: NOTRUN -> [SKIP][284] ([i915#12247] / [i915#14544] / [i915#8152]) +1 other test skip
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-rkl: [PASS][285] -> [SKIP][286] ([i915#14544] / [i915#6953] / [i915#8152])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20.html
* igt@kms_pm_dc@dc5-dpms-negative:
- shard-rkl: [PASS][287] -> [SKIP][288] ([i915#13441] / [i915#14544])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_pm_dc@dc5-dpms-negative.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_pm_dc@dc5-dpms-negative.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [PASS][289] -> [SKIP][290] ([i915#14544] / [i915#15073])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg1: NOTRUN -> [SKIP][291] ([i915#15073])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@fences:
- shard-dg1: NOTRUN -> [SKIP][292] ([i915#4077]) +6 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_pm_rpm@fences.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [PASS][293] -> [SKIP][294] ([i915#15073]) +2 other tests skip
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][295] ([i915#6524] / [i915#6805])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
- shard-rkl: NOTRUN -> [SKIP][296] ([i915#11520]) +3 other tests skip
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][297] ([i915#11520])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][298] ([i915#11520]) +1 other test skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-mtlp: NOTRUN -> [SKIP][299] ([i915#12316]) +1 other test skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][300] ([i915#9808])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][301] ([i915#11520]) +4 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-tglu: NOTRUN -> [SKIP][302] ([i915#11520]) +1 other test skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-glk10: NOTRUN -> [SKIP][303] ([i915#11520])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk10/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][304] ([i915#11520]) +6 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk1/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-tglu-1: NOTRUN -> [SKIP][305] ([i915#9683])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][306] ([i915#9683])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr-primary-blt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][307] ([i915#9688]) +4 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_psr@fbc-psr-primary-blt@edp-1.html
* igt@kms_psr@fbc-psr2-sprite-blt:
- shard-dg2: NOTRUN -> [SKIP][308] ([i915#1072] / [i915#9732]) +4 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_psr@fbc-psr2-sprite-blt.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-tglu-1: NOTRUN -> [SKIP][309] ([i915#9732]) +3 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@pr-primary-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][310] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_psr@pr-primary-mmap-gtt.html
* igt@kms_psr@pr-sprite-plane-onoff:
- shard-dg1: NOTRUN -> [SKIP][311] ([i915#1072] / [i915#9732]) +11 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_psr@pr-sprite-plane-onoff.html
* igt@kms_psr@psr2-primary-render:
- shard-tglu: NOTRUN -> [SKIP][312] ([i915#9732]) +4 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_psr@psr2-primary-render.html
* igt@kms_psr@psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][313] ([i915#1072] / [i915#9732]) +9 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_psr@psr2-suspend.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg1: NOTRUN -> [SKIP][314] ([i915#9685])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu-1: NOTRUN -> [SKIP][315] ([i915#5289])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg1: NOTRUN -> [SKIP][316] ([i915#5289]) +1 other test skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@basic:
- shard-rkl: [PASS][317] -> [SKIP][318] ([i915#14544] / [i915#3555])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_setmode@basic.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-mtlp: [PASS][319] -> [FAIL][320] ([i915#15106]) +2 other tests fail
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-mtlp-3/igt@kms_setmode@basic@pipe-b-edp-1.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-4/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][321] ([i915#3555]) +3 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_sharpness_filter@filter-basic:
- shard-rkl: NOTRUN -> [SKIP][322] ([i915#15232])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_sharpness_filter@filter-basic.html
* igt@kms_sharpness_filter@filter-modifiers:
- shard-mtlp: NOTRUN -> [SKIP][323] ([i915#15232])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@kms_sharpness_filter@filter-modifiers.html
* igt@kms_sharpness_filter@filter-scaler-upscale:
- shard-tglu-1: NOTRUN -> [SKIP][324] ([i915#15232])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_sharpness_filter@filter-scaler-upscale.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu: NOTRUN -> [SKIP][325] ([i915#8623])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [DMESG-WARN][326] ([i915#12964]) +1 other test dmesg-warn
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-2.html
* igt@kms_vrr@flip-suspend:
- shard-rkl: NOTRUN -> [SKIP][327] ([i915#15243] / [i915#3555])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@lobf:
- shard-tglu: NOTRUN -> [SKIP][328] ([i915#11920])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@kms_vrr@lobf.html
* igt@kms_writeback@writeback-check-output:
- shard-tglu-1: NOTRUN -> [SKIP][329] ([i915#2437])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][330] ([i915#2437])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_writeback@writeback-fb-id.html
- shard-dg1: NOTRUN -> [SKIP][331] ([i915#2437])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][332] ([i915#2437]) +1 other test skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk1/igt@kms_writeback@writeback-pixel-formats.html
- shard-dg1: NOTRUN -> [SKIP][333] ([i915#2437] / [i915#9412])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@kms_writeback@writeback-pixel-formats.html
* igt@panthor/panthor_group@group_submit:
- shard-dg1: NOTRUN -> [SKIP][334] ([i915#15265])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@panthor/panthor_group@group_submit.html
* igt@panthor/panthor_vm@vm_bind:
- shard-rkl: NOTRUN -> [SKIP][335] ([i915#15265])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@panthor/panthor_vm@vm_bind.html
* igt@panthor/panthor_vm@vm_unbind:
- shard-tglu: NOTRUN -> [SKIP][336] ([i915#2575])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-7/igt@panthor/panthor_vm@vm_unbind.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][337] ([i915#2434])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-7/igt@perf@mi-rpc.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][338] ([i915#8516])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@perf_pmu@rc6-all-gts.html
* igt@prime_busy@hang:
- shard-rkl: [PASS][339] -> [DMESG-WARN][340] ([i915#12917] / [i915#12964]) +1 other test dmesg-warn
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@prime_busy@hang.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@prime_busy@hang.html
* igt@prime_vgem@basic-read:
- shard-mtlp: NOTRUN -> [SKIP][341] ([i915#3708])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-rkl: NOTRUN -> [SKIP][342] ([i915#3708])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@prime_vgem@coherency-gtt.html
- shard-dg1: NOTRUN -> [SKIP][343] ([i915#3708] / [i915#4077])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-write-hang:
- shard-dg1: NOTRUN -> [SKIP][344] ([i915#3708])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg1: NOTRUN -> [SKIP][345] ([i915#9917]) +1 other test skip
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-17/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-all:
- shard-tglu-1: NOTRUN -> [FAIL][346] ([i915#12910]) +9 other tests fail
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-all.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg1: NOTRUN -> [SKIP][347] ([i915#4818])
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@tools_test@sysfs_l3_parity.html
- shard-dg2: NOTRUN -> [SKIP][348] ([i915#4818])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@fbdev@unaligned-write:
- shard-rkl: [SKIP][349] ([i915#14544] / [i915#2582]) -> [PASS][350] +1 other test pass
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@fbdev@unaligned-write.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@fbdev@unaligned-write.html
* igt@gem_exec_suspend@basic-s3:
- shard-rkl: [INCOMPLETE][351] ([i915#13356]) -> [PASS][352] +1 other test pass
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@gem_exec_suspend@basic-s3.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_offset@clear-via-pagefault:
- shard-mtlp: [ABORT][353] ([i915#14809]) -> [PASS][354] +1 other test pass
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-mtlp-6/igt@gem_mmap_offset@clear-via-pagefault.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-mtlp-6/igt@gem_mmap_offset@clear-via-pagefault.html
* igt@gem_pxp@create-regular-context-2:
- shard-rkl: [TIMEOUT][355] ([i915#12917] / [i915#12964]) -> [PASS][356] +1 other test pass
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-3/igt@gem_pxp@create-regular-context-2.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-rkl: [TIMEOUT][357] ([i915#12964]) -> [PASS][358]
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-rkl: [ABORT][359] ([i915#15140]) -> [PASS][360]
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-4/igt@i915_suspend@fence-restore-tiled2untiled.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait:
- shard-dg1: [DMESG-WARN][361] ([i915#4423]) -> [PASS][362] +9 other tests pass
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-18/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-18/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-dg2: [FAIL][363] ([i915#5956]) -> [PASS][364]
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-3/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_busy@extended-modeset-hang-newfb-with-reset:
- shard-rkl: [SKIP][365] ([i915#14544]) -> [PASS][366] +47 other tests pass
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_busy@extended-modeset-hang-newfb-with-reset.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_busy@extended-modeset-hang-newfb-with-reset.html
* igt@kms_color@ctm-negative:
- shard-rkl: [SKIP][367] ([i915#12655] / [i915#14544]) -> [PASS][368] +3 other tests pass
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_color@ctm-negative.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_color@ctm-negative.html
* igt@kms_cursor_crc@cursor-sliding-64x21:
- shard-glk: [INCOMPLETE][369] ([i915#14152]) -> [PASS][370] +1 other test pass
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-glk6/igt@kms_cursor_crc@cursor-sliding-64x21.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-glk9/igt@kms_cursor_crc@cursor-sliding-64x21.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- shard-rkl: [SKIP][371] ([i915#11190] / [i915#14544]) -> [PASS][372] +1 other test pass
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: [SKIP][373] ([i915#3555]) -> [PASS][374]
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-3/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-10/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-rkl: [SKIP][375] ([i915#14544] / [i915#3637]) -> [PASS][376] +4 other tests pass
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-dpms-on-nop:
- shard-rkl: [SKIP][377] ([i915#14544] / [i915#14553]) -> [PASS][378]
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_flip@flip-vs-dpms-on-nop.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_flip@flip-vs-dpms-on-nop.html
* igt@kms_flip@flip-vs-suspend:
- shard-rkl: [ABORT][379] ([i915#15132]) -> [PASS][380]
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-4/igt@kms_flip@flip-vs-suspend.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
- shard-rkl: [SKIP][381] ([i915#14544] / [i915#3555]) -> [PASS][382]
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-dg2: [ABORT][383] ([i915#15132]) -> [PASS][384]
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-suspend.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-rkl: [SKIP][385] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][386] +8 other tests pass
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_invalid_mode@clock-too-high:
- shard-rkl: [SKIP][387] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][388] +1 other test pass
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_invalid_mode@clock-too-high.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- shard-rkl: [INCOMPLETE][389] ([i915#12756] / [i915#13476]) -> [PASS][390]
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_pipe_crc_basic@suspend-read-crc.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
- shard-rkl: [INCOMPLETE][391] ([i915#13476]) -> [PASS][392]
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html
* igt@kms_plane@plane-position-hole-dpms:
- shard-rkl: [SKIP][393] ([i915#14544] / [i915#8825]) -> [PASS][394] +2 other tests pass
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_plane@plane-position-hole-dpms.html
* igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant:
- shard-rkl: [SKIP][395] ([i915#14544] / [i915#7294]) -> [PASS][396]
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant.html
* igt@kms_plane_scaling@invalid-num-scalers:
- shard-rkl: [SKIP][397] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) -> [PASS][398]
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@invalid-num-scalers.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_scaling@invalid-num-scalers.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-a:
- shard-rkl: [SKIP][399] ([i915#12247] / [i915#14544]) -> [PASS][400] +2 other tests pass
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-a.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25:
- shard-rkl: [SKIP][401] ([i915#14544] / [i915#6953] / [i915#8152]) -> [PASS][402]
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
- shard-rkl: [SKIP][403] ([i915#12247] / [i915#14544] / [i915#6953] / [i915#8152]) -> [PASS][404]
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
- shard-rkl: [SKIP][405] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][406] +3 other tests pass
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][407] ([i915#14544] / [i915#15073]) -> [PASS][408] +1 other test pass
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][409] ([i915#15073]) -> [PASS][410] +1 other test pass
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][411] ([i915#15073]) -> [PASS][412]
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3:
- shard-dg2: [FAIL][413] ([i915#9196]) -> [PASS][414] +2 other tests pass
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-1/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
* igt@perf_pmu@busy-accuracy-98@rcs0:
- shard-rkl: [FAIL][415] ([i915#4349]) -> [PASS][416] +1 other test pass
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@perf_pmu@busy-accuracy-98@rcs0.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@perf_pmu@busy-accuracy-98@rcs0.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-rkl: [DMESG-WARN][417] ([i915#12964]) -> [PASS][418] +12 other tests pass
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-3/igt@perf_pmu@busy-double-start@vecs0.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@perf_pmu@busy-double-start@vecs0.html
#### Warnings ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-rkl: [SKIP][419] ([i915#14544] / [i915#8411]) -> [SKIP][420] ([i915#8411]) +1 other test skip
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@api_intel_bb@blit-reloc-purge-cache.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: [SKIP][421] ([i915#8411]) -> [SKIP][422] ([i915#14544] / [i915#8411])
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@api_intel_bb@object-reloc-keep-cache.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: [SKIP][423] ([i915#14544] / [i915#7697]) -> [SKIP][424] ([i915#7697])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_close_race@multigpu-basic-process.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: [SKIP][425] ([i915#280]) -> [SKIP][426] ([i915#14544] / [i915#280])
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@gem_ctx_sseu@engines.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_ctx_sseu@engines.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-rkl: [SKIP][427] ([i915#14544] / [i915#4525]) -> [SKIP][428] ([i915#4525])
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_exec_balancer@parallel-contexts.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: [SKIP][429] ([i915#4525]) -> [SKIP][430] ([i915#14544] / [i915#4525])
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_capture@capture-invisible:
- shard-rkl: [SKIP][431] ([i915#14544] / [i915#6334]) -> [SKIP][432] ([i915#6334]) +1 other test skip
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_exec_capture@capture-invisible.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_reloc@basic-scanout:
- shard-rkl: [SKIP][433] ([i915#14544] / [i915#3281]) -> [SKIP][434] ([i915#3281]) +14 other tests skip
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_exec_reloc@basic-scanout.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_reloc@basic-write-read:
- shard-rkl: [SKIP][435] ([i915#3281]) -> [SKIP][436] ([i915#14544] / [i915#3281]) +7 other tests skip
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_exec_reloc@basic-write-read.html
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: [SKIP][437] ([i915#2190]) -> [SKIP][438] ([i915#14544] / [i915#2190])
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_huc_copy@huc-copy.html
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-rkl: [SKIP][439] ([i915#4613]) -> [SKIP][440] ([i915#14544] / [i915#4613]) +1 other test skip
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-random:
- shard-rkl: [SKIP][441] ([i915#14544] / [i915#4613]) -> [SKIP][442] ([i915#4613]) +1 other test skip
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: [SKIP][443] ([i915#3282]) -> [SKIP][444] ([i915#14544] / [i915#3282]) +3 other tests skip
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pwrite@basic-exhaustion:
- shard-rkl: [SKIP][445] ([i915#14544] / [i915#3282]) -> [SKIP][446] ([i915#3282]) +4 other tests skip
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_pwrite@basic-exhaustion.html
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-buffer:
- shard-rkl: [SKIP][447] ([i915#4270]) -> [TIMEOUT][448] ([i915#12917] / [i915#12964])
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_pxp@create-regular-buffer.html
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-rkl: [FAIL][449] ([i915#15169]) -> [SKIP][450] ([i915#13717])
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-3/igt@gem_pxp@hw-rejects-pxp-context.html
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: [SKIP][451] ([i915#14544] / [i915#4270]) -> [TIMEOUT][452] ([i915#12917] / [i915#12964])
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: [SKIP][453] ([i915#14544] / [i915#3297]) -> [SKIP][454] ([i915#3297]) +1 other test skip
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-rkl: [SKIP][455] ([i915#3297]) -> [SKIP][456] ([i915#14544] / [i915#3297])
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gem_userptr_blits@dmabuf-unsync.html
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen9_exec_parse@batch-without-end:
- shard-rkl: [SKIP][457] ([i915#2527]) -> [SKIP][458] ([i915#14544] / [i915#2527]) +1 other test skip
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@gen9_exec_parse@batch-without-end.html
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@shadow-peek:
- shard-rkl: [SKIP][459] ([i915#14544] / [i915#2527]) -> [SKIP][460] ([i915#2527]) +3 other tests skip
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@gen9_exec_parse@shadow-peek.html
* igt@intel_hwmon@hwmon-write:
- shard-rkl: [SKIP][461] ([i915#14544] / [i915#7707]) -> [SKIP][462] ([i915#7707])
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@intel_hwmon@hwmon-write.html
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-rkl: [SKIP][463] ([i915#12454] / [i915#12712]) -> [SKIP][464] ([i915#12454] / [i915#12712] / [i915#14544])
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-rkl: [SKIP][465] ([i915#5286]) -> [SKIP][466] ([i915#14544]) +1 other test skip
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-rkl: [SKIP][467] ([i915#14544]) -> [SKIP][468] ([i915#5286]) +4 other tests skip
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-rkl: [SKIP][469] ([i915#3638]) -> [SKIP][470] ([i915#14544]) +1 other test skip
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_big_fb@linear-16bpp-rotate-90.html
[470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-rkl: [SKIP][471] ([i915#14544]) -> [SKIP][472] ([i915#3638]) +2 other tests skip
[471]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
[472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-rkl: [SKIP][473] ([i915#14544]) -> [SKIP][474] ([i915#12313]) +1 other test skip
[473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-rkl: [SKIP][475] ([i915#12805]) -> [SKIP][476] ([i915#14544])
[475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
[476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][477] ([i915#14098] / [i915#6095]) -> [SKIP][478] ([i915#6095]) +7 other tests skip
[477]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html
[478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
- shard-rkl: [SKIP][479] ([i915#14544]) -> [SKIP][480] ([i915#14098] / [i915#6095]) +10 other tests skip
[479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html
[480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
- shard-rkl: [SKIP][481] ([i915#14098] / [i915#6095]) -> [SKIP][482] ([i915#14544]) +5 other tests skip
[481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
[482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg1: [SKIP][483] ([i915#4423] / [i915#6095]) -> [SKIP][484] ([i915#6095]) +1 other test skip
[483]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-rkl: [SKIP][485] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][486] ([i915#11151] / [i915#7828]) +6 other tests skip
[485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_chamelium_audio@hdmi-audio.html
[486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-rkl: [SKIP][487] ([i915#11151] / [i915#7828]) -> [SKIP][488] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
[487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_chamelium_frames@dp-crc-fast.html
[488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_color@deep-color:
- shard-rkl: [SKIP][489] ([i915#12655] / [i915#3555]) -> [SKIP][490] ([i915#12655] / [i915#14544] / [i915#3555])
[489]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_color@deep-color.html
[490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_color@deep-color.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: [SKIP][491] ([i915#3116]) -> [SKIP][492] ([i915#14544])
[491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_content_protection@dp-mst-type-1.html
[492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [SKIP][493] ([i915#9424]) -> [FAIL][494] ([i915#7173])
[493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-1/igt@kms_content_protection@lic-type-0.html
[494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][495] ([i915#9424]) -> [SKIP][496] ([i915#9433])
[495]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-19/igt@kms_content_protection@mei-interface.html
[496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-rkl: [SKIP][497] ([i915#7118] / [i915#9424]) -> [SKIP][498] ([i915#14544])
[497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_content_protection@uevent.html
[498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-rkl: [SKIP][499] ([i915#3555]) -> [SKIP][500] ([i915#14544])
[499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_cursor_crc@cursor-offscreen-32x32.html
[500]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-256x85:
- shard-rkl: [SKIP][501] ([i915#14544]) -> [FAIL][502] ([i915#13566])
[501]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html
[502]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-256x85.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-rkl: [SKIP][503] ([i915#14544]) -> [SKIP][504] ([i915#3555]) +3 other tests skip
[503]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-32x10.html
[504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: [SKIP][505] ([i915#14544]) -> [SKIP][506] ([i915#13049]) +1 other test skip
[505]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
[506]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-rkl: [SKIP][507] -> [SKIP][508] ([i915#14544]) +17 other tests skip
[507]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[508]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-rkl: [SKIP][509] ([i915#14544]) -> [SKIP][510] +18 other tests skip
[509]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: [SKIP][511] ([i915#9067]) -> [SKIP][512] ([i915#14544])
[511]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
[512]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: [SKIP][513] ([i915#14544]) -> [SKIP][514] ([i915#4103])
[513]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[514]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-rkl: [SKIP][515] ([i915#14544]) -> [SKIP][516] ([i915#13749])
[515]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-sst.html
[516]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-rkl: [SKIP][517] ([i915#13748]) -> [SKIP][518] ([i915#14544])
[517]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_dp_link_training@uhbr-mst.html
[518]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: [SKIP][519] ([i915#14544]) -> [SKIP][520] ([i915#3555] / [i915#3840])
[519]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_dsc@dsc-with-bpc-formats.html
[520]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-rkl: [SKIP][521] ([i915#9934]) -> [SKIP][522] ([i915#14544] / [i915#9934]) +3 other tests skip
[521]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
[522]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-rkl: [SKIP][523] ([i915#14544] / [i915#9934]) -> [SKIP][524] ([i915#9934]) +6 other tests skip
[523]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
[524]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: [SKIP][525] ([i915#2672] / [i915#3555]) -> [SKIP][526] ([i915#14544] / [i915#3555]) +4 other tests skip
[525]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
[526]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-rkl: [SKIP][527] ([i915#14544] / [i915#3555]) -> [SKIP][528] ([i915#2672] / [i915#3555]) +3 other tests skip
[527]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
[528]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-dg1: [SKIP][529] -> [SKIP][530] ([i915#4423]) +1 other test skip
[529]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[530]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][531] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][532] ([i915#1825]) +30 other tests skip
[531]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
[532]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-dg1: [SKIP][533] ([i915#4423]) -> [SKIP][534] +2 other tests skip
[533]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
[534]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
- shard-rkl: [SKIP][535] ([i915#14544]) -> [SKIP][536] ([i915#15102]) +5 other tests skip
[535]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
[536]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [SKIP][537] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][538] ([i915#15102] / [i915#3458]) +1 other test skip
[537]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[538]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][539] ([i915#15102] / [i915#3458]) -> [SKIP][540] ([i915#10433] / [i915#15102] / [i915#3458])
[539]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[540]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-rkl: [SKIP][541] ([i915#1825]) -> [SKIP][542] ([i915#14544] / [i915#1849] / [i915#5354]) +17 other tests skip
[541]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
[542]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-dg1: [SKIP][543] ([i915#4423] / [i915#8708]) -> [SKIP][544] ([i915#8708]) +1 other test skip
[543]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
[544]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
- shard-rkl: [SKIP][545] ([i915#15102]) -> [SKIP][546] ([i915#14544]) +2 other tests skip
[545]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
[546]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg1: [SKIP][547] ([i915#15102] / [i915#3458]) -> [SKIP][548] ([i915#15102] / [i915#3458] / [i915#4423])
[547]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[548]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][549] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][550] ([i915#15102] / [i915#3023]) +19 other tests skip
[549]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[550]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-rkl: [SKIP][551] ([i915#15102] / [i915#3023]) -> [SKIP][552] ([i915#14544] / [i915#1849] / [i915#5354]) +11 other tests skip
[551]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[552]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-dg1: [SKIP][553] ([i915#15102] / [i915#3458] / [i915#4423]) -> [SKIP][554] ([i915#15102] / [i915#3458])
[553]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
[554]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: [SKIP][555] ([i915#13331]) -> [SKIP][556] ([i915#12713])
[555]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg2-10/igt@kms_hdr@brightness-with-hdr.html
[556]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg2-4/igt@kms_hdr@brightness-with-hdr.html
- shard-rkl: [SKIP][557] ([i915#12713]) -> [SKIP][558] ([i915#14544])
[557]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html
[558]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-rkl: [SKIP][559] ([i915#12388] / [i915#14544]) -> [SKIP][560] ([i915#12388])
[559]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_joiner@basic-force-big-joiner.html
[560]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-rkl: [SKIP][561] ([i915#13688] / [i915#14544]) -> [SKIP][562] ([i915#13688])
[561]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html
[562]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-rkl: [SKIP][563] ([i915#12339]) -> [SKIP][564] ([i915#12339] / [i915#14544])
[563]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_joiner@basic-ultra-joiner.html
[564]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-rkl: [SKIP][565] ([i915#12394] / [i915#14544]) -> [SKIP][566] ([i915#12394])
[565]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
[566]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-rkl: [SKIP][567] ([i915#13522] / [i915#14544]) -> [SKIP][568] ([i915#13522])
[567]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
[568]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][569] ([i915#1839] / [i915#4816]) -> [SKIP][570] ([i915#4816])
[569]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[570]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-rkl: [SKIP][571] ([i915#6301]) -> [SKIP][572] ([i915#14544])
[571]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_panel_fitting@atomic-fastset.html
[572]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: [SKIP][573] ([i915#14544]) -> [SKIP][574] ([i915#6301])
[573]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_panel_fitting@legacy.html
[574]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-rkl: [SKIP][575] ([i915#14712]) -> [SKIP][576] ([i915#14544])
[575]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
[576]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-rkl: [SKIP][577] ([i915#14544]) -> [SKIP][578] ([i915#13958])
[577]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-4.html
[578]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: [SKIP][579] ([i915#14544]) -> [SKIP][580] ([i915#14259])
[579]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_multiple@tiling-yf.html
[580]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-rkl: [SKIP][581] ([i915#14544] / [i915#6953] / [i915#8152]) -> [SKIP][582] ([i915#6953])
[581]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size.html
[582]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_pm_backlight@fade:
- shard-rkl: [SKIP][583] ([i915#14544] / [i915#5354]) -> [SKIP][584] ([i915#5354])
[583]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_pm_backlight@fade.html
[584]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [FAIL][585] ([i915#9295]) -> [SKIP][586] ([i915#3361])
[585]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
[586]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][587] ([i915#4281]) -> [SKIP][588] ([i915#3361])
[587]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[588]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-8/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: [SKIP][589] ([i915#14544] / [i915#8430]) -> [SKIP][590] ([i915#8430])
[589]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_pm_lpsp@screens-disabled.html
[590]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-rkl: [SKIP][591] ([i915#14544]) -> [DMESG-WARN][592] ([i915#12964])
[591]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_pm_rpm@drm-resources-equal.html
[592]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-rkl: [SKIP][593] ([i915#6524]) -> [SKIP][594] ([i915#14544] / [i915#6524])
[593]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_prime@basic-modeset-hybrid.html
[594]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-rkl: [SKIP][595] ([i915#11520]) -> [SKIP][596] ([i915#11520] / [i915#14544]) +5 other tests skip
[595]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
[596]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: [SKIP][597] ([i915#11520] / [i915#14544]) -> [SKIP][598] ([i915#11520]) +7 other tests skip
[597]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
[598]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-dg1: [SKIP][599] ([i915#11520]) -> [SKIP][600] ([i915#11520] / [i915#4423])
[599]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
[600]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
- shard-dg1: [SKIP][601] ([i915#11520] / [i915#4423]) -> [SKIP][602] ([i915#11520])
[601]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-17/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
[602]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-15/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: [SKIP][603] ([i915#14544] / [i915#9683]) -> [SKIP][604] ([i915#9683]) +1 other test skip
[603]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_psr2_su@page_flip-xrgb8888.html
[604]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-rkl: [SKIP][605] ([i915#1072] / [i915#9732]) -> [SKIP][606] ([i915#1072] / [i915#14544] / [i915#9732]) +11 other tests skip
[605]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
[606]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-rkl: [SKIP][607] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][608] ([i915#1072] / [i915#9732]) +18 other tests skip
[607]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_psr@psr2-primary-mmap-gtt.html
[608]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: [SKIP][609] ([i915#14544] / [i915#9685]) -> [SKIP][610] ([i915#9685])
[609]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[610]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-rkl: [SKIP][611] ([i915#5289]) -> [SKIP][612] ([i915#14544])
[611]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
[612]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: [SKIP][613] ([i915#14544]) -> [SKIP][614] ([i915#5289])
[613]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
[614]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-rkl: [SKIP][615] ([i915#14544] / [i915#3555]) -> [SKIP][616] ([i915#3555])
[615]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[616]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sharpness_filter@filter-scaler-downscale:
- shard-rkl: [SKIP][617] ([i915#14544]) -> [SKIP][618] ([i915#15232]) +2 other tests skip
[617]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_sharpness_filter@filter-scaler-downscale.html
[618]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_sharpness_filter@filter-scaler-downscale.html
* igt@kms_vrr@lobf:
- shard-dg1: [SKIP][619] ([i915#11920] / [i915#4423]) -> [SKIP][620] ([i915#11920])
[619]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-dg1-15/igt@kms_vrr@lobf.html
[620]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-dg1-16/igt@kms_vrr@lobf.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: [SKIP][621] ([i915#14544]) -> [SKIP][622] ([i915#9906])
[621]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-virtual.html
[622]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-rkl: [SKIP][623] ([i915#14544] / [i915#2437] / [i915#9412]) -> [SKIP][624] ([i915#2437] / [i915#9412])
[623]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@kms_writeback@writeback-pixel-formats.html
[624]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@kms_writeback@writeback-pixel-formats.html
* igt@panthor/panthor_gem@bo_create:
- shard-rkl: [SKIP][625] ([i915#14544] / [i915#15265]) -> [SKIP][626] ([i915#15265]) +2 other tests skip
[625]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@panthor/panthor_gem@bo_create.html
[626]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@panthor/panthor_gem@bo_create.html
* igt@panthor/panthor_group@group_create:
- shard-rkl: [SKIP][627] ([i915#15265]) -> [SKIP][628] ([i915#14544] / [i915#15265])
[627]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-7/igt@panthor/panthor_group@group_create.html
[628]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@panthor/panthor_group@group_create.html
* igt@prime_vgem@basic-fence-read:
- shard-rkl: [SKIP][629] ([i915#14544] / [i915#3291] / [i915#3708]) -> [SKIP][630] ([i915#3291] / [i915#3708])
[629]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@prime_vgem@basic-fence-read.html
[630]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: [SKIP][631] ([i915#14544] / [i915#9917]) -> [SKIP][632] ([i915#9917]) +1 other test skip
[631]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-on.html
[632]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-rkl: [SKIP][633] ([i915#9917]) -> [SKIP][634] ([i915#14544] / [i915#9917])
[633]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17525/shard-rkl-5/igt@sriov_basic@enable-vfs-bind-unbind-each.html
[634]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
[i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
[i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12756]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12756
[i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13441
[i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
[i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
[i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
[i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
[i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
[i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
[i915#14553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14553
[i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
[i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
[i915#14785]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14785
[i915#14809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14809
[i915#14857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14857
[i915#15060]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15060
[i915#15070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15070
[i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
[i915#15095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15095
[i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
[i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
[i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106
[i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
[i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
[i915#15152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15152
[i915#15169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15169
[i915#15232]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15232
[i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
[i915#15265]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15265
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2065
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
[i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_17525 -> Patchwork_157342v1
CI-20190529: 20190529
CI_DRM_17525: a9792b1ab75123e4aceaba953a89809e745919c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8617: 8617
Patchwork_157342v1: a9792b1ab75123e4aceaba953a89809e745919c6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157342v1/index.html
[-- Attachment #2: Type: text/html, Size: 208355 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value
2025-11-10 17:27 ` [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value Ville Syrjala
@ 2025-11-11 4:14 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:14 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final
> register value
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We currently have a bunch of places that want the final register value after
> register polling. Currently those places are mostly using
> intel_de_wait_custom(). That is not a function that we want to keep around
> as it pretty much prevents conversion to poll_timeout_us().
>
> Have intel_de_wait() also return the final register value so that some of the
> current users can be converted over to the simpler interface.
>
> Done with cocci:
> @@
> @@
> int intel_de_wait(...
> + ,u32 *out_value
> )
> {
> ...
> __intel_wait_for_register(...,
> - NULL
> + out_value
> )
> ...
> }
>
> @@
> @@
> intel_de_wait(...
> + ,NULL
> )
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 8 ++++----
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index ea9973dbbffc..a4ad20030c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -116,14 +116,14 @@ __intel_de_wait_for_register_atomic_nowl(struct
> intel_display *display,
>
> static inline int
> intel_de_wait(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout_ms)
> + u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
> {
> int ret;
>
> intel_dmc_wl_get(display, reg);
>
> ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
> - value, 2, timeout_ms, NULL);
> + value, 2, timeout_ms, out_value);
>
> intel_dmc_wl_put(display, reg);
>
> @@ -169,14 +169,14 @@ static inline int
> intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
> u32 mask, unsigned int timeout_ms) {
> - return intel_de_wait(display, reg, mask, mask, timeout_ms);
> + return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
> }
>
> static inline int
> intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
> u32 mask, unsigned int timeout_ms)
> {
> - return intel_de_wait(display, reg, mask, 0, timeout_ms);
> + return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index eab7019f2252..afa5d8964f0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1446,7 +1446,7 @@ static void assert_chv_phy_status(struct
> intel_display *display)
> * so the power state can take a while to actually change.
> */
> if (intel_de_wait(display, DISPLAY_PHY_STATUS,
> - phy_status_mask, phy_status, 10))
> + phy_status_mask, phy_status, 10, NULL))
> drm_err(display->drm,
> "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> (PHY_CONTROL=0x%08x)\n",
> intel_de_read(display, DISPLAY_PHY_STATUS) &
> phy_status_mask, diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index bd757db85927..27bb2199659f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -784,7 +784,7 @@ intel_dp_mst_hdcp_stream_encryption(struct
> intel_connector *connector,
> /* Wait for encryption confirmation */
> if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
> stream_enc_status, enable ? stream_enc_status : 0,
> - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> drm_err(display->drm, "Timed out waiting for transcoder: %s
> stream encryption %s\n",
> transcoder_name(cpu_transcoder),
> str_enabled_disabled(enable));
> return -ETIMEDOUT;
> @@ -824,7 +824,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct
> intel_connector *connector,
> if (intel_de_wait(display, HDCP2_STREAM_STATUS(display,
> cpu_transcoder, pipe),
> STREAM_ENCRYPTION_STATUS,
> enable ? STREAM_ENCRYPTION_STATUS : 0,
> - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> drm_err(display->drm, "Timed out waiting for transcoder: %s
> stream encryption %s\n",
> transcoder_name(cpu_transcoder),
> str_enabled_disabled(enable));
> return -ETIMEDOUT;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 5df6347a420d..378f0836b5a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder
> *encoder,
> break;
> }
>
> - if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
> + if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000,
> +NULL))
> drm_WARN(display->drm, 1,
> "timed out waiting for [ENCODER:%d:%s] port ready:
> got 0x%x, expected 0x%x\n",
> encoder->base.base.id, encoder->base.name,
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names
2025-11-10 17:27 ` [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names Ville Syrjala
@ 2025-11-11 4:21 ` Kandpal, Suraj
2025-11-11 17:45 ` Ville Syrjälä
0 siblings, 1 reply; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*()
> function names
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_de_wait*() take the timeout in milliseconds. Incldue
Typo * Include
> that information in the function name to make life less
> confusing. And I'll also be introducing microsecond variants
Maybe no full stop if you are using "and" also should we be using references to what
One will be doing in later commits ?
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> of these later.
>
> Done with cocci:
> @@
> @@
> (
> static int
> - intel_de_wait
> + intel_de_wait_ms
> (...)
> {
> ...
> }
> |
> static int
> - intel_de_wait_fw
> + intel_de_wait_fw_ms
> (...)
> {
> ...
> }
> |
> static int
> - intel_de_wait_for_set
> + intel_de_wait_for_set_ms
> (...)
> {
> ...
> }
> |
> static int
> - intel_de_wait_for_clear
> + intel_de_wait_for_clear_ms
> (...)
> {
> ...
> }
> )
>
> @@
> @@
> (
> - intel_de_wait
> + intel_de_wait_ms
> |
> - intel_de_wait_fw
> + intel_de_wait_fw_ms
> |
> - intel_de_wait_for_set
> + intel_de_wait_for_set_ms
> |
> - intel_de_wait_for_clear
> + intel_de_wait_for_clear_ms
> )
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 20 +++----
> drivers/gpu/drm/i915/display/intel_crt.c | 16 +++---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 36 ++++++-------
> drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
> drivers/gpu/drm/i915/display/intel_de.h | 22 ++++----
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> .../drm/i915/display/intel_display_power.c | 4 +-
> .../i915/display/intel_display_power_well.c | 38 ++++++-------
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 ++---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 +--
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++--
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_flipq.c | 8 +--
> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 44 ++++++++-------
> drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +--
> drivers/gpu/drm/i915/display/intel_lvds.c | 6 +--
> .../gpu/drm/i915/display/intel_pch_display.c | 12 ++---
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 12 ++---
> drivers/gpu/drm/i915/display/intel_psr.c | 10 ++--
> drivers/gpu/drm/i915/display/intel_sbi.c | 6 ++-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +--
> drivers/gpu/drm/i915/display/intel_tc.c | 8 +--
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 +--
> drivers/gpu/drm/i915/display/vlv_dsi.c | 54 +++++++++----------
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +--
> 30 files changed, 207 insertions(+), 205 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> b/drivers/gpu/drm/i915/display/hsw_ips.c
> index f444c5b7a27b..008d339d5c21 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -56,7 +56,7 @@ static void hsw_ips_enable(const struct intel_crtc_state
> *crtc_state)
> * the HW state readout code will complain that the expected
> * IPS_CTL value is not the one we read.
> */
> - if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
> + if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE,
> 50))
> drm_err(display->drm,
> "Timed out waiting for IPS enable\n");
> }
> @@ -78,7 +78,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
> *crtc_state)
> * 42ms timeout value leads to occasional timeouts so use
> 100ms
> * instead.
> */
> - if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE,
> 100))
> + if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE,
> 100))
> drm_err(display->drm,
> "Timed out waiting for IPS disable\n");
> } else {
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 70d4c1bc70fc..6a11b3bb219b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1048,8 +1048,8 @@ static void gen11_dsi_enable_transcoder(struct
> intel_encoder *encoder)
> TRANSCONF_ENABLE);
>
> /* wait for transcoder to be enabled */
> - if (intel_de_wait_for_set(display, TRANSCONF(display,
> dsi_trans),
> - TRANSCONF_STATE_ENABLE, 10))
> + if (intel_de_wait_for_set_ms(display, TRANSCONF(display,
> dsi_trans),
> + TRANSCONF_STATE_ENABLE, 10))
> drm_err(display->drm,
> "DSI transcoder not enabled\n");
> }
> @@ -1317,8 +1317,8 @@ static void gen11_dsi_disable_transcoder(struct
> intel_encoder *encoder)
> TRANSCONF_ENABLE, 0);
>
> /* wait for transcoder to be disabled */
> - if (intel_de_wait_for_clear(display, TRANSCONF(display,
> dsi_trans),
> - TRANSCONF_STATE_ENABLE, 50))
> + if (intel_de_wait_for_clear_ms(display, TRANSCONF(display,
> dsi_trans),
> + TRANSCONF_STATE_ENABLE, 50))
> drm_err(display->drm,
> "DSI trancoder not disabled\n");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4d03cfefc72c..c0d798b1cf46 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1114,7 +1114,7 @@ static void skl_dpll0_enable(struct intel_display
> *display, int vco)
> intel_de_rmw(display, LCPLL1_CTL,
> 0, LCPLL_PLL_ENABLE);
>
> - if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
> + if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK,
> 5))
> drm_err(display->drm, "DPLL0 not locked\n");
>
> display->cdclk.hw.vco = vco;
> @@ -1128,7 +1128,7 @@ static void skl_dpll0_disable(struct intel_display
> *display)
> intel_de_rmw(display, LCPLL1_CTL,
> LCPLL_PLL_ENABLE, 0);
>
> - if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
> + if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK,
> 1))
> drm_err(display->drm, "Couldn't disable DPLL0\n");
>
> display->cdclk.hw.vco = 0;
> @@ -1835,8 +1835,8 @@ static void bxt_de_pll_disable(struct intel_display
> *display)
> intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_clear(display,
> - BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> 1))
> + if (intel_de_wait_for_clear_ms(display,
> + BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> 1))
> drm_err(display->drm, "timeout waiting for DE PLL
> unlock\n");
>
> display->cdclk.hw.vco = 0;
> @@ -1852,8 +1852,8 @@ static void bxt_de_pll_enable(struct intel_display
> *display, int vco)
> intel_de_write(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_PLL_ENABLE);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(display,
> - BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> + if (intel_de_wait_for_set_ms(display,
> + BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> 1))
> drm_err(display->drm, "timeout waiting for DE PLL lock\n");
>
> display->cdclk.hw.vco = vco;
> @@ -1865,7 +1865,7 @@ static void icl_cdclk_pll_disable(struct intel_display
> *display)
> BXT_DE_PLL_PLL_ENABLE, 0);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_LOCK, 1))
> + if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_LOCK, 1))
> drm_err(display->drm, "timeout waiting for CDCLK PLL
> unlock\n");
>
> display->cdclk.hw.vco = 0;
> @@ -1883,7 +1883,7 @@ static void icl_cdclk_pll_enable(struct intel_display
> *display, int vco)
> intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_LOCK, 1))
> + if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_LOCK, 1))
> drm_err(display->drm, "timeout waiting for CDCLK PLL
> lock\n");
>
> display->cdclk.hw.vco = vco;
> @@ -1903,8 +1903,8 @@ static void adlp_cdclk_pll_crawl(struct intel_display
> *display, int vco)
> intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
> - BXT_DE_PLL_LOCK |
> BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK |
> BXT_DE_PLL_FREQ_REQ_ACK, 1))
> drm_err(display->drm, "timeout waiting for FREQ change
> request ack\n");
>
> val &= ~BXT_DE_PLL_FREQ_REQ;
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 31e68047f217..82e89cdbe5a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -498,10 +498,10 @@ static bool ilk_crt_detect_hotplug(struct
> drm_connector *connector)
>
> intel_de_write(display, crt->adpa_reg, adpa);
>
> - if (intel_de_wait_for_clear(display,
> - crt->adpa_reg,
> -
> ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> - 1000))
> + if (intel_de_wait_for_clear_ms(display,
> + crt->adpa_reg,
> +
> ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> + 1000))
> drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_TRIGGER");
>
> @@ -553,8 +553,8 @@ static bool valleyview_crt_detect_hotplug(struct
> drm_connector *connector)
>
> intel_de_write(display, crt->adpa_reg, adpa);
>
> - if (intel_de_wait_for_clear(display, crt->adpa_reg,
> - ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> 1000)) {
> + if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,
> + ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> 1000)) {
> drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_TRIGGER");
> intel_de_write(display, crt->adpa_reg, save_adpa);
> @@ -604,8 +604,8 @@ static bool intel_crt_detect_hotplug(struct
> drm_connector *connector)
> CRT_HOTPLUG_FORCE_DETECT,
> CRT_HOTPLUG_FORCE_DETECT);
> /* wait for FORCE_DETECT to go off */
> - if (intel_de_wait_for_clear(display,
> PORT_HOTPLUG_EN(display),
> - CRT_HOTPLUG_FORCE_DETECT,
> 1000))
> + if (intel_de_wait_for_clear_ms(display,
> PORT_HOTPLUG_EN(display),
> + CRT_HOTPLUG_FORCE_DETECT,
> 1000))
> drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_DETECT to go
> off");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1551d30ec584..7870823235c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -145,9 +145,9 @@ void intel_cx0_bus_reset(struct intel_encoder
> *encoder, int lane)
> intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET);
>
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> - XELPDP_PORT_M2P_TRANSACTION_RESET,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_M2P_TRANSACTION_RESET,
> + XELPDP_MSGBUS_TIMEOUT_MS)) {
> drm_err_once(display->drm,
> "Failed to bring PHY %c to idle.\n",
> phy_name(phy));
> @@ -213,9 +213,9 @@ static int __intel_cx0_read_once(struct intel_encoder
> *encoder,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> -
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_MS)) {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to
> complete. Reset the bus and retry.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> @@ -284,9 +284,9 @@ static int __intel_cx0_write_once(struct intel_encoder
> *encoder,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> -
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_MS)) {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to
> complete. Resetting the bus.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> @@ -300,9 +300,9 @@ static int __intel_cx0_write_once(struct intel_encoder
> *encoder,
> XELPDP_PORT_M2P_DATA(data) |
> XELPDP_PORT_M2P_ADDRESS(addr));
>
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> -
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_MS)) {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for write to complete.
> Resetting the bus.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> @@ -2813,9 +2813,9 @@ void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>
> /* Wait for pending transactions.*/
> for_each_cx0_lane_in_mask(lane_mask, lane)
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> -
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_MS))
> {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous
> transaction to complete. Reset the bus.\n",
> phy_name(phy));
> @@ -2924,9 +2924,9 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
>
> intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_pipe_reset, 0);
>
> - if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> - lane_phy_current_status,
> - XELPDP_PORT_RESET_END_TIMEOUT_MS))
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status,
> +
> XELPDP_PORT_RESET_END_TIMEOUT_MS))
> drm_warn(display->drm,
> "PHY %c failed to bring out of lane reset\n",
> phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 733ef4559131..33fca83c22b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -210,8 +210,8 @@ void intel_wait_ddi_buf_idle(struct intel_display
> *display, enum port port)
> }
>
> static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
> - if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display,
> port),
> - DDI_BUF_IS_IDLE, 10))
> + if (intel_de_wait_for_set_ms(display,
> intel_ddi_buf_status_reg(display, port),
> + DDI_BUF_IS_IDLE, 10))
> drm_err(display->drm, "Timeout waiting for DDI BUF %c to get
> idle\n",
> port_name(port));
> }
> @@ -235,8 +235,8 @@ static void intel_wait_ddi_buf_active(struct
> intel_encoder *encoder)
> }
>
> static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
> - if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display,
> port),
> - DDI_BUF_IS_IDLE, 10))
> + if (intel_de_wait_for_clear_ms(display,
> intel_ddi_buf_status_reg(display, port),
> + DDI_BUF_IS_IDLE, 10))
> drm_err(display->drm, "Timeout waiting for DDI BUF %c to get
> active\n",
> port_name(port));
> }
> @@ -2307,8 +2307,8 @@ void intel_ddi_wait_for_act_sent(struct
> intel_encoder *encoder,
> {
> struct intel_display *display = to_intel_display(encoder);
>
> - if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder,
> crtc_state),
> - DP_TP_STATUS_ACT_SENT, 1))
> + if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder,
> crtc_state),
> + DP_TP_STATUS_ACT_SENT, 1))
> drm_err(display->drm, "Timed out waiting for ACT sent\n");
> }
>
> @@ -2383,11 +2383,11 @@ int intel_ddi_wait_for_fec_status(struct
> intel_encoder *encoder,
> return 0;
>
> if (enabled)
> - ret = intel_de_wait_for_set(display,
> dp_tp_status_reg(encoder, crtc_state),
> - DP_TP_STATUS_FEC_ENABLE_LIVE,
> 1);
> + ret = intel_de_wait_for_set_ms(display,
> dp_tp_status_reg(encoder, crtc_state),
> +
> DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
> else
> - ret = intel_de_wait_for_clear(display,
> dp_tp_status_reg(encoder, crtc_state),
> - DP_TP_STATUS_FEC_ENABLE_LIVE,
> 1);
> + ret = intel_de_wait_for_clear_ms(display,
> dp_tp_status_reg(encoder, crtc_state),
> +
> DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
>
> if (ret) {
> drm_err(display->drm,
> @@ -3868,9 +3868,9 @@ static void intel_ddi_set_idle_link_train(struct
> intel_dp *intel_dp,
> if (port == PORT_A && DISPLAY_VER(display) < 12)
> return;
>
> - if (intel_de_wait_for_set(display,
> - dp_tp_status_reg(encoder, crtc_state),
> - DP_TP_STATUS_IDLE_DONE, 2))
> + if (intel_de_wait_for_set_ms(display,
> + dp_tp_status_reg(encoder, crtc_state),
> + DP_TP_STATUS_IDLE_DONE, 2))
> drm_err(display->drm,
> "Timed out waiting for DP idle patterns\n");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index a4ad20030c09..d449180d1d22 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -115,8 +115,9 @@ __intel_de_wait_for_register_atomic_nowl(struct
> intel_display *display,
> }
>
> static inline int
> -intel_de_wait(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
> +intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout_ms,
> + u32 *out_value)
> {
> int ret;
>
> @@ -131,8 +132,9 @@ intel_de_wait(struct intel_display *display, i915_reg_t
> reg,
> }
>
> static inline int
> -intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout_ms, u32
> *out_value)
> +intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout_ms,
> + u32 *out_value)
> {
> int ret;
>
> @@ -166,17 +168,17 @@ intel_de_wait_custom(struct intel_display *display,
> i915_reg_t reg,
> }
>
> static inline int
> -intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
> - u32 mask, unsigned int timeout_ms)
> +intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
> + u32 mask, unsigned int timeout_ms)
> {
> - return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
> + return intel_de_wait_ms(display, reg, mask, mask, timeout_ms,
> NULL);
> }
>
> static inline int
> -intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
> - u32 mask, unsigned int timeout_ms)
> +intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
> + u32 mask, unsigned int timeout_ms)
> {
> - return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
> + return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 25986bd8fbdd..6bca186608ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -359,8 +359,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state
> *old_crtc_state)
> enum transcoder cpu_transcoder = old_crtc_state-
> >cpu_transcoder;
>
> /* Wait for the Pipe State to go off */
> - if (intel_de_wait_for_clear(display, TRANSCONF(display,
> cpu_transcoder),
> - TRANSCONF_STATE_ENABLE, 100))
> + if (intel_de_wait_for_clear_ms(display, TRANSCONF(display,
> cpu_transcoder),
> + TRANSCONF_STATE_ENABLE,
> 100))
> drm_WARN(display->drm, 1, "pipe_off wait timed
> out\n");
> } else {
> intel_wait_for_pipe_scanline_stopped(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 74fcd9cfe911..2b86a634c1f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1305,7 +1305,7 @@ static void hsw_disable_lcpll(struct intel_display
> *display,
> intel_de_write(display, LCPLL_CTL, val);
> intel_de_posting_read(display, LCPLL_CTL);
>
> - if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
> + if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK,
> 1))
> drm_err(display->drm, "LCPLL still locked\n");
>
> val = hsw_read_dcomp(display);
> @@ -1362,7 +1362,7 @@ static void hsw_restore_lcpll(struct intel_display
> *display)
> val &= ~LCPLL_PLL_DISABLE;
> intel_de_write(display, LCPLL_CTL, val);
>
> - if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
> + if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
> drm_err(display->drm, "LCPLL not locked yet\n");
>
> if (val & LCPLL_CD_SOURCE_FCLK) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index afa5d8964f0d..8593d2daeaa6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -293,8 +293,8 @@ static void hsw_wait_for_power_well_enable(struct
> intel_display *display,
> }
>
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> - if (intel_de_wait_for_set(display, regs->driver,
> - HSW_PWR_WELL_CTL_STATE(pw_idx),
> timeout)) {
> + if (intel_de_wait_for_set_ms(display, regs->driver,
> + HSW_PWR_WELL_CTL_STATE(pw_idx),
> timeout)) {
> drm_dbg_kms(display->drm, "%s power well enable
> timeout\n",
> intel_power_well_name(power_well));
>
> @@ -338,9 +338,9 @@ static void hsw_wait_for_power_well_disable(struct
> intel_display *display,
> */
> reqs = hsw_power_well_requesters(display, regs, pw_idx);
>
> - ret = intel_de_wait_for_clear(display, regs->driver,
> - HSW_PWR_WELL_CTL_STATE(pw_idx),
> - reqs ? 0 : 1);
> + ret = intel_de_wait_for_clear_ms(display, regs->driver,
> +
> HSW_PWR_WELL_CTL_STATE(pw_idx),
> + reqs ? 0 : 1);
> if (!ret)
> return;
>
> @@ -359,8 +359,8 @@ static void gen9_wait_for_power_well_fuses(struct
> intel_display *display,
> {
> /* Timeout 5us for PG#0, for other PGs 1us */
> drm_WARN_ON(display->drm,
> - intel_de_wait_for_set(display, SKL_FUSE_STATUS,
> - SKL_FUSE_PG_DIST_STATUS(pg), 1));
> + intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(pg),
> 1));
> }
>
> static void hsw_power_well_enable(struct intel_display *display,
> @@ -1445,8 +1445,8 @@ static void assert_chv_phy_status(struct
> intel_display *display)
> * The PHY may be busy with some initial calibration and whatnot,
> * so the power state can take a while to actually change.
> */
> - if (intel_de_wait(display, DISPLAY_PHY_STATUS,
> - phy_status_mask, phy_status, 10, NULL))
> + if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
> + phy_status_mask, phy_status, 10, NULL))
> drm_err(display->drm,
> "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> (PHY_CONTROL=0x%08x)\n",
> intel_de_read(display, DISPLAY_PHY_STATUS) &
> phy_status_mask,
> @@ -1476,8 +1476,8 @@ static void
> chv_dpio_cmn_power_well_enable(struct intel_display *display,
> vlv_set_power_well(display, power_well, true);
>
> /* Poll for phypwrgood signal */
> - if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
> - PHY_POWERGOOD(phy), 1))
> + if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,
> + PHY_POWERGOOD(phy), 1))
> drm_err(display->drm, "Display PHY %d is not power up\n",
> phy);
>
> @@ -1867,8 +1867,8 @@ static void xelpdp_aux_power_well_enable(struct
> intel_display *display,
> * bit.
> */
> if (DISPLAY_VER(display) >= 35) {
> - if (intel_de_wait_for_set(display,
> XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> -
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
> + if (intel_de_wait_for_set_ms(display,
> XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> +
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
> drm_warn(display->drm,
> "Timeout waiting for PHY %c AUX channel
> power to be up\n",
> phy_name(phy));
> @@ -1888,8 +1888,8 @@ static void xelpdp_aux_power_well_disable(struct
> intel_display *display,
> 0);
>
> if (DISPLAY_VER(display) >= 35) {
> - if (intel_de_wait_for_clear(display,
> XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> -
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> +
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
> drm_warn(display->drm,
> "Timeout waiting for PHY %c AUX channel to
> powerdown\n",
> phy_name(phy));
> @@ -1913,8 +1913,8 @@ static void xe2lpd_pica_power_well_enable(struct
> intel_display *display,
> intel_de_write(display, XE2LPD_PICA_PW_CTL,
> XE2LPD_PICA_CTL_POWER_REQUEST);
>
> - if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL,
> - XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> drm_dbg_kms(display->drm, "pica power well enable
> timeout\n");
>
> drm_WARN(display->drm, 1, "Power well PICA timeout when
> enabled");
> @@ -1926,8 +1926,8 @@ static void xe2lpd_pica_power_well_disable(struct
> intel_display *display,
> {
> intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);
>
> - if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL,
> - XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> drm_dbg_kms(display->drm, "pica power well disable
> timeout\n");
>
> drm_WARN(display->drm, 1, "Power well PICA timeout when
> disabled");
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 27bb2199659f..14ed0ea22dd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -782,9 +782,9 @@ intel_dp_mst_hdcp_stream_encryption(struct
> intel_connector *connector,
> return -EINVAL;
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder,
> port),
> - stream_enc_status, enable ? stream_enc_status : 0,
> - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> + if (intel_de_wait_ms(display, HDCP_STATUS(display, cpu_transcoder,
> port),
> + stream_enc_status, enable ? stream_enc_status : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> drm_err(display->drm, "Timed out waiting for transcoder: %s
> stream encryption %s\n",
> transcoder_name(cpu_transcoder),
> str_enabled_disabled(enable));
> return -ETIMEDOUT;
> @@ -821,10 +821,10 @@ intel_dp_mst_hdcp2_stream_encryption(struct
> intel_connector *connector,
> return ret;
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait(display, HDCP2_STREAM_STATUS(display,
> cpu_transcoder, pipe),
> - STREAM_ENCRYPTION_STATUS,
> - enable ? STREAM_ENCRYPTION_STATUS : 0,
> - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> + if (intel_de_wait_ms(display, HDCP2_STREAM_STATUS(display,
> cpu_transcoder, pipe),
> + STREAM_ENCRYPTION_STATUS,
> + enable ? STREAM_ENCRYPTION_STATUS : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> NULL)) {
> drm_err(display->drm, "Timed out waiting for transcoder: %s
> stream encryption %s\n",
> transcoder_name(cpu_transcoder),
> str_enabled_disabled(enable));
> return -ETIMEDOUT;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 378f0836b5a5..4d1b6e2b93dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -390,7 +390,7 @@ static u32 bxt_get_grc(struct intel_display *display,
> enum dpio_phy phy)
> static void bxt_phy_wait_grc_done(struct intel_display *display,
> enum dpio_phy phy)
> {
> - if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy),
> GRC_DONE, 10))
> + if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy),
> GRC_DONE, 10))
> drm_err(display->drm, "timeout waiting for PHY%d GRC\n",
> phy);
> }
>
> @@ -427,8 +427,8 @@ static void _bxt_dpio_phy_init(struct intel_display
> *display, enum dpio_phy phy)
> * The flag should get set in 100us according to the HW team, but
> * use 1ms due to occasional timeouts observed with that.
> */
> - if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
> - PHY_RESERVED | PHY_POWER_GOOD,
> PHY_POWER_GOOD, 1, NULL))
> + if (intel_de_wait_fw_ms(display, BXT_PORT_CL1CM_DW0(phy),
> + PHY_RESERVED | PHY_POWER_GOOD,
> PHY_POWER_GOOD, 1, NULL))
> drm_err(display->drm, "timeout during PHY%d power on\n",
> phy);
>
> @@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder
> *encoder,
> break;
> }
>
> - if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000,
> NULL))
> + if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask,
> 1000, NULL))
> drm_WARN(display->drm, 1,
> "timed out waiting for [ENCODER:%d:%s] port ready:
> got 0x%x, expected 0x%x\n",
> encoder->base.base.id, encoder->base.name,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2e1f67be8eda..4f1db8493a2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -2019,7 +2019,7 @@ static void _vlv_enable_pll(const struct
> intel_crtc_state *crtc_state)
> intel_de_posting_read(display, DPLL(display, pipe));
> udelay(150);
>
> - if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV,
> 1))
> + if (intel_de_wait_for_set_ms(display, DPLL(display, pipe),
> DPLL_LOCK_VLV, 1))
> drm_err(display->drm, "DPLL %d failed to lock\n", pipe);
> }
>
> @@ -2165,7 +2165,7 @@ static void _chv_enable_pll(const struct
> intel_crtc_state *crtc_state)
> intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
>
> /* Check PLL is locked */
> - if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV,
> 1))
> + if (intel_de_wait_for_set_ms(display, DPLL(display, pipe),
> DPLL_LOCK_VLV, 1))
> drm_err(display->drm, "PLL %d failed to lock\n", pipe);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 92c433f7b7e2..683bc61c03c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1395,7 +1395,7 @@ static void skl_ddi_pll_enable(struct intel_display
> *display,
> /* the enable bit is always bit 31 */
> intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
>
> - if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
> + if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id),
> 5))
> drm_err(display->drm, "DPLL %d not locked\n", id);
> }
>
> @@ -3921,7 +3921,7 @@ static void icl_pll_power_enable(struct
> intel_display *display,
> * The spec says we need to "wait" but it also says it should be
> * immediate.
> */
> - if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
> + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE,
> 1))
> drm_err(display->drm, "PLL %d Power not enabled\n",
> pll->info->id);
> }
> @@ -3933,7 +3933,7 @@ static void icl_pll_enable(struct intel_display
> *display,
> intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
>
> /* Timeout is actually 600us. */
> - if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
> + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
> drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> }
>
> @@ -4046,7 +4046,7 @@ static void icl_pll_disable(struct intel_display
> *display,
> intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
>
> /* Timeout is actually 1us. */
> - if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
> + if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
> drm_err(display->drm, "PLL %d locked\n", pll->info->id);
>
> /* DVFS post sequence would be here. See the comment above. */
> @@ -4057,7 +4057,7 @@ static void icl_pll_disable(struct intel_display
> *display,
> * The spec says we need to "wait" but it also says it should be
> * immediate.
> */
> - if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
> + if (intel_de_wait_for_clear_ms(display, enable_reg,
> PLL_POWER_STATE, 1))
> drm_err(display->drm, "PLL %d Power not disabled\n",
> pll->info->id);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a1e3083022ee..437d2fda20a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -328,8 +328,8 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
> intel_de_write(display, FBC_CONTROL, fbc_ctl);
>
> /* Wait for compressing bit to clear */
> - if (intel_de_wait_for_clear(display, FBC_STATUS,
> - FBC_STAT_COMPRESSING, 10)) {
> + if (intel_de_wait_for_clear_ms(display, FBC_STATUS,
> + FBC_STAT_COMPRESSING, 10)) {
> drm_dbg_kms(display->drm, "FBC idle timed out\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> index f162614a925d..1e9550cb66a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -163,10 +163,10 @@ static void intel_flipq_preempt(struct intel_crtc
> *crtc, bool preempt)
> PIPEDMC_FQ_CTRL_PREEMPT, preempt ?
> PIPEDMC_FQ_CTRL_PREEMPT : 0);
>
> if (preempt &&
> - intel_de_wait_for_clear(display,
> - PIPEDMC_FQ_STATUS(crtc->pipe),
> - PIPEDMC_FQ_STATUS_BUSY,
> - intel_flipq_preempt_timeout_ms(display)))
> + intel_de_wait_for_clear_ms(display,
> + PIPEDMC_FQ_STATUS(crtc->pipe),
> + PIPEDMC_FQ_STATUS_BUSY,
> +
> intel_flipq_preempt_timeout_ms(display)))
> drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt
> timeout\n",
> crtc->base.base.id, crtc->base.name);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 82f3a40ecac7..795012d7c24c 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -449,7 +449,7 @@ gmbus_wait_idle(struct intel_display *display)
> add_wait_queue(&display->gmbus.wait_queue, &wait);
> intel_de_write_fw(display, GMBUS4(display), irq_enable);
>
> - ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0,
> 10, NULL);
> + ret = intel_de_wait_fw_ms(display, GMBUS2(display),
> GMBUS_ACTIVE, 0, 10, NULL);
>
> intel_de_write_fw(display, GMBUS4(display), 0);
> remove_wait_queue(&display->gmbus.wait_queue, &wait);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index d01733b6460e..78c34466e402 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -428,7 +428,7 @@ static int intel_hdcp_load_keys(struct intel_display
> *display)
> static int intel_write_sha_text(struct intel_display *display, u32 sha_text)
> {
> intel_de_write(display, HDCP_SHA_TEXT, sha_text);
> - if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY,
> 1)) {
> + if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
> HDCP_SHA1_READY, 1)) {
> drm_err(display->drm, "Timed out waiting for SHA1
> ready\n");
> return -ETIMEDOUT;
> }
> @@ -707,8 +707,8 @@ int intel_hdcp_validate_v_prime(struct
> intel_connector *connector,
> /* Tell the HW we're done with the hash and wait for it to ACK */
> intel_de_write(display, HDCP_REP_CTL,
> rep_ctl | HDCP_SHA1_COMPLETE_HASH);
> - if (intel_de_wait_for_set(display, HDCP_REP_CTL,
> - HDCP_SHA1_COMPLETE, 1)) {
> + if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
> + HDCP_SHA1_COMPLETE, 1)) {
> drm_err(display->drm, "Timed out waiting for SHA1
> complete\n");
> return -ETIMEDOUT;
> }
> @@ -856,9 +856,9 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> HDCP_CONF_CAPTURE_AN);
>
> /* Wait for An to be acquired */
> - if (intel_de_wait_for_set(display,
> - HDCP_STATUS(display, cpu_transcoder,
> port),
> - HDCP_STATUS_AN_READY, 1)) {
> + if (intel_de_wait_for_set_ms(display,
> + HDCP_STATUS(display, cpu_transcoder,
> port),
> + HDCP_STATUS_AN_READY, 1)) {
> drm_err(display->drm, "Timed out waiting for An\n");
> return -ETIMEDOUT;
> }
> @@ -953,10 +953,10 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> }
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait_for_set(display,
> - HDCP_STATUS(display, cpu_transcoder,
> port),
> - HDCP_STATUS_ENC,
> -
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + if (intel_de_wait_for_set_ms(display,
> + HDCP_STATUS(display, cpu_transcoder,
> port),
> + HDCP_STATUS_ENC,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(display->drm, "Timed out waiting for encryption\n");
> return -ETIMEDOUT;
> }
> @@ -1013,9 +1013,9 @@ static int _intel_hdcp_disable(struct
> intel_connector *connector)
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),
> 0);
> - if (intel_de_wait_for_clear(display,
> - HDCP_STATUS(display, cpu_transcoder,
> port),
> - ~0,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> + HDCP_STATUS(display, cpu_transcoder,
> port),
> + ~0,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(display->drm,
> "Failed to disable HDCP, timeout clearing status\n");
> return -ETIMEDOUT;
> @@ -1940,11 +1940,10 @@ static int hdcp2_enable_encryption(struct
> intel_connector *connector)
> intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder,
> port),
> 0, CTL_LINK_ENCRYPTION_REQ);
>
> - ret = intel_de_wait_for_set(display,
> - HDCP2_STATUS(display, cpu_transcoder,
> - port),
> - LINK_ENCRYPTION_STATUS,
> -
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + ret = intel_de_wait_for_set_ms(display,
> + HDCP2_STATUS(display, cpu_transcoder,
> port),
> + LINK_ENCRYPTION_STATUS,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> dig_port->hdcp.auth_status = true;
>
> return ret;
> @@ -1966,11 +1965,10 @@ static int hdcp2_disable_encryption(struct
> intel_connector *connector)
> intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
> CTL_LINK_ENCRYPTION_REQ, 0);
>
> - ret = intel_de_wait_for_clear(display,
> - HDCP2_STATUS(display, cpu_transcoder,
> - port),
> - LINK_ENCRYPTION_STATUS,
> -
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + ret = intel_de_wait_for_clear_ms(display,
> + HDCP2_STATUS(display,
> cpu_transcoder, port),
> + LINK_ENCRYPTION_STATUS,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> if (ret == -ETIMEDOUT)
> drm_dbg_kms(display->drm, "Disable Encryption Timedout");
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 5c637341b210..908faf17f93d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1598,8 +1598,8 @@ bool intel_hdmi_hdcp_check_link_once(struct
> intel_digital_port *dig_port,
> intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port),
> ri.reg);
>
> /* Wait for Ri prime match */
> - ret = intel_de_wait_for_set(display, HDCP_STATUS(display,
> cpu_transcoder, port),
> - HDCP_STATUS_RI_MATCH |
> HDCP_STATUS_ENC, 1);
> + ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display,
> cpu_transcoder, port),
> + HDCP_STATUS_RI_MATCH |
> HDCP_STATUS_ENC, 1);
> if (ret) {
> drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
> intel_de_read(display, HDCP_STATUS(display,
> cpu_transcoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index b2413b385dc8..6bd42691de8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1067,9 +1067,9 @@ static int __intel_lt_phy_p2p_write_once(struct
> intel_encoder *encoder,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> -
> XELPDP_PORT_P2P_TRANSACTION_PENDING,
> - XELPDP_MSGBUS_TIMEOUT_MS)) {
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +
> XELPDP_PORT_P2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_MS)) {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to
> complete. Resetting bus.\n",
> phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 48f4d8ed4f15..89aeb4fb340e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -329,7 +329,7 @@ static void intel_enable_lvds(struct intel_atomic_state
> *state,
> intel_de_rmw(display, PP_CONTROL(display, 0), 0,
> PANEL_POWER_ON);
> intel_de_posting_read(display, lvds_encoder->reg);
>
> - if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON,
> 5000))
> + if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON,
> 5000))
> drm_err(display->drm,
> "timed out waiting for panel to power on\n");
>
> @@ -345,7 +345,7 @@ static void intel_disable_lvds(struct
> intel_atomic_state *state,
> struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
>
> intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON,
> 0);
> - if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_ON,
> 1000))
> + if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON,
> 1000))
> drm_err(display->drm,
> "timed out waiting for panel to power off\n");
>
> @@ -384,7 +384,7 @@ static void intel_lvds_shutdown(struct intel_encoder
> *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
>
> - if (intel_de_wait_for_clear(display, PP_STATUS(display, 0),
> PP_CYCLE_DELAY_ACTIVE, 5000))
> + if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0),
> PP_CYCLE_DELAY_ACTIVE, 5000))
> drm_err(display->drm,
> "timed out waiting for panel power cycle delay\n");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 3456c794e0e7..16619f7be5f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -305,7 +305,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> }
>
> intel_de_write(display, reg, val | TRANS_ENABLE);
> - if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
> + if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE,
> 100))
> drm_err(display->drm, "failed to enable transcoder %c\n",
> pipe_name(pipe));
> }
> @@ -326,7 +326,7 @@ static void ilk_disable_pch_transcoder(struct
> intel_crtc *crtc)
> reg = PCH_TRANSCONF(pipe);
> intel_de_rmw(display, reg, TRANS_ENABLE, 0);
> /* wait for PCH transcoder off, transcoder state */
> - if (intel_de_wait_for_clear(display, reg, TRANS_STATE_ENABLE, 50))
> + if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE,
> 50))
> drm_err(display->drm, "failed to disable transcoder %c\n",
> pipe_name(pipe));
>
> @@ -572,8 +572,8 @@ static void lpt_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> val |= TRANS_INTERLACE_PROGRESSIVE;
>
> intel_de_write(display, LPT_TRANSCONF, val);
> - if (intel_de_wait_for_set(display, LPT_TRANSCONF,
> - TRANS_STATE_ENABLE, 100))
> + if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
> + TRANS_STATE_ENABLE, 100))
> drm_err(display->drm, "Failed to enable PCH transcoder\n");
> }
>
> @@ -581,8 +581,8 @@ static void lpt_disable_pch_transcoder(struct
> intel_display *display)
> {
> intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);
> /* wait for PCH transcoder off, transcoder state */
> - if (intel_de_wait_for_clear(display, LPT_TRANSCONF,
> - TRANS_STATE_ENABLE, 50))
> + if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
> + TRANS_STATE_ENABLE, 50))
> drm_err(display->drm, "Failed to disable PCH transcoder\n");
>
> /* Workaround: clear timing override bit. */
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index 22d8f720ae7d..3cc89048b027 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -390,12 +390,12 @@ int intel_pmdemand_atomic_check(struct
> intel_atomic_state *state)
>
> static bool intel_pmdemand_check_prev_transaction(struct intel_display
> *display)
> {
> - return !(intel_de_wait_for_clear(display,
> -
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> - XELPDP_PMDEMAND_REQ_ENABLE,
> 10) ||
> - intel_de_wait_for_clear(display,
> - GEN12_DCPR_STATUS_1,
> -
> XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> + return !(intel_de_wait_for_clear_ms(display,
> +
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> +
> XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
> + intel_de_wait_for_clear_ms(display,
> + GEN12_DCPR_STATUS_1,
> +
> XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> }
>
> void
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 00b06771ae2d..00ac652809cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2277,8 +2277,8 @@ static void intel_psr_wait_exit_locked(struct
> intel_dp *intel_dp)
> }
>
> /* Wait till PSR is idle */
> - if (intel_de_wait_for_clear(display, psr_status,
> - psr_status_mask, 2000))
> + if (intel_de_wait_for_clear_ms(display, psr_status,
> + psr_status_mask, 2000))
> drm_err(display->drm, "Timed out waiting PSR idle state\n");
> }
>
> @@ -3166,7 +3166,7 @@ _psr2_ready_for_pipe_update_locked(const struct
> intel_crtc_state *new_crtc_state
> return true;
> }
>
> - return intel_de_wait_for_clear(display,
> + return intel_de_wait_for_clear_ms(display,
> EDP_PSR2_STATUS(display,
> cpu_transcoder),
> EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
> PSR_IDLE_TIMEOUT_MS);
> @@ -3186,7 +3186,7 @@ _psr1_ready_for_pipe_update_locked(const struct
> intel_crtc_state *new_crtc_state
> return true;
> }
>
> - return intel_de_wait_for_clear(display,
> + return intel_de_wait_for_clear_ms(display,
> psr_status_reg(display, cpu_transcoder),
> EDP_PSR_STATUS_STATE_MASK,
> PSR_IDLE_TIMEOUT_MS);
> @@ -3264,7 +3264,7 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
>
> mutex_unlock(&intel_dp->psr.lock);
>
> - err = intel_de_wait_for_clear(display, reg, mask, 50);
> + err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
> if (err)
> drm_err(display->drm,
> "Timed out waiting for PSR Idle for re-enable\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_sbi.c
> b/drivers/gpu/drm/i915/display/intel_sbi.c
> index dfcff924f0ed..b636a0060d39 100644
> --- a/drivers/gpu/drm/i915/display/intel_sbi.c
> +++ b/drivers/gpu/drm/i915/display/intel_sbi.c
> @@ -21,7 +21,8 @@ static int intel_sbi_rw(struct intel_display *display, u16
> reg,
>
> lockdep_assert_held(&display->sbi.lock);
>
> - if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK,
> SBI_STATUS_READY, 100, NULL)) {
> + if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
> + SBI_STATUS_MASK, SBI_STATUS_READY, 100,
> NULL)) {
> drm_err(display->drm, "timeout waiting for SBI to become
> ready\n");
> return -EBUSY;
> }
> @@ -37,7 +38,8 @@ static int intel_sbi_rw(struct intel_display *display, u16
> reg,
> cmd |= SBI_CTL_OP_WR;
> intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);
>
> - if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK,
> SBI_STATUS_READY, 100, &cmd)) {
> + if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
> + SBI_STATUS_MASK, SBI_STATUS_READY, 100,
> &cmd)) {
> drm_err(display->drm, "timeout waiting for SBI to complete
> read\n");
> return -ETIMEDOUT;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 4f028e6a91cd..295030742294 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -42,8 +42,8 @@ void intel_snps_phy_wait_for_calibration(struct
> intel_display *display)
> * which phy was affected and skip setup of the corresponding
> * output later.
> */
> - if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),
> - DG2_PHY_DP_TX_ACK_MASK, 25))
> + if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
> + DG2_PHY_DP_TX_ACK_MASK,
> 25))
> display->snps.phy_failed_calibration |= BIT(phy);
> }
> }
> @@ -1863,7 +1863,7 @@ void intel_mpllb_enable(struct intel_encoder
> *encoder,
> * is locked at new settings. This register bit is sampling PHY
> * dp_mpllb_state interface signal.
> */
> - if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5))
> + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
> drm_dbg_kms(display->drm, "Port %c PLL not locked\n",
> phy_name(phy));
>
> /*
> @@ -1903,7 +1903,7 @@ void intel_mpllb_disable(struct intel_encoder
> *encoder)
> * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
> * (dp_txX_ack) that the new transmitter setting request is completed.
> */
> - if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5))
> + if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
> drm_err(display->drm, "Port %c PLL not locked\n",
> phy_name(phy));
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 7e17ca018748..1e21fd02685d 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -1076,8 +1076,8 @@ xelpdp_tc_phy_wait_for_tcss_power(struct
> intel_tc_port *tc, bool enabled)
> static void xelpdp_tc_power_request_wa(struct intel_display *display, bool
> enable)
> {
> /* check if mailbox is running busy */
> - if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
> - TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY,
> 10)) {
> + if (intel_de_wait_for_clear_ms(display,
> TCSS_DISP_MAILBOX_IN_CMD,
> +
> TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
> drm_dbg_kms(display->drm,
> "Timeout waiting for TCSS mailbox run/busy bit to
> clear\n");
> return;
> @@ -1089,8 +1089,8 @@ static void xelpdp_tc_power_request_wa(struct
> intel_display *display, bool enabl
> TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1));
>
> /* wait to clear mailbox running busy bit before continuing */
> - if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
> - TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY,
> 10)) {
> + if (intel_de_wait_for_clear_ms(display,
> TCSS_DISP_MAILBOX_IN_CMD,
> +
> TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
> drm_dbg_kms(display->drm,
> "Timeout after writing data to mailbox. Mailbox
> run/busy bit did not clear\n");
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 00cbc126fb36..b92c42fde937 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -716,9 +716,9 @@ static void intel_vrr_tg_disable(const struct
> intel_crtc_state *old_crtc_state)
> intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> trans_vrr_ctl(old_crtc_state));
>
> - if (intel_de_wait_for_clear(display,
> - TRANS_VRR_STATUS(display,
> cpu_transcoder),
> - VRR_STATUS_VRR_EN_LIVE, 1000))
> + if (intel_de_wait_for_clear_ms(display,
> + TRANS_VRR_STATUS(display,
> cpu_transcoder),
> + VRR_STATUS_VRR_EN_LIVE, 1000))
> drm_err(display->drm, "Timed out waiting for VRR live status
> to clear\n");
>
> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 444682995658..19bdd8662359 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -94,8 +94,8 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi
> *intel_dsi, enum port port)
> mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
> LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
>
> - if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
> - mask, 100))
> + if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display,
> port),
> + mask, 100))
> drm_err(display->drm, "DPI FIFOs are not empty\n");
> }
>
> @@ -162,8 +162,8 @@ static ssize_t intel_dsi_host_transfer(struct
> mipi_dsi_host *host,
>
> /* note: this is never true for reads */
> if (packet.payload_length) {
> - if (intel_de_wait_for_clear(display,
> MIPI_GEN_FIFO_STAT(display, port),
> - data_mask, 50))
> + if (intel_de_wait_for_clear_ms(display,
> MIPI_GEN_FIFO_STAT(display, port),
> + data_mask, 50))
> drm_err(display->drm,
> "Timeout waiting for HS/LP DATA FIFO
> !full\n");
>
> @@ -176,8 +176,8 @@ static ssize_t intel_dsi_host_transfer(struct
> mipi_dsi_host *host,
> GEN_READ_DATA_AVAIL);
> }
>
> - if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display,
> port),
> - ctrl_mask, 50)) {
> + if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display,
> port),
> + ctrl_mask, 50)) {
> drm_err(display->drm,
> "Timeout waiting for HS/LP CTRL FIFO !full\n");
> }
> @@ -188,8 +188,8 @@ static ssize_t intel_dsi_host_transfer(struct
> mipi_dsi_host *host,
> /* ->rx_len is set only for reads */
> if (msg->rx_len) {
> data_mask = GEN_READ_DATA_AVAIL;
> - if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display,
> port),
> - data_mask, 50))
> + if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display,
> port),
> + data_mask, 50))
> drm_err(display->drm,
> "Timeout waiting for read data.\n");
>
> @@ -246,7 +246,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi,
> u32 cmd, bool hs,
> intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
>
> mask = SPL_PKT_SENT_INTERRUPT;
> - if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
> mask, 100))
> + if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),
> mask, 100))
> drm_err(display->drm,
> "Video mode command 0x%08x send failed.\n", cmd);
>
> @@ -352,8 +352,8 @@ static bool glk_dsi_enable_io(struct intel_encoder
> *encoder)
>
> /* Wait for Pwr ACK */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> - GLK_MIPIIO_PORT_POWERED, 20))
> + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> port),
> + GLK_MIPIIO_PORT_POWERED, 20))
> drm_err(display->drm, "MIPIO port is
> powergated\n");
> }
>
> @@ -374,8 +374,8 @@ static void glk_dsi_device_ready(struct intel_encoder
> *encoder)
>
> /* Wait for MIPI PHY status bit to set */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> - GLK_PHY_STATUS_PORT_READY, 20))
> + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> port),
> + GLK_PHY_STATUS_PORT_READY,
> 20))
> drm_err(display->drm, "PHY is not ON\n");
> }
>
> @@ -394,8 +394,8 @@ static void glk_dsi_device_ready(struct intel_encoder
> *encoder)
> ULPS_STATE_MASK, ULPS_STATE_ENTER |
> DEVICE_READY);
>
> /* Wait for ULPS active */
> - if (intel_de_wait_for_clear(display, MIPI_CTRL(display,
> port),
> - GLK_ULPS_NOT_ACTIVE,
> 20))
> + if (intel_de_wait_for_clear_ms(display,
> MIPI_CTRL(display, port),
> + GLK_ULPS_NOT_ACTIVE,
> 20))
> drm_err(display->drm, "ULPS not active\n");
>
> /* Exit ULPS */
> @@ -413,16 +413,16 @@ static void glk_dsi_device_ready(struct
> intel_encoder *encoder)
>
> /* Wait for Stop state */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> - GLK_DATA_LANE_STOP_STATE, 20))
> + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> port),
> + GLK_DATA_LANE_STOP_STATE, 20))
> drm_err(display->drm,
> "Date lane not in STOP state\n");
> }
>
> /* Wait for AFE LATCH */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
> - AFE_LATCHOUT, 20))
> + if (intel_de_wait_for_set_ms(display,
> BXT_MIPI_PORT_CTRL(port),
> + AFE_LATCHOUT, 20))
> drm_err(display->drm,
> "D-PHY not entering LP-11 state\n");
> }
> @@ -519,15 +519,15 @@ static void glk_dsi_enter_low_power_mode(struct
> intel_encoder *encoder)
>
> /* Wait for MIPI PHY status bit to unset */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> - GLK_PHY_STATUS_PORT_READY,
> 20))
> + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> port),
> + GLK_PHY_STATUS_PORT_READY,
> 20))
> drm_err(display->drm, "PHY is not turning OFF\n");
> }
>
> /* Wait for Pwr ACK bit to unset */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> - GLK_MIPIIO_PORT_POWERED, 20))
> + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> port),
> + GLK_MIPIIO_PORT_POWERED,
> 20))
> drm_err(display->drm,
> "MIPI IO Port is not powergated\n");
> }
> @@ -544,8 +544,8 @@ static void glk_dsi_disable_mipi_io(struct
> intel_encoder *encoder)
>
> /* Wait for MIPI PHY status bit to unset */
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> - GLK_PHY_STATUS_PORT_READY,
> 20))
> + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> port),
> + GLK_PHY_STATUS_PORT_READY,
> 20))
> drm_err(display->drm, "PHY is not turning OFF\n");
> }
>
> @@ -595,8 +595,8 @@ static void vlv_dsi_clear_device_ready(struct
> intel_encoder *encoder)
> * Port A only. MIPI Port C has no similar bit for checking.
> */
> if ((display->platform.broxton || port == PORT_A) &&
> - intel_de_wait_for_clear(display, port_ctrl,
> - AFE_LATCHOUT, 30))
> + intel_de_wait_for_clear_ms(display, port_ctrl,
> + AFE_LATCHOUT, 30))
> drm_err(display->drm, "DSI LP not going Low\n");
>
> /* Disable MIPI PHY transparent latch */
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index f078b9cda96c..a2da6285890b 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -319,8 +319,8 @@ void bxt_dsi_pll_disable(struct intel_encoder
> *encoder)
> * PLL lock should deassert within 200us.
> * Wait up to 1ms before timing out.
> */
> - if (intel_de_wait_for_clear(display, BXT_DSI_PLL_ENABLE,
> - BXT_DSI_PLL_LOCKED, 1))
> + if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,
> + BXT_DSI_PLL_LOCKED, 1))
> drm_err(display->drm,
> "Timeout waiting for PLL lock deassertion\n");
> }
> @@ -568,8 +568,8 @@ void bxt_dsi_pll_enable(struct intel_encoder
> *encoder,
> intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0,
> BXT_DSI_PLL_DO_ENABLE);
>
> /* Timeout and fail if PLL not locked */
> - if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE,
> - BXT_DSI_PLL_LOCKED, 1)) {
> + if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,
> + BXT_DSI_PLL_LOCKED, 1)) {
> drm_err(display->drm,
> "Timed out waiting for DSI PLL to lock\n");
> return;
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us()
2025-11-10 17:27 ` [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us() Ville Syrjala
@ 2025-11-11 4:24 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:24 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Introduce intel_de_wait_us() as the microsecond based counterpart to the
> millisecond based intel_de_wait_ms().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index d449180d1d22..43a4160f760a 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -114,6 +114,23 @@ __intel_de_wait_for_register_atomic_nowl(struct
> intel_display *display,
> value, fast_timeout_us, 0, NULL); }
>
> +static inline int
> +intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout_us,
> + u32 *out_value)
> +{
> + int ret;
> +
> + intel_dmc_wl_get(display, reg);
> +
> + ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
> + value, timeout_us, 0, out_value);
> +
> + intel_dmc_wl_put(display, reg);
> +
> + return ret;
> +}
> +
> static inline int
> intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
> u32 mask, u32 value, unsigned int timeout_ms,
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 05/16] drm/i915/de: Use intel_de_wait_us()
2025-11-10 17:27 ` [PATCH 05/16] drm/i915/de: Use intel_de_wait_us() Ville Syrjala
@ 2025-11-11 4:28 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 05/16] drm/i915/de: Use intel_de_wait_us()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Convert some of the intel_de_wait_custom() users over to intel_de_wait_us().
> We'll eventually want to eliminate
> intel_de_wait_custom() as it's a hinderance towards using poll_timeout_us().
>
> This includes all the obvious cases where we only specify a microsecond
> timeout to intel_de_wait_custom().
>
> Done with cocci (with manual formatting fixes):
> @@
> expression display, reg, mask, value, timeout_us, out_value; @@
> - intel_de_wait_custom(display, reg, mask, value, timeout_us, 0, out_value)
> + intel_de_wait_us(display, reg, mask, value, timeout_us, out_value)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 27 +++++------
> drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++--
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 48 +++++++++----------
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +---
> .../drm/i915/display/intel_display_power.c | 11 ++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 +++----
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 19 ++++----
> .../gpu/drm/i915/display/intel_pch_refclk.c | 11 ++---
> 8 files changed, 67 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6a11b3bb219b..151266ffd582 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -148,9 +148,8 @@ static void
> wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
>
> - ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
> - LPTX_IN_PROGRESS, 0,
> - 20, 0, NULL);
> + ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
> + LPTX_IN_PROGRESS, 0, 20, NULL);
> if (ret)
> drm_err(display->drm, "LPTX bit not cleared\n");
> }
> @@ -534,9 +533,8 @@ static void gen11_dsi_enable_ddi_buffer(struct
> intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> intel_de_rmw(display, DDI_BUF_CTL(port), 0,
> DDI_BUF_CTL_ENABLE);
>
> - ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
> - DDI_BUF_IS_IDLE, 0,
> - 500, 0, NULL);
> + ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
> + DDI_BUF_IS_IDLE, 0, 500, NULL);
> if (ret)
> drm_err(display->drm, "DDI port:%c buffer idle\n",
> port_name(port));
> @@ -857,9 +855,9 @@ gen11_dsi_configure_transcoder(struct
> intel_encoder *encoder,
>
> dsi_trans = dsi_port_to_transcoder(port);
>
> - ret = intel_de_wait_custom(display,
> DSI_TRANS_FUNC_CONF(dsi_trans),
> - LINK_READY, LINK_READY,
> - 2500, 0, NULL);
> + ret = intel_de_wait_us(display,
> + DSI_TRANS_FUNC_CONF(dsi_trans),
> + LINK_READY, LINK_READY, 2500, NULL);
> if (ret)
> drm_err(display->drm, "DSI link not ready\n");
> }
> @@ -1358,9 +1356,8 @@ static void
> gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> tmp &= ~LINK_ULPS_TYPE_LP11;
> intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
>
> - ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
> - LINK_IN_ULPS, LINK_IN_ULPS,
> - 10, 0, NULL);
> + ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
> + LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
> if (ret)
> drm_err(display->drm, "DSI link not in ULPS\n");
> }
> @@ -1395,9 +1392,9 @@ static void gen11_dsi_disable_port(struct
> intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> intel_de_rmw(display, DDI_BUF_CTL(port),
> DDI_BUF_CTL_ENABLE, 0);
>
> - ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
> - DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,
> - 8, 0, NULL);
> + ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
> + DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
> + NULL);
>
> if (ret)
> drm_err(display->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c0d798b1cf46..f7daebccb10f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -902,9 +902,8 @@ static void bdw_set_cdclk(struct intel_display
> *display,
> * According to the spec, it should be enough to poll for this 1 us.
> * However, extensive testing shows that this can take longer.
> */
> - ret = intel_de_wait_custom(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE,
> LCPLL_CD_SOURCE_FCLK_DONE,
> - 100, 0, NULL);
> + ret = intel_de_wait_us(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK_DONE,
> + LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
> if (ret)
> drm_err(display->drm, "Switching to FCLK failed\n");
>
> @@ -914,9 +913,8 @@ static void bdw_set_cdclk(struct intel_display
> *display,
> intel_de_rmw(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK, 0);
>
> - ret = intel_de_wait_custom(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE, 0,
> - 1, 0, NULL);
> + ret = intel_de_wait_us(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK_DONE,
> + 0, 1, NULL);
> if (ret)
> drm_err(display->drm, "Switching back to LCPLL failed\n");
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 7870823235c7..af97bd42495b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2888,10 +2888,10 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
>
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> :
> XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display,
> port),
> - XELPDP_PORT_BUF_SOC_PHY_READY,
> - XELPDP_PORT_BUF_SOC_PHY_READY,
> -
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US,
> NULL))
> drm_warn(display->drm,
> "PHY %c failed to bring out of SOC reset\n",
> phy_name(phy));
> @@ -2899,9 +2899,9 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
> intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_pipe_reset,
> lane_pipe_reset);
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> - lane_phy_current_status,
> lane_phy_current_status,
> - XELPDP_PORT_RESET_START_TIMEOUT_US,
> 0, NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status, lane_phy_current_status,
> + XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
> drm_warn(display->drm,
> "PHY %c failed to bring out of lane reset\n",
> phy_name(phy));
> @@ -2910,10 +2910,10 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
> intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> intel_cx0_get_pclk_refclk_request(lane_mask));
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> -
> intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> - intel_cx0_get_pclk_refclk_ack(lane_mask),
> - XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0,
> NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
> + intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> + intel_cx0_get_pclk_refclk_ack(lane_mask),
> + XELPDP_REFCLK_ENABLE_TIMEOUT_US, NULL))
> drm_warn(display->drm,
> "PHY %c failed to request refclk\n",
> phy_name(phy));
> @@ -3064,10 +3064,10 @@ static void __intel_cx0pll_enable(struct
> intel_encoder *encoder,
> intel_cx0_get_pclk_pll_request(maxpclk_lane));
>
> /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK>
> == "1". */
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> -
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> - intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> - XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0,
> NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> +
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> + XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
> drm_warn(display->drm, "Port %c PLL not locked\n",
> phy_name(phy));
>
> @@ -3188,10 +3188,8 @@ void intel_mtl_tbt_pll_enable(struct
> intel_encoder *encoder,
> intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> >port), val);
>
> /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> - XELPDP_TBT_CLOCK_ACK,
> - XELPDP_TBT_CLOCK_ACK,
> - 100, 0, NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> + XELPDP_TBT_CLOCK_ACK,
> XELPDP_TBT_CLOCK_ACK, 100, NULL))
> drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> locked\n",
> encoder->base.base.id, encoder->base.name,
> phy_name(phy));
>
> @@ -3302,10 +3300,10 @@ static void intel_cx0pll_disable(struct
> intel_encoder *encoder)
> /*
> * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**>
> == "0".
> */
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> -
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> -
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> - XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0,
> NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> +
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> +
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> + XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
> drm_warn(display->drm, "Port %c PLL not unlocked\n",
> phy_name(phy));
>
> @@ -3350,8 +3348,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder
> *encoder)
> XELPDP_TBT_CLOCK_REQUEST, 0);
>
> /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> - XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> + XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
> drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> unlocked\n",
> encoder->base.base.id, encoder->base.name,
> phy_name(phy));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 33fca83c22b3..3b2d2b51ebc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2577,9 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder
> *encoder)
>
> intel_de_rmw(display, reg, 0, set_bits);
>
> - ret = intel_de_wait_custom(display, reg,
> - wait_bits, wait_bits,
> - 100, 0, NULL);
> + ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
> if (ret) {
> drm_err(display->drm, "Timeout waiting for D2D Link enable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> @@ -3079,9 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder
> *encoder)
>
> intel_de_rmw(display, reg, clr_bits, 0);
>
> - ret = intel_de_wait_custom(display, reg,
> - wait_bits, 0,
> - 100, 0, NULL);
> + ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
> if (ret)
> drm_err(display->drm, "Timeout waiting for D2D Link disable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2b86a634c1f5..cc701f8277b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1292,9 +1292,9 @@ static void hsw_disable_lcpll(struct intel_display
> *display,
> val |= LCPLL_CD_SOURCE_FCLK;
> intel_de_write(display, LCPLL_CTL, val);
>
> - ret = intel_de_wait_custom(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE,
> LCPLL_CD_SOURCE_FCLK_DONE,
> - 1, 0, NULL);
> + ret = intel_de_wait_us(display, LCPLL_CTL,
> + LCPLL_CD_SOURCE_FCLK_DONE,
> + LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
> if (ret)
> drm_err(display->drm, "Switching to FCLK failed\n");
>
> @@ -1368,9 +1368,8 @@ static void hsw_restore_lcpll(struct intel_display
> *display)
> if (val & LCPLL_CD_SOURCE_FCLK) {
> intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK,
> 0);
>
> - ret = intel_de_wait_custom(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE, 0,
> - 1, 0, NULL);
> + ret = intel_de_wait_us(display, LCPLL_CTL,
> + LCPLL_CD_SOURCE_FCLK_DONE, 0, 1,
> NULL);
> if (ret)
> drm_err(display->drm,
> "Switching back to LCPLL failed\n"); diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 683bc61c03c1..1cc1a862c50b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
> 0, PORT_PLL_POWER_ENABLE);
>
> - ret = intel_de_wait_custom(display,
> BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_POWER_STATE,
> PORT_PLL_POWER_STATE,
> - 200, 0, NULL);
> + ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_POWER_STATE,
> + PORT_PLL_POWER_STATE, 200, NULL);
> if (ret)
> drm_err(display->drm,
> "Power state not set for PLL:%d\n", port);
> @@ -2122,9 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0,
> PORT_PLL_ENABLE);
> intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
>
> - ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_LOCK, PORT_PLL_LOCK,
> - 200, 0, NULL);
> + ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
> if (ret)
> drm_err(display->drm, "PLL %d not locked\n", port);
>
> @@ -2158,9 +2157,8 @@ static void bxt_ddi_pll_disable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
> PORT_PLL_POWER_ENABLE, 0);
>
> - ret = intel_de_wait_custom(display,
> BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_POWER_STATE, 0,
> - 200, 0, NULL);
> + ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_POWER_STATE, 0, 200, NULL);
> if (ret)
> drm_err(display->drm,
> "Power state not reset for PLL:%d\n", port);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6bd42691de8f..243fca1c6a2d 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1982,9 +1982,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
>
> /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> - if (intel_de_wait_custom(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> - XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> -
> XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
> + if (intel_de_wait_us(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> +
> XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack
> deassertion timeout\n",
> phy_name(phy));
>
> @@ -2089,10 +2089,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder
> *encoder)
> lane_pipe_reset);
>
> /* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY
> Current Status == 1. */
> - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> - lane_phy_current_status,
> - lane_phy_current_status,
> - XE3PLPD_RESET_START_LATENCY_US, 0,
> NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status, lane_phy_current_status,
> + XE3PLPD_RESET_START_LATENCY_US, NULL))
> drm_warn(display->drm, "PHY %c failed to reset lane\n",
> phy_name(phy));
>
> @@ -2113,9 +2112,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder
> *encoder)
> intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
>
> /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> - XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> - XE3PLPD_MACCLK_TURNOFF_LATENCY_US,
> 0, NULL))
> + if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> + XE3PLPD_MACCLK_TURNOFF_LATENCY_US,
> NULL))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion
> timeout\n",
> phy_name(phy));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index cca880c7eed4..ebf2d1c34b3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -21,17 +21,16 @@ static void lpt_fdi_reset_mphy(struct intel_display
> *display)
>
> intel_de_rmw(display, SOUTH_CHICKEN2, 0,
> FDI_MPHY_IOSFSB_RESET_CTL);
>
> - ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
> - FDI_MPHY_IOSFSB_RESET_STATUS,
> FDI_MPHY_IOSFSB_RESET_STATUS,
> - 100, 0, NULL);
> + ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
> + FDI_MPHY_IOSFSB_RESET_STATUS,
> + FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
> if (ret)
> drm_err(display->drm, "FDI mPHY reset assert timeout\n");
>
> intel_de_rmw(display, SOUTH_CHICKEN2,
> FDI_MPHY_IOSFSB_RESET_CTL, 0);
>
> - ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
> - FDI_MPHY_IOSFSB_RESET_STATUS, 0,
> - 100, 0, NULL);
> + ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
> + FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
> if (ret)
> drm_err(display->drm, "FDI mPHY reset de-assert
> timeout\n"); }
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases
2025-11-10 17:27 ` [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases Ville Syrjala
@ 2025-11-11 4:32 ` Kandpal, Suraj
2025-11-11 17:41 ` Ville Syrjälä
0 siblings, 1 reply; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:32 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious
> cases
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Replace some users of intel_de_wait_custom() with intel_de_wait_ms().
>
> This includes the cases where we pass in the default 2 microsecond fast
> timeout, which is also what intel_de_wait_ms() uses so there are no functional
> changes here.
>
> Done with cocci (with manual formatting fixes):
> @@
> expression display, reg, mask, value, timeout_ms, out_value; @@
> - intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value)
> + intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 15 ++++-----
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 ++--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 5 ++-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 32 +++++++++----------
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 6 ++--
> 5 files changed, 30 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index af97bd42495b..55fd95994ea7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -164,11 +164,10 @@ int intel_cx0_wait_for_ack(struct intel_encoder
> *encoder,
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> - if (intel_de_wait_custom(display,
> -
> XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
> - XELPDP_PORT_P2M_RESPONSE_READY,
> - XELPDP_PORT_P2M_RESPONSE_READY,
> - 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
> + if (intel_de_wait_ms(display,
> XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_MSGBUS_TIMEOUT_MS, val)) {
> drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for message ACK. Status:
> 0x%x\n",
> phy_name(phy), *val);
> @@ -2827,9 +2826,9 @@ void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> intel_cx0_get_powerdown_update(lane_mask));
>
> /* Update Timeout Value */
> - if (intel_de_wait_custom(display, buf_ctl2_reg,
> -
> intel_cx0_get_powerdown_update(lane_mask), 0,
> - 2,
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
> + if (intel_de_wait_ms(display, buf_ctl2_reg,
> + intel_cx0_get_powerdown_update(lane_mask), 0,
> +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
> drm_warn(display->drm,
> "PHY %c failed to bring out of lane reset\n",
> phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 2e7dbaf511b9..809799f63e32 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -62,9 +62,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> u32 status;
> int ret;
>
> - ret = intel_de_wait_custom(display, ch_ctl,
> DP_AUX_CH_CTL_SEND_BUSY,
> - 0,
> - 2, timeout_ms, &status);
> + ret = intel_de_wait_ms(display, ch_ctl,
> + DP_AUX_CH_CTL_SEND_BUSY, 0,
> + timeout_ms, &status);
>
> if (ret == -ETIMEDOUT)
> drm_err(display->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 78c34466e402..5e1a96223a9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -410,9 +410,8 @@ static int intel_hdcp_load_keys(struct intel_display
> *display)
> }
>
> /* Wait for the keys to load (500us) */
I would prefer this comment be changed/ removed since we now wait 1 ms
for the keys to load
other than that
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> - ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
> - HDCP_KEY_LOAD_DONE,
> HDCP_KEY_LOAD_DONE,
> - 2, 1, &val);
> + ret = intel_de_wait_ms(display, HDCP_KEY_STATUS,
> HDCP_KEY_LOAD_DONE,
> + HDCP_KEY_LOAD_DONE, 1, &val);
> if (ret)
> return ret;
> else if (!(val & HDCP_KEY_LOAD_STATUS)) diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 243fca1c6a2d..ac6f61107528 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1201,10 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0),
> XELPDP_LANE_PCLK_PLL_REQUEST(0));
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> - 2,
> XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> + if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> XELPDP_LANE_PCLK_PLL_ACK(0),
> + XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack
> not done\n",
> phy_name(phy));
>
> @@ -1215,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_pipe_reset | lane_phy_pulse_status, 0);
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> - lane_phy_current_status, 0,
> - 2, XE3PLPD_RESET_END_LATENCY_MS,
> NULL))
> + if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status, 0,
> + XE3PLPD_RESET_END_LATENCY_MS, NULL))
> drm_warn(display->drm, "PHY %c failed to bring out of lane
> reset\n",
> phy_name(phy));
>
> - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> - lane_phy_pulse_status,
> lane_phy_pulse_status,
> - 2,
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> + if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_pulse_status, lane_phy_pulse_status,
> + XE3PLPD_RATE_CALIB_DONE_LATENCY_MS,
> NULL))
> drm_warn(display->drm, "PHY %c PLL rate not changed\n",
> phy_name(phy));
>
> @@ -2002,10 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0));
>
> /* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> - if (intel_de_wait_custom(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> - 2,
> XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> + if (intel_de_wait_ms(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> XELPDP_LANE_PCLK_PLL_ACK(0),
> +
> XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack
> assertion timeout\n",
> phy_name(phy));
>
> @@ -2031,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> rate_update, MB_WRITE_COMMITTED);
>
> /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> for Owned PHY Lanes. */
> - if (intel_de_wait_custom(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_pulse_status,
> lane_phy_pulse_status,
> - 2,
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> + if (intel_de_wait_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_pulse_status,
> lane_phy_pulse_status,
> +
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> drm_warn(display->drm, "PHY %c PLL rate not
> changed\n",
> phy_name(phy));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index 3cc89048b027..dc44a7a169c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -462,9 +462,9 @@ static void intel_pmdemand_poll(struct intel_display
> *display)
> u32 status;
> int ret;
>
> - ret = intel_de_wait_custom(display,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> - XELPDP_PMDEMAND_REQ_ENABLE, 0,
> - 2, timeout_ms, &status);
> + ret = intel_de_wait_ms(display,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> + XELPDP_PMDEMAND_REQ_ENABLE, 0,
> + timeout_ms, &status);
>
> if (ret == -ETIMEDOUT)
> drm_err(display->drm,
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom()
2025-11-10 17:27 ` [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom() Ville Syrjala
@ 2025-11-11 4:33 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:33 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_de_wait_custom() is finally unused. Get rid of it before people start
> abusing it more.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 19 -------------------
> 1 file changed, 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 43a4160f760a..2566079f695e 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -165,25 +165,6 @@ intel_de_wait_fw_ms(struct intel_display *display,
> i915_reg_t reg,
> return ret;
> }
>
> -static inline int
> -intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value,
> - unsigned int fast_timeout_us,
> - unsigned int slow_timeout_ms, u32 *out_value)
> -{
> - int ret;
> -
> - intel_dmc_wl_get(display, reg);
> -
> - ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
> - value,
> - fast_timeout_us, slow_timeout_ms,
> out_value);
> -
> - intel_dmc_wl_put(display, reg);
> -
> - return ret;
> -}
> -
> static inline int
> intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
> u32 mask, unsigned int timeout_ms)
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us()
2025-11-10 17:27 ` [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us() Ville Syrjala
@ 2025-11-11 4:35 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:35 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set,
> clear}_us()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add intel_de_wait_for_set_us() and intel_de_wait_for_clear_us() as the
> microsecond counterparts to intel_de_wait_for_set_ms() and
> intel_de_wait_for_clear_ms().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 2566079f695e..a82da6443af9 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -165,6 +165,20 @@ intel_de_wait_fw_ms(struct intel_display *display,
> i915_reg_t reg,
> return ret;
> }
>
> +static inline int
> +intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
> + u32 mask, unsigned int timeout_us)
> +{
> + return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
> }
> +
> +static inline int
> +intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
> + u32 mask, unsigned int timeout_us) {
> + return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL); }
> +
> static inline int
> intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
> u32 mask, unsigned int timeout_ms)
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_us()
2025-11-10 17:27 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us() Ville Syrjala
@ 2025-11-11 4:38 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_de_wait_for_{set,clear}_us() instead of
> intel_de_wait_us() where appropriate.
>
> Done with cocci (with manual formatting fixes):
> @@
> identifier func !~ "intel_de_wait_for";
> expression display, reg, mask, timeout_us; @@
> func(...)
> {
> <...
> (
> - intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL)
> + intel_de_wait_for_set_us(display, reg, mask, timeout_us)
> |
> - intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL)
> + intel_de_wait_for_clear_us(display, reg, mask, timeout_us)
> )
> ...>
> }
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++--------
> drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 29 +++++++++----------
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
> .../drm/i915/display/intel_display_power.c | 9 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 +++++-----
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 18 ++++++------
> .../gpu/drm/i915/display/intel_pch_refclk.c | 9 +++---
> 8 files changed, 57 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 151266ffd582..9230792960f2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -148,8 +148,9 @@ static void
> wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
>
> - ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
> - LPTX_IN_PROGRESS, 0, 20, NULL);
> + ret = intel_de_wait_for_clear_us(display,
> + DSI_LP_MSG(dsi_trans),
> + LPTX_IN_PROGRESS, 20);
> if (ret)
> drm_err(display->drm, "LPTX bit not cleared\n");
> }
> @@ -533,8 +534,8 @@ static void gen11_dsi_enable_ddi_buffer(struct
> intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> intel_de_rmw(display, DDI_BUF_CTL(port), 0,
> DDI_BUF_CTL_ENABLE);
>
> - ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
> - DDI_BUF_IS_IDLE, 0, 500, NULL);
> + ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
> + DDI_BUF_IS_IDLE, 500);
> if (ret)
> drm_err(display->drm, "DDI port:%c buffer idle\n",
> port_name(port));
> @@ -855,9 +856,9 @@ gen11_dsi_configure_transcoder(struct
> intel_encoder *encoder,
>
> dsi_trans = dsi_port_to_transcoder(port);
>
> - ret = intel_de_wait_us(display,
> - DSI_TRANS_FUNC_CONF(dsi_trans),
> - LINK_READY, LINK_READY, 2500, NULL);
> + ret = intel_de_wait_for_set_us(display,
> +
> DSI_TRANS_FUNC_CONF(dsi_trans),
> + LINK_READY, 2500);
> if (ret)
> drm_err(display->drm, "DSI link not ready\n");
> }
> @@ -1356,8 +1357,8 @@ static void
> gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> tmp &= ~LINK_ULPS_TYPE_LP11;
> intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
>
> - ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
> - LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
> + ret = intel_de_wait_for_set_us(display,
> DSI_LP_MSG(dsi_trans),
> + LINK_IN_ULPS, 10);
> if (ret)
> drm_err(display->drm, "DSI link not in ULPS\n");
> }
> @@ -1392,9 +1393,8 @@ static void gen11_dsi_disable_port(struct
> intel_encoder *encoder)
> for_each_dsi_port(port, intel_dsi->ports) {
> intel_de_rmw(display, DDI_BUF_CTL(port),
> DDI_BUF_CTL_ENABLE, 0);
>
> - ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
> - DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
> - NULL);
> + ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
> + DDI_BUF_IS_IDLE, 8);
>
> if (ret)
> drm_err(display->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f7daebccb10f..37801c744b05 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -902,8 +902,8 @@ static void bdw_set_cdclk(struct intel_display
> *display,
> * According to the spec, it should be enough to poll for this 1 us.
> * However, extensive testing shows that this can take longer.
> */
> - ret = intel_de_wait_us(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK_DONE,
> - LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
> + ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
> + LCPLL_CD_SOURCE_FCLK_DONE, 100);
> if (ret)
> drm_err(display->drm, "Switching to FCLK failed\n");
>
> @@ -913,8 +913,8 @@ static void bdw_set_cdclk(struct intel_display
> *display,
> intel_de_rmw(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK, 0);
>
> - ret = intel_de_wait_us(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK_DONE,
> - 0, 1, NULL);
> + ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
> + LCPLL_CD_SOURCE_FCLK_DONE, 1);
> if (ret)
> drm_err(display->drm, "Switching back to LCPLL failed\n");
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 55fd95994ea7..68e9009d2556 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2887,10 +2887,9 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
>
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> :
> XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
> - if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
> - XELPDP_PORT_BUF_SOC_PHY_READY,
> - XELPDP_PORT_BUF_SOC_PHY_READY,
> - XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US,
> NULL))
> + if (intel_de_wait_for_set_us(display,
> XELPDP_PORT_BUF_CTL1(display, port),
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> +
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US))
> drm_warn(display->drm,
> "PHY %c failed to bring out of SOC reset\n",
> phy_name(phy));
> @@ -2898,9 +2897,9 @@ static void intel_cx0_phy_lane_reset(struct
> intel_encoder *encoder,
> intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_pipe_reset,
> lane_pipe_reset);
>
> - if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_current_status, lane_phy_current_status,
> - XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
> + if (intel_de_wait_for_set_us(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status,
> +
> XELPDP_PORT_RESET_START_TIMEOUT_US))
> drm_warn(display->drm,
> "PHY %c failed to bring out of lane reset\n",
> phy_name(phy));
> @@ -3187,8 +3186,8 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder
> *encoder,
> intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> >port), val);
>
> /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> - if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> - XELPDP_TBT_CLOCK_ACK,
> XELPDP_TBT_CLOCK_ACK, 100, NULL))
> + if (intel_de_wait_for_set_us(display,
> XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> + XELPDP_TBT_CLOCK_ACK, 100))
> drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> locked\n",
> encoder->base.base.id, encoder->base.name,
> phy_name(phy));
>
> @@ -3299,10 +3298,10 @@ static void intel_cx0pll_disable(struct
> intel_encoder *encoder)
> /*
> * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**>
> == "0".
> */
> - if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> -
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> -
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> - XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
> + if (intel_de_wait_for_clear_us(display,
> XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> +
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
> +
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US))
> drm_warn(display->drm, "Port %c PLL not unlocked\n",
> phy_name(phy));
>
> @@ -3347,8 +3346,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder
> *encoder)
> XELPDP_TBT_CLOCK_REQUEST, 0);
>
> /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> - if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port),
> - XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
> + if (intel_de_wait_for_clear_us(display,
> XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> + XELPDP_TBT_CLOCK_ACK, 10))
> drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> unlocked\n",
> encoder->base.base.id, encoder->base.name,
> phy_name(phy));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3b2d2b51ebc6..002ccd47856d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2577,7 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder
> *encoder)
>
> intel_de_rmw(display, reg, 0, set_bits);
>
> - ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
> + ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);
> if (ret) {
> drm_err(display->drm, "Timeout waiting for D2D Link enable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> @@ -3077,7 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder
> *encoder)
>
> intel_de_rmw(display, reg, clr_bits, 0);
>
> - ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
> + ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);
> if (ret)
> drm_err(display->drm, "Timeout waiting for D2D Link disable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cc701f8277b6..2a4cc1dcc293 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1292,9 +1292,8 @@ static void hsw_disable_lcpll(struct intel_display
> *display,
> val |= LCPLL_CD_SOURCE_FCLK;
> intel_de_write(display, LCPLL_CTL, val);
>
> - ret = intel_de_wait_us(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE,
> - LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
> + ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
> + LCPLL_CD_SOURCE_FCLK_DONE,
> 1);
> if (ret)
> drm_err(display->drm, "Switching to FCLK failed\n");
>
> @@ -1368,8 +1367,8 @@ static void hsw_restore_lcpll(struct intel_display
> *display)
> if (val & LCPLL_CD_SOURCE_FCLK) {
> intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK,
> 0);
>
> - ret = intel_de_wait_us(display, LCPLL_CTL,
> - LCPLL_CD_SOURCE_FCLK_DONE, 0, 1,
> NULL);
> + ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
> +
> LCPLL_CD_SOURCE_FCLK_DONE, 1);
> if (ret)
> drm_err(display->drm,
> "Switching back to LCPLL failed\n"); diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 1cc1a862c50b..9c7cf03cf022 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
> 0, PORT_PLL_POWER_ENABLE);
>
> - ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_POWER_STATE,
> - PORT_PLL_POWER_STATE, 200, NULL);
> + ret = intel_de_wait_for_set_us(display,
> + BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_POWER_STATE, 200);
> if (ret)
> drm_err(display->drm,
> "Power state not set for PLL:%d\n", port);
> @@ -2122,8 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0,
> PORT_PLL_ENABLE);
> intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
>
> - ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
> + ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_LOCK, 200);
> if (ret)
> drm_err(display->drm, "PLL %d not locked\n", port);
>
> @@ -2157,8 +2157,9 @@ static void bxt_ddi_pll_disable(struct intel_display
> *display,
> intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
> PORT_PLL_POWER_ENABLE, 0);
>
> - ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
> - PORT_PLL_POWER_STATE, 0, 200, NULL);
> + ret = intel_de_wait_for_clear_us(display,
> +
> BXT_PORT_PLL_ENABLE(port),
> + PORT_PLL_POWER_STATE,
> 200);
> if (ret)
> drm_err(display->drm,
> "Power state not reset for PLL:%d\n", port);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index ac6f61107528..ac6ff183bc97 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1981,9 +1981,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
>
> /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> - if (intel_de_wait_us(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> - XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> -
> XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
> + if (intel_de_wait_for_clear_us(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> +
> XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack
> deassertion timeout\n",
> phy_name(phy));
>
> @@ -2087,9 +2087,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder
> *encoder)
> lane_pipe_reset);
>
> /* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY
> Current Status == 1. */
> - if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_current_status, lane_phy_current_status,
> - XE3PLPD_RESET_START_LATENCY_US, NULL))
> + if (intel_de_wait_for_set_us(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status,
> + XE3PLPD_RESET_START_LATENCY_US))
> drm_warn(display->drm, "PHY %c failed to reset lane\n",
> phy_name(phy));
>
> @@ -2110,9 +2110,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder
> *encoder)
> intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
>
> /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> - if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
> - XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> - XE3PLPD_MACCLK_TURNOFF_LATENCY_US,
> NULL))
> + if (intel_de_wait_for_clear_us(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> +
> XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion
> timeout\n",
> phy_name(phy));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index ebf2d1c34b3e..9a89bb6dcf65 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -21,16 +21,15 @@ static void lpt_fdi_reset_mphy(struct intel_display
> *display)
>
> intel_de_rmw(display, SOUTH_CHICKEN2, 0,
> FDI_MPHY_IOSFSB_RESET_CTL);
>
> - ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
> - FDI_MPHY_IOSFSB_RESET_STATUS,
> - FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
> + ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2,
> + FDI_MPHY_IOSFSB_RESET_STATUS, 100);
> if (ret)
> drm_err(display->drm, "FDI mPHY reset assert timeout\n");
>
> intel_de_rmw(display, SOUTH_CHICKEN2,
> FDI_MPHY_IOSFSB_RESET_CTL, 0);
>
> - ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
> - FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
> + ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2,
> + FDI_MPHY_IOSFSB_RESET_STATUS,
> 100);
> if (ret)
> drm_err(display->drm, "FDI mPHY reset de-assert
> timeout\n"); }
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_ms()
2025-11-10 17:27 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Ville Syrjala
@ 2025-11-11 4:39 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:39 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_de_wait_for_{set,clear}_ms() instead of
> intel_de_wait_ms() where appropriate.
>
> Done with cocci (with manual formatting fixes):
> @@
> identifier func !~ "intel_de_wait_for";
> expression display, reg, mask, timeout_ms; @@
> func(...)
> {
> <...
> (
> - intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL)
> + intel_de_wait_for_set_ms(display, reg, mask, timeout_ms)
> |
> - intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL)
> + intel_de_wait_for_clear_ms(display, reg, mask, timeout_ms)
> )
> ...>
> }
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++--
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 30 ++++++++++----------
> 2 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 68e9009d2556..d98b4cf6b60e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2826,9 +2826,9 @@ void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> intel_cx0_get_powerdown_update(lane_mask));
>
> /* Update Timeout Value */
> - if (intel_de_wait_ms(display, buf_ctl2_reg,
> - intel_cx0_get_powerdown_update(lane_mask), 0,
> -
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
> + if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg,
> +
> intel_cx0_get_powerdown_update(lane_mask),
> +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS))
> drm_warn(display->drm,
> "PHY %c failed to bring out of lane reset\n",
> phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index ac6ff183bc97..bebd7488aab9 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1201,9 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0),
> XELPDP_LANE_PCLK_PLL_REQUEST(0));
>
> - if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> XELPDP_LANE_PCLK_PLL_ACK(0),
> - XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> + if (intel_de_wait_for_set_ms(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> +
> XE3PLPD_MACCLK_TURNON_LATENCY_MS))
> drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack
> not done\n",
> phy_name(phy));
>
> @@ -1214,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_pipe_reset | lane_phy_pulse_status, 0);
>
> - if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_current_status, 0,
> - XE3PLPD_RESET_END_LATENCY_MS, NULL))
> + if (intel_de_wait_for_clear_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_current_status,
> + XE3PLPD_RESET_END_LATENCY_MS))
> drm_warn(display->drm, "PHY %c failed to bring out of lane
> reset\n",
> phy_name(phy));
>
> - if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_pulse_status, lane_phy_pulse_status,
> - XE3PLPD_RATE_CALIB_DONE_LATENCY_MS,
> NULL))
> + if (intel_de_wait_for_set_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_pulse_status,
> +
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS))
> drm_warn(display->drm, "PHY %c PLL rate not changed\n",
> phy_name(phy));
>
> @@ -2001,9 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> XELPDP_LANE_PCLK_PLL_REQUEST(0));
>
> /* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> - if (intel_de_wait_ms(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> - XELPDP_LANE_PCLK_PLL_ACK(0),
> XELPDP_LANE_PCLK_PLL_ACK(0),
> -
> XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> + if (intel_de_wait_for_set_ms(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> + XELPDP_LANE_PCLK_PLL_ACK(0),
> +
> XE3PLPD_MACCLK_TURNON_LATENCY_MS))
> drm_warn(display->drm, "PHY %c PLL MacCLK ack
> assertion timeout\n",
> phy_name(phy));
>
> @@ -2029,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> rate_update, MB_WRITE_COMMITTED);
>
> /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> for Owned PHY Lanes. */
> - if (intel_de_wait_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> - lane_phy_pulse_status,
> lane_phy_pulse_status,
> -
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> + if (intel_de_wait_for_set_ms(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> + lane_phy_pulse_status,
> +
> XE3PLPD_RATE_CALIB_DONE_LATENCY_MS))
> drm_warn(display->drm, "PHY %c PLL rate not
> changed\n",
> phy_name(phy));
>
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms()
2025-11-10 17:27 ` [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms() Ville Syrjala
@ 2025-11-11 4:41 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> _bxt_dpio_phy_init() doesn't us the _fw() register accessors for anything else,
> so stop using them for the register polling as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 4d1b6e2b93dc..7b7a0461da36 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -427,8 +427,8 @@ static void _bxt_dpio_phy_init(struct intel_display
> *display, enum dpio_phy phy)
> * The flag should get set in 100us according to the HW team, but
> * use 1ms due to occasional timeouts observed with that.
> */
> - if (intel_de_wait_fw_ms(display, BXT_PORT_CL1CM_DW0(phy),
> - PHY_RESERVED | PHY_POWER_GOOD,
> PHY_POWER_GOOD, 1, NULL))
> + if (intel_de_wait_ms(display, BXT_PORT_CL1CM_DW0(phy),
> + PHY_RESERVED | PHY_POWER_GOOD,
> PHY_POWER_GOOD, 1, NULL))
> drm_err(display->drm, "timeout during PHY%d power on\n",
> phy);
>
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw()
2025-11-10 17:27 ` [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw() Ville Syrjala
@ 2025-11-11 4:44 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:44 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with
> intel_de_rmw_fw()
*i915
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already have the lower level intel_de_*_fw() stuff, so use that instead of
> hand rolling something custom for the DMC wakelock stuff.
>
> As the wakelock stuff exists only on platforms supported by the xe driver this
> doesn't even result in any functional changes since xe doesn't have
> uncore.lock nor unclaimed register access detection.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 21 +++++++++++++--------
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 11 +++++------
> 2 files changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index a82da6443af9..345b27ada04f 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -83,13 +83,6 @@ intel_de_write(struct intel_display *display, i915_reg_t
> reg, u32 val)
> intel_dmc_wl_put(display, reg);
> }
>
> -static inline u32
> -__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
> - u32 clear, u32 set)
> -{
> - return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
> -}
> -
> static inline u32
> intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
> { @@ -97,7 +90,7 @@ intel_de_rmw(struct intel_display *display, i915_reg_t
> reg, u32 clear, u32 set)
>
> intel_dmc_wl_get(display, reg);
>
> - val = __intel_de_rmw_nowl(display, reg, clear, set);
> + val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
>
> intel_dmc_wl_put(display, reg);
>
> @@ -219,6 +212,18 @@ intel_de_write_fw(struct intel_display *display,
> i915_reg_t reg, u32 val)
> intel_uncore_write_fw(__to_uncore(display), reg, val); }
>
> +static inline u32
> +intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32
> +clear, u32 set) {
> + u32 old, val;
> +
> + old = intel_de_read_fw(display, reg);
> + val = (old & ~clear) | set;
> + intel_de_write_fw(display, reg, val);
> +
> + return old;
> +}
> +
> static inline u32
> intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) { diff --git
> a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index b3bb89ba34f9..869beb6f280d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -179,7 +179,7 @@ static void intel_dmc_wl_work(struct work_struct
> *work)
> if (refcount_read(&wl->refcount))
> goto out_unlock;
>
> - __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_REQ, 0);
> + intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_REQ, 0);
>
> if (__intel_de_wait_for_register_atomic_nowl(display,
> DMC_WAKELOCK1_CTL,
>
> DMC_WAKELOCK_CTL_ACK, 0,
> @@ -207,8 +207,7 @@ static void __intel_dmc_wl_take(struct intel_display
> *display)
> if (wl->taken)
> return;
>
> - __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0,
> - DMC_WAKELOCK_CTL_REQ);
> + intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, 0,
> DMC_WAKELOCK_CTL_REQ);
>
> /*
> * We need to use the atomic variant of the waiting routine @@ -
> 360,7 +359,7 @@ void intel_dmc_wl_enable(struct intel_display *display, u32
> dc_state)
> * wakelock, because we're just enabling it, so call the
> * non-locking version directly here.
> */
> - __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0,
> DMC_WAKELOCK_CFG_ENABLE);
> + intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, 0,
> +DMC_WAKELOCK_CFG_ENABLE);
>
> wl->enabled = true;
>
> @@ -402,7 +401,7 @@ void intel_dmc_wl_disable(struct intel_display
> *display)
> goto out_unlock;
>
> /* Disable wakelock in DMC */
> - __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG,
> DMC_WAKELOCK_CFG_ENABLE, 0);
> + intel_de_rmw_fw(display, DMC_WAKELOCK_CFG,
> DMC_WAKELOCK_CFG_ENABLE,
> +0);
>
> wl->enabled = false;
>
> @@ -414,7 +413,7 @@ void intel_dmc_wl_disable(struct intel_display
> *display)
> *
> * TODO: Get the correct expectation from the hardware team.
> */
> - __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_REQ, 0);
> + intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_REQ, 0);
>
> wl->taken = false;
>
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms()
2025-11-10 17:27 ` [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms() Ville Syrjala
@ 2025-11-11 4:45 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:45 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 13/16] drm/i915/de: Nuke wakelocks from
> intel_de_wait_fw_ms()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The low level _fw() register accessors aren't supposed to grab the wakelock.
> Stop doing so in intel_de_wait_fw_ms().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 12 ++----------
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 345b27ada04f..655867ea76b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -146,16 +146,8 @@ intel_de_wait_fw_ms(struct intel_display *display,
> i915_reg_t reg,
> u32 mask, u32 value, unsigned int timeout_ms,
> u32 *out_value)
> {
> - int ret;
> -
> - intel_dmc_wl_get(display, reg);
> -
> - ret = __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
> - value, 2, timeout_ms, out_value);
> -
> - intel_dmc_wl_put(display, reg);
> -
> - return ret;
> + return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
> + value, 2, timeout_ms, out_value);
> }
>
> static inline int
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic()
2025-11-10 17:27 ` [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic() Ville Syrjala
@ 2025-11-11 4:46 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:46 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 14/16] drm/i915/de: Replace
> __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Nuke the remaining _nowl() stuff from the wakelock code in the form of
> __intel_de_wait_for_register_nowl(), and replace it with
> intel_de_wait_fw_us_atomic() that uses the low level _fw() register accessors
> on line with the rest of the code.
>
> No change in behaviour since wakelocks are only supported on xe, and xe
> doesn't have uncore.lock nor unclaimed register detection stuff.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 19 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 14 +++++++-------
> 2 files changed, 16 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 655867ea76b8..a7ce3b875e06 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -97,16 +97,6 @@ intel_de_rmw(struct intel_display *display, i915_reg_t
> reg, u32 clear, u32 set)
> return val;
> }
>
> -static inline int
> -__intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
> - i915_reg_t reg,
> - u32 mask, u32 value,
> - unsigned int fast_timeout_us)
> -{
> - return __intel_wait_for_register(__to_uncore(display), reg, mask,
> - value, fast_timeout_us, 0, NULL);
> -}
> -
> static inline int
> intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
> u32 mask, u32 value, unsigned int timeout_us, @@ -150,6
> +140,15 @@ intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t
> reg,
> value, 2, timeout_ms, out_value); }
>
> +static inline int
> +intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout_us,
> + u32 *out_value)
> +{
> + return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
> + value, timeout_us, 0, out_value); }
> +
> static inline int
> intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
> u32 mask, unsigned int timeout_us)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 869beb6f280d..73a3101514f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -181,9 +181,9 @@ static void intel_dmc_wl_work(struct work_struct
> *work)
>
> intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_REQ, 0);
>
> - if (__intel_de_wait_for_register_atomic_nowl(display,
> DMC_WAKELOCK1_CTL,
> -
> DMC_WAKELOCK_CTL_ACK, 0,
> -
> DMC_WAKELOCK_CTL_TIMEOUT_US)) {
> + if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
> + DMC_WAKELOCK_CTL_ACK, 0,
> + DMC_WAKELOCK_CTL_TIMEOUT_US,
> NULL)) {
> WARN_RATELIMIT(1, "DMC wakelock release timed out");
> goto out_unlock;
> }
> @@ -213,10 +213,10 @@ static void __intel_dmc_wl_take(struct
> intel_display *display)
> * We need to use the atomic variant of the waiting routine
> * because the DMC wakelock is also taken in atomic context.
> */
> - if (__intel_de_wait_for_register_atomic_nowl(display,
> DMC_WAKELOCK1_CTL,
> -
> DMC_WAKELOCK_CTL_ACK,
> -
> DMC_WAKELOCK_CTL_ACK,
> -
> DMC_WAKELOCK_CTL_TIMEOUT_US)) {
> + if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
> + DMC_WAKELOCK_CTL_ACK,
> + DMC_WAKELOCK_CTL_ACK,
> + DMC_WAKELOCK_CTL_TIMEOUT_US,
> NULL)) {
> WARN_RATELIMIT(1, "DMC wakelock ack timed out");
> return;
> }
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value
2025-11-10 17:27 ` [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value Ville Syrjala
@ 2025-11-11 4:48 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out
> value
>
> Utilize the 'out_value' output parameter of intel_de_wait_ms() isntead of re-
> readiong the PHY_CONTROL register after polling has finished.
* instead
* re-reading
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8593d2daeaa6..f4f7e73acc87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1358,6 +1358,7 @@ static void assert_chv_phy_status(struct
> intel_display *display)
> u32 phy_control = display->power.chv_phy_control;
> u32 phy_status = 0;
> u32 phy_status_mask = 0xffffffff;
> + u32 val;
>
> /*
> * The BIOS can leave the PHY is some weird state @@ -1446,11
> +1447,10 @@ static void assert_chv_phy_status(struct intel_display *display)
> * so the power state can take a while to actually change.
> */
> if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
> - phy_status_mask, phy_status, 10, NULL))
> + phy_status_mask, phy_status, 10, &val))
> drm_err(display->drm,
> "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> (PHY_CONTROL=0x%08x)\n",
> - intel_de_read(display, DISPLAY_PHY_STATUS) &
> phy_status_mask,
> - phy_status, display->power.chv_phy_control);
> + val & phy_status_mask, phy_status, display-
> >power.chv_phy_control);
> }
>
> #undef BITS_SET
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 16/16] drm/i915/dpio: Use the intel_de_wait_ms() out value
2025-11-10 17:27 ` [PATCH 16/16] drm/i915/dpio: " Ville Syrjala
@ 2025-11-11 4:50 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 16/16] drm/i915/dpio: Use the intel_de_wait_ms() out value
>
>
> Utilize the 'out_value' output parameter of intel_de_wait_ms() isntead of re-
> readiong the DPLL/DPIO_PHY_STATUS register after polling has finished.
* re-reading
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 7b7a0461da36..8027bab2951b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1173,6 +1173,7 @@ void vlv_wait_port_ready(struct intel_encoder
> *encoder,
> struct intel_display *display = to_intel_display(encoder);
> u32 port_mask;
> i915_reg_t dpll_reg;
> + u32 val;
>
> switch (encoder->port) {
> default:
> @@ -1193,10 +1194,9 @@ void vlv_wait_port_ready(struct intel_encoder
> *encoder,
> break;
> }
>
> - if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask,
> 1000, NULL))
> + if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask,
> +1000, &val))
> drm_WARN(display->drm, 1,
> "timed out waiting for [ENCODER:%d:%s] port ready:
> got 0x%x, expected 0x%x\n",
> encoder->base.base.id, encoder->base.name,
> - intel_de_read(display, dpll_reg) & port_mask,
> - expected_mask);
> + val & port_mask, expected_mask);
> }
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 01/16] drm/i915/de: Implement register waits one way
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
@ 2025-11-11 4:52 ` Kandpal, Suraj
0 siblings, 0 replies; 40+ messages in thread
From: Kandpal, Suraj @ 2025-11-11 4:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 01/16] drm/i915/de: Implement register waits one way
>
>
> Currently we use a messy mix of intel_wait_for_register*() and
> __intel_wait_for_register*() to implement various register polling functions.
> Make the mess a bit more understandable by always using the
> __intel_wait_for_register*() stuff.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 17 +++-------
> .../drm/xe/compat-i915-headers/intel_uncore.h | 31 ++++++-------------
> 2 files changed, 14 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 9ecdcf6b73e4..ea9973dbbffc 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -104,15 +104,6 @@ intel_de_rmw(struct intel_display *display,
> i915_reg_t reg, u32 clear, u32 set)
> return val;
> }
>
> -static inline int
> -__intel_de_wait_for_register_nowl(struct intel_display *display,
> - i915_reg_t reg,
> - u32 mask, u32 value, unsigned int
> timeout_ms)
> -{
> - return intel_wait_for_register(__to_uncore(display), reg, mask,
> - value, timeout_ms);
> -}
> -
> static inline int
> __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
> i915_reg_t reg,
> @@ -131,8 +122,8 @@ intel_de_wait(struct intel_display *display, i915_reg_t
> reg,
>
> intel_dmc_wl_get(display, reg);
>
> - ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
> - timeout_ms);
> + ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
> + value, 2, timeout_ms, NULL);
>
> intel_dmc_wl_put(display, reg);
>
> @@ -147,8 +138,8 @@ intel_de_wait_fw(struct intel_display *display,
> i915_reg_t reg,
>
> intel_dmc_wl_get(display, reg);
>
> - ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
> - value, timeout_ms, out_value);
> + ret = __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
> + value, 2, timeout_ms, out_value);
>
> intel_dmc_wl_put(display, reg);
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index d012f02bc84f..d93ddacdf743 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -91,27 +91,6 @@ static inline u32 intel_uncore_rmw(struct intel_uncore
> *uncore,
> return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg,
> clear, set); }
>
> -static inline int intel_wait_for_register(struct intel_uncore *uncore,
> - i915_reg_t i915_reg, u32 mask,
> - u32 value, unsigned int timeout)
> -{
> - struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> -
> - return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg,
> mask, value,
> - timeout * USEC_PER_MSEC, NULL, false);
> -}
> -
> -static inline int intel_wait_for_register_fw(struct intel_uncore *uncore,
> - i915_reg_t i915_reg, u32 mask,
> - u32 value, unsigned int timeout,
> - u32 *out_value)
> -{
> - struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> -
> - return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg,
> mask, value,
> - timeout * USEC_PER_MSEC, out_value, false);
> -}
> -
> static inline int
> __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
> u32 mask, u32 value, unsigned int fast_timeout_us,
> @@ -133,6 +112,16 @@ __intel_wait_for_register(struct intel_uncore
> *uncore, i915_reg_t i915_reg,
> out_value, atomic);
> }
>
> +static inline int
> +__intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t
> i915_reg,
> + u32 mask, u32 value, unsigned int fast_timeout_us,
> + unsigned int slow_timeout_ms, u32 *out_value) {
> + return __intel_wait_for_register(uncore, i915_reg, mask, value,
> + fast_timeout_us, slow_timeout_ms,
> + out_value);
> +}
> +
> static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
> i915_reg_t i915_reg)
> {
> --
> 2.49.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 00/16] drm/i915/de: Register polling cleanup
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (17 preceding siblings ...)
2025-11-11 3:41 ` ✗ i915.CI.Full: failure " Patchwork
@ 2025-11-11 8:01 ` Jani Nikula
2025-11-11 16:11 ` Ville Syrjälä
2025-11-11 19:09 ` Ville Syrjälä
19 siblings, 1 reply; 40+ messages in thread
From: Jani Nikula @ 2025-11-11 8:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 10 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clean up the register polling stuff:
> - rename the current wait stuff to
> intel_de_wait_{,for_set,for_clear}_ms()
> - introduce intel_de_wait_{,for_set,for_clear}_us()
> - nuke intel_de_wait_custom()
> - change the wakelock stuff to use _fw() instead of
> hand rolling yet another level of register accessors
> - a few other minor cleanups
>
> After this it should be fairly easy to switch over to
> poll_timeout_us().
Overall the series looks fine.
Acked-by: Jani Nikula <jani.nikula@intel.com>
since Suraj already did the detailed review.
One questions remains unanswered, and I guess I'll have to wait for
follow-up to see the answer. I really *really* dislike how the i915
variants are somewhat ambiguously atomic, i.e. atomic when slow timeout
is 0, and the xe wrappers replicate that behaviour. xe_mmio_wait32() has
atomic as parameter.
I would like the atomic variants to be explicit, and separate. Similar
to poll_timeout_us() and poll_timeout_us_atomic(). You immediately know
from the call whether you're doing the right thing or not. And that
really should not directly depend on the timeout length. Since you plan
on using the generic poll helpers, I presume this will propagate to the
register polling helpers.
Since we do a lot of non-atomic millisecond waits, I guess it's worth
having the _ms variants, although like I said before, I'd kind of like
going for _us all over the place. But no big deal, in the end the _ms
variants can be trivial wrappers on the non-atomic _us ones.
BR,
Jani.
>
> Ville Syrjälä (16):
> drm/i915/de: Implement register waits one way
> drm/i915/de: Have intel_de_wait() hand out the final register value
> drm/i915/de: Include units in intel_de_wait*() function names
> drm/i915/de: Introduce intel_de_wait_us()
> drm/i915/de: Use intel_de_wait_us()
> drm/i915/de: Use intel_de_wait_ms() for the obvious cases
> drm/i915/de: Nuke intel_de_wait_custom()
> drm/i915/de: Introduce intel_de_wait_for_{set,clear}_us()
> drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
> drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()
> drm/1915/dpio: Stop using intel_de_wait_fw_ms()
> drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw()
> drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms()
> drm/i915/de: Replace __intel_de_wait_for_register_nowl() with
> intel_de_wait_fw_us_atomic()
> drm/i915/power: Use the intel_de_wait_ms() out value
> drm/i915/dpio: Use the intel_de_wait_ms() out value
>
> drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
> drivers/gpu/drm/i915/display/icl_dsi.c | 35 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--
> drivers/gpu/drm/i915/display/intel_crt.c | 16 +--
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 98 ++++++++--------
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++---
> drivers/gpu/drm/i915/display/intel_de.h | 107 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> .../drm/i915/display/intel_display_power.c | 14 +--
> .../i915/display/intel_display_power_well.c | 42 +++----
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 25 ++--
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 +--
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 10 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 +++--
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_flipq.c | 8 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++----
> drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 57 +++++-----
> drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 12 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 10 +-
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 18 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> drivers/gpu/drm/i915/display/intel_sbi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +-
> drivers/gpu/drm/i915/display/intel_tc.c | 8 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 54 ++++-----
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +-
> .../drm/xe/compat-i915-headers/intel_uncore.h | 31 ++---
> 34 files changed, 369 insertions(+), 402 deletions(-)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 00/16] drm/i915/de: Register polling cleanup
2025-11-11 8:01 ` [PATCH 00/16] " Jani Nikula
@ 2025-11-11 16:11 ` Ville Syrjälä
0 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjälä @ 2025-11-11 16:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Nov 11, 2025 at 10:01:14AM +0200, Jani Nikula wrote:
> On Mon, 10 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Clean up the register polling stuff:
> > - rename the current wait stuff to
> > intel_de_wait_{,for_set,for_clear}_ms()
> > - introduce intel_de_wait_{,for_set,for_clear}_us()
> > - nuke intel_de_wait_custom()
> > - change the wakelock stuff to use _fw() instead of
> > hand rolling yet another level of register accessors
> > - a few other minor cleanups
> >
> > After this it should be fairly easy to switch over to
> > poll_timeout_us().
>
> Overall the series looks fine.
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> since Suraj already did the detailed review.
>
> One questions remains unanswered, and I guess I'll have to wait for
> follow-up to see the answer. I really *really* dislike how the i915
> variants are somewhat ambiguously atomic, i.e. atomic when slow timeout
> is 0, and the xe wrappers replicate that behaviour. xe_mmio_wait32() has
> atomic as parameter.
>
> I would like the atomic variants to be explicit, and separate. Similar
> to poll_timeout_us() and poll_timeout_us_atomic(). You immediately know
> from the call whether you're doing the right thing or not. And that
> really should not directly depend on the timeout length. Since you plan
> on using the generic poll helpers, I presume this will propagate to the
> register polling helpers.
>
> Since we do a lot of non-atomic millisecond waits, I guess it's worth
> having the _ms variants, although like I said before, I'd kind of like
> going for _us all over the place. But no big deal, in the end the _ms
> variants can be trivial wrappers on the non-atomic _us ones.
At the end of this series we have intel_de_wait_fw_us_atomic()
which is the only thing that anyone should call from atomic
context. Granted the _us() stuff all still work in atomic
context due to the underlying uncore implementation. But
when we switch to poll_timeout_us() I plan to make all the
other stuff unusable from atomic contexts.
Ideally we probably shouldn't even have intel_de_wait_fw_us_atomic().
I think the wakelock code is the only place that needs it,
due to the spinlock presumably. I haven't checked if we could
just eg. make that a mutex and use the non-atomic thing there
as well.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases
2025-11-11 4:32 ` Kandpal, Suraj
@ 2025-11-11 17:41 ` Ville Syrjälä
0 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjälä @ 2025-11-11 17:41 UTC (permalink / raw)
To: Kandpal, Suraj
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
On Tue, Nov 11, 2025 at 04:32:17AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious
> > cases
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Replace some users of intel_de_wait_custom() with intel_de_wait_ms().
> >
> > This includes the cases where we pass in the default 2 microsecond fast
> > timeout, which is also what intel_de_wait_ms() uses so there are no functional
> > changes here.
> >
> > Done with cocci (with manual formatting fixes):
> > @@
> > expression display, reg, mask, value, timeout_ms, out_value; @@
> > - intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value)
> > + intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value)
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 15 ++++-----
> > drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 ++--
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 5 ++-
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 32 +++++++++----------
> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 6 ++--
> > 5 files changed, 30 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index af97bd42495b..55fd95994ea7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -164,11 +164,10 @@ int intel_cx0_wait_for_ack(struct intel_encoder
> > *encoder,
> > enum port port = encoder->port;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > - if (intel_de_wait_custom(display,
> > -
> > XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
> > - XELPDP_PORT_P2M_RESPONSE_READY,
> > - XELPDP_PORT_P2M_RESPONSE_READY,
> > - 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
> > + if (intel_de_wait_ms(display,
> > XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
> > + XELPDP_PORT_P2M_RESPONSE_READY,
> > + XELPDP_PORT_P2M_RESPONSE_READY,
> > + XELPDP_MSGBUS_TIMEOUT_MS, val)) {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for message ACK. Status:
> > 0x%x\n",
> > phy_name(phy), *val);
> > @@ -2827,9 +2826,9 @@ void
> > intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> > intel_cx0_get_powerdown_update(lane_mask));
> >
> > /* Update Timeout Value */
> > - if (intel_de_wait_custom(display, buf_ctl2_reg,
> > -
> > intel_cx0_get_powerdown_update(lane_mask), 0,
> > - 2,
> > XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
> > + if (intel_de_wait_ms(display, buf_ctl2_reg,
> > + intel_cx0_get_powerdown_update(lane_mask), 0,
> > +
> > XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
> > drm_warn(display->drm,
> > "PHY %c failed to bring out of lane reset\n",
> > phy_name(phy));
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index 2e7dbaf511b9..809799f63e32 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -62,9 +62,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> > u32 status;
> > int ret;
> >
> > - ret = intel_de_wait_custom(display, ch_ctl,
> > DP_AUX_CH_CTL_SEND_BUSY,
> > - 0,
> > - 2, timeout_ms, &status);
> > + ret = intel_de_wait_ms(display, ch_ctl,
> > + DP_AUX_CH_CTL_SEND_BUSY, 0,
> > + timeout_ms, &status);
> >
> > if (ret == -ETIMEDOUT)
> > drm_err(display->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 78c34466e402..5e1a96223a9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -410,9 +410,8 @@ static int intel_hdcp_load_keys(struct intel_display
> > *display)
> > }
> >
> > /* Wait for the keys to load (500us) */
>
> I would prefer this comment be changed/ removed since we now wait 1 ms
> for the keys to load
I'm not changing the timeout here. Reviewign the comment vs.
code for correctness is a job for someone else (someone who
knows what the timeout should be and why the comment and
code disagree).
Though I think generally we do have other places where we use
eg. 1ms even when the specified timeout is less, especially if
the specified timeout varies between platforms. In those cases
I do prefer to have a comment that documents what the specified
timeout(s) is/are, and why we use some bigger value.
>
> other than that
>
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> > - ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
> > - HDCP_KEY_LOAD_DONE,
> > HDCP_KEY_LOAD_DONE,
> > - 2, 1, &val);
> > + ret = intel_de_wait_ms(display, HDCP_KEY_STATUS,
> > HDCP_KEY_LOAD_DONE,
> > + HDCP_KEY_LOAD_DONE, 1, &val);
> > if (ret)
> > return ret;
> > else if (!(val & HDCP_KEY_LOAD_STATUS)) diff --git
> > a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 243fca1c6a2d..ac6f61107528 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1201,10 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> > XELPDP_LANE_PCLK_PLL_REQUEST(0),
> > XELPDP_LANE_PCLK_PLL_REQUEST(0));
> >
> > - if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> > port),
> > - XELPDP_LANE_PCLK_PLL_ACK(0),
> > - XELPDP_LANE_PCLK_PLL_ACK(0),
> > - 2,
> > XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> > + if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display,
> > port),
> > + XELPDP_LANE_PCLK_PLL_ACK(0),
> > XELPDP_LANE_PCLK_PLL_ACK(0),
> > + XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> > drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack
> > not done\n",
> > phy_name(phy));
> >
> > @@ -1215,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> > intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > lane_pipe_reset | lane_phy_pulse_status, 0);
> >
> > - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > port),
> > - lane_phy_current_status, 0,
> > - 2, XE3PLPD_RESET_END_LATENCY_MS,
> > NULL))
> > + if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> > + lane_phy_current_status, 0,
> > + XE3PLPD_RESET_END_LATENCY_MS, NULL))
> > drm_warn(display->drm, "PHY %c failed to bring out of lane
> > reset\n",
> > phy_name(phy));
> >
> > - if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > port),
> > - lane_phy_pulse_status,
> > lane_phy_pulse_status,
> > - 2,
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> > + if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
> > + lane_phy_pulse_status, lane_phy_pulse_status,
> > + XE3PLPD_RATE_CALIB_DONE_LATENCY_MS,
> > NULL))
> > drm_warn(display->drm, "PHY %c PLL rate not changed\n",
> > phy_name(phy));
> >
> > @@ -2002,10 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > *encoder,
> > XELPDP_LANE_PCLK_PLL_REQUEST(0));
> >
> > /* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> > - if (intel_de_wait_custom(display,
> > XELPDP_PORT_CLOCK_CTL(display, port),
> > - XELPDP_LANE_PCLK_PLL_ACK(0),
> > - XELPDP_LANE_PCLK_PLL_ACK(0),
> > - 2,
> > XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> > + if (intel_de_wait_ms(display,
> > XELPDP_PORT_CLOCK_CTL(display, port),
> > + XELPDP_LANE_PCLK_PLL_ACK(0),
> > XELPDP_LANE_PCLK_PLL_ACK(0),
> > +
> > XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> > drm_warn(display->drm, "PHY %c PLL MacCLK ack
> > assertion timeout\n",
> > phy_name(phy));
> >
> > @@ -2031,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > *encoder,
> > rate_update, MB_WRITE_COMMITTED);
> >
> > /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> > for Owned PHY Lanes. */
> > - if (intel_de_wait_custom(display,
> > XELPDP_PORT_BUF_CTL2(display, port),
> > - lane_phy_pulse_status,
> > lane_phy_pulse_status,
> > - 2,
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> > + if (intel_de_wait_ms(display,
> > XELPDP_PORT_BUF_CTL2(display, port),
> > + lane_phy_pulse_status,
> > lane_phy_pulse_status,
> > +
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
> > drm_warn(display->drm, "PHY %c PLL rate not
> > changed\n",
> > phy_name(phy));
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > index 3cc89048b027..dc44a7a169c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -462,9 +462,9 @@ static void intel_pmdemand_poll(struct intel_display
> > *display)
> > u32 status;
> > int ret;
> >
> > - ret = intel_de_wait_custom(display,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > - XELPDP_PMDEMAND_REQ_ENABLE, 0,
> > - 2, timeout_ms, &status);
> > + ret = intel_de_wait_ms(display,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > + XELPDP_PMDEMAND_REQ_ENABLE, 0,
> > + timeout_ms, &status);
> >
> > if (ret == -ETIMEDOUT)
> > drm_err(display->drm,
> > --
> > 2.49.1
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names
2025-11-11 4:21 ` Kandpal, Suraj
@ 2025-11-11 17:45 ` Ville Syrjälä
0 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjälä @ 2025-11-11 17:45 UTC (permalink / raw)
To: Kandpal, Suraj
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
On Tue, Nov 11, 2025 at 04:21:09AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*()
> > function names
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > intel_de_wait*() take the timeout in milliseconds. Incldue
>
> Typo * Include
>
> > that information in the function name to make life less
> > confusing. And I'll also be introducing microsecond variants
>
> Maybe no full stop if you are using "and" also should we be using references to what
> One will be doing in later commits ?
I dropped the "and". As for referencing later commis, yeah it's perhaps
not the best thing to do (especially if those later commits end up not
happening for whatever reason). But the introduction of the _us() is a
good justification for the _ms() change so I think I'll keep it.
I suppose I could have reordered the patches to add _us() stuff first,
and then follow up with the _ms() rename. But I'm too lazy to reorder
the series now.
>
> Other than that LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> > of these later.
> >
> > Done with cocci:
> > @@
> > @@
> > (
> > static int
> > - intel_de_wait
> > + intel_de_wait_ms
> > (...)
> > {
> > ...
> > }
> > |
> > static int
> > - intel_de_wait_fw
> > + intel_de_wait_fw_ms
> > (...)
> > {
> > ...
> > }
> > |
> > static int
> > - intel_de_wait_for_set
> > + intel_de_wait_for_set_ms
> > (...)
> > {
> > ...
> > }
> > |
> > static int
> > - intel_de_wait_for_clear
> > + intel_de_wait_for_clear_ms
> > (...)
> > {
> > ...
> > }
> > )
> >
> > @@
> > @@
> > (
> > - intel_de_wait
> > + intel_de_wait_ms
> > |
> > - intel_de_wait_fw
> > + intel_de_wait_fw_ms
> > |
> > - intel_de_wait_for_set
> > + intel_de_wait_for_set_ms
> > |
> > - intel_de_wait_for_clear
> > + intel_de_wait_for_clear_ms
> > )
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +--
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 20 +++----
> > drivers/gpu/drm/i915/display/intel_crt.c | 16 +++---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 36 ++++++-------
> > drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
> > drivers/gpu/drm/i915/display/intel_de.h | 22 ++++----
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> > .../drm/i915/display/intel_display_power.c | 4 +-
> > .../i915/display/intel_display_power_well.c | 38 ++++++-------
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 ++---
> > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 +--
> > drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++--
> > drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_flipq.c | 8 +--
> > drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 44 ++++++++-------
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +--
> > drivers/gpu/drm/i915/display/intel_lvds.c | 6 +--
> > .../gpu/drm/i915/display/intel_pch_display.c | 12 ++---
> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 12 ++---
> > drivers/gpu/drm/i915/display/intel_psr.c | 10 ++--
> > drivers/gpu/drm/i915/display/intel_sbi.c | 6 ++-
> > drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +--
> > drivers/gpu/drm/i915/display/intel_tc.c | 8 +--
> > drivers/gpu/drm/i915/display/intel_vrr.c | 6 +--
> > drivers/gpu/drm/i915/display/vlv_dsi.c | 54 +++++++++----------
> > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +--
> > 30 files changed, 207 insertions(+), 205 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> > b/drivers/gpu/drm/i915/display/hsw_ips.c
> > index f444c5b7a27b..008d339d5c21 100644
> > --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> > +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> > @@ -56,7 +56,7 @@ static void hsw_ips_enable(const struct intel_crtc_state
> > *crtc_state)
> > * the HW state readout code will complain that the expected
> > * IPS_CTL value is not the one we read.
> > */
> > - if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
> > + if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE,
> > 50))
> > drm_err(display->drm,
> > "Timed out waiting for IPS enable\n");
> > }
> > @@ -78,7 +78,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
> > *crtc_state)
> > * 42ms timeout value leads to occasional timeouts so use
> > 100ms
> > * instead.
> > */
> > - if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE,
> > 100))
> > + if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE,
> > 100))
> > drm_err(display->drm,
> > "Timed out waiting for IPS disable\n");
> > } else {
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 70d4c1bc70fc..6a11b3bb219b 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1048,8 +1048,8 @@ static void gen11_dsi_enable_transcoder(struct
> > intel_encoder *encoder)
> > TRANSCONF_ENABLE);
> >
> > /* wait for transcoder to be enabled */
> > - if (intel_de_wait_for_set(display, TRANSCONF(display,
> > dsi_trans),
> > - TRANSCONF_STATE_ENABLE, 10))
> > + if (intel_de_wait_for_set_ms(display, TRANSCONF(display,
> > dsi_trans),
> > + TRANSCONF_STATE_ENABLE, 10))
> > drm_err(display->drm,
> > "DSI transcoder not enabled\n");
> > }
> > @@ -1317,8 +1317,8 @@ static void gen11_dsi_disable_transcoder(struct
> > intel_encoder *encoder)
> > TRANSCONF_ENABLE, 0);
> >
> > /* wait for transcoder to be disabled */
> > - if (intel_de_wait_for_clear(display, TRANSCONF(display,
> > dsi_trans),
> > - TRANSCONF_STATE_ENABLE, 50))
> > + if (intel_de_wait_for_clear_ms(display, TRANSCONF(display,
> > dsi_trans),
> > + TRANSCONF_STATE_ENABLE, 50))
> > drm_err(display->drm,
> > "DSI trancoder not disabled\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 4d03cfefc72c..c0d798b1cf46 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1114,7 +1114,7 @@ static void skl_dpll0_enable(struct intel_display
> > *display, int vco)
> > intel_de_rmw(display, LCPLL1_CTL,
> > 0, LCPLL_PLL_ENABLE);
> >
> > - if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
> > + if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK,
> > 5))
> > drm_err(display->drm, "DPLL0 not locked\n");
> >
> > display->cdclk.hw.vco = vco;
> > @@ -1128,7 +1128,7 @@ static void skl_dpll0_disable(struct intel_display
> > *display)
> > intel_de_rmw(display, LCPLL1_CTL,
> > LCPLL_PLL_ENABLE, 0);
> >
> > - if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
> > + if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK,
> > 1))
> > drm_err(display->drm, "Couldn't disable DPLL0\n");
> >
> > display->cdclk.hw.vco = 0;
> > @@ -1835,8 +1835,8 @@ static void bxt_de_pll_disable(struct intel_display
> > *display)
> > intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
> >
> > /* Timeout 200us */
> > - if (intel_de_wait_for_clear(display,
> > - BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> > 1))
> > + if (intel_de_wait_for_clear_ms(display,
> > + BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> > 1))
> > drm_err(display->drm, "timeout waiting for DE PLL
> > unlock\n");
> >
> > display->cdclk.hw.vco = 0;
> > @@ -1852,8 +1852,8 @@ static void bxt_de_pll_enable(struct intel_display
> > *display, int vco)
> > intel_de_write(display, BXT_DE_PLL_ENABLE,
> > BXT_DE_PLL_PLL_ENABLE);
> >
> > /* Timeout 200us */
> > - if (intel_de_wait_for_set(display,
> > - BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> > + if (intel_de_wait_for_set_ms(display,
> > + BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK,
> > 1))
> > drm_err(display->drm, "timeout waiting for DE PLL lock\n");
> >
> > display->cdclk.hw.vco = vco;
> > @@ -1865,7 +1865,7 @@ static void icl_cdclk_pll_disable(struct intel_display
> > *display)
> > BXT_DE_PLL_PLL_ENABLE, 0);
> >
> > /* Timeout 200us */
> > - if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE,
> > BXT_DE_PLL_LOCK, 1))
> > + if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE,
> > BXT_DE_PLL_LOCK, 1))
> > drm_err(display->drm, "timeout waiting for CDCLK PLL
> > unlock\n");
> >
> > display->cdclk.hw.vco = 0;
> > @@ -1883,7 +1883,7 @@ static void icl_cdclk_pll_enable(struct intel_display
> > *display, int vco)
> > intel_de_write(display, BXT_DE_PLL_ENABLE, val);
> >
> > /* Timeout 200us */
> > - if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
> > BXT_DE_PLL_LOCK, 1))
> > + if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
> > BXT_DE_PLL_LOCK, 1))
> > drm_err(display->drm, "timeout waiting for CDCLK PLL
> > lock\n");
> >
> > display->cdclk.hw.vco = vco;
> > @@ -1903,8 +1903,8 @@ static void adlp_cdclk_pll_crawl(struct intel_display
> > *display, int vco)
> > intel_de_write(display, BXT_DE_PLL_ENABLE, val);
> >
> > /* Timeout 200us */
> > - if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
> > - BXT_DE_PLL_LOCK |
> > BXT_DE_PLL_FREQ_REQ_ACK, 1))
> > + if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
> > + BXT_DE_PLL_LOCK |
> > BXT_DE_PLL_FREQ_REQ_ACK, 1))
> > drm_err(display->drm, "timeout waiting for FREQ change
> > request ack\n");
> >
> > val &= ~BXT_DE_PLL_FREQ_REQ;
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> > b/drivers/gpu/drm/i915/display/intel_crt.c
> > index 31e68047f217..82e89cdbe5a5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -498,10 +498,10 @@ static bool ilk_crt_detect_hotplug(struct
> > drm_connector *connector)
> >
> > intel_de_write(display, crt->adpa_reg, adpa);
> >
> > - if (intel_de_wait_for_clear(display,
> > - crt->adpa_reg,
> > -
> > ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> > - 1000))
> > + if (intel_de_wait_for_clear_ms(display,
> > + crt->adpa_reg,
> > +
> > ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> > + 1000))
> > drm_dbg_kms(display->drm,
> > "timed out waiting for FORCE_TRIGGER");
> >
> > @@ -553,8 +553,8 @@ static bool valleyview_crt_detect_hotplug(struct
> > drm_connector *connector)
> >
> > intel_de_write(display, crt->adpa_reg, adpa);
> >
> > - if (intel_de_wait_for_clear(display, crt->adpa_reg,
> > - ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> > 1000)) {
> > + if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,
> > + ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> > 1000)) {
> > drm_dbg_kms(display->drm,
> > "timed out waiting for FORCE_TRIGGER");
> > intel_de_write(display, crt->adpa_reg, save_adpa);
> > @@ -604,8 +604,8 @@ static bool intel_crt_detect_hotplug(struct
> > drm_connector *connector)
> > CRT_HOTPLUG_FORCE_DETECT,
> > CRT_HOTPLUG_FORCE_DETECT);
> > /* wait for FORCE_DETECT to go off */
> > - if (intel_de_wait_for_clear(display,
> > PORT_HOTPLUG_EN(display),
> > - CRT_HOTPLUG_FORCE_DETECT,
> > 1000))
> > + if (intel_de_wait_for_clear_ms(display,
> > PORT_HOTPLUG_EN(display),
> > + CRT_HOTPLUG_FORCE_DETECT,
> > 1000))
> > drm_dbg_kms(display->drm,
> > "timed out waiting for FORCE_DETECT to go
> > off");
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 1551d30ec584..7870823235c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -145,9 +145,9 @@ void intel_cx0_bus_reset(struct intel_encoder
> > *encoder, int lane)
> > intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> > port, lane),
> > XELPDP_PORT_M2P_TRANSACTION_RESET);
> >
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > - XELPDP_PORT_M2P_TRANSACTION_RESET,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_M2P_TRANSACTION_RESET,
> > + XELPDP_MSGBUS_TIMEOUT_MS)) {
> > drm_err_once(display->drm,
> > "Failed to bring PHY %c to idle.\n",
> > phy_name(phy));
> > @@ -213,9 +213,9 @@ static int __intel_cx0_read_once(struct intel_encoder
> > *encoder,
> > int ack;
> > u32 val;
> >
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > -
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_MS)) {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for previous transaction to
> > complete. Reset the bus and retry.\n", phy_name(phy));
> > intel_cx0_bus_reset(encoder, lane);
> > @@ -284,9 +284,9 @@ static int __intel_cx0_write_once(struct intel_encoder
> > *encoder,
> > int ack;
> > u32 val;
> >
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > -
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_MS)) {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for previous transaction to
> > complete. Resetting the bus.\n", phy_name(phy));
> > intel_cx0_bus_reset(encoder, lane);
> > @@ -300,9 +300,9 @@ static int __intel_cx0_write_once(struct intel_encoder
> > *encoder,
> > XELPDP_PORT_M2P_DATA(data) |
> > XELPDP_PORT_M2P_ADDRESS(addr));
> >
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > -
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_MS)) {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for write to complete.
> > Resetting the bus.\n", phy_name(phy));
> > intel_cx0_bus_reset(encoder, lane);
> > @@ -2813,9 +2813,9 @@ void
> > intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> >
> > /* Wait for pending transactions.*/
> > for_each_cx0_lane_in_mask(lane_mask, lane)
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > -
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_MS))
> > {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for previous
> > transaction to complete. Reset the bus.\n",
> > phy_name(phy));
> > @@ -2924,9 +2924,9 @@ static void intel_cx0_phy_lane_reset(struct
> > intel_encoder *encoder,
> >
> > intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > lane_pipe_reset, 0);
> >
> > - if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display,
> > port),
> > - lane_phy_current_status,
> > - XELPDP_PORT_RESET_END_TIMEOUT_MS))
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_BUF_CTL2(display, port),
> > + lane_phy_current_status,
> > +
> > XELPDP_PORT_RESET_END_TIMEOUT_MS))
> > drm_warn(display->drm,
> > "PHY %c failed to bring out of lane reset\n",
> > phy_name(phy));
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 733ef4559131..33fca83c22b3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -210,8 +210,8 @@ void intel_wait_ddi_buf_idle(struct intel_display
> > *display, enum port port)
> > }
> >
> > static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
> > - if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display,
> > port),
> > - DDI_BUF_IS_IDLE, 10))
> > + if (intel_de_wait_for_set_ms(display,
> > intel_ddi_buf_status_reg(display, port),
> > + DDI_BUF_IS_IDLE, 10))
> > drm_err(display->drm, "Timeout waiting for DDI BUF %c to get
> > idle\n",
> > port_name(port));
> > }
> > @@ -235,8 +235,8 @@ static void intel_wait_ddi_buf_active(struct
> > intel_encoder *encoder)
> > }
> >
> > static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
> > - if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display,
> > port),
> > - DDI_BUF_IS_IDLE, 10))
> > + if (intel_de_wait_for_clear_ms(display,
> > intel_ddi_buf_status_reg(display, port),
> > + DDI_BUF_IS_IDLE, 10))
> > drm_err(display->drm, "Timeout waiting for DDI BUF %c to get
> > active\n",
> > port_name(port));
> > }
> > @@ -2307,8 +2307,8 @@ void intel_ddi_wait_for_act_sent(struct
> > intel_encoder *encoder,
> > {
> > struct intel_display *display = to_intel_display(encoder);
> >
> > - if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder,
> > crtc_state),
> > - DP_TP_STATUS_ACT_SENT, 1))
> > + if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder,
> > crtc_state),
> > + DP_TP_STATUS_ACT_SENT, 1))
> > drm_err(display->drm, "Timed out waiting for ACT sent\n");
> > }
> >
> > @@ -2383,11 +2383,11 @@ int intel_ddi_wait_for_fec_status(struct
> > intel_encoder *encoder,
> > return 0;
> >
> > if (enabled)
> > - ret = intel_de_wait_for_set(display,
> > dp_tp_status_reg(encoder, crtc_state),
> > - DP_TP_STATUS_FEC_ENABLE_LIVE,
> > 1);
> > + ret = intel_de_wait_for_set_ms(display,
> > dp_tp_status_reg(encoder, crtc_state),
> > +
> > DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
> > else
> > - ret = intel_de_wait_for_clear(display,
> > dp_tp_status_reg(encoder, crtc_state),
> > - DP_TP_STATUS_FEC_ENABLE_LIVE,
> > 1);
> > + ret = intel_de_wait_for_clear_ms(display,
> > dp_tp_status_reg(encoder, crtc_state),
> > +
> > DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
> >
> > if (ret) {
> > drm_err(display->drm,
> > @@ -3868,9 +3868,9 @@ static void intel_ddi_set_idle_link_train(struct
> > intel_dp *intel_dp,
> > if (port == PORT_A && DISPLAY_VER(display) < 12)
> > return;
> >
> > - if (intel_de_wait_for_set(display,
> > - dp_tp_status_reg(encoder, crtc_state),
> > - DP_TP_STATUS_IDLE_DONE, 2))
> > + if (intel_de_wait_for_set_ms(display,
> > + dp_tp_status_reg(encoder, crtc_state),
> > + DP_TP_STATUS_IDLE_DONE, 2))
> > drm_err(display->drm,
> > "Timed out waiting for DP idle patterns\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.h
> > b/drivers/gpu/drm/i915/display/intel_de.h
> > index a4ad20030c09..d449180d1d22 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.h
> > +++ b/drivers/gpu/drm/i915/display/intel_de.h
> > @@ -115,8 +115,9 @@ __intel_de_wait_for_register_atomic_nowl(struct
> > intel_display *display,
> > }
> >
> > static inline int
> > -intel_de_wait(struct intel_display *display, i915_reg_t reg,
> > - u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
> > +intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
> > + u32 mask, u32 value, unsigned int timeout_ms,
> > + u32 *out_value)
> > {
> > int ret;
> >
> > @@ -131,8 +132,9 @@ intel_de_wait(struct intel_display *display, i915_reg_t
> > reg,
> > }
> >
> > static inline int
> > -intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
> > - u32 mask, u32 value, unsigned int timeout_ms, u32
> > *out_value)
> > +intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
> > + u32 mask, u32 value, unsigned int timeout_ms,
> > + u32 *out_value)
> > {
> > int ret;
> >
> > @@ -166,17 +168,17 @@ intel_de_wait_custom(struct intel_display *display,
> > i915_reg_t reg,
> > }
> >
> > static inline int
> > -intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
> > - u32 mask, unsigned int timeout_ms)
> > +intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
> > + u32 mask, unsigned int timeout_ms)
> > {
> > - return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
> > + return intel_de_wait_ms(display, reg, mask, mask, timeout_ms,
> > NULL);
> > }
> >
> > static inline int
> > -intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
> > - u32 mask, unsigned int timeout_ms)
> > +intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
> > + u32 mask, unsigned int timeout_ms)
> > {
> > - return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
> > + return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
> > }
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 25986bd8fbdd..6bca186608ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -359,8 +359,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state
> > *old_crtc_state)
> > enum transcoder cpu_transcoder = old_crtc_state-
> > >cpu_transcoder;
> >
> > /* Wait for the Pipe State to go off */
> > - if (intel_de_wait_for_clear(display, TRANSCONF(display,
> > cpu_transcoder),
> > - TRANSCONF_STATE_ENABLE, 100))
> > + if (intel_de_wait_for_clear_ms(display, TRANSCONF(display,
> > cpu_transcoder),
> > + TRANSCONF_STATE_ENABLE,
> > 100))
> > drm_WARN(display->drm, 1, "pipe_off wait timed
> > out\n");
> > } else {
> > intel_wait_for_pipe_scanline_stopped(crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 74fcd9cfe911..2b86a634c1f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1305,7 +1305,7 @@ static void hsw_disable_lcpll(struct intel_display
> > *display,
> > intel_de_write(display, LCPLL_CTL, val);
> > intel_de_posting_read(display, LCPLL_CTL);
> >
> > - if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
> > + if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK,
> > 1))
> > drm_err(display->drm, "LCPLL still locked\n");
> >
> > val = hsw_read_dcomp(display);
> > @@ -1362,7 +1362,7 @@ static void hsw_restore_lcpll(struct intel_display
> > *display)
> > val &= ~LCPLL_PLL_DISABLE;
> > intel_de_write(display, LCPLL_CTL, val);
> >
> > - if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
> > + if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
> > drm_err(display->drm, "LCPLL not locked yet\n");
> >
> > if (val & LCPLL_CD_SOURCE_FCLK) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index afa5d8964f0d..8593d2daeaa6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -293,8 +293,8 @@ static void hsw_wait_for_power_well_enable(struct
> > intel_display *display,
> > }
> >
> > /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> > - if (intel_de_wait_for_set(display, regs->driver,
> > - HSW_PWR_WELL_CTL_STATE(pw_idx),
> > timeout)) {
> > + if (intel_de_wait_for_set_ms(display, regs->driver,
> > + HSW_PWR_WELL_CTL_STATE(pw_idx),
> > timeout)) {
> > drm_dbg_kms(display->drm, "%s power well enable
> > timeout\n",
> > intel_power_well_name(power_well));
> >
> > @@ -338,9 +338,9 @@ static void hsw_wait_for_power_well_disable(struct
> > intel_display *display,
> > */
> > reqs = hsw_power_well_requesters(display, regs, pw_idx);
> >
> > - ret = intel_de_wait_for_clear(display, regs->driver,
> > - HSW_PWR_WELL_CTL_STATE(pw_idx),
> > - reqs ? 0 : 1);
> > + ret = intel_de_wait_for_clear_ms(display, regs->driver,
> > +
> > HSW_PWR_WELL_CTL_STATE(pw_idx),
> > + reqs ? 0 : 1);
> > if (!ret)
> > return;
> >
> > @@ -359,8 +359,8 @@ static void gen9_wait_for_power_well_fuses(struct
> > intel_display *display,
> > {
> > /* Timeout 5us for PG#0, for other PGs 1us */
> > drm_WARN_ON(display->drm,
> > - intel_de_wait_for_set(display, SKL_FUSE_STATUS,
> > - SKL_FUSE_PG_DIST_STATUS(pg), 1));
> > + intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,
> > + SKL_FUSE_PG_DIST_STATUS(pg),
> > 1));
> > }
> >
> > static void hsw_power_well_enable(struct intel_display *display,
> > @@ -1445,8 +1445,8 @@ static void assert_chv_phy_status(struct
> > intel_display *display)
> > * The PHY may be busy with some initial calibration and whatnot,
> > * so the power state can take a while to actually change.
> > */
> > - if (intel_de_wait(display, DISPLAY_PHY_STATUS,
> > - phy_status_mask, phy_status, 10, NULL))
> > + if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
> > + phy_status_mask, phy_status, 10, NULL))
> > drm_err(display->drm,
> > "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> > (PHY_CONTROL=0x%08x)\n",
> > intel_de_read(display, DISPLAY_PHY_STATUS) &
> > phy_status_mask,
> > @@ -1476,8 +1476,8 @@ static void
> > chv_dpio_cmn_power_well_enable(struct intel_display *display,
> > vlv_set_power_well(display, power_well, true);
> >
> > /* Poll for phypwrgood signal */
> > - if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
> > - PHY_POWERGOOD(phy), 1))
> > + if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,
> > + PHY_POWERGOOD(phy), 1))
> > drm_err(display->drm, "Display PHY %d is not power up\n",
> > phy);
> >
> > @@ -1867,8 +1867,8 @@ static void xelpdp_aux_power_well_enable(struct
> > intel_display *display,
> > * bit.
> > */
> > if (DISPLAY_VER(display) >= 35) {
> > - if (intel_de_wait_for_set(display,
> > XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> > -
> > XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
> > + if (intel_de_wait_for_set_ms(display,
> > XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> > +
> > XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
> > drm_warn(display->drm,
> > "Timeout waiting for PHY %c AUX channel
> > power to be up\n",
> > phy_name(phy));
> > @@ -1888,8 +1888,8 @@ static void xelpdp_aux_power_well_disable(struct
> > intel_display *display,
> > 0);
> >
> > if (DISPLAY_VER(display) >= 35) {
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> > -
> > XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> > +
> > XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
> > drm_warn(display->drm,
> > "Timeout waiting for PHY %c AUX channel to
> > powerdown\n",
> > phy_name(phy));
> > @@ -1913,8 +1913,8 @@ static void xe2lpd_pica_power_well_enable(struct
> > intel_display *display,
> > intel_de_write(display, XE2LPD_PICA_PW_CTL,
> > XE2LPD_PICA_CTL_POWER_REQUEST);
> >
> > - if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL,
> > - XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > + if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,
> > + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > drm_dbg_kms(display->drm, "pica power well enable
> > timeout\n");
> >
> > drm_WARN(display->drm, 1, "Power well PICA timeout when
> > enabled");
> > @@ -1926,8 +1926,8 @@ static void xe2lpd_pica_power_well_disable(struct
> > intel_display *display,
> > {
> > intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);
> >
> > - if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL,
> > - XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > + if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,
> > + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > drm_dbg_kms(display->drm, "pica power well disable
> > timeout\n");
> >
> > drm_WARN(display->drm, 1, "Power well PICA timeout when
> > disabled");
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 27bb2199659f..14ed0ea22dd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -782,9 +782,9 @@ intel_dp_mst_hdcp_stream_encryption(struct
> > intel_connector *connector,
> > return -EINVAL;
> >
> > /* Wait for encryption confirmation */
> > - if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder,
> > port),
> > - stream_enc_status, enable ? stream_enc_status : 0,
> > - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> > NULL)) {
> > + if (intel_de_wait_ms(display, HDCP_STATUS(display, cpu_transcoder,
> > port),
> > + stream_enc_status, enable ? stream_enc_status : 0,
> > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> > NULL)) {
> > drm_err(display->drm, "Timed out waiting for transcoder: %s
> > stream encryption %s\n",
> > transcoder_name(cpu_transcoder),
> > str_enabled_disabled(enable));
> > return -ETIMEDOUT;
> > @@ -821,10 +821,10 @@ intel_dp_mst_hdcp2_stream_encryption(struct
> > intel_connector *connector,
> > return ret;
> >
> > /* Wait for encryption confirmation */
> > - if (intel_de_wait(display, HDCP2_STREAM_STATUS(display,
> > cpu_transcoder, pipe),
> > - STREAM_ENCRYPTION_STATUS,
> > - enable ? STREAM_ENCRYPTION_STATUS : 0,
> > - HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> > NULL)) {
> > + if (intel_de_wait_ms(display, HDCP2_STREAM_STATUS(display,
> > cpu_transcoder, pipe),
> > + STREAM_ENCRYPTION_STATUS,
> > + enable ? STREAM_ENCRYPTION_STATUS : 0,
> > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS,
> > NULL)) {
> > drm_err(display->drm, "Timed out waiting for transcoder: %s
> > stream encryption %s\n",
> > transcoder_name(cpu_transcoder),
> > str_enabled_disabled(enable));
> > return -ETIMEDOUT;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> > b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> > index 378f0836b5a5..4d1b6e2b93dc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> > @@ -390,7 +390,7 @@ static u32 bxt_get_grc(struct intel_display *display,
> > enum dpio_phy phy)
> > static void bxt_phy_wait_grc_done(struct intel_display *display,
> > enum dpio_phy phy)
> > {
> > - if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy),
> > GRC_DONE, 10))
> > + if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy),
> > GRC_DONE, 10))
> > drm_err(display->drm, "timeout waiting for PHY%d GRC\n",
> > phy);
> > }
> >
> > @@ -427,8 +427,8 @@ static void _bxt_dpio_phy_init(struct intel_display
> > *display, enum dpio_phy phy)
> > * The flag should get set in 100us according to the HW team, but
> > * use 1ms due to occasional timeouts observed with that.
> > */
> > - if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
> > - PHY_RESERVED | PHY_POWER_GOOD,
> > PHY_POWER_GOOD, 1, NULL))
> > + if (intel_de_wait_fw_ms(display, BXT_PORT_CL1CM_DW0(phy),
> > + PHY_RESERVED | PHY_POWER_GOOD,
> > PHY_POWER_GOOD, 1, NULL))
> > drm_err(display->drm, "timeout during PHY%d power on\n",
> > phy);
> >
> > @@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder
> > *encoder,
> > break;
> > }
> >
> > - if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000,
> > NULL))
> > + if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask,
> > 1000, NULL))
> > drm_WARN(display->drm, 1,
> > "timed out waiting for [ENCODER:%d:%s] port ready:
> > got 0x%x, expected 0x%x\n",
> > encoder->base.base.id, encoder->base.name,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 2e1f67be8eda..4f1db8493a2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -2019,7 +2019,7 @@ static void _vlv_enable_pll(const struct
> > intel_crtc_state *crtc_state)
> > intel_de_posting_read(display, DPLL(display, pipe));
> > udelay(150);
> >
> > - if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV,
> > 1))
> > + if (intel_de_wait_for_set_ms(display, DPLL(display, pipe),
> > DPLL_LOCK_VLV, 1))
> > drm_err(display->drm, "DPLL %d failed to lock\n", pipe);
> > }
> >
> > @@ -2165,7 +2165,7 @@ static void _chv_enable_pll(const struct
> > intel_crtc_state *crtc_state)
> > intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
> >
> > /* Check PLL is locked */
> > - if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV,
> > 1))
> > + if (intel_de_wait_for_set_ms(display, DPLL(display, pipe),
> > DPLL_LOCK_VLV, 1))
> > drm_err(display->drm, "PLL %d failed to lock\n", pipe);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 92c433f7b7e2..683bc61c03c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -1395,7 +1395,7 @@ static void skl_ddi_pll_enable(struct intel_display
> > *display,
> > /* the enable bit is always bit 31 */
> > intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
> >
> > - if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
> > + if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id),
> > 5))
> > drm_err(display->drm, "DPLL %d not locked\n", id);
> > }
> >
> > @@ -3921,7 +3921,7 @@ static void icl_pll_power_enable(struct
> > intel_display *display,
> > * The spec says we need to "wait" but it also says it should be
> > * immediate.
> > */
> > - if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
> > + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE,
> > 1))
> > drm_err(display->drm, "PLL %d Power not enabled\n",
> > pll->info->id);
> > }
> > @@ -3933,7 +3933,7 @@ static void icl_pll_enable(struct intel_display
> > *display,
> > intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
> >
> > /* Timeout is actually 600us. */
> > - if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
> > + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
> > drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> > }
> >
> > @@ -4046,7 +4046,7 @@ static void icl_pll_disable(struct intel_display
> > *display,
> > intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
> >
> > /* Timeout is actually 1us. */
> > - if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
> > + if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
> > drm_err(display->drm, "PLL %d locked\n", pll->info->id);
> >
> > /* DVFS post sequence would be here. See the comment above. */
> > @@ -4057,7 +4057,7 @@ static void icl_pll_disable(struct intel_display
> > *display,
> > * The spec says we need to "wait" but it also says it should be
> > * immediate.
> > */
> > - if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
> > + if (intel_de_wait_for_clear_ms(display, enable_reg,
> > PLL_POWER_STATE, 1))
> > drm_err(display->drm, "PLL %d Power not disabled\n",
> > pll->info->id);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a1e3083022ee..437d2fda20a7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -328,8 +328,8 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
> > intel_de_write(display, FBC_CONTROL, fbc_ctl);
> >
> > /* Wait for compressing bit to clear */
> > - if (intel_de_wait_for_clear(display, FBC_STATUS,
> > - FBC_STAT_COMPRESSING, 10)) {
> > + if (intel_de_wait_for_clear_ms(display, FBC_STATUS,
> > + FBC_STAT_COMPRESSING, 10)) {
> > drm_dbg_kms(display->drm, "FBC idle timed out\n");
> > return;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> > b/drivers/gpu/drm/i915/display/intel_flipq.c
> > index f162614a925d..1e9550cb66a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> > @@ -163,10 +163,10 @@ static void intel_flipq_preempt(struct intel_crtc
> > *crtc, bool preempt)
> > PIPEDMC_FQ_CTRL_PREEMPT, preempt ?
> > PIPEDMC_FQ_CTRL_PREEMPT : 0);
> >
> > if (preempt &&
> > - intel_de_wait_for_clear(display,
> > - PIPEDMC_FQ_STATUS(crtc->pipe),
> > - PIPEDMC_FQ_STATUS_BUSY,
> > - intel_flipq_preempt_timeout_ms(display)))
> > + intel_de_wait_for_clear_ms(display,
> > + PIPEDMC_FQ_STATUS(crtc->pipe),
> > + PIPEDMC_FQ_STATUS_BUSY,
> > +
> > intel_flipq_preempt_timeout_ms(display)))
> > drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt
> > timeout\n",
> > crtc->base.base.id, crtc->base.name);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > index 82f3a40ecac7..795012d7c24c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > @@ -449,7 +449,7 @@ gmbus_wait_idle(struct intel_display *display)
> > add_wait_queue(&display->gmbus.wait_queue, &wait);
> > intel_de_write_fw(display, GMBUS4(display), irq_enable);
> >
> > - ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0,
> > 10, NULL);
> > + ret = intel_de_wait_fw_ms(display, GMBUS2(display),
> > GMBUS_ACTIVE, 0, 10, NULL);
> >
> > intel_de_write_fw(display, GMBUS4(display), 0);
> > remove_wait_queue(&display->gmbus.wait_queue, &wait);
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index d01733b6460e..78c34466e402 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -428,7 +428,7 @@ static int intel_hdcp_load_keys(struct intel_display
> > *display)
> > static int intel_write_sha_text(struct intel_display *display, u32 sha_text)
> > {
> > intel_de_write(display, HDCP_SHA_TEXT, sha_text);
> > - if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY,
> > 1)) {
> > + if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
> > HDCP_SHA1_READY, 1)) {
> > drm_err(display->drm, "Timed out waiting for SHA1
> > ready\n");
> > return -ETIMEDOUT;
> > }
> > @@ -707,8 +707,8 @@ int intel_hdcp_validate_v_prime(struct
> > intel_connector *connector,
> > /* Tell the HW we're done with the hash and wait for it to ACK */
> > intel_de_write(display, HDCP_REP_CTL,
> > rep_ctl | HDCP_SHA1_COMPLETE_HASH);
> > - if (intel_de_wait_for_set(display, HDCP_REP_CTL,
> > - HDCP_SHA1_COMPLETE, 1)) {
> > + if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
> > + HDCP_SHA1_COMPLETE, 1)) {
> > drm_err(display->drm, "Timed out waiting for SHA1
> > complete\n");
> > return -ETIMEDOUT;
> > }
> > @@ -856,9 +856,9 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > HDCP_CONF_CAPTURE_AN);
> >
> > /* Wait for An to be acquired */
> > - if (intel_de_wait_for_set(display,
> > - HDCP_STATUS(display, cpu_transcoder,
> > port),
> > - HDCP_STATUS_AN_READY, 1)) {
> > + if (intel_de_wait_for_set_ms(display,
> > + HDCP_STATUS(display, cpu_transcoder,
> > port),
> > + HDCP_STATUS_AN_READY, 1)) {
> > drm_err(display->drm, "Timed out waiting for An\n");
> > return -ETIMEDOUT;
> > }
> > @@ -953,10 +953,10 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > }
> >
> > /* Wait for encryption confirmation */
> > - if (intel_de_wait_for_set(display,
> > - HDCP_STATUS(display, cpu_transcoder,
> > port),
> > - HDCP_STATUS_ENC,
> > -
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_set_ms(display,
> > + HDCP_STATUS(display, cpu_transcoder,
> > port),
> > + HDCP_STATUS_ENC,
> > +
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > drm_err(display->drm, "Timed out waiting for encryption\n");
> > return -ETIMEDOUT;
> > }
> > @@ -1013,9 +1013,9 @@ static int _intel_hdcp_disable(struct
> > intel_connector *connector)
> >
> > hdcp->hdcp_encrypted = false;
> > intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),
> > 0);
> > - if (intel_de_wait_for_clear(display,
> > - HDCP_STATUS(display, cpu_transcoder,
> > port),
> > - ~0,
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > + HDCP_STATUS(display, cpu_transcoder,
> > port),
> > + ~0,
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > drm_err(display->drm,
> > "Failed to disable HDCP, timeout clearing status\n");
> > return -ETIMEDOUT;
> > @@ -1940,11 +1940,10 @@ static int hdcp2_enable_encryption(struct
> > intel_connector *connector)
> > intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder,
> > port),
> > 0, CTL_LINK_ENCRYPTION_REQ);
> >
> > - ret = intel_de_wait_for_set(display,
> > - HDCP2_STATUS(display, cpu_transcoder,
> > - port),
> > - LINK_ENCRYPTION_STATUS,
> > -
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > + ret = intel_de_wait_for_set_ms(display,
> > + HDCP2_STATUS(display, cpu_transcoder,
> > port),
> > + LINK_ENCRYPTION_STATUS,
> > +
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > dig_port->hdcp.auth_status = true;
> >
> > return ret;
> > @@ -1966,11 +1965,10 @@ static int hdcp2_disable_encryption(struct
> > intel_connector *connector)
> > intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
> > CTL_LINK_ENCRYPTION_REQ, 0);
> >
> > - ret = intel_de_wait_for_clear(display,
> > - HDCP2_STATUS(display, cpu_transcoder,
> > - port),
> > - LINK_ENCRYPTION_STATUS,
> > -
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > + ret = intel_de_wait_for_clear_ms(display,
> > + HDCP2_STATUS(display,
> > cpu_transcoder, port),
> > + LINK_ENCRYPTION_STATUS,
> > +
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > if (ret == -ETIMEDOUT)
> > drm_dbg_kms(display->drm, "Disable Encryption Timedout");
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 5c637341b210..908faf17f93d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1598,8 +1598,8 @@ bool intel_hdmi_hdcp_check_link_once(struct
> > intel_digital_port *dig_port,
> > intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port),
> > ri.reg);
> >
> > /* Wait for Ri prime match */
> > - ret = intel_de_wait_for_set(display, HDCP_STATUS(display,
> > cpu_transcoder, port),
> > - HDCP_STATUS_RI_MATCH |
> > HDCP_STATUS_ENC, 1);
> > + ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display,
> > cpu_transcoder, port),
> > + HDCP_STATUS_RI_MATCH |
> > HDCP_STATUS_ENC, 1);
> > if (ret) {
> > drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
> > intel_de_read(display, HDCP_STATUS(display,
> > cpu_transcoder,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index b2413b385dc8..6bd42691de8f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1067,9 +1067,9 @@ static int __intel_lt_phy_p2p_write_once(struct
> > intel_encoder *encoder,
> > int ack;
> > u32 val;
> >
> > - if (intel_de_wait_for_clear(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > -
> > XELPDP_PORT_P2P_TRANSACTION_PENDING,
> > - XELPDP_MSGBUS_TIMEOUT_MS)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> > +
> > XELPDP_PORT_P2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_MS)) {
> > drm_dbg_kms(display->drm,
> > "PHY %c Timeout waiting for previous transaction to
> > complete. Resetting bus.\n",
> > phy_name(phy));
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> > b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index 48f4d8ed4f15..89aeb4fb340e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -329,7 +329,7 @@ static void intel_enable_lvds(struct intel_atomic_state
> > *state,
> > intel_de_rmw(display, PP_CONTROL(display, 0), 0,
> > PANEL_POWER_ON);
> > intel_de_posting_read(display, lvds_encoder->reg);
> >
> > - if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON,
> > 5000))
> > + if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON,
> > 5000))
> > drm_err(display->drm,
> > "timed out waiting for panel to power on\n");
> >
> > @@ -345,7 +345,7 @@ static void intel_disable_lvds(struct
> > intel_atomic_state *state,
> > struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
> >
> > intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON,
> > 0);
> > - if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_ON,
> > 1000))
> > + if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON,
> > 1000))
> > drm_err(display->drm,
> > "timed out waiting for panel to power off\n");
> >
> > @@ -384,7 +384,7 @@ static void intel_lvds_shutdown(struct intel_encoder
> > *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> >
> > - if (intel_de_wait_for_clear(display, PP_STATUS(display, 0),
> > PP_CYCLE_DELAY_ACTIVE, 5000))
> > + if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0),
> > PP_CYCLE_DELAY_ACTIVE, 5000))
> > drm_err(display->drm,
> > "timed out waiting for panel power cycle delay\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 3456c794e0e7..16619f7be5f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -305,7 +305,7 @@ static void ilk_enable_pch_transcoder(const struct
> > intel_crtc_state *crtc_state)
> > }
> >
> > intel_de_write(display, reg, val | TRANS_ENABLE);
> > - if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
> > + if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE,
> > 100))
> > drm_err(display->drm, "failed to enable transcoder %c\n",
> > pipe_name(pipe));
> > }
> > @@ -326,7 +326,7 @@ static void ilk_disable_pch_transcoder(struct
> > intel_crtc *crtc)
> > reg = PCH_TRANSCONF(pipe);
> > intel_de_rmw(display, reg, TRANS_ENABLE, 0);
> > /* wait for PCH transcoder off, transcoder state */
> > - if (intel_de_wait_for_clear(display, reg, TRANS_STATE_ENABLE, 50))
> > + if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE,
> > 50))
> > drm_err(display->drm, "failed to disable transcoder %c\n",
> > pipe_name(pipe));
> >
> > @@ -572,8 +572,8 @@ static void lpt_enable_pch_transcoder(const struct
> > intel_crtc_state *crtc_state)
> > val |= TRANS_INTERLACE_PROGRESSIVE;
> >
> > intel_de_write(display, LPT_TRANSCONF, val);
> > - if (intel_de_wait_for_set(display, LPT_TRANSCONF,
> > - TRANS_STATE_ENABLE, 100))
> > + if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
> > + TRANS_STATE_ENABLE, 100))
> > drm_err(display->drm, "Failed to enable PCH transcoder\n");
> > }
> >
> > @@ -581,8 +581,8 @@ static void lpt_disable_pch_transcoder(struct
> > intel_display *display)
> > {
> > intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);
> > /* wait for PCH transcoder off, transcoder state */
> > - if (intel_de_wait_for_clear(display, LPT_TRANSCONF,
> > - TRANS_STATE_ENABLE, 50))
> > + if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
> > + TRANS_STATE_ENABLE, 50))
> > drm_err(display->drm, "Failed to disable PCH transcoder\n");
> >
> > /* Workaround: clear timing override bit. */
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > index 22d8f720ae7d..3cc89048b027 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -390,12 +390,12 @@ int intel_pmdemand_atomic_check(struct
> > intel_atomic_state *state)
> >
> > static bool intel_pmdemand_check_prev_transaction(struct intel_display
> > *display)
> > {
> > - return !(intel_de_wait_for_clear(display,
> > -
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > - XELPDP_PMDEMAND_REQ_ENABLE,
> > 10) ||
> > - intel_de_wait_for_clear(display,
> > - GEN12_DCPR_STATUS_1,
> > -
> > XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> > + return !(intel_de_wait_for_clear_ms(display,
> > +
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > +
> > XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
> > + intel_de_wait_for_clear_ms(display,
> > + GEN12_DCPR_STATUS_1,
> > +
> > XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> > }
> >
> > void
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 00b06771ae2d..00ac652809cc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2277,8 +2277,8 @@ static void intel_psr_wait_exit_locked(struct
> > intel_dp *intel_dp)
> > }
> >
> > /* Wait till PSR is idle */
> > - if (intel_de_wait_for_clear(display, psr_status,
> > - psr_status_mask, 2000))
> > + if (intel_de_wait_for_clear_ms(display, psr_status,
> > + psr_status_mask, 2000))
> > drm_err(display->drm, "Timed out waiting PSR idle state\n");
> > }
> >
> > @@ -3166,7 +3166,7 @@ _psr2_ready_for_pipe_update_locked(const struct
> > intel_crtc_state *new_crtc_state
> > return true;
> > }
> >
> > - return intel_de_wait_for_clear(display,
> > + return intel_de_wait_for_clear_ms(display,
> > EDP_PSR2_STATUS(display,
> > cpu_transcoder),
> > EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
> > PSR_IDLE_TIMEOUT_MS);
> > @@ -3186,7 +3186,7 @@ _psr1_ready_for_pipe_update_locked(const struct
> > intel_crtc_state *new_crtc_state
> > return true;
> > }
> >
> > - return intel_de_wait_for_clear(display,
> > + return intel_de_wait_for_clear_ms(display,
> > psr_status_reg(display, cpu_transcoder),
> > EDP_PSR_STATUS_STATE_MASK,
> > PSR_IDLE_TIMEOUT_MS);
> > @@ -3264,7 +3264,7 @@ static bool __psr_wait_for_idle_locked(struct
> > intel_dp *intel_dp)
> >
> > mutex_unlock(&intel_dp->psr.lock);
> >
> > - err = intel_de_wait_for_clear(display, reg, mask, 50);
> > + err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
> > if (err)
> > drm_err(display->drm,
> > "Timed out waiting for PSR Idle for re-enable\n");
> > diff --git a/drivers/gpu/drm/i915/display/intel_sbi.c
> > b/drivers/gpu/drm/i915/display/intel_sbi.c
> > index dfcff924f0ed..b636a0060d39 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sbi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sbi.c
> > @@ -21,7 +21,8 @@ static int intel_sbi_rw(struct intel_display *display, u16
> > reg,
> >
> > lockdep_assert_held(&display->sbi.lock);
> >
> > - if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK,
> > SBI_STATUS_READY, 100, NULL)) {
> > + if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
> > + SBI_STATUS_MASK, SBI_STATUS_READY, 100,
> > NULL)) {
> > drm_err(display->drm, "timeout waiting for SBI to become
> > ready\n");
> > return -EBUSY;
> > }
> > @@ -37,7 +38,8 @@ static int intel_sbi_rw(struct intel_display *display, u16
> > reg,
> > cmd |= SBI_CTL_OP_WR;
> > intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);
> >
> > - if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK,
> > SBI_STATUS_READY, 100, &cmd)) {
> > + if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
> > + SBI_STATUS_MASK, SBI_STATUS_READY, 100,
> > &cmd)) {
> > drm_err(display->drm, "timeout waiting for SBI to complete
> > read\n");
> > return -ETIMEDOUT;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > index 4f028e6a91cd..295030742294 100644
> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > @@ -42,8 +42,8 @@ void intel_snps_phy_wait_for_calibration(struct
> > intel_display *display)
> > * which phy was affected and skip setup of the corresponding
> > * output later.
> > */
> > - if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),
> > - DG2_PHY_DP_TX_ACK_MASK, 25))
> > + if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
> > + DG2_PHY_DP_TX_ACK_MASK,
> > 25))
> > display->snps.phy_failed_calibration |= BIT(phy);
> > }
> > }
> > @@ -1863,7 +1863,7 @@ void intel_mpllb_enable(struct intel_encoder
> > *encoder,
> > * is locked at new settings. This register bit is sampling PHY
> > * dp_mpllb_state interface signal.
> > */
> > - if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5))
> > + if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
> > drm_dbg_kms(display->drm, "Port %c PLL not locked\n",
> > phy_name(phy));
> >
> > /*
> > @@ -1903,7 +1903,7 @@ void intel_mpllb_disable(struct intel_encoder
> > *encoder)
> > * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
> > * (dp_txX_ack) that the new transmitter setting request is completed.
> > */
> > - if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5))
> > + if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
> > drm_err(display->drm, "Port %c PLL not locked\n",
> > phy_name(phy));
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 7e17ca018748..1e21fd02685d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -1076,8 +1076,8 @@ xelpdp_tc_phy_wait_for_tcss_power(struct
> > intel_tc_port *tc, bool enabled)
> > static void xelpdp_tc_power_request_wa(struct intel_display *display, bool
> > enable)
> > {
> > /* check if mailbox is running busy */
> > - if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
> > - TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY,
> > 10)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > TCSS_DISP_MAILBOX_IN_CMD,
> > +
> > TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
> > drm_dbg_kms(display->drm,
> > "Timeout waiting for TCSS mailbox run/busy bit to
> > clear\n");
> > return;
> > @@ -1089,8 +1089,8 @@ static void xelpdp_tc_power_request_wa(struct
> > intel_display *display, bool enabl
> > TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1));
> >
> > /* wait to clear mailbox running busy bit before continuing */
> > - if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
> > - TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY,
> > 10)) {
> > + if (intel_de_wait_for_clear_ms(display,
> > TCSS_DISP_MAILBOX_IN_CMD,
> > +
> > TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
> > drm_dbg_kms(display->drm,
> > "Timeout after writing data to mailbox. Mailbox
> > run/busy bit did not clear\n");
> > return;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 00cbc126fb36..b92c42fde937 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -716,9 +716,9 @@ static void intel_vrr_tg_disable(const struct
> > intel_crtc_state *old_crtc_state)
> > intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > trans_vrr_ctl(old_crtc_state));
> >
> > - if (intel_de_wait_for_clear(display,
> > - TRANS_VRR_STATUS(display,
> > cpu_transcoder),
> > - VRR_STATUS_VRR_EN_LIVE, 1000))
> > + if (intel_de_wait_for_clear_ms(display,
> > + TRANS_VRR_STATUS(display,
> > cpu_transcoder),
> > + VRR_STATUS_VRR_EN_LIVE, 1000))
> > drm_err(display->drm, "Timed out waiting for VRR live status
> > to clear\n");
> >
> > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index 444682995658..19bdd8662359 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -94,8 +94,8 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi
> > *intel_dsi, enum port port)
> > mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
> > LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
> >
> > - if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
> > - mask, 100))
> > + if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display,
> > port),
> > + mask, 100))
> > drm_err(display->drm, "DPI FIFOs are not empty\n");
> > }
> >
> > @@ -162,8 +162,8 @@ static ssize_t intel_dsi_host_transfer(struct
> > mipi_dsi_host *host,
> >
> > /* note: this is never true for reads */
> > if (packet.payload_length) {
> > - if (intel_de_wait_for_clear(display,
> > MIPI_GEN_FIFO_STAT(display, port),
> > - data_mask, 50))
> > + if (intel_de_wait_for_clear_ms(display,
> > MIPI_GEN_FIFO_STAT(display, port),
> > + data_mask, 50))
> > drm_err(display->drm,
> > "Timeout waiting for HS/LP DATA FIFO
> > !full\n");
> >
> > @@ -176,8 +176,8 @@ static ssize_t intel_dsi_host_transfer(struct
> > mipi_dsi_host *host,
> > GEN_READ_DATA_AVAIL);
> > }
> >
> > - if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display,
> > port),
> > - ctrl_mask, 50)) {
> > + if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display,
> > port),
> > + ctrl_mask, 50)) {
> > drm_err(display->drm,
> > "Timeout waiting for HS/LP CTRL FIFO !full\n");
> > }
> > @@ -188,8 +188,8 @@ static ssize_t intel_dsi_host_transfer(struct
> > mipi_dsi_host *host,
> > /* ->rx_len is set only for reads */
> > if (msg->rx_len) {
> > data_mask = GEN_READ_DATA_AVAIL;
> > - if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display,
> > port),
> > - data_mask, 50))
> > + if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display,
> > port),
> > + data_mask, 50))
> > drm_err(display->drm,
> > "Timeout waiting for read data.\n");
> >
> > @@ -246,7 +246,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi,
> > u32 cmd, bool hs,
> > intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
> >
> > mask = SPL_PKT_SENT_INTERRUPT;
> > - if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
> > mask, 100))
> > + if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),
> > mask, 100))
> > drm_err(display->drm,
> > "Video mode command 0x%08x send failed.\n", cmd);
> >
> > @@ -352,8 +352,8 @@ static bool glk_dsi_enable_io(struct intel_encoder
> > *encoder)
> >
> > /* Wait for Pwr ACK */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> > - GLK_MIPIIO_PORT_POWERED, 20))
> > + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_MIPIIO_PORT_POWERED, 20))
> > drm_err(display->drm, "MIPIO port is
> > powergated\n");
> > }
> >
> > @@ -374,8 +374,8 @@ static void glk_dsi_device_ready(struct intel_encoder
> > *encoder)
> >
> > /* Wait for MIPI PHY status bit to set */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> > - GLK_PHY_STATUS_PORT_READY, 20))
> > + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_PHY_STATUS_PORT_READY,
> > 20))
> > drm_err(display->drm, "PHY is not ON\n");
> > }
> >
> > @@ -394,8 +394,8 @@ static void glk_dsi_device_ready(struct intel_encoder
> > *encoder)
> > ULPS_STATE_MASK, ULPS_STATE_ENTER |
> > DEVICE_READY);
> >
> > /* Wait for ULPS active */
> > - if (intel_de_wait_for_clear(display, MIPI_CTRL(display,
> > port),
> > - GLK_ULPS_NOT_ACTIVE,
> > 20))
> > + if (intel_de_wait_for_clear_ms(display,
> > MIPI_CTRL(display, port),
> > + GLK_ULPS_NOT_ACTIVE,
> > 20))
> > drm_err(display->drm, "ULPS not active\n");
> >
> > /* Exit ULPS */
> > @@ -413,16 +413,16 @@ static void glk_dsi_device_ready(struct
> > intel_encoder *encoder)
> >
> > /* Wait for Stop state */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
> > - GLK_DATA_LANE_STOP_STATE, 20))
> > + if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_DATA_LANE_STOP_STATE, 20))
> > drm_err(display->drm,
> > "Date lane not in STOP state\n");
> > }
> >
> > /* Wait for AFE LATCH */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
> > - AFE_LATCHOUT, 20))
> > + if (intel_de_wait_for_set_ms(display,
> > BXT_MIPI_PORT_CTRL(port),
> > + AFE_LATCHOUT, 20))
> > drm_err(display->drm,
> > "D-PHY not entering LP-11 state\n");
> > }
> > @@ -519,15 +519,15 @@ static void glk_dsi_enter_low_power_mode(struct
> > intel_encoder *encoder)
> >
> > /* Wait for MIPI PHY status bit to unset */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> > - GLK_PHY_STATUS_PORT_READY,
> > 20))
> > + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_PHY_STATUS_PORT_READY,
> > 20))
> > drm_err(display->drm, "PHY is not turning OFF\n");
> > }
> >
> > /* Wait for Pwr ACK bit to unset */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> > - GLK_MIPIIO_PORT_POWERED, 20))
> > + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_MIPIIO_PORT_POWERED,
> > 20))
> > drm_err(display->drm,
> > "MIPI IO Port is not powergated\n");
> > }
> > @@ -544,8 +544,8 @@ static void glk_dsi_disable_mipi_io(struct
> > intel_encoder *encoder)
> >
> > /* Wait for MIPI PHY status bit to unset */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
> > - GLK_PHY_STATUS_PORT_READY,
> > 20))
> > + if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display,
> > port),
> > + GLK_PHY_STATUS_PORT_READY,
> > 20))
> > drm_err(display->drm, "PHY is not turning OFF\n");
> > }
> >
> > @@ -595,8 +595,8 @@ static void vlv_dsi_clear_device_ready(struct
> > intel_encoder *encoder)
> > * Port A only. MIPI Port C has no similar bit for checking.
> > */
> > if ((display->platform.broxton || port == PORT_A) &&
> > - intel_de_wait_for_clear(display, port_ctrl,
> > - AFE_LATCHOUT, 30))
> > + intel_de_wait_for_clear_ms(display, port_ctrl,
> > + AFE_LATCHOUT, 30))
> > drm_err(display->drm, "DSI LP not going Low\n");
> >
> > /* Disable MIPI PHY transparent latch */
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> > index f078b9cda96c..a2da6285890b 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> > @@ -319,8 +319,8 @@ void bxt_dsi_pll_disable(struct intel_encoder
> > *encoder)
> > * PLL lock should deassert within 200us.
> > * Wait up to 1ms before timing out.
> > */
> > - if (intel_de_wait_for_clear(display, BXT_DSI_PLL_ENABLE,
> > - BXT_DSI_PLL_LOCKED, 1))
> > + if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,
> > + BXT_DSI_PLL_LOCKED, 1))
> > drm_err(display->drm,
> > "Timeout waiting for PLL lock deassertion\n");
> > }
> > @@ -568,8 +568,8 @@ void bxt_dsi_pll_enable(struct intel_encoder
> > *encoder,
> > intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0,
> > BXT_DSI_PLL_DO_ENABLE);
> >
> > /* Timeout and fail if PLL not locked */
> > - if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE,
> > - BXT_DSI_PLL_LOCKED, 1)) {
> > + if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,
> > + BXT_DSI_PLL_LOCKED, 1)) {
> > drm_err(display->drm,
> > "Timed out waiting for DSI PLL to lock\n");
> > return;
> > --
> > 2.49.1
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 00/16] drm/i915/de: Register polling cleanup
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
` (18 preceding siblings ...)
2025-11-11 8:01 ` [PATCH 00/16] " Jani Nikula
@ 2025-11-11 19:09 ` Ville Syrjälä
19 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjälä @ 2025-11-11 19:09 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
On Mon, Nov 10, 2025 at 07:27:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clean up the register polling stuff:
> - rename the current wait stuff to
> intel_de_wait_{,for_set,for_clear}_ms()
> - introduce intel_de_wait_{,for_set,for_clear}_us()
> - nuke intel_de_wait_custom()
> - change the wakelock stuff to use _fw() instead of
> hand rolling yet another level of register accessors
> - a few other minor cleanups
>
> After this it should be fairly easy to switch over to
> poll_timeout_us().
>
> Ville Syrjälä (16):
> drm/i915/de: Implement register waits one way
> drm/i915/de: Have intel_de_wait() hand out the final register value
> drm/i915/de: Include units in intel_de_wait*() function names
> drm/i915/de: Introduce intel_de_wait_us()
> drm/i915/de: Use intel_de_wait_us()
> drm/i915/de: Use intel_de_wait_ms() for the obvious cases
> drm/i915/de: Nuke intel_de_wait_custom()
> drm/i915/de: Introduce intel_de_wait_for_{set,clear}_us()
> drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
> drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()
> drm/1915/dpio: Stop using intel_de_wait_fw_ms()
> drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw()
> drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms()
> drm/i915/de: Replace __intel_de_wait_for_register_nowl() with
> intel_de_wait_fw_us_atomic()
> drm/i915/power: Use the intel_de_wait_ms() out value
> drm/i915/dpio: Use the intel_de_wait_ms() out value
Pushed to drm-intel-next. Thanks for the reviews.
>
> drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
> drivers/gpu/drm/i915/display/icl_dsi.c | 35 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--
> drivers/gpu/drm/i915/display/intel_crt.c | 16 +--
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 98 ++++++++--------
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++---
> drivers/gpu/drm/i915/display/intel_de.h | 107 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> .../drm/i915/display/intel_display_power.c | 14 +--
> .../i915/display/intel_display_power_well.c | 42 +++----
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 25 ++--
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 14 +--
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 10 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 +++--
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_flipq.c | 8 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++----
> drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 57 +++++-----
> drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 12 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 10 +-
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 18 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> drivers/gpu/drm/i915/display/intel_sbi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +-
> drivers/gpu/drm/i915/display/intel_tc.c | 8 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 54 ++++-----
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 8 +-
> .../drm/xe/compat-i915-headers/intel_uncore.h | 31 ++---
> 34 files changed, 369 insertions(+), 402 deletions(-)
>
> --
> 2.49.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2025-11-11 19:09 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
2025-11-11 4:52 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value Ville Syrjala
2025-11-11 4:14 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names Ville Syrjala
2025-11-11 4:21 ` Kandpal, Suraj
2025-11-11 17:45 ` Ville Syrjälä
2025-11-10 17:27 ` [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us() Ville Syrjala
2025-11-11 4:24 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 05/16] drm/i915/de: Use intel_de_wait_us() Ville Syrjala
2025-11-11 4:28 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases Ville Syrjala
2025-11-11 4:32 ` Kandpal, Suraj
2025-11-11 17:41 ` Ville Syrjälä
2025-11-10 17:27 ` [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom() Ville Syrjala
2025-11-11 4:33 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us() Ville Syrjala
2025-11-11 4:35 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us() Ville Syrjala
2025-11-11 4:38 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_us() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Ville Syrjala
2025-11-11 4:39 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_ms() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms() Ville Syrjala
2025-11-11 4:41 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw() Ville Syrjala
2025-11-11 4:44 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms() Ville Syrjala
2025-11-11 4:45 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic() Ville Syrjala
2025-11-11 4:46 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value Ville Syrjala
2025-11-11 4:48 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 16/16] drm/i915/dpio: " Ville Syrjala
2025-11-11 4:50 ` Kandpal, Suraj
2025-11-10 21:24 ` ✓ i915.CI.BAT: success for drm/i915/de: Register polling cleanup Patchwork
2025-11-11 3:41 ` ✗ i915.CI.Full: failure " Patchwork
2025-11-11 8:01 ` [PATCH 00/16] " Jani Nikula
2025-11-11 16:11 ` Ville Syrjälä
2025-11-11 19:09 ` Ville Syrjälä
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