* [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes
@ 2021-04-21 16:48 Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala
` (26 more replies)
0 siblings, 27 replies; 37+ messages in thread
From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The DDI buf trans functions keep turning into bad
spaghetti every time a new platform gets added.
Split the platforms up properly and turn the whole
thing into a vfunc to make it easier to manage
multiple platforms.
Ville Syrjälä (17):
drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans
drm/i915: Introduce hsw_get_buf_trans()
drm/i915: Wrap the platform specific buf trans structs into a union
drm/i915: Rename dkl phy buf trans tables
drm/i915: Wrap the buf trans tables into a struct
drm/i915: Introduce intel_get_buf_trans()
drm/i915; Return the whole buf_trans struct from get_buf_trans()
drm/i915: Store the HDMI default entry in the bug trans struct
drm/i915: Introduce encoder->get_buf_trans()
drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs
drm/i915: Introduce rkl_get_combo_buf_trans()
drm/i915: Fix dg1 buf trans tables
drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table
drm/i915: Fix ehl edp hbr2 vswing table
drm/i915: Clean up jsl/ehl buf trans functions
drm/i915: Nuke buf_trans hdmi functions
drm/i915: Add the missing adls vswing tables
drivers/gpu/drm/i915/display/intel_crt.c | 3 +
drivers/gpu/drm/i915/display/intel_ddi.c | 162 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 2354 ++++++++++-------
.../drm/i915/display/intel_ddi_buf_trans.h | 63 +-
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_fdi.c | 5 +-
7 files changed, 1432 insertions(+), 1163 deletions(-)
--
2.26.3
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^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala ` (25 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Give the hsw/bdw/skl buf trans stuff a better namespace. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++---- drivers/gpu/drm/i915/display/intel_ddi.h | 4 +- .../drm/i915/display/intel_ddi_buf_trans.c | 79 +++++++++---------- .../drm/i915/display/intel_ddi_buf_trans.h | 20 +++-- drivers/gpu/drm/i915/display/intel_fdi.c | 4 +- 5 files changed, 70 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f4249f087fa7..f40472cfce10 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -93,24 +93,21 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder, * values in advance. This function programs the correct values for * DP/eDP/FDI use cases. */ -void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = intel_ddi_get_buf_trans_edp(encoder, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(encoder, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && @@ -130,16 +127,16 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, * values in advance. This function programs the correct values for * HDMI/DVI use cases. */ -static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, - int level) +static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, + int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; - ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -912,15 +909,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); if (iboost == 0) { - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; int n_entries; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -993,9 +990,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, bxt_get_buf_trans(encoder, crtc_state, &n_entries); } else { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - intel_ddi_get_buf_trans_edp(encoder, &n_entries); + hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - intel_ddi_get_buf_trans_dp(encoder, &n_entries); + hsw_ddi_get_buf_trans_dp(encoder, &n_entries); } if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) @@ -2653,7 +2650,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else - intel_prepare_dp_ddi_buffers(encoder, crtc_state); + hsw_prepare_dp_ddi_buffers(encoder, crtc_state); intel_ddi_power_up_lanes(encoder, crtc_state); @@ -3101,7 +3098,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else - intel_prepare_hdmi_ddi_buffers(encoder, level); + hsw_prepare_hdmi_ddi_buffers(encoder, level); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) skl_ddi_set_iboost(encoder, crtc_state, level); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 59c6b01d4199..7d448485d887 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -40,8 +40,8 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder); void hsw_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); -void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port); void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 58d6417b8f3e..5b8c67c439a7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -12,7 +12,7 @@ * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_dp[] = { { 0x00FFFFFF, 0x0006000E, 0x0 }, { 0x00D75FFF, 0x0005000A, 0x0 }, { 0x00C30FFF, 0x00040006, 0x0 }, @@ -24,7 +24,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { { 0x80D75FFF, 0x000B0000, 0x0 }, }; -static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_fdi[] = { { 0x00FFFFFF, 0x0007000E, 0x0 }, { 0x00D75FFF, 0x000F000A, 0x0 }, { 0x00C30FFF, 0x00060006, 0x0 }, @@ -36,7 +36,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { { 0x00D75FFF, 0x001E0000, 0x0 }, }; -static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV d db */ { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ @@ -52,7 +52,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ }; -static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_edp[] = { { 0x00FFFFFF, 0x00000012, 0x0 }, { 0x00EBAFFF, 0x00020011, 0x0 }, { 0x00C71FFF, 0x0006000F, 0x0 }, @@ -64,7 +64,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { { 0x00DB6FFF, 0x000A000C, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_dp[] = { { 0x00FFFFFF, 0x0007000E, 0x0 }, { 0x00D75FFF, 0x000E000A, 0x0 }, { 0x00BEFFFF, 0x00140006, 0x0 }, @@ -76,7 +76,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { { 0x80D75FFF, 0x001B0002, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_fdi[] = { { 0x00FFFFFF, 0x0001000E, 0x0 }, { 0x00D75FFF, 0x0004000A, 0x0 }, { 0x00C30FFF, 0x00070006, 0x0 }, @@ -88,7 +88,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { { 0x00D75FFF, 0x000C0000, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV df db */ { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ @@ -103,7 +103,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { }; /* Skylake H and S */ -static const struct ddi_buf_trans skl_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_dp[] = { { 0x00002016, 0x000000A0, 0x0 }, { 0x00005012, 0x0000009B, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -116,7 +116,7 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = { }; /* Skylake U */ -static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_u_ddi_translations_dp[] = { { 0x0000201B, 0x000000A2, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x1 }, @@ -129,7 +129,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { }; /* Skylake Y */ -static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_dp[] = { { 0x00000018, 0x000000A2, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -142,7 +142,7 @@ static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { }; /* Kabylake H and S */ -static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_ddi_translations_dp[] = { { 0x00002016, 0x000000A0, 0x0 }, { 0x00005012, 0x0000009B, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -155,7 +155,7 @@ static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { }; /* Kabylake U */ -static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_u_ddi_translations_dp[] = { { 0x0000201B, 0x000000A1, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -168,7 +168,7 @@ static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { }; /* Kabylake Y */ -static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_y_ddi_translations_dp[] = { { 0x00001017, 0x000000A1, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -184,7 +184,7 @@ static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { * Skylake/Kabylake H and S * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000A9, 0x0 }, { 0x00007011, 0x000000A2, 0x0 }, @@ -201,7 +201,7 @@ static const struct ddi_buf_trans skl_ddi_translations_edp[] = { * Skylake/Kabylake U * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_u_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000A9, 0x0 }, { 0x00007011, 0x000000A2, 0x0 }, @@ -218,7 +218,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { * Skylake/Kabylake Y * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000AB, 0x0 }, { 0x00007011, 0x000000A4, 0x0 }, @@ -232,7 +232,7 @@ static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { }; /* Skylake/Kabylake U, H and S */ -static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_hdmi[] = { { 0x00000018, 0x000000AC, 0x0 }, { 0x00005012, 0x0000009D, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -247,7 +247,7 @@ static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { }; /* Skylake/Kabylake Y */ -static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_hdmi[] = { { 0x00000018, 0x000000A1, 0x0 }, { 0x00005012, 0x000000DF, 0x0 }, { 0x80007011, 0x000000CB, 0x3 }, @@ -261,7 +261,6 @@ static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { { 0x80000018, 0x000000C0, 0x3 }, }; - static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { /* Idx NT mV diff db */ { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ @@ -739,7 +738,7 @@ bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -753,7 +752,7 @@ bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -770,7 +769,7 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -791,7 +790,7 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -823,7 +822,7 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return skl_get_buf_trans_dp(encoder, n_entries); } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { if (IS_SKL_ULX(dev_priv) || @@ -847,20 +846,20 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) return min(n_entries, 9); } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_SKYLAKE(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = skl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -876,13 +875,13 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -897,9 +896,9 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, - int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, + int *n_entries) { if (IS_BROADWELL(dev_priv)) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); @@ -913,9 +912,9 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, + int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1374,13 +1373,13 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, bxt_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = n_entries - 1; } else if (DISPLAY_VER(dev_priv) == 9) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 7; } else if (IS_HASWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 6; } else { drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index f8f0ef87e977..6147d089e8e4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -12,7 +12,7 @@ struct drm_i915_private; struct intel_encoder; struct intel_crtc_state; -struct ddi_buf_trans { +struct hsw_ddi_buf_trans { u32 trans1; /* balance leg enable, de-emph level */ u32 trans2; /* vref sel, vswing */ u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ @@ -51,16 +51,14 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, - int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries); const struct bxt_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index d719cd9c5b73..4ee7dd2e124f 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -568,9 +568,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, u32 temp, i, rx_ctl_val; int n_entries; - intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries); + hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); - intel_prepare_dp_ddi_buffers(encoder, crtc_state); + hsw_prepare_dp_ddi_buffers(encoder, crtc_state); /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the * mode set "sequence for CRT port" document: -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala ` (24 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> All the other platforms handle the output_type stuff in their *_get_buf_trans() functions. Do the same for hsw/bdw/skl. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++-------- .../drm/i915/display/intel_ddi_buf_trans.c | 43 +++++++++++++------ .../drm/i915/display/intel_ddi_buf_trans.h | 10 ++--- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 4 files changed, 43 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f40472cfce10..3ebf3503bdf7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -102,12 +102,10 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct hsw_ddi_buf_trans *ddi_translations; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - ddi_translations = hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); - else - ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); + ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); + + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + return; /* If we're boosting the current, set bit 31 of trans1 */ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && @@ -128,6 +126,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, * HDMI/DVI use cases. */ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -136,7 +135,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct hsw_ddi_buf_trans *ddi_translations; - ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); + ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -912,12 +911,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, const struct hsw_ddi_buf_trans *ddi_translations; int n_entries; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); - else - ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); + ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -989,10 +983,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_get_buf_trans(encoder, crtc_state, &n_entries); } else { - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - hsw_ddi_get_buf_trans_edp(encoder, &n_entries); - else - hsw_ddi_get_buf_trans_dp(encoder, &n_entries); + hsw_get_buf_trans(encoder, crtc_state, &n_entries); } if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) @@ -3098,7 +3089,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else - hsw_prepare_hdmi_ddi_buffers(encoder, level); + hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) skl_ddi_set_iboost(encoder, crtc_state, level); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 5b8c67c439a7..56b521d030e1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -846,8 +846,8 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) return min(n_entries, 9); } -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) +static const struct hsw_ddi_buf_trans * +hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -875,8 +875,8 @@ hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) +static const struct hsw_ddi_buf_trans * +hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -896,10 +896,12 @@ hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, - int *n_entries) +static const struct hsw_ddi_buf_trans * +hsw_get_buf_trans_fdi(struct intel_encoder *encoder, + int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_BROADWELL(dev_priv)) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); return bdw_ddi_translations_fdi; @@ -912,9 +914,9 @@ hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, return NULL; } -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries) +static const struct hsw_ddi_buf_trans * +hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, + int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -932,6 +934,21 @@ hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, return NULL; } +const struct hsw_ddi_buf_trans * +hsw_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) + return hsw_get_buf_trans_fdi(encoder, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return hsw_get_buf_trans_hdmi(encoder, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return hsw_get_buf_trans_edp(encoder, n_entries); + else + return hsw_get_buf_trans_dp(encoder, n_entries); +} + static const struct bxt_ddi_buf_trans * bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { @@ -1373,13 +1390,13 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, bxt_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = n_entries - 1; } else if (DISPLAY_VER(dev_priv) == 9) { - hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { - hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 7; } else if (IS_HASWELL(dev_priv)) { - hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 6; } else { drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 6147d089e8e4..e5b64e94030c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -52,13 +52,9 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, int *default_entry); const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries); -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, int *n_entries); -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries); -const struct hsw_ddi_buf_trans * -hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries); +hsw_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries); const struct bxt_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 4ee7dd2e124f..223762020afe 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -568,7 +568,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, u32 temp, i, rx_ctl_val; int n_entries; - hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); + hsw_get_buf_trans(encoder, crtc_state, &n_entries); hsw_prepare_dp_ddi_buffers(encoder, crtc_state); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala ` (23 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> In order to abstact the buf trans stuff let's wrap the platform specific structs into a union. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 76 +- .../drm/i915/display/intel_ddi_buf_trans.c | 1318 ++++++++--------- .../drm/i915/display/intel_ddi_buf_trans.h | 28 +- 3 files changed, 715 insertions(+), 707 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3ebf3503bdf7..fd2dff10fc83 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -100,7 +100,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; - const struct hsw_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -114,9 +114,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, for (i = 0; i < n_entries; i++) { intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), - ddi_translations[i].trans1 | iboost_bit); + ddi_translations[i].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), - ddi_translations[i].trans2); + ddi_translations[i].hsw.trans2); } } @@ -133,7 +133,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; - const struct hsw_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -149,9 +149,9 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, /* Entry 9 is for HDMI: */ intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), - ddi_translations[level].trans1 | iboost_bit); + ddi_translations[level].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), - ddi_translations[level].trans2); + ddi_translations[level].hsw.trans2); } void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -908,7 +908,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); if (iboost == 0) { - const struct hsw_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; int n_entries; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -918,7 +918,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; - iboost = ddi_translations[level].i_boost; + iboost = ddi_translations[level].hsw.i_boost; } /* Make sure that the requested I_boost is valid */ @@ -938,7 +938,7 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct bxt_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; enum port port = encoder->port; int n_entries; @@ -949,10 +949,10 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, level = n_entries - 1; bxt_ddi_phy_set_signal_level(dev_priv, port, - ddi_translations[level].margin, - ddi_translations[level].scale, - ddi_translations[level].enable, - ddi_translations[level].deemphasis); + ddi_translations[level].bxt.margin, + ddi_translations[level].bxt.scale, + ddi_translations[level].bxt.enable, + ddi_translations[level].bxt.deemphasis); } static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, @@ -1011,7 +1011,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct cnl_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; enum port port = encoder->port; int n_entries, ln; u32 val; @@ -1033,8 +1033,8 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); + val |= SWING_SEL_UPPER(ddi_translations[level].cnl.dw2_swing_sel); + val |= SWING_SEL_LOWER(ddi_translations[level].cnl.dw2_swing_sel); /* Rcomp scalar is fixed as 0x98 for every table entry */ val |= RCOMP_SCALAR(0x98); intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); @@ -1045,9 +1045,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); - val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); - val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); + val |= POST_CURSOR_1(ddi_translations[level].cnl.dw4_post_cursor_1); + val |= POST_CURSOR_2(ddi_translations[level].cnl.dw4_post_cursor_2); + val |= CURSOR_COEFF(ddi_translations[level].cnl.dw4_cursor_coeff); intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); } @@ -1062,7 +1062,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, /* Program PORT_TX_DW7 */ val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); val &= ~N_SCALAR_MASK; - val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); + val |= N_SCALAR(ddi_translations[level].cnl.dw7_n_scalar); intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); } @@ -1132,7 +1132,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct cnl_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; u32 val; @@ -1173,8 +1173,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); + val |= SWING_SEL_UPPER(ddi_translations[level].cnl.dw2_swing_sel); + val |= SWING_SEL_LOWER(ddi_translations[level].cnl.dw2_swing_sel); /* Program Rcomp scalar for every table entry */ val |= RCOMP_SCALAR(0x98); intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); @@ -1185,16 +1185,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); - val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); - val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); + val |= POST_CURSOR_1(ddi_translations[level].cnl.dw4_post_cursor_1); + val |= POST_CURSOR_2(ddi_translations[level].cnl.dw4_post_cursor_2); + val |= CURSOR_COEFF(ddi_translations[level].cnl.dw4_cursor_coeff); intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); } /* Program PORT_TX_DW7 */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); val &= ~N_SCALAR_MASK; - val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); + val |= N_SCALAR(ddi_translations[level].cnl.dw7_n_scalar); intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); } @@ -1265,7 +1265,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const struct icl_mg_phy_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; int n_entries, ln; u32 val; @@ -1295,13 +1295,13 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations[level].cri_txdeemph_override_17_12); + ddi_translations[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations[level].cri_txdeemph_override_17_12); + ddi_translations[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); } @@ -1311,9 +1311,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations[level].cri_txdeemph_override_5_0) | + ddi_translations[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations[level].cri_txdeemph_override_11_6) | + ddi_translations[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); @@ -1321,9 +1321,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations[level].cri_txdeemph_override_5_0) | + ddi_translations[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations[level].cri_txdeemph_override_11_6) | + ddi_translations[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); @@ -1403,7 +1403,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; + const union intel_ddi_buf_trans_entry *ddi_translations; u32 val, dpcnt_mask, dpcnt_val; int n_entries, ln; @@ -1420,9 +1420,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK); - dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); - dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); - dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); + dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl.dkl_vswing_control); + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl.dkl_de_emphasis_control); + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl.dkl_preshoot_control); for (ln = 0; ln < 2; ln++) { intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 56b521d030e1..feef9d9a9dd8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -12,733 +12,733 @@ * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const struct hsw_ddi_buf_trans hsw_ddi_translations_dp[] = { - { 0x00FFFFFF, 0x0006000E, 0x0 }, - { 0x00D75FFF, 0x0005000A, 0x0 }, - { 0x00C30FFF, 0x00040006, 0x0 }, - { 0x80AAAFFF, 0x000B0000, 0x0 }, - { 0x00FFFFFF, 0x0005000A, 0x0 }, - { 0x00D75FFF, 0x000C0004, 0x0 }, - { 0x80C30FFF, 0x000B0000, 0x0 }, - { 0x00FFFFFF, 0x00040006, 0x0 }, - { 0x80D75FFF, 0x000B0000, 0x0 }, +static const union intel_ddi_buf_trans_entry hsw_ddi_translations_dp[] = { + { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, + { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, + { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, + { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, + { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, }; -static const struct hsw_ddi_buf_trans hsw_ddi_translations_fdi[] = { - { 0x00FFFFFF, 0x0007000E, 0x0 }, - { 0x00D75FFF, 0x000F000A, 0x0 }, - { 0x00C30FFF, 0x00060006, 0x0 }, - { 0x00AAAFFF, 0x001E0000, 0x0 }, - { 0x00FFFFFF, 0x000F000A, 0x0 }, - { 0x00D75FFF, 0x00160004, 0x0 }, - { 0x00C30FFF, 0x001E0000, 0x0 }, - { 0x00FFFFFF, 0x00060006, 0x0 }, - { 0x00D75FFF, 0x001E0000, 0x0 }, +static const union intel_ddi_buf_trans_entry hsw_ddi_translations_fdi[] = { + { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, + { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, + { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } }, + { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, }; -static const struct hsw_ddi_buf_trans hsw_ddi_translations_hdmi[] = { - /* Idx NT mV d T mV d db */ - { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ - { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ - { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ - { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ - { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ - { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ - { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ - { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ - { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ - { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ - { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ - { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ +static const union intel_ddi_buf_trans_entry hsw_ddi_translations_hdmi[] = { + /* Idx NT mV d T mV d db */ + { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ + { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ + { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2: 400 600 3.5 */ + { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3: 600 600 0 */ + { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */ + { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */ + { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6: 800 800 0 */ + { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7: 800 1000 2 */ + { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8: 850 850 0 */ + { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9: 900 900 0 */ + { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10: 950 950 0 */ + { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ }; -static const struct hsw_ddi_buf_trans bdw_ddi_translations_edp[] = { - { 0x00FFFFFF, 0x00000012, 0x0 }, - { 0x00EBAFFF, 0x00020011, 0x0 }, - { 0x00C71FFF, 0x0006000F, 0x0 }, - { 0x00AAAFFF, 0x000E000A, 0x0 }, - { 0x00FFFFFF, 0x00020011, 0x0 }, - { 0x00DB6FFF, 0x0005000F, 0x0 }, - { 0x00BEEFFF, 0x000A000C, 0x0 }, - { 0x00FFFFFF, 0x0005000F, 0x0 }, - { 0x00DB6FFF, 0x000A000C, 0x0 }, +static const union intel_ddi_buf_trans_entry bdw_ddi_translations_edp[] = { + { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, + { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, + { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, + { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } }, + { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } }, + { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } }, + { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, }; -static const struct hsw_ddi_buf_trans bdw_ddi_translations_dp[] = { - { 0x00FFFFFF, 0x0007000E, 0x0 }, - { 0x00D75FFF, 0x000E000A, 0x0 }, - { 0x00BEFFFF, 0x00140006, 0x0 }, - { 0x80B2CFFF, 0x001B0002, 0x0 }, - { 0x00FFFFFF, 0x000E000A, 0x0 }, - { 0x00DB6FFF, 0x00160005, 0x0 }, - { 0x80C71FFF, 0x001A0002, 0x0 }, - { 0x00F7DFFF, 0x00180004, 0x0 }, - { 0x80D75FFF, 0x001B0002, 0x0 }, +static const union intel_ddi_buf_trans_entry bdw_ddi_translations_dp[] = { + { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, + { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, + { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, + { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } }, + { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } }, + { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } }, + { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, }; -static const struct hsw_ddi_buf_trans bdw_ddi_translations_fdi[] = { - { 0x00FFFFFF, 0x0001000E, 0x0 }, - { 0x00D75FFF, 0x0004000A, 0x0 }, - { 0x00C30FFF, 0x00070006, 0x0 }, - { 0x00AAAFFF, 0x000C0000, 0x0 }, - { 0x00FFFFFF, 0x0004000A, 0x0 }, - { 0x00D75FFF, 0x00090004, 0x0 }, - { 0x00C30FFF, 0x000C0000, 0x0 }, - { 0x00FFFFFF, 0x00070006, 0x0 }, - { 0x00D75FFF, 0x000C0000, 0x0 }, +static const union intel_ddi_buf_trans_entry bdw_ddi_translations_fdi[] = { + { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, + { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, + { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } }, + { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } }, + { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } }, + { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, }; -static const struct hsw_ddi_buf_trans bdw_ddi_translations_hdmi[] = { - /* Idx NT mV d T mV df db */ - { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ - { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ - { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ - { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ - { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ - { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ - { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ - { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ - { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ - { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ +static const union intel_ddi_buf_trans_entry bdw_ddi_translations_hdmi[] = { + /* Idx NT mV d T mV df db */ + { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ + { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ + { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2: 400 800 6 */ + { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3: 450 450 0 */ + { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */ + { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */ + { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6: 600 1000 4.5 */ + { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7: 800 800 0 */ + { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8: 800 1000 2 */ + { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ }; /* Skylake H and S */ -static const struct hsw_ddi_buf_trans skl_ddi_translations_dp[] = { - { 0x00002016, 0x000000A0, 0x0 }, - { 0x00005012, 0x0000009B, 0x0 }, - { 0x00007011, 0x00000088, 0x0 }, - { 0x80009010, 0x000000C0, 0x1 }, - { 0x00002016, 0x0000009B, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000C0, 0x1 }, - { 0x00002016, 0x000000DF, 0x0 }, - { 0x80005012, 0x000000C0, 0x1 }, +static const union intel_ddi_buf_trans_entry skl_ddi_translations_dp[] = { + { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, + { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, + { .hsw = { 0x00007011, 0x00000088, 0x0 } }, + { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, + { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, + { .hsw = { 0x00002016, 0x000000DF, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; /* Skylake U */ -static const struct hsw_ddi_buf_trans skl_u_ddi_translations_dp[] = { - { 0x0000201B, 0x000000A2, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000CD, 0x1 }, - { 0x80009010, 0x000000C0, 0x1 }, - { 0x0000201B, 0x0000009D, 0x0 }, - { 0x80005012, 0x000000C0, 0x1 }, - { 0x80007011, 0x000000C0, 0x1 }, - { 0x00002016, 0x00000088, 0x0 }, - { 0x80005012, 0x000000C0, 0x1 }, +static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_dp[] = { + { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, + { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, + { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, + { .hsw = { 0x00002016, 0x00000088, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; /* Skylake Y */ -static const struct hsw_ddi_buf_trans skl_y_ddi_translations_dp[] = { - { 0x00000018, 0x000000A2, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000CD, 0x3 }, - { 0x80009010, 0x000000C0, 0x3 }, - { 0x00000018, 0x0000009D, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, - { 0x80007011, 0x000000C0, 0x3 }, - { 0x00000018, 0x00000088, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, +static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_dp[] = { + { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, + { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, + { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, + { .hsw = { 0x00000018, 0x00000088, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; /* Kabylake H and S */ -static const struct hsw_ddi_buf_trans kbl_ddi_translations_dp[] = { - { 0x00002016, 0x000000A0, 0x0 }, - { 0x00005012, 0x0000009B, 0x0 }, - { 0x00007011, 0x00000088, 0x0 }, - { 0x80009010, 0x000000C0, 0x1 }, - { 0x00002016, 0x0000009B, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000C0, 0x1 }, - { 0x00002016, 0x00000097, 0x0 }, - { 0x80005012, 0x000000C0, 0x1 }, +static const union intel_ddi_buf_trans_entry kbl_ddi_translations_dp[] = { + { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, + { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, + { .hsw = { 0x00007011, 0x00000088, 0x0 } }, + { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, + { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, + { .hsw = { 0x00002016, 0x00000097, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; /* Kabylake U */ -static const struct hsw_ddi_buf_trans kbl_u_ddi_translations_dp[] = { - { 0x0000201B, 0x000000A1, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000CD, 0x3 }, - { 0x80009010, 0x000000C0, 0x3 }, - { 0x0000201B, 0x0000009D, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, - { 0x80007011, 0x000000C0, 0x3 }, - { 0x00002016, 0x0000004F, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, +static const union intel_ddi_buf_trans_entry kbl_u_ddi_translations_dp[] = { + { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, + { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, + { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, + { .hsw = { 0x00002016, 0x0000004F, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; /* Kabylake Y */ -static const struct hsw_ddi_buf_trans kbl_y_ddi_translations_dp[] = { - { 0x00001017, 0x000000A1, 0x0 }, - { 0x00005012, 0x00000088, 0x0 }, - { 0x80007011, 0x000000CD, 0x3 }, - { 0x8000800F, 0x000000C0, 0x3 }, - { 0x00001017, 0x0000009D, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, - { 0x80007011, 0x000000C0, 0x3 }, - { 0x00001017, 0x0000004C, 0x0 }, - { 0x80005012, 0x000000C0, 0x3 }, +static const union intel_ddi_buf_trans_entry kbl_y_ddi_translations_dp[] = { + { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, + { .hsw = { 0x00005012, 0x00000088, 0x0 } }, + { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, + { .hsw = { 0x8000800F, 0x000000C0, 0x3 } }, + { .hsw = { 0x00001017, 0x0000009D, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, + { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, + { .hsw = { 0x00001017, 0x0000004C, 0x0 } }, + { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; /* * Skylake/Kabylake H and S * eDP 1.4 low vswing translation parameters */ -static const struct hsw_ddi_buf_trans skl_ddi_translations_edp[] = { - { 0x00000018, 0x000000A8, 0x0 }, - { 0x00004013, 0x000000A9, 0x0 }, - { 0x00007011, 0x000000A2, 0x0 }, - { 0x00009010, 0x0000009C, 0x0 }, - { 0x00000018, 0x000000A9, 0x0 }, - { 0x00006013, 0x000000A2, 0x0 }, - { 0x00007011, 0x000000A6, 0x0 }, - { 0x00000018, 0x000000AB, 0x0 }, - { 0x00007013, 0x0000009F, 0x0 }, - { 0x00000018, 0x000000DF, 0x0 }, +static const union intel_ddi_buf_trans_entry skl_ddi_translations_edp[] = { + { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, + { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, + { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, + { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, + { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, + { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, + { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, + { .hsw = { 0x00000018, 0x000000AB, 0x0 } }, + { .hsw = { 0x00007013, 0x0000009F, 0x0 } }, + { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; /* * Skylake/Kabylake U * eDP 1.4 low vswing translation parameters */ -static const struct hsw_ddi_buf_trans skl_u_ddi_translations_edp[] = { - { 0x00000018, 0x000000A8, 0x0 }, - { 0x00004013, 0x000000A9, 0x0 }, - { 0x00007011, 0x000000A2, 0x0 }, - { 0x00009010, 0x0000009C, 0x0 }, - { 0x00000018, 0x000000A9, 0x0 }, - { 0x00006013, 0x000000A2, 0x0 }, - { 0x00007011, 0x000000A6, 0x0 }, - { 0x00002016, 0x000000AB, 0x0 }, - { 0x00005013, 0x0000009F, 0x0 }, - { 0x00000018, 0x000000DF, 0x0 }, +static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_edp[] = { + { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, + { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, + { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, + { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, + { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, + { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, + { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, + { .hsw = { 0x00002016, 0x000000AB, 0x0 } }, + { .hsw = { 0x00005013, 0x0000009F, 0x0 } }, + { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; /* * Skylake/Kabylake Y * eDP 1.4 low vswing translation parameters */ -static const struct hsw_ddi_buf_trans skl_y_ddi_translations_edp[] = { - { 0x00000018, 0x000000A8, 0x0 }, - { 0x00004013, 0x000000AB, 0x0 }, - { 0x00007011, 0x000000A4, 0x0 }, - { 0x00009010, 0x000000DF, 0x0 }, - { 0x00000018, 0x000000AA, 0x0 }, - { 0x00006013, 0x000000A4, 0x0 }, - { 0x00007011, 0x0000009D, 0x0 }, - { 0x00000018, 0x000000A0, 0x0 }, - { 0x00006012, 0x000000DF, 0x0 }, - { 0x00000018, 0x0000008A, 0x0 }, +static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_edp[] = { + { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, + { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, + { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, + { .hsw = { 0x00009010, 0x000000DF, 0x0 } }, + { .hsw = { 0x00000018, 0x000000AA, 0x0 } }, + { .hsw = { 0x00006013, 0x000000A4, 0x0 } }, + { .hsw = { 0x00007011, 0x0000009D, 0x0 } }, + { .hsw = { 0x00000018, 0x000000A0, 0x0 } }, + { .hsw = { 0x00006012, 0x000000DF, 0x0 } }, + { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, }; /* Skylake/Kabylake U, H and S */ -static const struct hsw_ddi_buf_trans skl_ddi_translations_hdmi[] = { - { 0x00000018, 0x000000AC, 0x0 }, - { 0x00005012, 0x0000009D, 0x0 }, - { 0x00007011, 0x00000088, 0x0 }, - { 0x00000018, 0x000000A1, 0x0 }, - { 0x00000018, 0x00000098, 0x0 }, - { 0x00004013, 0x00000088, 0x0 }, - { 0x80006012, 0x000000CD, 0x1 }, - { 0x00000018, 0x000000DF, 0x0 }, - { 0x80003015, 0x000000CD, 0x1 }, /* Default */ - { 0x80003015, 0x000000C0, 0x1 }, - { 0x80000018, 0x000000C0, 0x1 }, +static const union intel_ddi_buf_trans_entry skl_ddi_translations_hdmi[] = { + { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, + { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, + { .hsw = { 0x00007011, 0x00000088, 0x0 } }, + { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, + { .hsw = { 0x00000018, 0x00000098, 0x0 } }, + { .hsw = { 0x00004013, 0x00000088, 0x0 } }, + { .hsw = { 0x80006012, 0x000000CD, 0x1 } }, + { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, + { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */ + { .hsw = { 0x80003015, 0x000000C0, 0x1 } }, + { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, }; /* Skylake/Kabylake Y */ -static const struct hsw_ddi_buf_trans skl_y_ddi_translations_hdmi[] = { - { 0x00000018, 0x000000A1, 0x0 }, - { 0x00005012, 0x000000DF, 0x0 }, - { 0x80007011, 0x000000CB, 0x3 }, - { 0x00000018, 0x000000A4, 0x0 }, - { 0x00000018, 0x0000009D, 0x0 }, - { 0x00004013, 0x00000080, 0x0 }, - { 0x80006013, 0x000000C0, 0x3 }, - { 0x00000018, 0x0000008A, 0x0 }, - { 0x80003015, 0x000000C0, 0x3 }, /* Default */ - { 0x80003015, 0x000000C0, 0x3 }, - { 0x80000018, 0x000000C0, 0x3 }, +static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_hdmi[] = { + { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, + { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, + { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, + { .hsw = { 0x00000018, 0x000000A4, 0x0 } }, + { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, + { .hsw = { 0x00004013, 0x00000080, 0x0 } }, + { .hsw = { 0x80006013, 0x000000C0, 0x3 } }, + { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, + { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */ + { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, + { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, }; -static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { - /* Idx NT mV diff db */ - { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ - { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ - { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ - { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ - { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ - { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ - { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ - { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ - { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ - { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ +static const union intel_ddi_buf_trans_entry bxt_ddi_translations_dp[] = { + /* Idx NT mV diff db */ + { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ + { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ + { .bxt = { 104, 0x9A, 0, 64, } }, /* 2: 400 6 */ + { .bxt = { 154, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ + { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ + { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ + { .bxt = { 154, 0x9A, 0, 64, } }, /* 6: 600 6 */ + { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ + { .bxt = { 154, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ + { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; -static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry bxt_ddi_translations_edp[] = { /* Idx NT mV diff db */ - { 26, 0, 0, 128, }, /* 0: 200 0 */ - { 38, 0, 0, 112, }, /* 1: 200 1.5 */ - { 48, 0, 0, 96, }, /* 2: 200 4 */ - { 54, 0, 0, 69, }, /* 3: 200 6 */ - { 32, 0, 0, 128, }, /* 4: 250 0 */ - { 48, 0, 0, 104, }, /* 5: 250 1.5 */ - { 54, 0, 0, 85, }, /* 6: 250 4 */ - { 43, 0, 0, 128, }, /* 7: 300 0 */ - { 54, 0, 0, 101, }, /* 8: 300 1.5 */ - { 48, 0, 0, 128, }, /* 9: 300 0 */ + { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ + { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ + { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */ + { .bxt = { 54, 0, 0, 69, } }, /* 3: 200 6 */ + { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */ + { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */ + { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */ + { .bxt = { 43, 0, 0, 128, } }, /* 7: 300 0 */ + { .bxt = { 54, 0, 0, 101, } }, /* 8: 300 1.5 */ + { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ }; /* BSpec has 2 recommended values - entries 0 and 8. * Using the entry with higher vswing. */ -static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { - /* Idx NT mV diff db */ - { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ - { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ - { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ - { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ - { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ - { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ - { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ - { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ - { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ - { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ +static const union intel_ddi_buf_trans_entry bxt_ddi_translations_hdmi[] = { + /* Idx NT mV diff db */ + { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ + { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ + { .bxt = { 52, 0x9A, 0, 64, } }, /* 2: 400 6 */ + { .bxt = { 42, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ + { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ + { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ + { .bxt = { 77, 0x9A, 0, 64, } }, /* 6: 600 6 */ + { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ + { .bxt = { 102, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ + { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; /* Voltage Swing Programming for VccIO 0.85V for DP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ - { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ - { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ - { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ - { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ - { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ - { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ - { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_85V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ + { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ + { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */ + { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; /* Voltage Swing Programming for VccIO 0.85V for HDMI */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ - { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ - { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ - { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ - { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_85V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ + { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ + { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */ + { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 */ + { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ }; /* Voltage Swing Programming for VccIO 0.85V for eDP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ - { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ - { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ - { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ - { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ - { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ - { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ - { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ - { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_85V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ + { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ + { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ + { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ + { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ + { .cnl = { 0xA, 0x66, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ + { .cnl = { 0xB, 0x70, 0x3C, 0x00, 0x03 } }, /* 460 600 2.3 */ + { .cnl = { 0xC, 0x75, 0x3C, 0x00, 0x03 } }, /* 537 700 2.3 */ + { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; /* Voltage Swing Programming for VccIO 0.95V for DP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ - { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ - { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ - { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ - { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ - { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ - { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ - { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_95V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ + { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ + { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */ + { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; /* Voltage Swing Programming for VccIO 0.95V for HDMI */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ - { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ - { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ - { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ - { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ - { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ - { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ - { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ - { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ - { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_95V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ + { .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ + { .cnl = { 0x5, 0x76, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ + { .cnl = { 0xA, 0x5E, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ + { .cnl = { 0xB, 0x69, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ + { .cnl = { 0xB, 0x79, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ + { .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */ + { .cnl = { 0x5, 0x76, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */ + { .cnl = { 0x6, 0x7D, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */ + { .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; /* Voltage Swing Programming for VccIO 0.95V for eDP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ - { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ - { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ - { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ - { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ - { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ - { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ - { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ - { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ - { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_95V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ + { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ + { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ + { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ + { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ + { .cnl = { 0xA, 0x61, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ + { .cnl = { 0xB, 0x68, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */ + { .cnl = { 0xC, 0x6E, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */ + { .cnl = { 0x4, 0x7F, 0x3A, 0x00, 0x05 } }, /* 460 600 2.3 */ + { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; /* Voltage Swing Programming for VccIO 1.05V for DP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ - { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ - { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ - { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ - { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ - { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ - { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ - { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_1_05V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ + { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ + { .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 400 1050 8.4 */ + { .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ + { .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ + { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 550 1050 5.6 */ + { .cnl = { 0x5, 0x76, 0x3E, 0x00, 0x01 } }, /* 850 900 0.5 */ + { .cnl = { 0x6, 0x7F, 0x36, 0x00, 0x09 } }, /* 750 1050 2.9 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; /* Voltage Swing Programming for VccIO 1.05V for HDMI */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ - { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ - { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ - { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ - { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ - { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ - { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ - { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ - { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ - { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_1_05V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ + { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ + { .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ + { .cnl = { 0xA, 0x5B, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ + { .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ + { .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ + { .cnl = { 0x6, 0x7C, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */ + { .cnl = { 0x5, 0x70, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */ + { .cnl = { 0x6, 0x7C, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */ + { .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; /* Voltage Swing Programming for VccIO 1.05V for eDP */ -static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { - /* NT mV Trans mV db */ - { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ - { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ - { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ - { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ - { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ - { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ - { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ - { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ - { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ +static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_1_05V[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ + { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ + { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ + { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ + { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ + { .cnl = { 0xA, 0x5E, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ + { .cnl = { 0xB, 0x64, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */ + { .cnl = { 0xE, 0x6A, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */ + { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; /* icl_combo_phy_ddi_translations */ -static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { - /* NT mV Trans mV db */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ - { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ - { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { - /* NT mV Trans mV db */ - { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ - { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ - { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ - { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ - { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ - { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ - { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ - { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ - { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ -}; - -static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { - /* NT mV Trans mV db */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ - { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ - { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { - /* NT mV Trans mV db */ - { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ - { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ - { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ - { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ - { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ -}; - -static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { - /* NT mV Trans mV db */ - { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ - { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ - { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ - { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { - /* NT mV Trans mV db */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ - { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ - { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ - { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ - { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ - { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ - { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ - { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ -}; - -static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { - /* NT mV Trans mV db */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ - { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ - { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ - { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ - { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ - { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ - { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ - { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ -}; - -static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { - /* NT mV Trans mV db */ - { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ - { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ - { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ - { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { - /* NT mV Trans mV db */ - { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ - { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ - { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ - { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { - /* Voltage swing pre-emphasis */ - { 0x18, 0x00, 0x00 }, /* 0 0 */ - { 0x1D, 0x00, 0x05 }, /* 0 1 */ - { 0x24, 0x00, 0x0C }, /* 0 2 */ - { 0x2B, 0x00, 0x14 }, /* 0 3 */ - { 0x21, 0x00, 0x00 }, /* 1 0 */ - { 0x2B, 0x00, 0x08 }, /* 1 1 */ - { 0x30, 0x00, 0x0F }, /* 1 2 */ - { 0x31, 0x00, 0x03 }, /* 2 0 */ - { 0x34, 0x00, 0x0B }, /* 2 1 */ - { 0x3F, 0x00, 0x00 }, /* 3 0 */ -}; - -static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { - /* Voltage swing pre-emphasis */ - { 0x18, 0x00, 0x00 }, /* 0 0 */ - { 0x1D, 0x00, 0x05 }, /* 0 1 */ - { 0x24, 0x00, 0x0C }, /* 0 2 */ - { 0x2B, 0x00, 0x14 }, /* 0 3 */ - { 0x26, 0x00, 0x00 }, /* 1 0 */ - { 0x2C, 0x00, 0x07 }, /* 1 1 */ - { 0x33, 0x00, 0x0C }, /* 1 2 */ - { 0x2E, 0x00, 0x00 }, /* 2 0 */ - { 0x36, 0x00, 0x09 }, /* 2 1 */ - { 0x3F, 0x00, 0x00 }, /* 3 0 */ -}; - -static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { - /* HDMI Preset VS Pre-emph */ - { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ - { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ - { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ - { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ - { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ - { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ - { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ - { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ - { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ - { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ -}; - -static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { - /* VS pre-emp Non-trans mV Pre-emph dB */ - { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ - { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ - { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ - { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ - { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ - { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ - { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ - { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ - { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ - { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ -}; - -static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { - /* VS pre-emp Non-trans mV Pre-emph dB */ - { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ - { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ - { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ - { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ - { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ - { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ - { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ - { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ - { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ - { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ -}; - -static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { - /* HDMI Preset VS Pre-emph */ - { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ - { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ - { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ - { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ - { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ - { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ - { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ - { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ - { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ - { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ -}; - -static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { - /* NT mV Trans mV db */ - { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ - { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ - { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { - /* NT mV Trans mV db */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ - { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ - { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ - { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ -}; - -static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { - /* NT mV Trans mV db */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ - { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ - { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ - { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ - { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ - { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_dp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ + { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ + { .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ + { .cnl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ + { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ + { .cnl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ + { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ + { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_hdmi[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ + { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ + { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */ + { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */ + { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ +}; + +static const union intel_ddi_buf_trans_entry ehl_combo_phy_ddi_translations_dp[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_hbr[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ + { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ + { .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ + { .cnl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ + { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ + { .cnl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ + { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ + { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ + { .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ + { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ + { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */ + { .cnl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */ + { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ + { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_rbr_hbr[] = { + /* Voltage swing pre-emphasis */ + { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ + { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ + { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ + { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ + { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */ + { .mg = { 0x2B, 0x00, 0x08 } }, /* 1 1 */ + { .mg = { 0x30, 0x00, 0x0F } }, /* 1 2 */ + { .mg = { 0x31, 0x00, 0x03 } }, /* 2 0 */ + { .mg = { 0x34, 0x00, 0x0B } }, /* 2 1 */ + { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hbr2_hbr3[] = { + /* Voltage swing pre-emphasis */ + { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ + { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ + { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ + { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ + { .mg = { 0x26, 0x00, 0x00 } }, /* 1 0 */ + { .mg = { 0x2C, 0x00, 0x07 } }, /* 1 1 */ + { .mg = { 0x33, 0x00, 0x0C } }, /* 1 2 */ + { .mg = { 0x2E, 0x00, 0x00 } }, /* 2 0 */ + { .mg = { 0x36, 0x00, 0x09 } }, /* 2 1 */ + { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ +}; + +static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hdmi[] = { + /* HDMI Preset VS Pre-emph */ + { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ + { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ + { .mg = { 0x29, 0x0, 0x0 } }, /* 3 650mV 0dB */ + { .mg = { 0x32, 0x0, 0x0 } }, /* 4 800mV 0dB */ + { .mg = { 0x3F, 0x0, 0x0 } }, /* 5 1000mV 0dB */ + { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ + { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ + { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */ + { .mg = { 0x37, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ + { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ +}; + +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans[] = { + /* VS pre-emp Non-trans mV Pre-emph dB */ + { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ + { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ + { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ + { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */ + { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ + { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ + { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ + { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ + { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ + { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ +}; + +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans_hbr2[] = { + /* VS pre-emp Non-trans mV Pre-emph dB */ + { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ + { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ + { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ + { .dkl = { 0x0, 0x0, 0x19 } }, /* 0 3 400mV 9.5 dB */ + { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ + { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ + { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ + { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ + { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ + { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ +}; + +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_hdmi_ddi_trans[] = { + /* HDMI Preset VS Pre-emph */ + { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ + { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ + { .dkl = { 0x4, 0x0, 0x0 } }, /* 3 650mV 0dB */ + { .dkl = { 0x2, 0x0, 0x0 } }, /* 4 800mV 0dB */ + { .dkl = { 0x0, 0x0, 0x0 } }, /* 5 1000mV 0dB */ + { .dkl = { 0x0, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ + { .dkl = { 0x0, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ + { .dkl = { 0x0, 0x0, 0x7 } }, /* 8 Full -2 dB */ + { .dkl = { 0x0, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ + { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ +}; + +static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_hbr[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const union intel_ddi_buf_trans_entry tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ + { .cnl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ + { .cnl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ + { .cnl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; /* * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries * that DisplayPort specification requires */ -static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { - /* VS pre-emp */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ +static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { + /* VS pre-emp */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ }; -static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = { - /* NT mV Trans mV db */ - { 0xA, 0x2F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ - { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ - { 0x6, 0x7D, 0x2A, 0x00, 0x15 }, /* 350 900 8.2 */ - { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x6E, 0x3E, 0x00, 0x01 }, /* 650 700 0.6 */ - { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_hbr[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { - /* NT mV Trans mV db */ - { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ - { 0xA, 0x50, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ - { 0xC, 0x61, 0x33, 0x00, 0x0C }, /* 350 700 6.0 */ - { 0x6, 0x7F, 0x2E, 0x00, 0x11 }, /* 350 900 8.2 */ - { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ - { 0xC, 0x5F, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ - { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ - { 0xC, 0x5F, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ - { 0x6, 0x7E, 0x36, 0x00, 0x09 }, /* 600 900 3.5 */ - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) +bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table) { return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -752,7 +752,7 @@ bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -769,7 +769,7 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -790,7 +790,7 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -822,7 +822,7 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return skl_get_buf_trans_dp(encoder, n_entries); } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { if (IS_SKL_ULX(dev_priv) || @@ -846,7 +846,7 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) return min(n_entries, 9); } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -854,12 +854,12 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - const struct hsw_ddi_buf_trans *ddi_translations = + const union intel_ddi_buf_trans_entry *ddi_translations = kbl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_SKYLAKE(dev_priv)) { - const struct hsw_ddi_buf_trans *ddi_translations = + const union intel_ddi_buf_trans_entry *ddi_translations = skl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -875,13 +875,13 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - const struct hsw_ddi_buf_trans *ddi_translations = + const union intel_ddi_buf_trans_entry *ddi_translations = skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -896,7 +896,7 @@ hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * hsw_get_buf_trans_fdi(struct intel_encoder *encoder, int *n_entries) { @@ -914,7 +914,7 @@ hsw_get_buf_trans_fdi(struct intel_encoder *encoder, return NULL; } -static const struct hsw_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { @@ -934,7 +934,7 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, return NULL; } -const struct hsw_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * hsw_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -949,14 +949,14 @@ hsw_get_buf_trans(struct intel_encoder *encoder, return hsw_get_buf_trans_dp(encoder, n_entries); } -static const struct bxt_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); return bxt_ddi_translations_dp; } -static const struct bxt_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -969,14 +969,14 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return bxt_get_buf_trans_dp(encoder, n_entries); } -static const struct bxt_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); return bxt_ddi_translations_hdmi; } -const struct bxt_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -988,7 +988,7 @@ bxt_get_buf_trans(struct intel_encoder *encoder, return bxt_get_buf_trans_dp(encoder, n_entries); } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1010,7 +1010,7 @@ cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1032,7 +1032,7 @@ cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1058,7 +1058,7 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * cnl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1070,7 +1070,7 @@ cnl_get_buf_trans(struct intel_encoder *encoder, return cnl_get_buf_trans_dp(encoder, n_entries); } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1079,7 +1079,7 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_hdmi; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1088,7 +1088,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_dp_hbr2; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1112,7 +1112,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * icl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1125,7 +1125,7 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct icl_mg_phy_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1134,7 +1134,7 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, return icl_mg_phy_ddi_translations_hdmi; } -static const struct icl_mg_phy_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1148,7 +1148,7 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, } } -const struct icl_mg_phy_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * icl_get_mg_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1159,7 +1159,7 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1168,7 +1168,7 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_hdmi; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1177,7 +1177,7 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, return ehl_combo_phy_ddi_translations_dp; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1192,7 +1192,7 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1205,7 +1205,7 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1214,7 +1214,7 @@ jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_hdmi; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1223,7 +1223,7 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_dp_hbr2; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1243,7 +1243,7 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1256,7 +1256,7 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1265,7 +1265,7 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, return icl_combo_phy_ddi_translations_hdmi; } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1294,7 +1294,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, } } -static const struct cnl_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1316,7 +1316,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * tgl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1329,7 +1329,7 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct tgl_dkl_phy_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1338,7 +1338,7 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, return tgl_dkl_phy_hdmi_ddi_trans; } -static const struct tgl_dkl_phy_ddi_buf_trans * +static const union intel_ddi_buf_trans_entry * tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1352,7 +1352,7 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, } } -const struct tgl_dkl_phy_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * tgl_get_dkl_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index e5b64e94030c..1f5ae0cd676b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -45,48 +45,56 @@ struct tgl_dkl_phy_ddi_buf_trans { u32 dkl_de_emphasis_control; }; -bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table); +union intel_ddi_buf_trans_entry { + struct hsw_ddi_buf_trans hsw; + struct bxt_ddi_buf_trans bxt; + struct cnl_ddi_buf_trans cnl; + struct icl_mg_phy_ddi_buf_trans mg; + struct tgl_dkl_phy_ddi_buf_trans dkl; +}; + +bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table); int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry); -const struct hsw_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * hsw_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct bxt_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * tgl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct tgl_dkl_phy_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * tgl_get_dkl_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * icl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct icl_mg_phy_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * icl_get_mg_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const struct cnl_ddi_buf_trans * +const union intel_ddi_buf_trans_entry * cnl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (2 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala ` (22 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Rename the dkl phy buf trans tables to follow the same naming pattern used by everyone else. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../gpu/drm/i915/display/intel_ddi_buf_trans.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index feef9d9a9dd8..879a2aca1140 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -604,7 +604,7 @@ static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hdmi[] { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -618,7 +618,7 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans[] = { { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans_hbr2[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr2[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -632,7 +632,7 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans_hbr2[] = { { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_hdmi_ddi_trans[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -1334,8 +1334,8 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); - return tgl_dkl_phy_hdmi_ddi_trans; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_hdmi); + return tgl_dkl_phy_ddi_translations_hdmi; } static const union intel_ddi_buf_trans_entry * @@ -1344,11 +1344,11 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); - return tgl_dkl_phy_dp_ddi_trans_hbr2; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr2); + return tgl_dkl_phy_ddi_translations_dp_hbr2; } else { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); - return tgl_dkl_phy_dp_ddi_trans; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr); + return tgl_dkl_phy_ddi_translations_dp_hbr; } } -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (3 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala ` (21 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Put a wrapper struct around the buf trans tables so that we can declare the number of entries and default HDMI entry alongside the table. @wrap@ identifier old =~ "^.*translations.*"; fresh identifier new = "_" ## old; type T; @@ <... static const T - old + new [] = { ... }; + + static const struct intel_ddi_buf_trans old = { + .entries = new, + .num_entries = ARRAY_SIZE(new), + }; ...> @@ identifier wrap.old; @@ ( - ARRAY_SIZE(old) + old.num_entries | - old + old.entries ) @@ @@ union intel_ddi_buf_trans_entry { ... }; + +struct intel_ddi_buf_trans { + const union intel_ddi_buf_trans_entry *entries; + u8 num_entries; +}; Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 599 +++++++++++++----- .../drm/i915/display/intel_ddi_buf_trans.h | 5 + 2 files changed, 432 insertions(+), 172 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 879a2aca1140..f87533200322 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -12,7 +12,7 @@ * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const union intel_ddi_buf_trans_entry hsw_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, @@ -24,7 +24,12 @@ static const union intel_ddi_buf_trans_entry hsw_ddi_translations_dp[] = { { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, }; -static const union intel_ddi_buf_trans_entry hsw_ddi_translations_fdi[] = { +static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = { + .entries = _hsw_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp), +}; + +static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, @@ -36,7 +41,12 @@ static const union intel_ddi_buf_trans_entry hsw_ddi_translations_fdi[] = { { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, }; -static const union intel_ddi_buf_trans_entry hsw_ddi_translations_hdmi[] = { +static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = { + .entries = _hsw_ddi_translations_fdi, + .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi), +}; + +static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV d db */ { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ @@ -52,7 +62,12 @@ static const union intel_ddi_buf_trans_entry hsw_ddi_translations_hdmi[] = { { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ }; -static const union intel_ddi_buf_trans_entry bdw_ddi_translations_edp[] = { +static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { + .entries = _hsw_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), +}; + +static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, @@ -64,7 +79,12 @@ static const union intel_ddi_buf_trans_entry bdw_ddi_translations_edp[] = { { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, }; -static const union intel_ddi_buf_trans_entry bdw_ddi_translations_dp[] = { +static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = { + .entries = _bdw_ddi_translations_edp, + .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp), +}; + +static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, @@ -76,7 +96,12 @@ static const union intel_ddi_buf_trans_entry bdw_ddi_translations_dp[] = { { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, }; -static const union intel_ddi_buf_trans_entry bdw_ddi_translations_fdi[] = { +static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = { + .entries = _bdw_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp), +}; + +static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, @@ -88,7 +113,12 @@ static const union intel_ddi_buf_trans_entry bdw_ddi_translations_fdi[] = { { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, }; -static const union intel_ddi_buf_trans_entry bdw_ddi_translations_hdmi[] = { +static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = { + .entries = _bdw_ddi_translations_fdi, + .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi), +}; + +static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV df db */ { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ @@ -102,8 +132,13 @@ static const union intel_ddi_buf_trans_entry bdw_ddi_translations_hdmi[] = { { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ }; +static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { + .entries = _bdw_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), +}; + /* Skylake H and S */ -static const union intel_ddi_buf_trans_entry skl_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -115,8 +150,13 @@ static const union intel_ddi_buf_trans_entry skl_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; +static const struct intel_ddi_buf_trans skl_ddi_translations_dp = { + .entries = _skl_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp), +}; + /* Skylake U */ -static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, @@ -128,8 +168,13 @@ static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; +static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = { + .entries = _skl_u_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp), +}; + /* Skylake Y */ -static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -141,8 +186,13 @@ static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; +static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = { + .entries = _skl_y_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp), +}; + /* Kabylake H and S */ -static const union intel_ddi_buf_trans_entry kbl_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -154,8 +204,13 @@ static const union intel_ddi_buf_trans_entry kbl_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; +static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = { + .entries = _kbl_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp), +}; + /* Kabylake U */ -static const union intel_ddi_buf_trans_entry kbl_u_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -167,8 +222,13 @@ static const union intel_ddi_buf_trans_entry kbl_u_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; +static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = { + .entries = _kbl_u_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp), +}; + /* Kabylake Y */ -static const union intel_ddi_buf_trans_entry kbl_y_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -180,11 +240,16 @@ static const union intel_ddi_buf_trans_entry kbl_y_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; +static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = { + .entries = _kbl_y_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp), +}; + /* * Skylake/Kabylake H and S * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry skl_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, @@ -197,11 +262,16 @@ static const union intel_ddi_buf_trans_entry skl_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; +static const struct intel_ddi_buf_trans skl_ddi_translations_edp = { + .entries = _skl_ddi_translations_edp, + .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp), +}; + /* * Skylake/Kabylake U * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, @@ -214,11 +284,16 @@ static const union intel_ddi_buf_trans_entry skl_u_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; +static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = { + .entries = _skl_u_ddi_translations_edp, + .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp), +}; + /* * Skylake/Kabylake Y * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, @@ -231,8 +306,13 @@ static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, }; +static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = { + .entries = _skl_y_ddi_translations_edp, + .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp), +}; + /* Skylake/Kabylake U, H and S */ -static const union intel_ddi_buf_trans_entry skl_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -246,8 +326,13 @@ static const union intel_ddi_buf_trans_entry skl_ddi_translations_hdmi[] = { { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, }; +static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { + .entries = _skl_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), +}; + /* Skylake/Kabylake Y */ -static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, @@ -261,7 +346,12 @@ static const union intel_ddi_buf_trans_entry skl_y_ddi_translations_hdmi[] = { { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, }; -static const union intel_ddi_buf_trans_entry bxt_ddi_translations_dp[] = { +static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { + .entries = _skl_y_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), +}; + +static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { /* Idx NT mV diff db */ { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ @@ -275,7 +365,12 @@ static const union intel_ddi_buf_trans_entry bxt_ddi_translations_dp[] = { { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; -static const union intel_ddi_buf_trans_entry bxt_ddi_translations_edp[] = { +static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = { + .entries = _bxt_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp), +}; + +static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { /* Idx NT mV diff db */ { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ @@ -289,10 +384,15 @@ static const union intel_ddi_buf_trans_entry bxt_ddi_translations_edp[] = { { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ }; +static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = { + .entries = _bxt_ddi_translations_edp, + .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp), +}; + /* BSpec has 2 recommended values - entries 0 and 8. * Using the entry with higher vswing. */ -static const union intel_ddi_buf_trans_entry bxt_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { /* Idx NT mV diff db */ { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ @@ -306,8 +406,13 @@ static const union intel_ddi_buf_trans_entry bxt_ddi_translations_hdmi[] = { { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; +static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { + .entries = _bxt_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), +}; + /* Voltage Swing Programming for VccIO 0.85V for DP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_85V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ @@ -321,8 +426,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_85V[] = { { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = { + .entries = _cnl_ddi_translations_dp_0_85V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V), +}; + /* Voltage Swing Programming for VccIO 0.85V for HDMI */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_85V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ @@ -333,8 +443,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_85V[] = { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = { + .entries = _cnl_ddi_translations_hdmi_0_85V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V), +}; + /* Voltage Swing Programming for VccIO 0.85V for eDP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_85V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_85V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ @@ -347,8 +462,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_85V[] = { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_85V = { + .entries = _cnl_ddi_translations_edp_0_85V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_85V), +}; + /* Voltage Swing Programming for VccIO 0.95V for DP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_95V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_95V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ @@ -362,8 +482,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_0_95V[] = { { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_95V = { + .entries = _cnl_ddi_translations_dp_0_95V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_95V), +}; + /* Voltage Swing Programming for VccIO 0.95V for HDMI */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_95V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ { .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ @@ -378,8 +503,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_0_95V[] = { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = { + .entries = _cnl_ddi_translations_hdmi_0_95V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V), +}; + /* Voltage Swing Programming for VccIO 0.95V for eDP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_95V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_95V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ @@ -393,8 +523,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_0_95V[] = { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_95V = { + .entries = _cnl_ddi_translations_edp_0_95V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_95V), +}; + /* Voltage Swing Programming for VccIO 1.05V for DP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_1_05V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_1_05V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ @@ -408,8 +543,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_dp_1_05V[] = { { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_1_05V = { + .entries = _cnl_ddi_translations_dp_1_05V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_1_05V), +}; + /* Voltage Swing Programming for VccIO 1.05V for HDMI */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_1_05V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ @@ -424,8 +564,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_hdmi_1_05V[] = { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = { + .entries = _cnl_ddi_translations_hdmi_1_05V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V), +}; + /* Voltage Swing Programming for VccIO 1.05V for eDP */ -static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_1_05V[] = { +static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_1_05V[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ @@ -438,8 +583,13 @@ static const union intel_ddi_buf_trans_entry cnl_ddi_translations_edp_1_05V[] = { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ }; +static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = { + .entries = _cnl_ddi_translations_edp_1_05V, + .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_1_05V), +}; + /* icl_combo_phy_ddi_translations */ -static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_dp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -453,7 +603,12 @@ static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_hbr2[] = { +static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2 = { + .entries = _icl_combo_phy_ddi_translations_dp_hbr2, + .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { /* NT mV Trans mV db */ { .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ @@ -467,7 +622,12 @@ static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_ { .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_hbr3[] = { +static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = { + .entries = _icl_combo_phy_ddi_translations_edp_hbr2, + .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr3[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -481,7 +641,12 @@ static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_edp_ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_hdmi[] = { +static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3 = { + .entries = _icl_combo_phy_ddi_translations_edp_hbr3, + .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr3), +}; + +static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ @@ -492,7 +657,12 @@ static const union intel_ddi_buf_trans_entry icl_combo_phy_ddi_translations_hdmi { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ }; -static const union intel_ddi_buf_trans_entry ehl_combo_phy_ddi_translations_dp[] = { +static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { + .entries = _icl_combo_phy_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), +}; + +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ @@ -506,7 +676,12 @@ static const union intel_ddi_buf_trans_entry ehl_combo_phy_ddi_translations_dp[] { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_hbr[] = { +static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { + .entries = _ehl_combo_phy_ddi_translations_dp, + .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), +}; + +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { /* NT mV Trans mV db */ { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ @@ -520,7 +695,12 @@ static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_hbr2[] = { +static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = { + .entries = _jsl_combo_phy_ddi_translations_edp_hbr, + .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr), +}; + +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = { /* NT mV Trans mV db */ { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ @@ -534,7 +714,12 @@ static const union intel_ddi_buf_trans_entry jsl_combo_phy_ddi_translations_edp_ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { +static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = { + .entries = _jsl_combo_phy_ddi_translations_edp_hbr2, + .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ @@ -548,7 +733,12 @@ static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_r { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = { + .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr, + .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr), +}; + +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ @@ -562,7 +752,12 @@ static const union intel_ddi_buf_trans_entry dg1_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_rbr_hbr[] = { +static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = { + .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3), +}; + +static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = { /* Voltage swing pre-emphasis */ { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ @@ -576,7 +771,12 @@ static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_rbr_hbr { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ }; -static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hbr2_hbr3[] = { +static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = { + .entries = _icl_mg_phy_ddi_translations_rbr_hbr, + .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr), +}; + +static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = { /* Voltage swing pre-emphasis */ { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ @@ -590,7 +790,12 @@ static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hbr2_hb { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ }; -static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hdmi[] = { +static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = { + .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3), +}; + +static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -604,7 +809,12 @@ static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hdmi[] { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr[] = { +static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { + .entries = _icl_mg_phy_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), +}; + +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -618,7 +828,12 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr2[] = { +static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = { + .entries = _tgl_dkl_phy_ddi_translations_dp_hbr, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr), +}; + +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -632,7 +847,12 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_hdmi[] = { +static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = { + .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -646,7 +866,12 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_hdmi[] { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ }; -static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_hbr[] = { +static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { + .entries = _tgl_dkl_phy_ddi_translations_hdmi, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), +}; + +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -660,7 +885,12 @@ static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_hbr2[] = { +static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = { + .entries = _tgl_combo_phy_ddi_translations_dp_hbr, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr), +}; + +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -674,7 +904,12 @@ static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { +static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = { + .entries = _tgl_combo_phy_ddi_translations_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ @@ -688,11 +923,16 @@ static const union intel_ddi_buf_trans_entry tgl_uy_combo_phy_ddi_translations_d { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; +static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = { + .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2), +}; + /* * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries * that DisplayPort specification requires */ -static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { /* VS pre-emp */ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ @@ -705,7 +945,12 @@ static const union intel_ddi_buf_trans_entry tgl_combo_phy_ddi_translations_edp_ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ }; -static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_hbr[] = { +static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = { + .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl), +}; + +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -719,7 +964,12 @@ static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = { + .entries = _rkl_combo_phy_ddi_translations_dp_hbr, + .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr), +}; + +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ @@ -733,9 +983,14 @@ static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; +static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = { + .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), +}; + bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table) { - return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; + return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl.entries; } static const union intel_ddi_buf_trans_entry * @@ -744,11 +999,11 @@ bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); - return bdw_ddi_translations_edp; + *n_entries = bdw_ddi_translations_edp.num_entries; + return bdw_ddi_translations_edp.entries; } else { - *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); - return bdw_ddi_translations_dp; + *n_entries = bdw_ddi_translations_dp.num_entries; + return bdw_ddi_translations_dp.entries; } } @@ -758,14 +1013,14 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_SKL_ULX(dev_priv)) { - *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); - return skl_y_ddi_translations_dp; + *n_entries = skl_y_ddi_translations_dp.num_entries; + return skl_y_ddi_translations_dp.entries; } else if (IS_SKL_ULT(dev_priv)) { - *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); - return skl_u_ddi_translations_dp; + *n_entries = skl_u_ddi_translations_dp.num_entries; + return skl_u_ddi_translations_dp.entries; } else { - *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); - return skl_ddi_translations_dp; + *n_entries = skl_ddi_translations_dp.num_entries; + return skl_ddi_translations_dp.entries; } } @@ -777,16 +1032,16 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); - return kbl_y_ddi_translations_dp; + *n_entries = kbl_y_ddi_translations_dp.num_entries; + return kbl_y_ddi_translations_dp.entries; } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv) || IS_CML_ULT(dev_priv)) { - *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); - return kbl_u_ddi_translations_dp; + *n_entries = kbl_u_ddi_translations_dp.num_entries; + return kbl_u_ddi_translations_dp.entries; } else { - *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); - return kbl_ddi_translations_dp; + *n_entries = kbl_ddi_translations_dp.num_entries; + return kbl_ddi_translations_dp.entries; } } @@ -800,17 +1055,17 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); - return skl_y_ddi_translations_edp; + *n_entries = skl_y_ddi_translations_edp.num_entries; + return skl_y_ddi_translations_edp.entries; } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv) || IS_CML_ULT(dev_priv)) { - *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); - return skl_u_ddi_translations_edp; + *n_entries = skl_u_ddi_translations_edp.num_entries; + return skl_u_ddi_translations_edp.entries; } else { - *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); - return skl_ddi_translations_edp; + *n_entries = skl_ddi_translations_edp.num_entries; + return skl_ddi_translations_edp.entries; } } @@ -829,11 +1084,11 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); - return skl_y_ddi_translations_hdmi; + *n_entries = skl_y_ddi_translations_hdmi.num_entries; + return skl_y_ddi_translations_hdmi.entries; } else { - *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); - return skl_ddi_translations_hdmi; + *n_entries = skl_ddi_translations_hdmi.num_entries; + return skl_ddi_translations_hdmi.entries; } } @@ -864,11 +1119,11 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_BROADWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); - return bdw_ddi_translations_dp; + *n_entries = bdw_ddi_translations_dp.num_entries; + return bdw_ddi_translations_dp.entries; } else if (IS_HASWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); - return hsw_ddi_translations_dp; + *n_entries = hsw_ddi_translations_dp.num_entries; + return hsw_ddi_translations_dp.entries; } *n_entries = 0; @@ -888,8 +1143,8 @@ hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } else if (IS_BROADWELL(dev_priv)) { return bdw_get_buf_trans_edp(encoder, n_entries); } else if (IS_HASWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); - return hsw_ddi_translations_dp; + *n_entries = hsw_ddi_translations_dp.num_entries; + return hsw_ddi_translations_dp.entries; } *n_entries = 0; @@ -903,11 +1158,11 @@ hsw_get_buf_trans_fdi(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_BROADWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); - return bdw_ddi_translations_fdi; + *n_entries = bdw_ddi_translations_fdi.num_entries; + return bdw_ddi_translations_fdi.entries; } else if (IS_HASWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); - return hsw_ddi_translations_fdi; + *n_entries = hsw_ddi_translations_fdi.num_entries; + return hsw_ddi_translations_fdi.entries; } *n_entries = 0; @@ -923,11 +1178,11 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { return skl_get_buf_trans_hdmi(dev_priv, n_entries); } else if (IS_BROADWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); - return bdw_ddi_translations_hdmi; + *n_entries = bdw_ddi_translations_hdmi.num_entries; + return bdw_ddi_translations_hdmi.entries; } else if (IS_HASWELL(dev_priv)) { - *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); - return hsw_ddi_translations_hdmi; + *n_entries = hsw_ddi_translations_hdmi.num_entries; + return hsw_ddi_translations_hdmi.entries; } *n_entries = 0; @@ -952,8 +1207,8 @@ hsw_get_buf_trans(struct intel_encoder *encoder, static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { - *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); - return bxt_ddi_translations_dp; + *n_entries = bxt_ddi_translations_dp.num_entries; + return bxt_ddi_translations_dp.entries; } static const union intel_ddi_buf_trans_entry * @@ -962,8 +1217,8 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); - return bxt_ddi_translations_edp; + *n_entries = bxt_ddi_translations_edp.num_entries; + return bxt_ddi_translations_edp.entries; } return bxt_get_buf_trans_dp(encoder, n_entries); @@ -972,8 +1227,8 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { - *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); - return bxt_ddi_translations_hdmi; + *n_entries = bxt_ddi_translations_hdmi.num_entries; + return bxt_ddi_translations_hdmi.entries; } const union intel_ddi_buf_trans_entry * @@ -995,14 +1250,14 @@ cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); - return cnl_ddi_translations_hdmi_0_85V; + *n_entries = cnl_ddi_translations_hdmi_0_85V.num_entries; + return cnl_ddi_translations_hdmi_0_85V.entries; } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); - return cnl_ddi_translations_hdmi_0_95V; + *n_entries = cnl_ddi_translations_hdmi_0_95V.num_entries; + return cnl_ddi_translations_hdmi_0_95V.entries; } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); - return cnl_ddi_translations_hdmi_1_05V; + *n_entries = cnl_ddi_translations_hdmi_1_05V.num_entries; + return cnl_ddi_translations_hdmi_1_05V.entries; } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1017,14 +1272,14 @@ cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); - return cnl_ddi_translations_dp_0_85V; + *n_entries = cnl_ddi_translations_dp_0_85V.num_entries; + return cnl_ddi_translations_dp_0_85V.entries; } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); - return cnl_ddi_translations_dp_0_95V; + *n_entries = cnl_ddi_translations_dp_0_95V.num_entries; + return cnl_ddi_translations_dp_0_95V.entries; } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); - return cnl_ddi_translations_dp_1_05V; + *n_entries = cnl_ddi_translations_dp_1_05V.num_entries; + return cnl_ddi_translations_dp_1_05V.entries; } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1040,14 +1295,14 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) if (dev_priv->vbt.edp.low_vswing) { if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); - return cnl_ddi_translations_edp_0_85V; + *n_entries = cnl_ddi_translations_edp_0_85V.num_entries; + return cnl_ddi_translations_edp_0_85V.entries; } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); - return cnl_ddi_translations_edp_0_95V; + *n_entries = cnl_ddi_translations_edp_0_95V.num_entries; + return cnl_ddi_translations_edp_0_95V.entries; } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); - return cnl_ddi_translations_edp_1_05V; + *n_entries = cnl_ddi_translations_edp_1_05V.num_entries; + return cnl_ddi_translations_edp_1_05V.entries; } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1075,8 +1330,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); - return icl_combo_phy_ddi_translations_hdmi; + *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; + return icl_combo_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1084,8 +1339,8 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); - return icl_combo_phy_ddi_translations_dp_hbr2; + *n_entries = icl_combo_phy_ddi_translations_dp_hbr2.num_entries; + return icl_combo_phy_ddi_translations_dp_hbr2.entries; } static const union intel_ddi_buf_trans_entry * @@ -1096,17 +1351,17 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 540000) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); - return icl_combo_phy_ddi_translations_edp_hbr3; + *n_entries = icl_combo_phy_ddi_translations_edp_hbr3.num_entries; + return icl_combo_phy_ddi_translations_edp_hbr3.entries; } else if (dev_priv->vbt.edp.low_vswing) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); - return icl_combo_phy_ddi_translations_edp_hbr2; + *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; + return icl_combo_phy_ddi_translations_edp_hbr2.entries; } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3); - return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3; + *n_entries = dg1_combo_phy_ddi_translations_dp_hbr2_hbr3.num_entries; + return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3.entries; } else if (IS_DG1(dev_priv)) { - *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr); - return dg1_combo_phy_ddi_translations_dp_rbr_hbr; + *n_entries = dg1_combo_phy_ddi_translations_dp_rbr_hbr.num_entries; + return dg1_combo_phy_ddi_translations_dp_rbr_hbr.entries; } return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1130,8 +1385,8 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); - return icl_mg_phy_ddi_translations_hdmi; + *n_entries = icl_mg_phy_ddi_translations_hdmi.num_entries; + return icl_mg_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1140,11 +1395,11 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); - return icl_mg_phy_ddi_translations_hbr2_hbr3; + *n_entries = icl_mg_phy_ddi_translations_hbr2_hbr3.num_entries; + return icl_mg_phy_ddi_translations_hbr2_hbr3.entries; } else { - *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); - return icl_mg_phy_ddi_translations_rbr_hbr; + *n_entries = icl_mg_phy_ddi_translations_rbr_hbr.num_entries; + return icl_mg_phy_ddi_translations_rbr_hbr.entries; } } @@ -1164,8 +1419,8 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); - return icl_combo_phy_ddi_translations_hdmi; + *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; + return icl_combo_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1173,8 +1428,8 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); - return ehl_combo_phy_ddi_translations_dp; + *n_entries = ehl_combo_phy_ddi_translations_dp.num_entries; + return ehl_combo_phy_ddi_translations_dp.entries; } static const union intel_ddi_buf_trans_entry * @@ -1185,8 +1440,8 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); - return icl_combo_phy_ddi_translations_edp_hbr2; + *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; + return icl_combo_phy_ddi_translations_edp_hbr2.entries; } return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1210,8 +1465,8 @@ jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); - return icl_combo_phy_ddi_translations_hdmi; + *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; + return icl_combo_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1219,8 +1474,8 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); - return icl_combo_phy_ddi_translations_dp_hbr2; + *n_entries = icl_combo_phy_ddi_translations_dp_hbr2.num_entries; + return icl_combo_phy_ddi_translations_dp_hbr2.entries; } static const union intel_ddi_buf_trans_entry * @@ -1232,11 +1487,11 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, if (dev_priv->vbt.edp.low_vswing) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); - return jsl_combo_phy_ddi_translations_edp_hbr2; + *n_entries = jsl_combo_phy_ddi_translations_edp_hbr2.num_entries; + return jsl_combo_phy_ddi_translations_edp_hbr2.entries; } else { - *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); - return jsl_combo_phy_ddi_translations_edp_hbr; + *n_entries = jsl_combo_phy_ddi_translations_edp_hbr.num_entries; + return jsl_combo_phy_ddi_translations_edp_hbr.entries; } } @@ -1261,8 +1516,8 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); - return icl_combo_phy_ddi_translations_hdmi; + *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; + return icl_combo_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1274,22 +1529,22 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, if (crtc_state->port_clock > 270000) { if (IS_ROCKETLAKE(dev_priv)) { - *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3); - return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3; + *n_entries = rkl_combo_phy_ddi_translations_dp_hbr2_hbr3.num_entries; + return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3.entries; } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { - *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); - return tgl_uy_combo_phy_ddi_translations_dp_hbr2; + *n_entries = tgl_uy_combo_phy_ddi_translations_dp_hbr2.num_entries; + return tgl_uy_combo_phy_ddi_translations_dp_hbr2.entries; } else { - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); - return tgl_combo_phy_ddi_translations_dp_hbr2; + *n_entries = tgl_combo_phy_ddi_translations_dp_hbr2.num_entries; + return tgl_combo_phy_ddi_translations_dp_hbr2.entries; } } else { if (IS_ROCKETLAKE(dev_priv)) { - *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr); - return rkl_combo_phy_ddi_translations_dp_hbr; + *n_entries = rkl_combo_phy_ddi_translations_dp_hbr.num_entries; + return rkl_combo_phy_ddi_translations_dp_hbr.entries; } else { - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); - return tgl_combo_phy_ddi_translations_dp_hbr; + *n_entries = tgl_combo_phy_ddi_translations_dp_hbr.num_entries; + return tgl_combo_phy_ddi_translations_dp_hbr.entries; } } } @@ -1303,14 +1558,14 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); - return icl_combo_phy_ddi_translations_edp_hbr3; + *n_entries = icl_combo_phy_ddi_translations_edp_hbr3.num_entries; + return icl_combo_phy_ddi_translations_edp_hbr3.entries; } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); - return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; + *n_entries = tgl_combo_phy_ddi_translations_edp_hbr2_hobl.num_entries; + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl.entries; } else if (dev_priv->vbt.edp.low_vswing) { - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); - return icl_combo_phy_ddi_translations_edp_hbr2; + *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; + return icl_combo_phy_ddi_translations_edp_hbr2.entries; } return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1334,8 +1589,8 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_hdmi); - return tgl_dkl_phy_ddi_translations_hdmi; + *n_entries = tgl_dkl_phy_ddi_translations_hdmi.num_entries; + return tgl_dkl_phy_ddi_translations_hdmi.entries; } static const union intel_ddi_buf_trans_entry * @@ -1344,11 +1599,11 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr2); - return tgl_dkl_phy_ddi_translations_dp_hbr2; + *n_entries = tgl_dkl_phy_ddi_translations_dp_hbr2.num_entries; + return tgl_dkl_phy_ddi_translations_dp_hbr2.entries; } else { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr); - return tgl_dkl_phy_ddi_translations_dp_hbr; + *n_entries = tgl_dkl_phy_ddi_translations_dp_hbr.num_entries; + return tgl_dkl_phy_ddi_translations_dp_hbr.entries; } } diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 1f5ae0cd676b..363f96709079 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -53,6 +53,11 @@ union intel_ddi_buf_trans_entry { struct tgl_dkl_phy_ddi_buf_trans dkl; }; +struct intel_ddi_buf_trans { + const union intel_ddi_buf_trans_entry *entries; + u8 num_entries; +}; + bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table); int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (4 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala ` (20 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Add a small helper to get the buf trans entris+num_entries from the struct. Should avoid copy-paste errors in the platform specific get_buf_trans() functions. @@ identifier T, N; @@ - *N = T.num_entries; - return T.entries; + return intel_get_buf_trans(&T, N); @@ @@ is_hobl_buf_trans(...) { ... } + + static const union intel_ddi_buf_trans_entry * + intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) + { + *num_entries = ddi_translations->num_entries; + return ddi_translations->entries; + } Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 245 +++++++++--------- 1 file changed, 125 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index f87533200322..413e3c55027e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -993,17 +993,24 @@ bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table) return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl.entries; } +static const union intel_ddi_buf_trans_entry * +intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) +{ + *num_entries = ddi_translations->num_entries; + return ddi_translations->entries; +} + static const union intel_ddi_buf_trans_entry * bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = bdw_ddi_translations_edp.num_entries; - return bdw_ddi_translations_edp.entries; + return intel_get_buf_trans(&bdw_ddi_translations_edp, + n_entries); } else { - *n_entries = bdw_ddi_translations_dp.num_entries; - return bdw_ddi_translations_dp.entries; + return intel_get_buf_trans(&bdw_ddi_translations_dp, + n_entries); } } @@ -1013,14 +1020,14 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_SKL_ULX(dev_priv)) { - *n_entries = skl_y_ddi_translations_dp.num_entries; - return skl_y_ddi_translations_dp.entries; + return intel_get_buf_trans(&skl_y_ddi_translations_dp, + n_entries); } else if (IS_SKL_ULT(dev_priv)) { - *n_entries = skl_u_ddi_translations_dp.num_entries; - return skl_u_ddi_translations_dp.entries; + return intel_get_buf_trans(&skl_u_ddi_translations_dp, + n_entries); } else { - *n_entries = skl_ddi_translations_dp.num_entries; - return skl_ddi_translations_dp.entries; + return intel_get_buf_trans(&skl_ddi_translations_dp, + n_entries); } } @@ -1032,16 +1039,16 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = kbl_y_ddi_translations_dp.num_entries; - return kbl_y_ddi_translations_dp.entries; + return intel_get_buf_trans(&kbl_y_ddi_translations_dp, + n_entries); } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv) || IS_CML_ULT(dev_priv)) { - *n_entries = kbl_u_ddi_translations_dp.num_entries; - return kbl_u_ddi_translations_dp.entries; + return intel_get_buf_trans(&kbl_u_ddi_translations_dp, + n_entries); } else { - *n_entries = kbl_ddi_translations_dp.num_entries; - return kbl_ddi_translations_dp.entries; + return intel_get_buf_trans(&kbl_ddi_translations_dp, + n_entries); } } @@ -1055,17 +1062,17 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = skl_y_ddi_translations_edp.num_entries; - return skl_y_ddi_translations_edp.entries; + return intel_get_buf_trans(&skl_y_ddi_translations_edp, + n_entries); } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv) || IS_CML_ULT(dev_priv)) { - *n_entries = skl_u_ddi_translations_edp.num_entries; - return skl_u_ddi_translations_edp.entries; + return intel_get_buf_trans(&skl_u_ddi_translations_edp, + n_entries); } else { - *n_entries = skl_ddi_translations_edp.num_entries; - return skl_ddi_translations_edp.entries; + return intel_get_buf_trans(&skl_ddi_translations_edp, + n_entries); } } @@ -1084,11 +1091,11 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { - *n_entries = skl_y_ddi_translations_hdmi.num_entries; - return skl_y_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, + n_entries); } else { - *n_entries = skl_ddi_translations_hdmi.num_entries; - return skl_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&skl_ddi_translations_hdmi, + n_entries); } } @@ -1119,11 +1126,11 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_BROADWELL(dev_priv)) { - *n_entries = bdw_ddi_translations_dp.num_entries; - return bdw_ddi_translations_dp.entries; + return intel_get_buf_trans(&bdw_ddi_translations_dp, + n_entries); } else if (IS_HASWELL(dev_priv)) { - *n_entries = hsw_ddi_translations_dp.num_entries; - return hsw_ddi_translations_dp.entries; + return intel_get_buf_trans(&hsw_ddi_translations_dp, + n_entries); } *n_entries = 0; @@ -1143,8 +1150,8 @@ hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } else if (IS_BROADWELL(dev_priv)) { return bdw_get_buf_trans_edp(encoder, n_entries); } else if (IS_HASWELL(dev_priv)) { - *n_entries = hsw_ddi_translations_dp.num_entries; - return hsw_ddi_translations_dp.entries; + return intel_get_buf_trans(&hsw_ddi_translations_dp, + n_entries); } *n_entries = 0; @@ -1158,11 +1165,11 @@ hsw_get_buf_trans_fdi(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_BROADWELL(dev_priv)) { - *n_entries = bdw_ddi_translations_fdi.num_entries; - return bdw_ddi_translations_fdi.entries; + return intel_get_buf_trans(&bdw_ddi_translations_fdi, + n_entries); } else if (IS_HASWELL(dev_priv)) { - *n_entries = hsw_ddi_translations_fdi.num_entries; - return hsw_ddi_translations_fdi.entries; + return intel_get_buf_trans(&hsw_ddi_translations_fdi, + n_entries); } *n_entries = 0; @@ -1178,11 +1185,11 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { return skl_get_buf_trans_hdmi(dev_priv, n_entries); } else if (IS_BROADWELL(dev_priv)) { - *n_entries = bdw_ddi_translations_hdmi.num_entries; - return bdw_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&bdw_ddi_translations_hdmi, + n_entries); } else if (IS_HASWELL(dev_priv)) { - *n_entries = hsw_ddi_translations_hdmi.num_entries; - return hsw_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&hsw_ddi_translations_hdmi, + n_entries); } *n_entries = 0; @@ -1207,8 +1214,7 @@ hsw_get_buf_trans(struct intel_encoder *encoder, static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { - *n_entries = bxt_ddi_translations_dp.num_entries; - return bxt_ddi_translations_dp.entries; + return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1217,8 +1223,8 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = bxt_ddi_translations_edp.num_entries; - return bxt_ddi_translations_edp.entries; + return intel_get_buf_trans(&bxt_ddi_translations_edp, + n_entries); } return bxt_get_buf_trans_dp(encoder, n_entries); @@ -1227,8 +1233,7 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) static const union intel_ddi_buf_trans_entry * bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { - *n_entries = bxt_ddi_translations_hdmi.num_entries; - return bxt_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); } const union intel_ddi_buf_trans_entry * @@ -1250,14 +1255,14 @@ cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = cnl_ddi_translations_hdmi_0_85V.num_entries; - return cnl_ddi_translations_hdmi_0_85V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_85V, + n_entries); } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = cnl_ddi_translations_hdmi_0_95V.num_entries; - return cnl_ddi_translations_hdmi_0_95V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_95V, + n_entries); } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = cnl_ddi_translations_hdmi_1_05V.num_entries; - return cnl_ddi_translations_hdmi_1_05V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_hdmi_1_05V, + n_entries); } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1272,14 +1277,14 @@ cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = cnl_ddi_translations_dp_0_85V.num_entries; - return cnl_ddi_translations_dp_0_85V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_dp_0_85V, + n_entries); } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = cnl_ddi_translations_dp_0_95V.num_entries; - return cnl_ddi_translations_dp_0_95V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_dp_0_95V, + n_entries); } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = cnl_ddi_translations_dp_1_05V.num_entries; - return cnl_ddi_translations_dp_1_05V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_dp_1_05V, + n_entries); } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1295,14 +1300,14 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) if (dev_priv->vbt.edp.low_vswing) { if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = cnl_ddi_translations_edp_0_85V.num_entries; - return cnl_ddi_translations_edp_0_85V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V, + n_entries); } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = cnl_ddi_translations_edp_0_95V.num_entries; - return cnl_ddi_translations_edp_0_95V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_edp_0_95V, + n_entries); } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = cnl_ddi_translations_edp_1_05V.num_entries; - return cnl_ddi_translations_edp_1_05V.entries; + return intel_get_buf_trans(&cnl_ddi_translations_edp_1_05V, + n_entries); } else { *n_entries = 1; /* shut up gcc */ MISSING_CASE(voltage); @@ -1330,8 +1335,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; - return icl_combo_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1339,8 +1344,8 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_dp_hbr2.num_entries; - return icl_combo_phy_ddi_translations_dp_hbr2.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1351,17 +1356,17 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 540000) { - *n_entries = icl_combo_phy_ddi_translations_edp_hbr3.num_entries; - return icl_combo_phy_ddi_translations_edp_hbr3.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; - return icl_combo_phy_ddi_translations_edp_hbr2.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { - *n_entries = dg1_combo_phy_ddi_translations_dp_hbr2_hbr3.num_entries; - return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3.entries; + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + n_entries); } else if (IS_DG1(dev_priv)) { - *n_entries = dg1_combo_phy_ddi_translations_dp_rbr_hbr.num_entries; - return dg1_combo_phy_ddi_translations_dp_rbr_hbr.entries; + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, + n_entries); } return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1385,8 +1390,8 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_mg_phy_ddi_translations_hdmi.num_entries; - return icl_mg_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1395,11 +1400,11 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = icl_mg_phy_ddi_translations_hbr2_hbr3.num_entries; - return icl_mg_phy_ddi_translations_hbr2_hbr3.entries; + return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3, + n_entries); } else { - *n_entries = icl_mg_phy_ddi_translations_rbr_hbr.num_entries; - return icl_mg_phy_ddi_translations_rbr_hbr.entries; + return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr, + n_entries); } } @@ -1419,8 +1424,8 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; - return icl_combo_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1428,8 +1433,8 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ehl_combo_phy_ddi_translations_dp.num_entries; - return ehl_combo_phy_ddi_translations_dp.entries; + return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1440,8 +1445,8 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; - return icl_combo_phy_ddi_translations_edp_hbr2.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); } return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1465,8 +1470,8 @@ jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; - return icl_combo_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1474,8 +1479,8 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_dp_hbr2.num_entries; - return icl_combo_phy_ddi_translations_dp_hbr2.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1487,11 +1492,11 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, if (dev_priv->vbt.edp.low_vswing) { if (crtc_state->port_clock > 270000) { - *n_entries = jsl_combo_phy_ddi_translations_edp_hbr2.num_entries; - return jsl_combo_phy_ddi_translations_edp_hbr2.entries; + return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, + n_entries); } else { - *n_entries = jsl_combo_phy_ddi_translations_edp_hbr.num_entries; - return jsl_combo_phy_ddi_translations_edp_hbr.entries; + return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, + n_entries); } } @@ -1516,8 +1521,8 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = icl_combo_phy_ddi_translations_hdmi.num_entries; - return icl_combo_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1529,22 +1534,22 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, if (crtc_state->port_clock > 270000) { if (IS_ROCKETLAKE(dev_priv)) { - *n_entries = rkl_combo_phy_ddi_translations_dp_hbr2_hbr3.num_entries; - return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3.entries; + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, + n_entries); } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { - *n_entries = tgl_uy_combo_phy_ddi_translations_dp_hbr2.num_entries; - return tgl_uy_combo_phy_ddi_translations_dp_hbr2.entries; + return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, + n_entries); } else { - *n_entries = tgl_combo_phy_ddi_translations_dp_hbr2.num_entries; - return tgl_combo_phy_ddi_translations_dp_hbr2.entries; + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2, + n_entries); } } else { if (IS_ROCKETLAKE(dev_priv)) { - *n_entries = rkl_combo_phy_ddi_translations_dp_hbr.num_entries; - return rkl_combo_phy_ddi_translations_dp_hbr.entries; + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, + n_entries); } else { - *n_entries = tgl_combo_phy_ddi_translations_dp_hbr.num_entries; - return tgl_combo_phy_ddi_translations_dp_hbr.entries; + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, + n_entries); } } } @@ -1558,14 +1563,14 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - *n_entries = icl_combo_phy_ddi_translations_edp_hbr3.num_entries; - return icl_combo_phy_ddi_translations_edp_hbr3.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { - *n_entries = tgl_combo_phy_ddi_translations_edp_hbr2_hobl.num_entries; - return tgl_combo_phy_ddi_translations_edp_hbr2_hobl.entries; + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - *n_entries = icl_combo_phy_ddi_translations_edp_hbr2.num_entries; - return icl_combo_phy_ddi_translations_edp_hbr2.entries; + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); } return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1589,8 +1594,8 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = tgl_dkl_phy_ddi_translations_hdmi.num_entries; - return tgl_dkl_phy_ddi_translations_hdmi.entries; + return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, + n_entries); } static const union intel_ddi_buf_trans_entry * @@ -1599,11 +1604,11 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = tgl_dkl_phy_ddi_translations_dp_hbr2.num_entries; - return tgl_dkl_phy_ddi_translations_dp_hbr2.entries; + return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2, + n_entries); } else { - *n_entries = tgl_dkl_phy_ddi_translations_dp_hbr.num_entries; - return tgl_dkl_phy_ddi_translations_dp_hbr.entries; + return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr, + n_entries); } } -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (5 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala ` (19 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Raise the abstraction level of the get_buf_trans() functions a bit more by returning the whole wrapper intel_ddi_buf_trans struct. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 76 +++++++-------- .../drm/i915/display/intel_ddi_buf_trans.c | 94 +++++++++---------- .../drm/i915/display/intel_ddi_buf_trans.h | 20 ++-- 3 files changed, 95 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index fd2dff10fc83..5ac31bd13b3e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -100,7 +100,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -114,9 +114,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, for (i = 0; i < n_entries; i++) { intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), - ddi_translations[i].hsw.trans1 | iboost_bit); + ddi_translations->entries[i].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), - ddi_translations[i].hsw.trans2); + ddi_translations->entries[i].hsw.trans2); } } @@ -133,7 +133,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -149,9 +149,9 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, /* Entry 9 is for HDMI: */ intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), - ddi_translations[level].hsw.trans1 | iboost_bit); + ddi_translations->entries[level].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), - ddi_translations[level].hsw.trans2); + ddi_translations->entries[level].hsw.trans2); } void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -908,7 +908,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); if (iboost == 0) { - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; int n_entries; ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); @@ -918,7 +918,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; - iboost = ddi_translations[level].hsw.i_boost; + iboost = ddi_translations->entries[level].hsw.i_boost; } /* Make sure that the requested I_boost is valid */ @@ -938,7 +938,7 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; enum port port = encoder->port; int n_entries; @@ -949,10 +949,10 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, level = n_entries - 1; bxt_ddi_phy_set_signal_level(dev_priv, port, - ddi_translations[level].bxt.margin, - ddi_translations[level].bxt.scale, - ddi_translations[level].bxt.enable, - ddi_translations[level].bxt.deemphasis); + ddi_translations->entries[level].bxt.margin, + ddi_translations->entries[level].bxt.scale, + ddi_translations->entries[level].bxt.enable, + ddi_translations->entries[level].bxt.deemphasis); } static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, @@ -1011,7 +1011,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; enum port port = encoder->port; int n_entries, ln; u32 val; @@ -1033,8 +1033,8 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations[level].cnl.dw2_swing_sel); - val |= SWING_SEL_LOWER(ddi_translations[level].cnl.dw2_swing_sel); + val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel); + val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel); /* Rcomp scalar is fixed as 0x98 for every table entry */ val |= RCOMP_SCALAR(0x98); intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); @@ -1045,9 +1045,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= POST_CURSOR_1(ddi_translations[level].cnl.dw4_post_cursor_1); - val |= POST_CURSOR_2(ddi_translations[level].cnl.dw4_post_cursor_2); - val |= CURSOR_COEFF(ddi_translations[level].cnl.dw4_cursor_coeff); + val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1); + val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2); + val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff); intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); } @@ -1062,7 +1062,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, /* Program PORT_TX_DW7 */ val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); val &= ~N_SCALAR_MASK; - val |= N_SCALAR(ddi_translations[level].cnl.dw7_n_scalar); + val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar); intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); } @@ -1132,7 +1132,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; u32 val; @@ -1173,8 +1173,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations[level].cnl.dw2_swing_sel); - val |= SWING_SEL_LOWER(ddi_translations[level].cnl.dw2_swing_sel); + val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel); + val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel); /* Program Rcomp scalar for every table entry */ val |= RCOMP_SCALAR(0x98); intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); @@ -1185,16 +1185,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= POST_CURSOR_1(ddi_translations[level].cnl.dw4_post_cursor_1); - val |= POST_CURSOR_2(ddi_translations[level].cnl.dw4_post_cursor_2); - val |= CURSOR_COEFF(ddi_translations[level].cnl.dw4_cursor_coeff); + val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1); + val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2); + val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff); intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); } /* Program PORT_TX_DW7 */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); val &= ~N_SCALAR_MASK; - val |= N_SCALAR(ddi_translations[level].cnl.dw7_n_scalar); + val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar); intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); } @@ -1265,7 +1265,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; int n_entries, ln; u32 val; @@ -1295,13 +1295,13 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations[level].mg.cri_txdeemph_override_17_12); + ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations[level].mg.cri_txdeemph_override_17_12); + ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); } @@ -1311,9 +1311,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations[level].mg.cri_txdeemph_override_5_0) | + ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations[level].mg.cri_txdeemph_override_11_6) | + ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); @@ -1321,9 +1321,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations[level].mg.cri_txdeemph_override_5_0) | + ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations[level].mg.cri_txdeemph_override_11_6) | + ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); @@ -1403,7 +1403,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const union intel_ddi_buf_trans_entry *ddi_translations; + const struct intel_ddi_buf_trans *ddi_translations; u32 val, dpcnt_mask, dpcnt_val; int n_entries, ln; @@ -1420,9 +1420,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK); - dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl.dkl_vswing_control); - dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl.dkl_de_emphasis_control); - dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl.dkl_preshoot_control); + dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control); + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); for (ln = 0; ln < 2; ln++) { intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 413e3c55027e..d91b946dfa66 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -988,19 +988,19 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), }; -bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table) +bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { - return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl.entries; + return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) { *num_entries = ddi_translations->num_entries; - return ddi_translations->entries; + return ddi_translations; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1014,7 +1014,7 @@ bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1031,7 +1031,7 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1052,7 +1052,7 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1084,7 +1084,7 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return skl_get_buf_trans_dp(encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { if (IS_SKL_ULX(dev_priv) || @@ -1108,7 +1108,7 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) return min(n_entries, 9); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1116,12 +1116,12 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - const union intel_ddi_buf_trans_entry *ddi_translations = + const struct intel_ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_SKYLAKE(dev_priv)) { - const union intel_ddi_buf_trans_entry *ddi_translations = + const struct intel_ddi_buf_trans *ddi_translations = skl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -1137,13 +1137,13 @@ hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - const union intel_ddi_buf_trans_entry *ddi_translations = + const struct intel_ddi_buf_trans *ddi_translations = skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -1158,7 +1158,7 @@ hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * hsw_get_buf_trans_fdi(struct intel_encoder *encoder, int *n_entries) { @@ -1176,7 +1176,7 @@ hsw_get_buf_trans_fdi(struct intel_encoder *encoder, return NULL; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { @@ -1196,7 +1196,7 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, return NULL; } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * hsw_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1211,13 +1211,13 @@ hsw_get_buf_trans(struct intel_encoder *encoder, return hsw_get_buf_trans_dp(encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1230,13 +1230,13 @@ bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return bxt_get_buf_trans_dp(encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1248,7 +1248,7 @@ bxt_get_buf_trans(struct intel_encoder *encoder, return bxt_get_buf_trans_dp(encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1270,7 +1270,7 @@ cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1292,7 +1292,7 @@ cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1318,7 +1318,7 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * cnl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1330,7 +1330,7 @@ cnl_get_buf_trans(struct intel_encoder *encoder, return cnl_get_buf_trans_dp(encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1339,7 +1339,7 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1348,7 +1348,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1372,7 +1372,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * icl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1385,7 +1385,7 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1394,7 +1394,7 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1408,7 +1408,7 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, } } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * icl_get_mg_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1419,7 +1419,7 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1428,7 +1428,7 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1437,7 +1437,7 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1452,7 +1452,7 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1465,7 +1465,7 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1474,7 +1474,7 @@ jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1483,7 +1483,7 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1503,7 +1503,7 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1516,7 +1516,7 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1525,7 +1525,7 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1554,7 +1554,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, } } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1576,7 +1576,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1589,7 +1589,7 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1598,7 +1598,7 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, n_entries); } -static const union intel_ddi_buf_trans_entry * +static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1612,7 +1612,7 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, } } -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 363f96709079..24072411e0b0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -58,48 +58,48 @@ struct intel_ddi_buf_trans { u8 num_entries; }; -bool is_hobl_buf_trans(const union intel_ddi_buf_trans_entry *table); +bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table); int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * hsw_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * icl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * icl_get_mg_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -const union intel_ddi_buf_trans_entry * +const struct intel_ddi_buf_trans * cnl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (6 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala ` (18 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Store the default HDMI buf trans entry in struct intel_ddi_buf_trans so that it's next to the actual table. This let's us start ridding ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 49 ++++++++++--------- .../drm/i915/display/intel_ddi_buf_trans.h | 1 + 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index d91b946dfa66..7574d6390a39 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -65,6 +65,7 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { .entries = _hsw_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), + .hdmi_default_entry = 6, }; static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { @@ -135,6 +136,7 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { .entries = _bdw_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), + .hdmi_default_entry = 7, }; /* Skylake H and S */ @@ -329,6 +331,7 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { .entries = _skl_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), + .hdmi_default_entry = 8, }; /* Skylake/Kabylake Y */ @@ -349,6 +352,7 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { .entries = _skl_y_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), + .hdmi_default_entry = 8, }; static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { @@ -409,6 +413,7 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { .entries = _bxt_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, }; /* Voltage Swing Programming for VccIO 0.85V for DP */ @@ -446,6 +451,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = { .entries = _cnl_ddi_translations_hdmi_0_85V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1, }; /* Voltage Swing Programming for VccIO 0.85V for eDP */ @@ -506,6 +512,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = { .entries = _cnl_ddi_translations_hdmi_0_95V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1, }; /* Voltage Swing Programming for VccIO 0.95V for eDP */ @@ -567,6 +574,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = { .entries = _cnl_ddi_translations_hdmi_1_05V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1, }; /* Voltage Swing Programming for VccIO 1.05V for eDP */ @@ -660,6 +668,7 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { .entries = _icl_combo_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { @@ -812,6 +821,7 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { .entries = _icl_mg_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { @@ -869,6 +879,7 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[ static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { .entries = _tgl_dkl_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { @@ -1629,42 +1640,34 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + const struct intel_ddi_buf_trans *ddi_translations = NULL; int n_entries; if (DISPLAY_VER(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); + ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); else - tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); } else if (DISPLAY_VER(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); + ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); else - icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); } else if (IS_CANNONLAKE(dev_priv)) { - cnl_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - bxt_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = n_entries - 1; - } else if (DISPLAY_VER(dev_priv) == 9) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 8; - } else if (IS_BROADWELL(dev_priv)) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 7; - } else if (IS_HASWELL(dev_priv)) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 6; - } else { - drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); - return 0; + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); + } else if (DISPLAY_VER(dev_priv) == 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries); } - if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) + if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { + *default_entry = 0; return 0; + } + + *default_entry = ddi_translations->hdmi_default_entry; return n_entries; } diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 24072411e0b0..940140e64c76 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -56,6 +56,7 @@ union intel_ddi_buf_trans_entry { struct intel_ddi_buf_trans { const union intel_ddi_buf_trans_entry *entries; u8 num_entries; + u8 hdmi_default_entry; }; bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (7 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-05-11 18:31 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala ` (17 subsequent siblings) 26 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Convert the get_buf_trans() functions into an encoder vfunc. Allows us to get rid of bunch of platform if-ladders. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_crt.c | 3 + drivers/gpu/drm/i915/display/intel_ddi.c | 56 +++------------ .../drm/i915/display/intel_ddi_buf_trans.c | 68 +++++++++++-------- .../drm/i915/display/intel_ddi_buf_trans.h | 39 +---------- .../drm/i915/display/intel_display_types.h | 4 ++ drivers/gpu/drm/i915/display/intel_fdi.c | 3 +- 6 files changed, 59 insertions(+), 114 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index c85092eaa5c2..42da2e35bc7c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -37,6 +37,7 @@ #include "intel_connector.h" #include "intel_crt.h" #include "intel_ddi.h" +#include "intel_ddi_buf_trans.h" #include "intel_display_types.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" @@ -1079,6 +1080,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) crt->base.enable_clock = hsw_ddi_enable_clock; crt->base.disable_clock = hsw_ddi_disable_clock; crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; + + intel_ddi_buf_trans_init(&crt->base); } else { if (HAS_PCH_SPLIT(dev_priv)) { crt->base.compute_config = pch_crt_compute_config; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5ac31bd13b3e..906fea249eaf 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -102,8 +102,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct intel_ddi_buf_trans *ddi_translations; - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -135,8 +134,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct intel_ddi_buf_trans *ddi_translations; - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -911,8 +909,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, const struct intel_ddi_buf_trans *ddi_translations; int n_entries; - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -942,7 +939,7 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, enum port port = encoder->port; int n_entries; - ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries); + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -960,31 +957,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); int n_entries; - if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_phy_is_combo(dev_priv, phy)) - tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else - tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); - } else if (DISPLAY_VER(dev_priv) == 11) { - if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) - jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) - ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else - icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); - } else if (IS_CANNONLAKE(dev_priv)) { - cnl_get_buf_trans(encoder, crtc_state, &n_entries); - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - bxt_get_buf_trans(encoder, crtc_state, &n_entries); - } else { - hsw_get_buf_trans(encoder, crtc_state, &n_entries); - } + encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) n_entries = 1; @@ -1016,8 +991,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, int n_entries, ln; u32 val; - ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -1137,15 +1111,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, int n_entries, ln; u32 val; - if (DISPLAY_VER(dev_priv) >= 12) - ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) - ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) - ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else - ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -1272,8 +1238,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) return; - ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -1410,8 +1375,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) return; - ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); - + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) @@ -4590,6 +4554,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->get_config = hsw_ddi_get_config; } + intel_ddi_buf_trans_init(encoder); + if (IS_DG1(dev_priv)) encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 7574d6390a39..37a9c3b2c03c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1207,7 +1207,7 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, return NULL; } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * hsw_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1247,7 +1247,7 @@ bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1329,7 +1329,7 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * cnl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1383,7 +1383,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * icl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1419,7 +1419,7 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, } } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * icl_get_mg_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1463,7 +1463,7 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1514,7 +1514,7 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1587,7 +1587,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1623,7 +1623,7 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, } } -const struct intel_ddi_buf_trans * +static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) @@ -1639,28 +1639,10 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, int *default_entry) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - const struct intel_ddi_buf_trans *ddi_translations = NULL; + const struct intel_ddi_buf_trans *ddi_translations; int n_entries; - if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_phy_is_combo(dev_priv, phy)) - ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); - else - ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); - } else if (DISPLAY_VER(dev_priv) == 11) { - if (intel_phy_is_combo(dev_priv, phy)) - ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); - else - ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); - } else if (IS_CANNONLAKE(dev_priv)) { - ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); - } else if (DISPLAY_VER(dev_priv) == 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { - ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries); - } + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { *default_entry = 0; @@ -1671,3 +1653,31 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, return n_entries; } + +void intel_ddi_buf_trans_init(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + if (DISPLAY_VER(i915) >= 12) { + if (intel_phy_is_combo(i915, phy)) + encoder->get_buf_trans = tgl_get_combo_buf_trans; + else + encoder->get_buf_trans = tgl_get_dkl_buf_trans; + } else if (DISPLAY_VER(i915) == 11) { + if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) + encoder->get_buf_trans = jsl_get_combo_buf_trans; + else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) + encoder->get_buf_trans = ehl_get_combo_buf_trans; + else if (intel_phy_is_combo(i915, phy)) + encoder->get_buf_trans = icl_get_combo_buf_trans; + else + encoder->get_buf_trans = icl_get_mg_buf_trans; + } else if (IS_CANNONLAKE(i915)) { + encoder->get_buf_trans = cnl_get_buf_trans; + } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { + encoder->get_buf_trans = bxt_get_buf_trans; + } else { + encoder->get_buf_trans = hsw_get_buf_trans; + } +} diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 940140e64c76..5f46af36794b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -65,44 +65,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry); -const struct intel_ddi_buf_trans * -hsw_get_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); +void intel_ddi_buf_trans_init(struct intel_encoder *encoder); -const struct intel_ddi_buf_trans * -bxt_get_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); - -const struct intel_ddi_buf_trans * -tgl_get_combo_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); -const struct intel_ddi_buf_trans * -tgl_get_dkl_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); -const struct intel_ddi_buf_trans * -jsl_get_combo_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); -const struct intel_ddi_buf_trans * -ehl_get_combo_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); -const struct intel_ddi_buf_trans * -icl_get_combo_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); -const struct intel_ddi_buf_trans * -icl_get_mg_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); - -const struct intel_ddi_buf_trans * -cnl_get_buf_trans(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2e707c4dff5..3451d7d6570d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -49,6 +49,7 @@ struct drm_printer; struct __intel_global_objs_state; +struct intel_ddi_buf_trans; /* * Display related stuff @@ -260,6 +261,9 @@ struct intel_encoder { * Returns whether the port clock is enabled or not. */ bool (*is_clock_enabled)(struct intel_encoder *encoder); + const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries); enum hpd_pin hpd_pin; enum intel_display_power_domain power_domain; /* for communication with audio component; protected by av_mutex */ diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 223762020afe..b61f6b74f81a 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -4,7 +4,6 @@ */ #include "intel_atomic.h" #include "intel_ddi.h" -#include "intel_ddi_buf_trans.h" #include "intel_display_types.h" #include "intel_fdi.h" @@ -568,7 +567,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, u32 temp, i, rx_ctl_val; int n_entries; - hsw_get_buf_trans(encoder, crtc_state, &n_entries); + encoder->get_buf_trans(encoder, crtc_state, &n_entries); hsw_prepare_dp_ddi_buffers(encoder, crtc_state); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() 2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala @ 2021-05-11 18:31 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-05-11 18:31 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Wed, 21 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Convert the get_buf_trans() functions into an encoder vfunc. > Allows us to get rid of bunch of platform if-ladders. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> The series up to and including this patch, Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_crt.c | 3 + > drivers/gpu/drm/i915/display/intel_ddi.c | 56 +++------------ > .../drm/i915/display/intel_ddi_buf_trans.c | 68 +++++++++++-------- > .../drm/i915/display/intel_ddi_buf_trans.h | 39 +---------- > .../drm/i915/display/intel_display_types.h | 4 ++ > drivers/gpu/drm/i915/display/intel_fdi.c | 3 +- > 6 files changed, 59 insertions(+), 114 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c > index c85092eaa5c2..42da2e35bc7c 100644 > --- a/drivers/gpu/drm/i915/display/intel_crt.c > +++ b/drivers/gpu/drm/i915/display/intel_crt.c > @@ -37,6 +37,7 @@ > #include "intel_connector.h" > #include "intel_crt.h" > #include "intel_ddi.h" > +#include "intel_ddi_buf_trans.h" > #include "intel_display_types.h" > #include "intel_fdi.h" > #include "intel_fifo_underrun.h" > @@ -1079,6 +1080,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) > crt->base.enable_clock = hsw_ddi_enable_clock; > crt->base.disable_clock = hsw_ddi_disable_clock; > crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; > + > + intel_ddi_buf_trans_init(&crt->base); > } else { > if (HAS_PCH_SPLIT(dev_priv)) { > crt->base.compute_config = pch_crt_compute_config; > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 5ac31bd13b3e..906fea249eaf 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -102,8 +102,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > enum port port = encoder->port; > const struct intel_ddi_buf_trans *ddi_translations; > > - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > > @@ -135,8 +134,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > enum port port = encoder->port; > const struct intel_ddi_buf_trans *ddi_translations; > > - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -911,8 +909,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > const struct intel_ddi_buf_trans *ddi_translations; > int n_entries; > > - ddi_translations = hsw_get_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -942,7 +939,7 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, > enum port port = encoder->port; > int n_entries; > > - ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries); > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -960,31 +957,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum port port = encoder->port; > - enum phy phy = intel_port_to_phy(dev_priv, port); > int n_entries; > > - if (DISPLAY_VER(dev_priv) >= 12) { > - if (intel_phy_is_combo(dev_priv, phy)) > - tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else > - tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); > - } else if (DISPLAY_VER(dev_priv) == 11) { > - if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > - jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > - ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (intel_phy_is_combo(dev_priv, phy)) > - icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else > - icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); > - } else if (IS_CANNONLAKE(dev_priv)) { > - cnl_get_buf_trans(encoder, crtc_state, &n_entries); > - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > - bxt_get_buf_trans(encoder, crtc_state, &n_entries); > - } else { > - hsw_get_buf_trans(encoder, crtc_state, &n_entries); > - } > + encoder->get_buf_trans(encoder, crtc_state, &n_entries); > > if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) > n_entries = 1; > @@ -1016,8 +991,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, > int n_entries, ln; > u32 val; > > - ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -1137,15 +1111,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > int n_entries, ln; > u32 val; > > - if (DISPLAY_VER(dev_priv) >= 12) > - ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > - ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > - ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else > - ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -1272,8 +1238,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) > return; > > - ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -1410,8 +1375,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) > return; > > - ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); > - > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > @@ -4590,6 +4554,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > encoder->get_config = hsw_ddi_get_config; > } > > + intel_ddi_buf_trans_init(encoder); > + > if (IS_DG1(dev_priv)) > encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); > else if (IS_ROCKETLAKE(dev_priv)) > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 7574d6390a39..37a9c3b2c03c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1207,7 +1207,7 @@ hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, > return NULL; > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > hsw_get_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1247,7 +1247,7 @@ bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) > return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > bxt_get_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1329,7 +1329,7 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > } > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > cnl_get_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1383,7 +1383,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > icl_get_combo_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1419,7 +1419,7 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, > } > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > icl_get_mg_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1463,7 +1463,7 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > ehl_get_combo_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1514,7 +1514,7 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > jsl_get_combo_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1587,7 +1587,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > tgl_get_combo_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1623,7 +1623,7 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, > } > } > > -const struct intel_ddi_buf_trans * > +static const struct intel_ddi_buf_trans * > tgl_get_dkl_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > @@ -1639,28 +1639,10 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > int *default_entry) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > - const struct intel_ddi_buf_trans *ddi_translations = NULL; > + const struct intel_ddi_buf_trans *ddi_translations; > int n_entries; > > - if (DISPLAY_VER(dev_priv) >= 12) { > - if (intel_phy_is_combo(dev_priv, phy)) > - ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); > - else > - ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); > - } else if (DISPLAY_VER(dev_priv) == 11) { > - if (intel_phy_is_combo(dev_priv, phy)) > - ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); > - else > - ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); > - } else if (IS_CANNONLAKE(dev_priv)) { > - ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); > - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > - ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); > - } else if (DISPLAY_VER(dev_priv) == 9 || > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > - ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries); > - } > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > > if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { > *default_entry = 0; > @@ -1671,3 +1653,31 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > > return n_entries; > } > + > +void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > +{ > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(i915, encoder->port); > + > + if (DISPLAY_VER(i915) >= 12) { > + if (intel_phy_is_combo(i915, phy)) > + encoder->get_buf_trans = tgl_get_combo_buf_trans; > + else > + encoder->get_buf_trans = tgl_get_dkl_buf_trans; > + } else if (DISPLAY_VER(i915) == 11) { > + if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) > + encoder->get_buf_trans = jsl_get_combo_buf_trans; > + else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) > + encoder->get_buf_trans = ehl_get_combo_buf_trans; > + else if (intel_phy_is_combo(i915, phy)) > + encoder->get_buf_trans = icl_get_combo_buf_trans; > + else > + encoder->get_buf_trans = icl_get_mg_buf_trans; > + } else if (IS_CANNONLAKE(i915)) { > + encoder->get_buf_trans = cnl_get_buf_trans; > + } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { > + encoder->get_buf_trans = bxt_get_buf_trans; > + } else { > + encoder->get_buf_trans = hsw_get_buf_trans; > + } > +} > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > index 940140e64c76..5f46af36794b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > @@ -65,44 +65,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *default_entry); > > -const struct intel_ddi_buf_trans * > -hsw_get_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > +void intel_ddi_buf_trans_init(struct intel_encoder *encoder); > > -const struct intel_ddi_buf_trans * > -bxt_get_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > - > -const struct intel_ddi_buf_trans * > -tgl_get_combo_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > -const struct intel_ddi_buf_trans * > -tgl_get_dkl_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > -const struct intel_ddi_buf_trans * > -jsl_get_combo_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > -const struct intel_ddi_buf_trans * > -ehl_get_combo_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > -const struct intel_ddi_buf_trans * > -icl_get_combo_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > -const struct intel_ddi_buf_trans * > -icl_get_mg_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > - > -const struct intel_ddi_buf_trans * > -cnl_get_buf_trans(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *n_entries); > > #endif > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index e2e707c4dff5..3451d7d6570d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -49,6 +49,7 @@ > > struct drm_printer; > struct __intel_global_objs_state; > +struct intel_ddi_buf_trans; > > /* > * Display related stuff > @@ -260,6 +261,9 @@ struct intel_encoder { > * Returns whether the port clock is enabled or not. > */ > bool (*is_clock_enabled)(struct intel_encoder *encoder); > + const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries); > enum hpd_pin hpd_pin; > enum intel_display_power_domain power_domain; > /* for communication with audio component; protected by av_mutex */ > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c > index 223762020afe..b61f6b74f81a 100644 > --- a/drivers/gpu/drm/i915/display/intel_fdi.c > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c > @@ -4,7 +4,6 @@ > */ > #include "intel_atomic.h" > #include "intel_ddi.h" > -#include "intel_ddi_buf_trans.h" > #include "intel_display_types.h" > #include "intel_fdi.h" > > @@ -568,7 +567,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > u32 temp, i, rx_ctl_val; > int n_entries; > > - hsw_get_buf_trans(encoder, crtc_state, &n_entries); > + encoder->get_buf_trans(encoder, crtc_state, &n_entries); > > hsw_prepare_dp_ddi_buffers(encoder, crtc_state); -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (8 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-05-12 18:53 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala ` (16 subsequent siblings) 26 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Split the hsw/bdw/skl/kbl get_buf_trans() functions into clean platform specific variants. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 308 +++++++----------- 1 file changed, 118 insertions(+), 190 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 37a9c3b2c03c..1d78640c439e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1012,102 +1012,34 @@ intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num } static const struct intel_ddi_buf_trans * -bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) +hsw_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&bdw_ddi_translations_edp, - n_entries); - } else { - return intel_get_buf_trans(&bdw_ddi_translations_dp, - n_entries); - } -} - -static const struct intel_ddi_buf_trans * -skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (IS_SKL_ULX(dev_priv)) { - return intel_get_buf_trans(&skl_y_ddi_translations_dp, - n_entries); - } else if (IS_SKL_ULT(dev_priv)) { - return intel_get_buf_trans(&skl_u_ddi_translations_dp, - n_entries); - } else { - return intel_get_buf_trans(&skl_ddi_translations_dp, - n_entries); - } -} - -static const struct intel_ddi_buf_trans * -kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv) || - IS_CML_ULX(dev_priv)) { - return intel_get_buf_trans(&kbl_y_ddi_translations_dp, - n_entries); - } else if (IS_KBL_ULT(dev_priv) || - IS_CFL_ULT(dev_priv) || - IS_CML_ULT(dev_priv)) { - return intel_get_buf_trans(&kbl_u_ddi_translations_dp, - n_entries); - } else { - return intel_get_buf_trans(&kbl_ddi_translations_dp, - n_entries); - } -} - -static const struct intel_ddi_buf_trans * -skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (dev_priv->vbt.edp.low_vswing) { - if (IS_SKL_ULX(dev_priv) || - IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv) || - IS_CML_ULX(dev_priv)) { - return intel_get_buf_trans(&skl_y_ddi_translations_edp, - n_entries); - } else if (IS_SKL_ULT(dev_priv) || - IS_KBL_ULT(dev_priv) || - IS_CFL_ULT(dev_priv) || - IS_CML_ULT(dev_priv)) { - return intel_get_buf_trans(&skl_u_ddi_translations_edp, - n_entries); - } else { - return intel_get_buf_trans(&skl_ddi_translations_edp, - n_entries); - } - } - - if (IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv) || - IS_COMETLAKE(dev_priv)) - return kbl_get_buf_trans_dp(encoder, n_entries); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) + return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); else - return skl_get_buf_trans_dp(encoder, n_entries); + return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) +bdw_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - if (IS_SKL_ULX(dev_priv) || - IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv) || - IS_CML_ULX(dev_priv)) { - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, - n_entries); - } else { - return intel_get_buf_trans(&skl_ddi_translations_hdmi, - n_entries); - } + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) + return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); + else + return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); } static int skl_buf_trans_num_entries(enum port port, int n_entries) @@ -1120,131 +1052,109 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) } static const struct intel_ddi_buf_trans * -hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv) || - IS_COMETLAKE(dev_priv)) { - const struct intel_ddi_buf_trans *ddi_translations = - kbl_get_buf_trans_dp(encoder, n_entries); - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); - return ddi_translations; - } else if (IS_SKYLAKE(dev_priv)) { - const struct intel_ddi_buf_trans *ddi_translations = - skl_get_buf_trans_dp(encoder, n_entries); - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); - return ddi_translations; - } else if (IS_BROADWELL(dev_priv)) { - return intel_get_buf_trans(&bdw_ddi_translations_dp, - n_entries); - } else if (IS_HASWELL(dev_priv)) { - return intel_get_buf_trans(&hsw_ddi_translations_dp, - n_entries); - } - - *n_entries = 0; - return NULL; -} - -static const struct intel_ddi_buf_trans * -hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - const struct intel_ddi_buf_trans *ddi_translations = - skl_get_buf_trans_edp(encoder, n_entries); - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); - return ddi_translations; - } else if (IS_BROADWELL(dev_priv)) { - return bdw_get_buf_trans_edp(encoder, n_entries); - } else if (IS_HASWELL(dev_priv)) { - return intel_get_buf_trans(&hsw_ddi_translations_dp, - n_entries); - } - - *n_entries = 0; - return NULL; -} - -static const struct intel_ddi_buf_trans * -hsw_get_buf_trans_fdi(struct intel_encoder *encoder, +_skl_get_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_ddi_buf_trans *ddi_translations, int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); + *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); + return ddi_translations; +} - if (IS_BROADWELL(dev_priv)) { - return intel_get_buf_trans(&bdw_ddi_translations_fdi, - n_entries); - } else if (IS_HASWELL(dev_priv)) { - return intel_get_buf_trans(&hsw_ddi_translations_fdi, - n_entries); - } +static const struct intel_ddi_buf_trans * +skl_y_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); - *n_entries = 0; - return NULL; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); + else + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries) +skl_u_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - return skl_get_buf_trans_hdmi(dev_priv, n_entries); - } else if (IS_BROADWELL(dev_priv)) { - return intel_get_buf_trans(&bdw_ddi_translations_hdmi, - n_entries); - } else if (IS_HASWELL(dev_priv)) { - return intel_get_buf_trans(&hsw_ddi_translations_hdmi, - n_entries); - } - - *n_entries = 0; - return NULL; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); + else + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -hsw_get_buf_trans(struct intel_encoder *encoder, +skl_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - return hsw_get_buf_trans_fdi(encoder, n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return hsw_get_buf_trans_hdmi(encoder, n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - return hsw_get_buf_trans_edp(encoder, n_entries); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); else - return hsw_get_buf_trans_dp(encoder, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) +kbl_y_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); + else + return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) +kbl_u_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&bxt_ddi_translations_edp, - n_entries); - } + struct drm_i915_private *i915 = to_i915(encoder->base.dev); - return bxt_get_buf_trans_dp(encoder, n_entries); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); + else + return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * -bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) +kbl_get_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) { - return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); + else + return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1252,11 +1162,15 @@ bxt_get_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return bxt_get_buf_trans_hdmi(encoder, n_entries); - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - return bxt_get_buf_trans_edp(encoder, n_entries); - return bxt_get_buf_trans_dp(encoder, n_entries); + return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + i915->vbt.edp.low_vswing) + return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); + else + return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1677,6 +1591,20 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) encoder->get_buf_trans = cnl_get_buf_trans; } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { encoder->get_buf_trans = bxt_get_buf_trans; + } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) { + encoder->get_buf_trans = kbl_y_get_buf_trans; + } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) { + encoder->get_buf_trans = kbl_u_get_buf_trans; + } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { + encoder->get_buf_trans = kbl_get_buf_trans; + } else if (IS_SKL_ULX(i915)) { + encoder->get_buf_trans = skl_y_get_buf_trans; + } else if (IS_SKL_ULT(i915)) { + encoder->get_buf_trans = skl_u_get_buf_trans; + } else if (IS_SKYLAKE(i915)) { + encoder->get_buf_trans = skl_get_buf_trans; + } else if (IS_BROADWELL(i915)) { + encoder->get_buf_trans = bdw_get_buf_trans; } else { encoder->get_buf_trans = hsw_get_buf_trans; } -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs 2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala @ 2021-05-12 18:53 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-05-12 18:53 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Wed, 21 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Split the hsw/bdw/skl/kbl get_buf_trans() functions into > clean platform specific variants. One of the most obnoxious patches to review lately, but it was worth it. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 308 +++++++----------- > 1 file changed, 118 insertions(+), 190 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 37a9c3b2c03c..1d78640c439e 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1012,102 +1012,34 @@ intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num > } > > static const struct intel_ddi_buf_trans * > -bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > +hsw_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&bdw_ddi_translations_edp, > - n_entries); > - } else { > - return intel_get_buf_trans(&bdw_ddi_translations_dp, > - n_entries); > - } > -} > - > -static const struct intel_ddi_buf_trans * > -skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (IS_SKL_ULX(dev_priv)) { > - return intel_get_buf_trans(&skl_y_ddi_translations_dp, > - n_entries); > - } else if (IS_SKL_ULT(dev_priv)) { > - return intel_get_buf_trans(&skl_u_ddi_translations_dp, > - n_entries); > - } else { > - return intel_get_buf_trans(&skl_ddi_translations_dp, > - n_entries); > - } > -} > - > -static const struct intel_ddi_buf_trans * > -kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (IS_KBL_ULX(dev_priv) || > - IS_CFL_ULX(dev_priv) || > - IS_CML_ULX(dev_priv)) { > - return intel_get_buf_trans(&kbl_y_ddi_translations_dp, > - n_entries); > - } else if (IS_KBL_ULT(dev_priv) || > - IS_CFL_ULT(dev_priv) || > - IS_CML_ULT(dev_priv)) { > - return intel_get_buf_trans(&kbl_u_ddi_translations_dp, > - n_entries); > - } else { > - return intel_get_buf_trans(&kbl_ddi_translations_dp, > - n_entries); > - } > -} > - > -static const struct intel_ddi_buf_trans * > -skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (dev_priv->vbt.edp.low_vswing) { > - if (IS_SKL_ULX(dev_priv) || > - IS_KBL_ULX(dev_priv) || > - IS_CFL_ULX(dev_priv) || > - IS_CML_ULX(dev_priv)) { > - return intel_get_buf_trans(&skl_y_ddi_translations_edp, > - n_entries); > - } else if (IS_SKL_ULT(dev_priv) || > - IS_KBL_ULT(dev_priv) || > - IS_CFL_ULT(dev_priv) || > - IS_CML_ULT(dev_priv)) { > - return intel_get_buf_trans(&skl_u_ddi_translations_edp, > - n_entries); > - } else { > - return intel_get_buf_trans(&skl_ddi_translations_edp, > - n_entries); > - } > - } > - > - if (IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv) || > - IS_COMETLAKE(dev_priv)) > - return kbl_get_buf_trans_dp(encoder, n_entries); > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > + return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); > else > - return skl_get_buf_trans_dp(encoder, n_entries); > + return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) > +bdw_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - if (IS_SKL_ULX(dev_priv) || > - IS_KBL_ULX(dev_priv) || > - IS_CFL_ULX(dev_priv) || > - IS_CML_ULX(dev_priv)) { > - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, > - n_entries); > - } else { > - return intel_get_buf_trans(&skl_ddi_translations_hdmi, > - n_entries); > - } > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > + return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); > + else > + return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); > } > > static int skl_buf_trans_num_entries(enum port port, int n_entries) > @@ -1120,131 +1052,109 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > } > > static const struct intel_ddi_buf_trans * > -hsw_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv) || > - IS_COMETLAKE(dev_priv)) { > - const struct intel_ddi_buf_trans *ddi_translations = > - kbl_get_buf_trans_dp(encoder, n_entries); > - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); > - return ddi_translations; > - } else if (IS_SKYLAKE(dev_priv)) { > - const struct intel_ddi_buf_trans *ddi_translations = > - skl_get_buf_trans_dp(encoder, n_entries); > - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); > - return ddi_translations; > - } else if (IS_BROADWELL(dev_priv)) { > - return intel_get_buf_trans(&bdw_ddi_translations_dp, > - n_entries); > - } else if (IS_HASWELL(dev_priv)) { > - return intel_get_buf_trans(&hsw_ddi_translations_dp, > - n_entries); > - } > - > - *n_entries = 0; > - return NULL; > -} > - > -static const struct intel_ddi_buf_trans * > -hsw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { > - const struct intel_ddi_buf_trans *ddi_translations = > - skl_get_buf_trans_edp(encoder, n_entries); > - *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); > - return ddi_translations; > - } else if (IS_BROADWELL(dev_priv)) { > - return bdw_get_buf_trans_edp(encoder, n_entries); > - } else if (IS_HASWELL(dev_priv)) { > - return intel_get_buf_trans(&hsw_ddi_translations_dp, > - n_entries); > - } > - > - *n_entries = 0; > - return NULL; > -} > - > -static const struct intel_ddi_buf_trans * > -hsw_get_buf_trans_fdi(struct intel_encoder *encoder, > +_skl_get_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_ddi_buf_trans *ddi_translations, > int *n_entries) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); > + *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); > + return ddi_translations; > +} > > - if (IS_BROADWELL(dev_priv)) { > - return intel_get_buf_trans(&bdw_ddi_translations_fdi, > - n_entries); > - } else if (IS_HASWELL(dev_priv)) { > - return intel_get_buf_trans(&hsw_ddi_translations_fdi, > - n_entries); > - } > +static const struct intel_ddi_buf_trans * > +skl_y_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > - *n_entries = 0; > - return NULL; > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); > + else > + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -hsw_get_buf_trans_hdmi(struct intel_encoder *encoder, > - int *n_entries) > +skl_u_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { > - return skl_get_buf_trans_hdmi(dev_priv, n_entries); > - } else if (IS_BROADWELL(dev_priv)) { > - return intel_get_buf_trans(&bdw_ddi_translations_hdmi, > - n_entries); > - } else if (IS_HASWELL(dev_priv)) { > - return intel_get_buf_trans(&hsw_ddi_translations_hdmi, > - n_entries); > - } > - > - *n_entries = 0; > - return NULL; > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); > + else > + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -hsw_get_buf_trans(struct intel_encoder *encoder, > +skl_get_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > { > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > - return hsw_get_buf_trans_fdi(encoder, n_entries); > - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return hsw_get_buf_trans_hdmi(encoder, n_entries); > - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > - return hsw_get_buf_trans_edp(encoder, n_entries); > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); > else > - return hsw_get_buf_trans_dp(encoder, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > +kbl_y_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); > + else > + return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > +kbl_u_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&bxt_ddi_translations_edp, > - n_entries); > - } > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > - return bxt_get_buf_trans_dp(encoder, n_entries); > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); > + else > + return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > -bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) > +kbl_get_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > { > - return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); > + else > + return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1252,11 +1162,15 @@ bxt_get_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return bxt_get_buf_trans_hdmi(encoder, n_entries); > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > - return bxt_get_buf_trans_edp(encoder, n_entries); > - return bxt_get_buf_trans_dp(encoder, n_entries); > + return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > + i915->vbt.edp.low_vswing) > + return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); > + else > + return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1677,6 +1591,20 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > encoder->get_buf_trans = cnl_get_buf_trans; > } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { > encoder->get_buf_trans = bxt_get_buf_trans; > + } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) { > + encoder->get_buf_trans = kbl_y_get_buf_trans; > + } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) { > + encoder->get_buf_trans = kbl_u_get_buf_trans; > + } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { > + encoder->get_buf_trans = kbl_get_buf_trans; > + } else if (IS_SKL_ULX(i915)) { > + encoder->get_buf_trans = skl_y_get_buf_trans; > + } else if (IS_SKL_ULT(i915)) { > + encoder->get_buf_trans = skl_u_get_buf_trans; > + } else if (IS_SKYLAKE(i915)) { > + encoder->get_buf_trans = skl_get_buf_trans; > + } else if (IS_BROADWELL(i915)) { > + encoder->get_buf_trans = bdw_get_buf_trans; > } else { > encoder->get_buf_trans = hsw_get_buf_trans; > } -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (9 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-05-12 18:58 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala ` (15 subsequent siblings) 26 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Give RKL its own get_buf_trans() func. Note that the spec currently only lists values for DP. Until we get that clarified let's just assume that for HDMI and eDP we should do what TGL does (except we fall back to the RKL DP values instead of TGL DP values when not using the eDP specific values, whereas previously we used all TGL values for eDP). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 65 +++++++++++++++---- 1 file changed, 53 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 1d78640c439e..fd55c812f14a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1458,10 +1458,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 270000) { - if (IS_ROCKETLAKE(dev_priv)) { - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, - n_entries); - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, n_entries); } else { @@ -1469,13 +1466,8 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, n_entries); } } else { - if (IS_ROCKETLAKE(dev_priv)) { - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, - n_entries); - } else { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, - n_entries); - } + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, + n_entries); } } @@ -1514,6 +1506,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + else + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); +} + +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) { + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); + } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + n_entries); + } else if (dev_priv->vbt.edp.low_vswing) { + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + } + + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + /* FIXME unclear what values we should use for HDMI and eDP */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1573,7 +1612,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port); - if (DISPLAY_VER(i915) >= 12) { + if (IS_ROCKETLAKE(i915)) { + encoder->get_buf_trans = rkl_get_combo_buf_trans; + } else if (DISPLAY_VER(i915) >= 12) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = tgl_get_combo_buf_trans; else -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() 2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala @ 2021-05-12 18:58 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-05-12 18:58 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Wed, 21 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Give RKL its own get_buf_trans() func. > > Note that the spec currently only lists values for DP. > Until we get that clarified let's just assume that for > HDMI and eDP we should do what TGL does (except we fall > back to the RKL DP values instead of TGL DP values when > not using the eDP specific values, whereas previously > we used all TGL values for eDP). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 65 +++++++++++++++---- > 1 file changed, 53 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 1d78640c439e..fd55c812f14a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1458,10 +1458,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 270000) { > - if (IS_ROCKETLAKE(dev_priv)) { > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, > - n_entries); > - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, > n_entries); > } else { > @@ -1469,13 +1466,8 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > n_entries); > } > } else { > - if (IS_ROCKETLAKE(dev_priv)) { > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, > - n_entries); > - } else { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, > - n_entries); > - } > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, > + n_entries); > } > } > > @@ -1514,6 +1506,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, > return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (crtc_state->port_clock > 270000) > + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); > + else > + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + if (crtc_state->port_clock > 540000) { > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, > + n_entries); > + } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + n_entries); > + } else if (dev_priv->vbt.edp.low_vswing) { > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + n_entries); > + } > + > + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + /* FIXME unclear what values we should use for HDMI and eDP */ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct intel_ddi_buf_trans * > tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -1573,7 +1612,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > enum phy phy = intel_port_to_phy(i915, encoder->port); > > - if (DISPLAY_VER(i915) >= 12) { > + if (IS_ROCKETLAKE(i915)) { > + encoder->get_buf_trans = rkl_get_combo_buf_trans; > + } else if (DISPLAY_VER(i915) >= 12) { > if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = tgl_get_combo_buf_trans; > else -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (10 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala ` (14 subsequent siblings) 26 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> For some reason the dg1 buf trans tables have been stuffed into icl_get_combo_buf_trans_edp() which doesn't even get called on dg1. Split them out into a proper dg1 specific function, and also make sure we use the proper buf trans tables for DP as well as eDP. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 51 ++++++++++++++++--- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index fd55c812f14a..25702f40b3ce 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1286,12 +1286,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, } else if (dev_priv->vbt.edp.low_vswing) { return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, - n_entries); - } else if (IS_DG1(dev_priv)) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, - n_entries); } return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1506,6 +1500,49 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + n_entries); + else + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, + n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + if (crtc_state->port_clock > 540000) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); + else if (dev_priv->vbt.edp.low_vswing) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1614,6 +1651,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) if (IS_ROCKETLAKE(i915)) { encoder->get_buf_trans = rkl_get_combo_buf_trans; + } else if (IS_DG1(i915)) { + encoder->get_buf_trans = dg1_get_combo_buf_trans; } else if (DISPLAY_VER(i915) >= 12) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = tgl_get_combo_buf_trans; -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables 2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala @ 2021-05-04 10:15 ` Ville Syrjala 2021-05-12 19:05 ` Jani Nikula 0 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-05-04 10:15 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> For some reason the dg1 buf trans tables have been stuffed into icl_get_combo_buf_trans_edp() which doesn't even get called on dg1. Split them out into a proper dg1 specific function, and also make sure we use the proper buf trans tables for DP as well as eDP. v2: Add the hobl stuff Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 55 +++++++++++++++++-- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index fd55c812f14a..7a1dbf5281cb 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1286,12 +1286,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, } else if (dev_priv->vbt.edp.low_vswing) { return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, - n_entries); - } else if (IS_DG1(dev_priv)) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, - n_entries); } return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1506,6 +1500,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + n_entries); + else + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, + n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); + else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + n_entries); + else if (dev_priv->vbt.edp.low_vswing) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1614,6 +1655,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) if (IS_ROCKETLAKE(i915)) { encoder->get_buf_trans = rkl_get_combo_buf_trans; + } else if (IS_DG1(i915)) { + encoder->get_buf_trans = dg1_get_combo_buf_trans; } else if (DISPLAY_VER(i915) >= 12) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = tgl_get_combo_buf_trans; -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables 2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala @ 2021-05-12 19:05 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-05-12 19:05 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Tue, 04 May 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > For some reason the dg1 buf trans tables have been stuffed into > icl_get_combo_buf_trans_edp() which doesn't even get called > on dg1. Split them out into a proper dg1 specific function, > and also make sure we use the proper buf trans tables for > DP as well as eDP. > > v2: Add the hobl stuff > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 55 +++++++++++++++++-- > 1 file changed, 49 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index fd55c812f14a..7a1dbf5281cb 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1286,12 +1286,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > } else if (dev_priv->vbt.edp.low_vswing) { > return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > n_entries); > - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > - n_entries); > - } else if (IS_DG1(dev_priv)) { > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, > - n_entries); > } > > return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > @@ -1506,6 +1500,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, > return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (crtc_state->port_clock > 270000) > + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > + n_entries); > + else > + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, > + n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + if (crtc_state->port_clock > 540000) > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, > + n_entries); > + else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + n_entries); > + else if (dev_priv->vbt.edp.low_vswing) > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + n_entries); > + else > + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct intel_ddi_buf_trans * > rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -1614,6 +1655,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > > if (IS_ROCKETLAKE(i915)) { > encoder->get_buf_trans = rkl_get_combo_buf_trans; > + } else if (IS_DG1(i915)) { > + encoder->get_buf_trans = dg1_get_combo_buf_trans; > } else if (DISPLAY_VER(i915) >= 12) { > if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = tgl_get_combo_buf_trans; -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (11 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala ` (13 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The icl combo phy DP HBR2 is identical to the eDP HBR3 table. Get rid of one redundant copy. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 39 +++++-------------- 1 file changed, 10 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 25702f40b3ce..0facbf556634 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -597,7 +597,7 @@ static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = { }; /* icl_combo_phy_ddi_translations */ -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -611,9 +611,9 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2 = { - .entries = _icl_combo_phy_ddi_translations_dp_hbr2, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2), +static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = { + .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), }; static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { @@ -635,25 +635,6 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr3[] = { - /* NT mV Trans mV db */ - { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ - { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ - { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ - { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ - { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ - { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ - { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ - { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ - { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ - { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ -}; - -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3 = { - .entries = _icl_combo_phy_ddi_translations_edp_hbr3, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr3), -}; - static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { /* NT mV Trans mV db */ { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ @@ -1269,7 +1250,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } @@ -1281,7 +1262,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.low_vswing) { return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, @@ -1398,7 +1379,7 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } @@ -1474,7 +1455,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, @@ -1521,7 +1502,7 @@ dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 540000) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); else if (dev_priv->vbt.edp.low_vswing) return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, @@ -1563,7 +1544,7 @@ rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (12 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala ` (12 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> EHL is supposed to use special buf trans values for eDP HBR2+. Add such a table. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 0facbf556634..85db309ec57d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -671,6 +671,25 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), }; +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ + { .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ + { .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */ + { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ + { .cnl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */ + { .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */ + { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ + { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ +}; + +static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = { + .entries = _ehl_combo_phy_ddi_translations_edp_hbr2, + .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2), +}; + static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { /* NT mV Trans mV db */ { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ @@ -1345,8 +1364,13 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, - n_entries); + if (crtc_state->port_clock > 270000) { + return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + } else { + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + } } return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (13 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala ` (11 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The jsl/ehl buf trans functions are needlessly conplicated. Simplify them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 87 +++++-------------- 1 file changed, 20 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 85db309ec57d..80d659b229b7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1338,42 +1338,16 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct intel_ddi_buf_trans * -ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, - n_entries); -} - -static const struct intel_ddi_buf_trans * -ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, - n_entries); -} static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (dev_priv->vbt.edp.low_vswing) { - if (crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, - n_entries); - } else { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, - n_entries); - } - } - - return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries); + else + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); } static const struct intel_ddi_buf_trans * @@ -1381,30 +1355,15 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + dev_priv->vbt.edp.low_vswing) return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else - return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); -} - -static const struct intel_ddi_buf_trans * -jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, - n_entries); -} - -static const struct intel_ddi_buf_trans * -jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, - n_entries); + return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1412,19 +1371,10 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (dev_priv->vbt.edp.low_vswing) { - if (crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, - n_entries); - } else { - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, - n_entries); - } - } - - return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries); + else + return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries); } static const struct intel_ddi_buf_trans * @@ -1432,12 +1382,15 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && + dev_priv->vbt.edp.low_vswing) return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else - return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } static const struct intel_ddi_buf_trans * -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (14 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala ` (10 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> All the foo_get_buf_trans_hdmi() functions just reuturn a single table. Remove the pointless wrappers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 49 +++---------------- 1 file changed, 6 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 80d659b229b7..c5b7ce7464bc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1255,15 +1255,6 @@ cnl_get_buf_trans(struct intel_encoder *encoder, return cnl_get_buf_trans_dp(encoder, n_entries); } -static const struct intel_ddi_buf_trans * -icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, - n_entries); -} - static const struct intel_ddi_buf_trans * icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1297,22 +1288,13 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct intel_ddi_buf_trans * -icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, - n_entries); -} - static const struct intel_ddi_buf_trans * icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1333,12 +1315,11 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries); else return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); } - static const struct intel_ddi_buf_trans * ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1393,15 +1374,6 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); } -static const struct intel_ddi_buf_trans * -tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, - n_entries); -} - static const struct intel_ddi_buf_trans * tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1451,7 +1423,7 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1494,7 +1466,7 @@ dg1_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1541,22 +1513,13 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder, { /* FIXME unclear what values we should use for HDMI and eDP */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } -static const struct intel_ddi_buf_trans * -tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *n_entries) -{ - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, - n_entries); -} - static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1577,7 +1540,7 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); + return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); else return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); } -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (15 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala @ 2021-04-21 16:48 ` Ville Syrjala 2021-04-22 6:20 ` kernel test robot 2021-05-04 10:16 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork ` (9 subsequent siblings) 26 siblings, 2 replies; 37+ messages in thread From: Ville Syrjala @ 2021-04-21 16:48 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> adls is supposed to use special buf trans tables. Add what's missing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 122 +++++++++++++++++- 1 file changed, 121 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index c5b7ce7464bc..7acb24a55738 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -999,6 +999,82 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), }; +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_rbr_hbr[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_rbr_hbr = { + .entries = _adls_combo_phy_ddi_translations_dp_rbr_hbr, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_rbr_hbr), +}; + +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { + .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), +}; + +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200 200 0.0 */ + { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200 250 1.9 */ + { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200 300 3.5 */ + { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */ + { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */ + { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ + { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */ + { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300 300 0.0 */ + { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { + .entries = _adls_combo_phy_ddi_translations_edp_hbr2, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { + .entries = _adls_combo_phy_ddi_translations_edp_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), +}; + bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; @@ -1520,6 +1596,48 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder, return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + else + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); +} + +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); + else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); + else if (i915->vbt.edp.low_vswing) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); + else + return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1570,7 +1688,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port); - if (IS_ROCKETLAKE(i915)) { + if (IS_ALDERLAKE_S(i915)) { + encoder->get_buf_trans = adls_get_combo_buf_trans; + } else if (IS_ROCKETLAKE(i915)) { encoder->get_buf_trans = rkl_get_combo_buf_trans; } else if (IS_DG1(i915)) { encoder->get_buf_trans = dg1_get_combo_buf_trans; -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables 2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala @ 2021-04-22 6:20 ` kernel test robot 2021-05-04 10:16 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 1 sibling, 0 replies; 37+ messages in thread From: kernel test robot @ 2021-04-22 6:20 UTC (permalink / raw) To: Ville Syrjala, intel-gfx; +Cc: clang-built-linux, kbuild-all [-- Attachment #1: Type: text/plain, Size: 2456 bytes --] Hi Ville, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on next-20210421] [cannot apply to drm-intel/for-linux-next v5.12-rc8] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-DDI-buf-trans-cleaup-and-fixes/20210422-005122 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: x86_64-randconfig-a011-20210421 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project d87b9b81ccb95217181ce75515c6c68bbb408ca4) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # https://github.com/0day-ci/linux/commit/1e2b73915eb7fa55d9b0f0836ecc25a01d904cd1 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Ville-Syrjala/drm-i915-DDI-buf-trans-cleaup-and-fixes/20210422-005122 git checkout 1e2b73915eb7fa55d9b0f0836ecc25a01d904cd1 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1016:41: error: unused variable 'adls_combo_phy_ddi_translations_dp_rbr_hbr' [-Werror,-Wunused-const-variable] static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_rbr_hbr = { ^ 1 error generated. vim +/adls_combo_phy_ddi_translations_dp_rbr_hbr +1016 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 1015 > 1016 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_rbr_hbr = { 1017 .entries = _adls_combo_phy_ddi_translations_dp_rbr_hbr, 1018 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_rbr_hbr), 1019 }; 1020 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 30891 bytes --] [-- Attachment #3: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v2 17/17] drm/i915: Add the missing adls vswing tables 2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala 2021-04-22 6:20 ` kernel test robot @ 2021-05-04 10:16 ` Ville Syrjala 1 sibling, 0 replies; 37+ messages in thread From: Ville Syrjala @ 2021-05-04 10:16 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> adls is supposed to use special buf trans tables. Add what's missing. v2: Drop the RBR/HBR table since it's the same as for tgl Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 103 +++++++++++++++++- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index d38bf04cf23c..189a93b8277e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -999,6 +999,63 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), }; +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { + .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), +}; + +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200 200 0.0 */ + { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200 250 1.9 */ + { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200 300 3.5 */ + { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */ + { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */ + { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ + { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */ + { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300 300 0.0 */ + { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ + { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { + .entries = _adls_combo_phy_ddi_translations_edp_hbr2, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), +}; + +static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { + /* NT mV Trans mV db */ + { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350 350 0.0 */ + { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350 500 3.1 */ + { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ + { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ + { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ + { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ + { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500 900 5.1 */ + { .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ + { .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } }, /* 600 900 3.5 */ + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ +}; + +static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { + .entries = _adls_combo_phy_ddi_translations_edp_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), +}; + bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; @@ -1524,6 +1581,48 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder, return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + else + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); +} + +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); + else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); + else if (i915->vbt.edp.low_vswing) + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); + else + return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +adls_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1574,7 +1673,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port); - if (IS_ROCKETLAKE(i915)) { + if (IS_ALDERLAKE_S(i915)) { + encoder->get_buf_trans = adls_get_combo_buf_trans; + } else if (IS_ROCKETLAKE(i915)) { encoder->get_buf_trans = rkl_get_combo_buf_trans; } else if (IS_DG1(i915)) { encoder->get_buf_trans = dg1_get_combo_buf_trans; -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (16 preceding siblings ...) 2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala @ 2021-04-21 17:17 ` Patchwork 2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (8 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-04-21 17:17 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes URL : https://patchwork.freedesktop.org/series/89311/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1a9fc1bd6978 drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans 23e893369885 drm/i915: Introduce hsw_get_buf_trans() 16aeb28e7179 drm/i915: Wrap the platform specific buf trans structs into a union cb81a56fecaa drm/i915: Rename dkl phy buf trans tables 23cb70d43cd2 drm/i915: Wrap the buf trans tables into a struct e90b18869846 drm/i915: Introduce intel_get_buf_trans() -:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #25: + intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) total: 0 errors, 1 warnings, 0 checks, 473 lines checked 3684eb6e7604 drm/i915; Return the whole buf_trans struct from get_buf_trans() -:253: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #253: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1424: + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); -:254: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #254: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1425: + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); total: 0 errors, 2 warnings, 0 checks, 630 lines checked a4ad121c30b4 drm/i915: Store the HDMI default entry in the bug trans struct -:118: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #118: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1648: + ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:122: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #122: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1650: + ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:126: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #126: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1653: + ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:130: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #130: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1655: + ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); total: 0 errors, 4 warnings, 0 checks, 141 lines checked 2fd199ee08cc drm/i915: Introduce encoder->get_buf_trans() -:382: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #382: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:265: + const struct intel_crtc_state *crtc_state, total: 0 errors, 1 warnings, 0 checks, 342 lines checked ec6e9e43811f drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs a8fc2844edc9 drm/i915: Introduce rkl_get_combo_buf_trans() 6a8d3e2986f0 drm/i915: Fix dg1 buf trans tables c02fe1383c62 drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table 87baaa79a82e drm/i915: Fix ehl edp hbr2 vswing table 578e59ec142f drm/i915: Clean up jsl/ehl buf trans functions -:141: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #141: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1393: + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); total: 0 errors, 1 warnings, 0 checks, 123 lines checked 7b6d286d856b drm/i915: Nuke buf_trans hdmi functions 3b7edb1bd0f7 drm/i915: Add the missing adls vswing tables -:111: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #111: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1605: + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); -:127: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #127: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1621: + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); total: 0 errors, 2 warnings, 0 checks, 140 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (17 preceding siblings ...) 2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork @ 2021-04-21 17:18 ` Patchwork 2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork ` (7 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-04-21 17:18 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes URL : https://patchwork.freedesktop.org/series/89311/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (18 preceding siblings ...) 2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-04-21 17:22 ` Patchwork 2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (6 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-04-21 17:22 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes URL : https://patchwork.freedesktop.org/series/89311/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (19 preceding siblings ...) 2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork @ 2021-04-21 17:45 ` Patchwork 2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork ` (5 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-04-21 17:45 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3890 bytes --] == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes URL : https://patchwork.freedesktop.org/series/89311/ State : success == Summary == CI Bug Log - changes from CI_DRM_9993 -> Patchwork_19965 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/index.html Known issues ------------ Here are the changes found in Patchwork_19965 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@runner@aborted: - fi-cfl-8700k: NOTRUN -> [FAIL][1] ([i915#2292] / [i915#2426] / [k.org#204565]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/fi-cfl-8700k/igt@runner@aborted.html #### Possible fixes #### * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-soraka: [FAIL][2] ([i915#2346]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt@kms_frontbuffer_tracking@basic: - {fi-rkl-11500t}: [SKIP][4] ([i915#1849] / [i915#3180]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565 Participating hosts (42 -> 40) ------------------------------ Missing (2): fi-bsw-cyan fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9993 -> Patchwork_19965 CI-20190529: 20190529 CI_DRM_9993: 629d3809e6d926c77ba5e9c5405e64eeba564560 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19965: 3b7edb1bd0f7046814cef8409b635d5e0f3d2908 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3b7edb1bd0f7 drm/i915: Add the missing adls vswing tables 7b6d286d856b drm/i915: Nuke buf_trans hdmi functions 578e59ec142f drm/i915: Clean up jsl/ehl buf trans functions 87baaa79a82e drm/i915: Fix ehl edp hbr2 vswing table c02fe1383c62 drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table 6a8d3e2986f0 drm/i915: Fix dg1 buf trans tables a8fc2844edc9 drm/i915: Introduce rkl_get_combo_buf_trans() ec6e9e43811f drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs 2fd199ee08cc drm/i915: Introduce encoder->get_buf_trans() a4ad121c30b4 drm/i915: Store the HDMI default entry in the bug trans struct 3684eb6e7604 drm/i915; Return the whole buf_trans struct from get_buf_trans() e90b18869846 drm/i915: Introduce intel_get_buf_trans() 23cb70d43cd2 drm/i915: Wrap the buf trans tables into a struct cb81a56fecaa drm/i915: Rename dkl phy buf trans tables 16aeb28e7179 drm/i915: Wrap the platform specific buf trans structs into a union 23e893369885 drm/i915: Introduce hsw_get_buf_trans() 1a9fc1bd6978 drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/index.html [-- Attachment #1.2: Type: text/html, Size: 4574 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (20 preceding siblings ...) 2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-04-22 1:15 ` Patchwork 2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork ` (4 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-04-22 1:15 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30263 bytes --] == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes URL : https://patchwork.freedesktop.org/series/89311/ State : success == Summary == CI Bug Log - changes from CI_DRM_9993_full -> Patchwork_19965_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_19965_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb7/igt@gem_ctx_persistence@engines-mixed-process.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#3063]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb1/igt@gem_eio@unwedge-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-tglb5/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +86 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl10/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][12] ([i915#2389]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_whisper@basic-queues-priority: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([i915#1895]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb6/igt@gem_exec_whisper@basic-queues-priority.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl6/igt@gem_huc_copy@huc-copy.html * igt@gem_mmap_gtt@cpuset-medium-copy-odd: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#307]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl9/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl2/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb7/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@set-cache-level: - shard-snb: NOTRUN -> [FAIL][19] ([i915#3324]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb2/igt@gem_userptr_blits@set-cache-level.html - shard-skl: NOTRUN -> [FAIL][20] ([i915#3324]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl7/igt@gem_userptr_blits@set-cache-level.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][21] ([i915#2724]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb6/igt@gem_userptr_blits@vma-merge.html * igt@gem_vm_create@destroy-race: - shard-tglb: [PASS][22] -> [TIMEOUT][23] ([i915#2795]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb5/igt@gem_vm_create@destroy-race.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-tglb2/igt@gem_vm_create@destroy-race.html * igt@gen9_exec_parse@bb-large: - shard-skl: NOTRUN -> [FAIL][24] ([i915#3296]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl1/igt@gen9_exec_parse@bb-large.html - shard-apl: NOTRUN -> [FAIL][25] ([i915#3296]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@gen9_exec_parse@bb-large.html * igt@i915_hangman@engine-error@vecs0: - shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271]) +72 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@i915_hangman@engine-error@vecs0.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][27] ([i915#454]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl7/igt@i915_pm_dc@dc6-psr.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][28] ([i915#2782]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb5/igt@i915_selftest@live@hangcheck.html * igt@kms_ccs@pipe-a-ccs-on-another-bo: - shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271]) +263 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb6/igt@kms_ccs@pipe-a-ccs-on-another-bo.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111304]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic.html * igt@kms_chamelium@dp-mode-timings: - shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +19 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@kms_chamelium@dp-mode-timings.html * igt@kms_color_chamelium@pipe-a-degamma: - shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +5 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html - shard-snb: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +12 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-snb5/igt@kms_color_chamelium@pipe-a-degamma.html * igt@kms_color_chamelium@pipe-c-ctm-negative: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +7 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl1/igt@kms_color_chamelium@pipe-c-ctm-negative.html * igt@kms_content_protection@atomic: - shard-apl: NOTRUN -> [TIMEOUT][35] ([i915#1319]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@kms_content_protection@atomic.html * igt@kms_content_protection@uevent: - shard-kbl: NOTRUN -> [FAIL][36] ([i915#2105]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@kms_content_protection@uevent.html - shard-apl: NOTRUN -> [FAIL][37] ([i915#2105]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl7/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +4 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-apl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1: - shard-skl: [PASS][42] -> [FAIL][43] ([i915#2122]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2672]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html - shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#2672]) +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile: - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#2642]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c: - shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271]) +227 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html - shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][51] -> [DMESG-WARN][52] ([i915#180] / [i915#533]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][54] ([i915#265]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html - shard-kbl: NOTRUN -> [FAIL][55] ([i915#265]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping: - shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2733]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl10/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +5 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +2 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl10/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][63] -> [SKIP][64] ([fdo#109441]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html * igt@kms_sysfs_edid_timing: - shard-apl: NOTRUN -> [FAIL][65] ([IGT#2]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl7/igt@kms_sysfs_edid_timing.html - shard-kbl: NOTRUN -> [FAIL][66] ([IGT#2]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@kms_sysfs_edid_timing.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@kms_writeback@writeback-check-output.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994]) +5 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl8/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@sema-50: - shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +2 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@sysfs_clients@sema-50.html #### Possible fixes #### * igt@gem_exec_fair@basic-pace@rcs0: - shard-tglb: [FAIL][70] ([i915#2842]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [SKIP][72] ([fdo#109271]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][74] ([i915#2842]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [FAIL][76] ([i915#2428]) -> [PASS][77] +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_workarounds@suspend-resume-fd: - shard-skl: [INCOMPLETE][78] ([i915#198] / [i915#2405]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@gem_workarounds@suspend-resume-fd.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl10/igt@gem_workarounds@suspend-resume-fd.html * igt@i915_selftest@mock@requests: - shard-skl: [INCOMPLETE][80] ([i915#198]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl6/igt@i915_selftest@mock@requests.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl7/igt@i915_selftest@mock@requests.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83] +2 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [FAIL][84] ([i915#2346]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: - shard-glk: [FAIL][86] ([i915#52] / [i915#54]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-glk3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1: - shard-skl: [FAIL][88] ([i915#2122]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-apl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_hdr@bpc-switch: - shard-skl: [FAIL][92] ([i915#1188]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@kms_hdr@bpc-switch.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl4/igt@kms_hdr@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][94] ([fdo#108145] / [i915#265]) -> [PASS][95] +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][96] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb4/igt@kms_psr2_su@frontbuffer.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb2/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][98] ([fdo#109441]) -> [PASS][99] +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-skl: [INCOMPLETE][100] ([i915#198] / [i915#2828]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html * igt@perf@polling-parameterized: - shard-skl: [FAIL][102] ([i915#1542]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@perf@polling-parameterized.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl4/igt@perf@polling-parameterized.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][104] ([i915#2681] / [i915#2684]) -> [WARN][105] ([i915#1804] / [i915#2684]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][106] ([i915#1804] / [i915#2684]) -> [WARN][107] ([i915#2684]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][108] ([i915#658]) -> [SKIP][109] ([i915#2920]) +2 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb4/igt@kms_psr2_sf@cursor-plane-update-sf.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2: - shard-iclb: [SKIP][110] ([i915#2920]) -> [SKIP][111] ([i915#658]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html * igt@runner@aborted: - shard-kbl: ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) -> ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@runner@aborted.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@runner@aborted.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@runner@aborted.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@runner@aborted.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@runner@aborted.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl2/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl2/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl2/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl6/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl6/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl2/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl6/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-kbl1/igt@runner@aborted.html - shard-apl: ([FAIL][126], [FAIL][127], [FAIL][128]) ([i915#180] / [i915#3002]) -> ([FAIL][129], [FAIL][130], [FAIL][131]) ([i915#180] / [i915#1814] / [i915#3002]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl3/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl6/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl8/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl6/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl6/igt@runner@aborted.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-apl1/igt@runner@aborted.html - shard-skl: ([FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1436] / [i915#2722] / [i915#3002]) -> ([FAIL][135], [FAIL][136], [FAIL][137]) ([i915#1814] / [i915#2029] / [i915#3002]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl10/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl6/igt@runner@aborted.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl6/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl2/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/shard-skl6/igt@runner@aborted.html [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2428]: https://gitlab.freedesktop.org/drm/intel/issues/2428 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795 [i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307 [i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296 [i915#3324]: https://gitlab.freedesktop.org/drm/intel/issues/3324 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#602]: https://gitlab.freedesktop.org/drm/intel/i == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19965/index.html [-- Attachment #1.2: Type: text/html, Size: 38256 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (21 preceding siblings ...) 2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-05-04 12:13 ` Patchwork 2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-05-04 12:13 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes (rev3) URL : https://patchwork.freedesktop.org/series/89311/ State : warning == Summary == $ dim checkpatch origin/drm-tip 41597e735d81 drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans f12ad854bbba drm/i915: Introduce hsw_get_buf_trans() 92c909de2a5f drm/i915: Wrap the platform specific buf trans structs into a union c2887df88bd7 drm/i915: Rename dkl phy buf trans tables 681adec95a5c drm/i915: Wrap the buf trans tables into a struct 1e6b611520e0 drm/i915: Introduce intel_get_buf_trans() -:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #25: + intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) total: 0 errors, 1 warnings, 0 checks, 473 lines checked 4aefdd5efa28 drm/i915; Return the whole buf_trans struct from get_buf_trans() -:253: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #253: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1425: + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); -:254: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #254: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1426: + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); total: 0 errors, 2 warnings, 0 checks, 630 lines checked 89125d4782bd drm/i915: Store the HDMI default entry in the bug trans struct -:118: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #118: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1648: + ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:122: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #122: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1650: + ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:126: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #126: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1653: + ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); -:130: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #130: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1655: + ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); total: 0 errors, 4 warnings, 0 checks, 141 lines checked 8d20186e4a5b drm/i915: Introduce encoder->get_buf_trans() -:382: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #382: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:265: + const struct intel_crtc_state *crtc_state, total: 0 errors, 1 warnings, 0 checks, 342 lines checked 2f814a8d7445 drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs bd2188204d3a drm/i915: Introduce rkl_get_combo_buf_trans() ed4788c769b6 drm/i915: Fix dg1 buf trans tables 56b9a07d75d5 drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table 7f03efbc37b6 drm/i915: Fix ehl edp hbr2 vswing table edbc05ee202f drm/i915: Clean up jsl/ehl buf trans functions -:141: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #141: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1393: + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); total: 0 errors, 1 warnings, 0 checks, 123 lines checked 5b1bb03f7c33 drm/i915: Nuke buf_trans hdmi functions e8816b2c1069 drm/i915: Add the missing adls vswing tables -:94: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #94: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1590: + return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); -:110: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #110: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1606: + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); total: 0 errors, 2 warnings, 0 checks, 121 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (22 preceding siblings ...) 2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork @ 2021-05-04 12:14 ` Patchwork 2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-05-04 12:14 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes (rev3) URL : https://patchwork.freedesktop.org/series/89311/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (23 preceding siblings ...) 2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-05-04 12:41 ` Patchwork 2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula 2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-05-04 12:41 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3790 bytes --] == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes (rev3) URL : https://patchwork.freedesktop.org/series/89311/ State : success == Summary == CI Bug Log - changes from CI_DRM_10041 -> Patchwork_20061 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/index.html Known issues ------------ Here are the changes found in Patchwork_20061 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_prime@amd-to-i915: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/fi-kbl-soraka/igt@amdgpu/amd_prime@amd-to-i915.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s0: - {fi-tgl-1115g4}: [FAIL][2] ([i915#1888]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html #### Warnings #### * igt@i915_selftest@live@gt_lrc: - fi-tgl-y: [DMESG-FAIL][4] ([i915#2373]) -> [INCOMPLETE][5] ([i915#750]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373 [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277 [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283 [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750 Participating hosts (46 -> 41) ------------------------------ Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_10041 -> Patchwork_20061 CI-20190529: 20190529 CI_DRM_10041: 54c7983f58407208cb3bd82f04112debb4ee3440 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6077: 126a3f6fc0e97786e2819085efc84e741093aed5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20061: e8816b2c10691631133d8104d2c056f867963b3b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e8816b2c1069 drm/i915: Add the missing adls vswing tables 5b1bb03f7c33 drm/i915: Nuke buf_trans hdmi functions edbc05ee202f drm/i915: Clean up jsl/ehl buf trans functions 7f03efbc37b6 drm/i915: Fix ehl edp hbr2 vswing table 56b9a07d75d5 drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table ed4788c769b6 drm/i915: Fix dg1 buf trans tables bd2188204d3a drm/i915: Introduce rkl_get_combo_buf_trans() 2f814a8d7445 drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs 8d20186e4a5b drm/i915: Introduce encoder->get_buf_trans() 89125d4782bd drm/i915: Store the HDMI default entry in the bug trans struct 4aefdd5efa28 drm/i915; Return the whole buf_trans struct from get_buf_trans() 1e6b611520e0 drm/i915: Introduce intel_get_buf_trans() 681adec95a5c drm/i915: Wrap the buf trans tables into a struct c2887df88bd7 drm/i915: Rename dkl phy buf trans tables 92c909de2a5f drm/i915: Wrap the platform specific buf trans structs into a union f12ad854bbba drm/i915: Introduce hsw_get_buf_trans() 41597e735d81 drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/index.html [-- Attachment #1.2: Type: text/html, Size: 4403 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (24 preceding siblings ...) 2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-05-04 14:05 ` Jani Nikula 2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork 26 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-05-04 14:05 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Wed, 21 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The DDI buf trans functions keep turning into bad > spaghetti every time a new platform gets added. > Split the platforms up properly and turn the whole > thing into a vfunc to make it easier to manage > multiple platforms. One of the most wanted refactoring series I've seen in a while! I haven't reviewed it, but I've glanced through it all. Almost started nitpicking about some function naming early on, but realized they were made static later in the series. Overall looked like good stuff. Acked-by: Jani Nikula <jani.nikula@intel.com> > > Ville Syrjälä (17): > drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans > drm/i915: Introduce hsw_get_buf_trans() > drm/i915: Wrap the platform specific buf trans structs into a union > drm/i915: Rename dkl phy buf trans tables > drm/i915: Wrap the buf trans tables into a struct > drm/i915: Introduce intel_get_buf_trans() > drm/i915; Return the whole buf_trans struct from get_buf_trans() ^ Here's one review comment. ;) > drm/i915: Store the HDMI default entry in the bug trans struct > drm/i915: Introduce encoder->get_buf_trans() > drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs > drm/i915: Introduce rkl_get_combo_buf_trans() > drm/i915: Fix dg1 buf trans tables > drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table > drm/i915: Fix ehl edp hbr2 vswing table > drm/i915: Clean up jsl/ehl buf trans functions > drm/i915: Nuke buf_trans hdmi functions > drm/i915: Add the missing adls vswing tables > > drivers/gpu/drm/i915/display/intel_crt.c | 3 + > drivers/gpu/drm/i915/display/intel_ddi.c | 162 +- > drivers/gpu/drm/i915/display/intel_ddi.h | 4 +- > .../drm/i915/display/intel_ddi_buf_trans.c | 2354 ++++++++++------- > .../drm/i915/display/intel_ddi_buf_trans.h | 63 +- > .../drm/i915/display/intel_display_types.h | 4 + > drivers/gpu/drm/i915/display/intel_fdi.c | 5 +- > 7 files changed, 1432 insertions(+), 1163 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala ` (25 preceding siblings ...) 2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula @ 2021-05-04 14:18 ` Patchwork 26 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2021-05-04 14:18 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30267 bytes --] == Series Details == Series: drm/i915: DDI buf trans cleaup and fixes (rev3) URL : https://patchwork.freedesktop.org/series/89311/ State : success == Summary == CI Bug Log - changes from CI_DRM_10041_full -> Patchwork_20061_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_20061_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@clone: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb7/igt@gem_ctx_persistence@clone.html * igt@gem_ctx_persistence@legacy-engines-hostile@vebox: - shard-apl: [PASS][2] -> [FAIL][3] ([i915#2410]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl2/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html * igt@gem_ctx_ringsize@active@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#3316]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl9/igt@gem_ctx_ringsize@active@bcs0.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][13] ([i915#2389]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb2/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#307]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#307]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl8/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl7/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb7/igt@gem_pwrite@basic-exhaustion.html - shard-apl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl6/igt@gem_pwrite@basic-exhaustion.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@vma-merge: - shard-skl: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl4/igt@gem_userptr_blits@vma-merge.html * igt@gen7_exec_parse@basic-offset: - shard-tglb: NOTRUN -> [SKIP][22] ([fdo#109289]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@bb-large: - shard-apl: NOTRUN -> [FAIL][23] ([i915#3296]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@gen9_exec_parse@bb-large.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#111644] / [i915#1397] / [i915#2411]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][25] -> [INCOMPLETE][26] ([i915#2782]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-snb6/igt@i915_selftest@live@hangcheck.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb6/igt@i915_selftest@live@hangcheck.html * igt@kms_big_fb@yf-tiled-addfb: - shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111615]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb.html * igt@kms_big_joiner@invalid-modeset: - shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#2705]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl6/igt@kms_big_joiner@invalid-modeset.html * igt@kms_ccs@pipe-c-random-ccs-data: - shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111304]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl4/igt@kms_ccs@pipe-c-random-ccs-data.html * igt@kms_chamelium@dp-mode-timings: - shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +13 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@kms_chamelium@dp-mode-timings.html * igt@kms_color@pipe-a-ctm-green-to-red: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl9/igt@kms_color@pipe-a-ctm-green-to-red.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl2/igt@kms_color@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +20 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-a-gamma: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109284] / [fdo#111827]) +2 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb5/igt@kms_color_chamelium@pipe-a-gamma.html * igt@kms_color_chamelium@pipe-b-ctm-0-5: - shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl2/igt@kms_color_chamelium@pipe-b-ctm-0-5.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +8 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl4/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][37] ([i915#3319]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: NOTRUN -> [FAIL][38] ([i915#2346] / [i915#533]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-skl: [PASS][39] -> [FAIL][40] ([i915#2346]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#533]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2: - shard-glk: [PASS][42] -> [FAIL][43] ([i915#79]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][44] -> [FAIL][45] ([i915#79]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-kbl: [PASS][46] -> [INCOMPLETE][47] ([i915#155] / [i915#180]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile: - shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#2642]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271]) +404 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move: - shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271]) +3 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271]) +104 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][52] -> [DMESG-WARN][53] ([i915#180]) +4 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: NOTRUN -> [SKIP][54] ([fdo#111825]) +4 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-apl: NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][58] -> [FAIL][59] ([fdo#108145] / [i915#265]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][60] ([i915#265]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping: - shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2733]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +3 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2: - shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3: - shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +2 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109441]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb5/igt@kms_psr@psr2_no_drrs.html * igt@kms_psr@psr2_sprite_render: - shard-tglb: NOTRUN -> [FAIL][67] ([i915#132]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb5/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: - shard-snb: NOTRUN -> [FAIL][68] ([i915#31]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-snb2/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][69] -> [DMESG-WARN][70] ([i915#180] / [i915#295]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271]) +152 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2437]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl8/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-fb-id: - shard-tglb: NOTRUN -> [SKIP][73] ([i915#2437]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@kms_writeback@writeback-fb-id.html * igt@perf@polling-parameterized: - shard-skl: [PASS][74] -> [FAIL][75] ([i915#1542]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl9/igt@perf@polling-parameterized.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl2/igt@perf@polling-parameterized.html * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name: - shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109291]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html * igt@sysfs_clients@fair-0: - shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl10/igt@sysfs_clients@fair-0.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994]) +4 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@pidname: - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl2/igt@sysfs_clients@pidname.html * igt@sysfs_heartbeat_interval@mixed@rcs0: - shard-skl: [PASS][80] -> [FAIL][81] ([i915#1731]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl8/igt@sysfs_heartbeat_interval@mixed@rcs0.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl7/igt@sysfs_heartbeat_interval@mixed@rcs0.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83] +2 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][84] ([i915#2369] / [i915#3063]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-tglb5/igt@gem_eio@unwedge-stress.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb3/igt@gem_eio@unwedge-stress.html - shard-skl: [TIMEOUT][86] ([i915#2369] / [i915#3063]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl8/igt@gem_eio@unwedge-stress.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl8/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [FAIL][88] ([i915#2842]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-glk: [FAIL][90] ([i915#307]) -> [PASS][91] +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-glk6/igt@gem_mmap_gtt@cpuset-big-copy.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-glk2/igt@gem_mmap_gtt@cpuset-big-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [FAIL][92] ([i915#2428]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-xy.html * igt@gem_mmap_offset@clear: - shard-skl: [FAIL][94] ([i915#3160]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl1/igt@gem_mmap_offset@clear.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl4/igt@gem_mmap_offset@clear.html - shard-glk: [FAIL][96] ([i915#1888] / [i915#3160]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-glk2/igt@gem_mmap_offset@clear.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-glk1/igt@gem_mmap_offset@clear.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][98] ([i915#644]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-skl: [FAIL][100] ([i915#2346]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [INCOMPLETE][102] ([i915#180]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1: - shard-skl: [FAIL][104] ([i915#2122]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html * igt@kms_hdr@bpc-switch: - shard-skl: [FAIL][106] ([i915#1188]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl8/igt@kms_hdr@bpc-switch.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl8/igt@kms_hdr@bpc-switch.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [INCOMPLETE][108] ([i915#198]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][112] ([fdo#109441]) -> [PASS][113] +2 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html #### Warnings #### * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [FAIL][114] ([i915#2842]) -> [SKIP][115] ([fdo#109271]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-iclb: [SKIP][116] ([i915#658]) -> [SKIP][117] ([i915#2920]) +2 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4: - shard-iclb: [SKIP][118] ([i915#2920]) -> [SKIP][119] ([i915#658]) +2 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html * igt@runner@aborted: - shard-kbl: ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl6/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl1/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl3/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl6/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl1/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-kbl6/igt@runner@aborted.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl3/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl3/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@runner@aborted.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl3/igt@runner@aborted.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl6/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl7/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-kbl7/igt@runner@aborted.html - shard-apl: ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> [FAIL][139] ([i915#3002] / [i915#3363]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl1/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl7/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl2/igt@runner@aborted.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10041/shard-apl6/igt@runner@aborted.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/shard-apl3/igt@runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2428]: https://gitlab.freedesktop.org/drm/intel/issues/2428 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20061/index.html [-- Attachment #1.2: Type: text/html, Size: 36741 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v2 00/17] drm/i915: DDI buf trans cleaup and fixes @ 2021-06-08 7:35 Ville Syrjala 2021-06-08 7:35 ` [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala 0 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-06-08 7:35 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The DDI buf trans functions keep turning into bad spaghetti every time a new platform gets added. Split the platforms up properly and turn the whole thing into a vfunc to make it easier to manage multiple platforms. v2: Rebase due to adl-p landing in the meantime Ville Syrjälä (17): drm/i915: s/intel/hsw/ for hsw/bdw/skl buf trans drm/i915: Introduce hsw_get_buf_trans() drm/i915: Wrap the platform specific buf trans structs into a union drm/i915: Rename dkl phy buf trans tables drm/i915: Wrap the buf trans tables into a struct drm/i915: Introduce intel_get_buf_trans() drm/i915; Return the whole buf_trans struct from get_buf_trans() drm/i915: Store the HDMI default entry in the bug trans struct drm/i915: Introduce encoder->get_buf_trans() drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs drm/i915: Introduce rkl_get_combo_buf_trans() drm/i915: Fix dg1 buf trans tables drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table drm/i915: Fix ehl edp hbr2 vswing table drm/i915: Clean up jsl/ehl buf trans functions drm/i915: Nuke buf_trans hdmi functions drm/i915: Add the missing adls vswing tables drivers/gpu/drm/i915/display/intel_crt.c | 3 + drivers/gpu/drm/i915/display/intel_ddi.c | 167 +- drivers/gpu/drm/i915/display/intel_ddi.h | 4 +- .../drm/i915/display/intel_ddi_buf_trans.c | 2437 ++++++++++------- .../drm/i915/display/intel_ddi_buf_trans.h | 68 +- .../drm/i915/display/intel_display_types.h | 4 + drivers/gpu/drm/i915/display/intel_fdi.c | 5 +- 7 files changed, 1473 insertions(+), 1215 deletions(-) -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables 2021-06-08 7:35 [Intel-gfx] [PATCH v2 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala @ 2021-06-08 7:35 ` Ville Syrjala 2021-06-18 12:28 ` Jani Nikula 0 siblings, 1 reply; 37+ messages in thread From: Ville Syrjala @ 2021-06-08 7:35 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula From: Ville Syrjälä <ville.syrjala@linux.intel.com> For some reason the dg1 buf trans tables have been stuffed into icl_get_combo_buf_trans_edp() which doesn't even get called on dg1. Split them out into a proper dg1 specific function, and also make sure we use the proper buf trans tables for DP as well as eDP. v2: Add the hobl stuff Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 55 +++++++++++++++++-- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index fcb67deb46dd..52bc6cbe36cf 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1325,12 +1325,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, } else if (dev_priv->vbt.edp.low_vswing) { return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, - n_entries); - } else if (IS_DG1(dev_priv)) { - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, - n_entries); } return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1545,6 +1539,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + n_entries); + else + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, + n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); + else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + n_entries); + else if (dev_priv->vbt.edp.low_vswing) + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +dg1_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1682,6 +1723,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) encoder->get_buf_trans = adlp_get_dkl_buf_trans; } else if (IS_ROCKETLAKE(i915)) { encoder->get_buf_trans = rkl_get_combo_buf_trans; + } else if (IS_DG1(i915)) { + encoder->get_buf_trans = dg1_get_combo_buf_trans; } else if (DISPLAY_VER(i915) >= 12) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = tgl_get_combo_buf_trans; -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables 2021-06-08 7:35 ` [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala @ 2021-06-18 12:28 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2021-06-18 12:28 UTC (permalink / raw) To: Ville Syrjala, intel-gfx On Tue, 08 Jun 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > For some reason the dg1 buf trans tables have been stuffed into > icl_get_combo_buf_trans_edp() which doesn't even get called > on dg1. Split them out into a proper dg1 specific function, > and also make sure we use the proper buf trans tables for > DP as well as eDP. > > v2: Add the hobl stuff > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Holds for v2. > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 55 +++++++++++++++++-- > 1 file changed, 49 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index fcb67deb46dd..52bc6cbe36cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1325,12 +1325,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > } else if (dev_priv->vbt.edp.low_vswing) { > return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > n_entries); > - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > - n_entries); > - } else if (IS_DG1(dev_priv)) { > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, > - n_entries); > } > > return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > @@ -1545,6 +1539,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, > return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (crtc_state->port_clock > 270000) > + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > + n_entries); > + else > + return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, > + n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + if (crtc_state->port_clock > 540000) > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, > + n_entries); > + else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + n_entries); > + else if (dev_priv->vbt.edp.low_vswing) > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + n_entries); > + else > + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +dg1_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct intel_ddi_buf_trans * > rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -1682,6 +1723,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > encoder->get_buf_trans = adlp_get_dkl_buf_trans; > } else if (IS_ROCKETLAKE(i915)) { > encoder->get_buf_trans = rkl_get_combo_buf_trans; > + } else if (IS_DG1(i915)) { > + encoder->get_buf_trans = dg1_get_combo_buf_trans; > } else if (DISPLAY_VER(i915) >= 12) { > if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = tgl_get_combo_buf_trans; -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2021-06-18 12:28 UTC | newest] Thread overview: 37+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala 2021-05-11 18:31 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala 2021-05-12 18:53 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala 2021-05-12 18:58 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala 2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-05-12 19:05 ` Jani Nikula 2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala 2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala 2021-04-22 6:20 ` kernel test robot 2021-05-04 10:16 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork 2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork 2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula 2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-06-08 7:35 [Intel-gfx] [PATCH v2 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala 2021-06-08 7:35 ` [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala 2021-06-18 12:28 ` Jani Nikula
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