[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Dnyaneshwar Bhadane]

Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, 
MTL with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, 
KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform
defines. This way there is a consistent pattern to how platforms 
are referred. While the change is minor and could be combined to 
have lesser patches, splitting to per subpaltform for easier 
cherrypicks, if needed.

v2:
 - Fix the checkpatch warning.

Anusha Srivatsa (5):
  drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
  drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
  drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
  drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
  drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

Dnyaneshwar Bhadane (6):
  drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
  drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
  drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
  drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
  drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
  drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines

 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
 .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
 .../drm/i915/display/skl_universal_plane.c    | 10 +--
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
 drivers/gpu/drm/i915/intel_step.c             | 10 +--
 drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
 34 files changed, 143 insertions(+), 143 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace TGL with
TIGERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 drivers/gpu/drm/i915/intel_step.c                  | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..9e34cc103aeb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (crtc_state->port_clock > 270000) {
-		if (IS_TGL_UY(dev_priv)) {
+		if (IS_TIGERLAKE_UY(dev_priv)) {
 			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
 						   n_entries);
 		} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..26def9cb86e4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 
 	/* Wa_14010477008 */
 	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
-	    IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+	    IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4cf6f0f636d..0f30dc890209 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_WITH_PORT_F(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -662,7 +662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 8a9ff6227e53..67054c87bb5f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ROCKETLAKE(i915)) {
 		revids = rkl_revids;
 		size = ARRAY_SIZE(rkl_revids);
-	} else if (IS_TGL_UY(i915)) {
+	} else if (IS_TIGERLAKE_UY(i915)) {
 		revids = tgl_uy_revids;
 		size = ARRAY_SIZE(tgl_uy_revids);
 	} else if (IS_TIGERLAKE(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               |  6 +--
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d58ed9b62e67..06b464229efe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 26def9cb86e4..25b06ced9ce7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca..eb72610a8588 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..f9af6b1a7c01 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2ebd937f3b4c..901ecd59afbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_engine_wait_for_pending_mi_fw(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..1dc7180eeb27 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..cd9a76f048f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..cc8b09b8a7fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..a109ecd54944 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 
 	mtl_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..3af0fcd7dd57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
@@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(gt->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 		flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..5914c7348aba 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
 		intel_engine_stop_cs(engine);
@@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f30dc890209..472a36cf1a72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a111b281578..e943ffbaecbc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
 		struct intel_gt *gt;
 		int i;
 
-- 
2.34.1

[Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace RKL with
ROCKETLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index db5437043904..c65505b82065 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1586,7 +1586,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	    IS_ROCKETLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 472a36cf1a72..3e9567f9ad15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -666,7 +666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
+#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-- 
2.34.1

[Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c         |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c     |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c       |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +++++++++---------
 drivers/gpu/drm/i915/display/intel_hdmi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c       |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                | 10 +++++-----
 drivers/gpu/drm/i915/intel_step.c              |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c           |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
 		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+		if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
 			intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 		}
 	}
 
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		for_each_dsi_phy(phy, intel_dsi->phys)
 			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (dev_priv->display.cdclk.hw.ref == 24000)
 			dev_priv->display.cdclk.max_cdclk_freq = 552000;
 		else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 
 	if (IS_ALDERLAKE_S(i915))
 		return phy == PHY_A;
-	else if (IS_JSL_EHL(i915) ||
+	else if (IS_JASPERLAKE_EHL(i915) ||
 		 IS_ROCKETLAKE(i915) ||
 		 IS_DG1(i915))
 		return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-		if (IS_JSL_EHL(dev_priv)) {
+		if (IS_JASPERLAKE_EHL(dev_priv)) {
 			if (ehl_vbt_ddi_d_present(dev_priv))
 				expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * "internal" child devices.
 		 */
 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
 			val &= ~ICL_PHY_MISC_MUX_DDID;
 
 			if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 090f242e610c..106387ff3658 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3582,7 +3582,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 {
 	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
-	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
+	else if (IS_JASPERLAKE_EHL(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 3;
 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
@@ -4801,7 +4801,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->disable_clock = dg1_ddi_disable_clock;
 		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
 		encoder->get_config = dg1_ddi_get_config;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (intel_ddi_is_tc(dev_priv, port)) {
 			encoder->enable_clock = jsl_ddi_tc_enable_clock;
 			encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4872,7 +4872,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d8533603ad05..e659f8abaec8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1750,7 +1750,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 		return phy <= PHY_E;
 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		return phy <= PHY_C;
 	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
 		return phy <= PHY_B;
@@ -1802,7 +1802,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 		return PHY_B + port - PORT_TC1;
 	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
-	else if (IS_JSL_EHL(i915) && port == PORT_D)
+	else if (IS_JASPERLAKE_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
 	return PHY_A + port - PORT_A;
@@ -7440,7 +7440,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_TC5);
 		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 09dc6c88ad28..da9962b914f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -500,7 +500,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 			max_rate = 810000;
-		else if (IS_JSL_EHL(dev_priv))
+		else if (IS_JASPERLAKE_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..c6d376d414b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -191,7 +191,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 {
 	if (IS_DG1(i915))
 		return DG1_DPLL_ENABLE(pll->info->id);
-	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+	else if (IS_JASPERLAKE_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
 	return ICL_DPLL_ENABLE(pll->info->id);
@@ -2461,7 +2461,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
+		 IS_JASPERLAKE_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->display.dpll.ref_clks.nssc == 38400;
 }
@@ -3226,7 +3226,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv) && port != PORT_A) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3567,7 +3567,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
 		}
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			hw_state->cfgcr0 = intel_de_read(dev_priv,
 							 ICL_DPLL_CFGCR0(4));
 			hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3623,7 +3623,7 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 		div0_reg = TGL_DPLL0_DIV0(id);
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
 		} else {
@@ -3806,7 +3806,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 {
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 
 		/*
@@ -3914,7 +3914,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
 					pll->wakeref);
@@ -4150,7 +4150,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 		dpll_mgr = &rkl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
@@ -4335,7 +4335,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 
 	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
 
-	if (IS_JSL_EHL(i915) && pll->on &&
+	if (IS_JASPERLAKE_EHL(i915) && pll->on &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 		pll->wakeref = intel_display_power_get(i915,
 						       POWER_DOMAIN_DC_OFF);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..4e557594ba62 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2903,7 +2903,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
 		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 06b464229efe..f61d39d2b0fc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -963,7 +963,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 
 	/* JSL and EHL only supports eDP 1.3 */
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 97ac6fb37958..0b34518d051c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -226,7 +226,7 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
 	 * it, but since i915 takes the stance of always zeroing memory before
 	 * handing it to userspace, we need to prevent this.
 	 */
-	return IS_JSL_EHL(i915);
+	return IS_JASPERLAKE_EHL(i915);
 }
 
 static void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 1141f875f5bd..6945a0bc9778 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -302,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	u8 eu_en;
 	u8 s_en;
 
-	if (IS_JSL_EHL(gt->i915))
+	if (IS_JASPERLAKE_EHL(gt->i915))
 		intel_sseu_set_info(sseu, 1, 4, 8);
 	else
 		intel_sseu_set_info(sseu, 1, 8, 8);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a109ecd54944..a62dcbc2f901 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1441,7 +1441,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
+	    IS_JASPERLAKE_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    GEN11_SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e9567f9ad15..3981b890f053 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
 #define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
-#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
 				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
 #define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
@@ -657,10 +657,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
-#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
-#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 67054c87bb5f..847c7de50e1f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -219,7 +219,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
-	} else if (IS_JSL_EHL(i915)) {
+	} else if (IS_JASPERLAKE_EHL(i915)) {
 		revids = jsl_ehl_revids;
 		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index ba9843cb1b13..2e78b17843da 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_ICP;
 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* MCC is TGP compatible */
 		return PCH_TGP;
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
@@ -127,7 +127,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_TGP;
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* JSP is ICP compatible */
 		return PCH_ICP;
 	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
@@ -177,7 +177,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
 		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
 	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
-- 
2.34.1

[Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace KBL with
KABYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h                    | 12 ++++++------
 drivers/gpu/drm/i915/intel_clock_gating.c          |  4 ++--
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 9e34cc103aeb..84b09d188d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1718,9 +1718,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 			encoder->get_buf_trans = icl_get_mg_buf_trans;
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		encoder->get_buf_trans = bxt_get_buf_trans;
-	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KABYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = kbl_y_get_buf_trans;
-	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KABYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index eb72610a8588..ec0771dc662a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
 			vf_flush_wa = true;
 
 		/* WaForGAMHang:kbl */
-		if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+		if (IS_KABYLAKE_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
 			dc_flush_wa = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a62dcbc2f901..b632fb5592a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -584,7 +584,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	gen9_ctx_workarounds_init(engine, wal);
 
 	/* WaToEnableHwFixForPushConstHWBug:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
 		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 			     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
@@ -1185,7 +1185,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	gen9_gt_workarounds_init(gt, wal);
 
 	/* WaDisableDynamicCreditSharing:kbl */
-	if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
 		wa_write_or(wal,
 			    GAMT_CHKN_BIT_REG,
 			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2933,7 +2933,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
 		wa_write(wal,
 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
 			 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3981b890f053..f19915115cff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -614,9 +614,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_SKL_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -624,9 +624,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
-#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT3(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_CFL_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
@@ -652,9 +652,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
-#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
+#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
-#define IS_KBL_DISPLAY_STEP(i915, since, until) \
+#define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
 #define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a27600bc5976..bb349043522c 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -456,12 +456,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
 	/* WaDisableSDEUnitClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
 				 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableGamClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-- 
2.34.1

[Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace SKL with
SKYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 14 +++++++-------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 84b09d188d2a..ab84d003232c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
-	} else if (IS_SKL_ULX(i915)) {
+	} else if (IS_SKYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = skl_y_get_buf_trans;
-	} else if (IS_SKL_ULT(i915)) {
+	} else if (IS_SKYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = skl_u_get_buf_trans;
 	} else if (IS_SKYLAKE(i915)) {
 		encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b632fb5592a8..10a4e0fc23ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+	if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f19915115cff..3c4a66f1a7ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KABYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KABYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
 #define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TIGERLAKE_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
-	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+	(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
-- 
2.34.1

[Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2acfa0435675..034454233d87 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		/* Wa_22011320316:adl-p[a0] */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6d376d414b8..47fe8311067e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 {
 	u32 val;
 
-	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+	if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f61d39d2b0fc..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	/* Wa_22012278275:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
 			1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	/* Wa_16011303918:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return;
 
 	/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 		return false;
 	}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
-	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	    IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 25b06ced9ce7..2458a9ea25ba 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c4a66f1a7ba..08e14cf225b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-- 
2.34.1

[Intel-gfx] [PATCH 08/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_step.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08e14cf225b5..bff9218b9f78 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -589,7 +589,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 847c7de50e1f..9072f4ccd3c1 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ADLP_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
-	} else if (IS_ADLP_RPLP(i915)) {
+	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
 		revids = adlp_rplp_revids;
 		size = ARRAY_SIZE(adlp_rplp_revids);
 	} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c        | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                 | 2 +-
 drivers/gpu/drm/i915/intel_step.c               | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-	if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
 		return true;
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
 		return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d408856ae4c0..dfb2837a3ed4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -279,7 +279,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 	 * ADL-S, otherwise the GuC might attempt to fetch a config table that
 	 * does not exist.
 	 */
-	if (IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P_N(i915))
 		p = INTEL_ALDERLAKE_S;
 
 	GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bff9218b9f78..d3ce6ed3be86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -587,7 +587,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 9072f4ccd3c1..fe447063a064 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_XEHPSDV(i915)) {
 		revids = xehpsdv_revids;
 		size = ARRAY_SIZE(xehpsdv_revids);
-	} else if (IS_ADLP_N(i915)) {
+	} else if (IS_ALDERLAKE_P_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
 	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platfrom Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c               | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                     | 6 +++---
 drivers/gpu/drm/i915/intel_step.c                   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 3fd30e7f0062..f3090b8afc60 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -797,7 +797,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 	enum pipe pipe;
 
 	/* Wa_14011765242: adl-s A0,A1 */
-	if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+	if (IS_ALDERLAKE_S_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
 		for_each_pipe(i915, pipe)
 			display_runtime->num_scalers[pipe] = 0;
 	else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..eb28705b88bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
 	}
 
 	/* Intermediate platforms are HuC authentication only */
-	if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+	if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) {
 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3ce6ed3be86..1dad0c9b4f30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -585,7 +585,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_ALDERLAKE_S_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index fe447063a064..f410aa2a8077 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_P(i915)) {
 		revids = adlp_revids;
 		size = ARRAY_SIZE(adlp_revids);
-	} else if (IS_ADLS_RPLS(i915)) {
+	} else if (IS_ALDERLAKE_S_RPLS(i915)) {
 		revids = adls_rpls_revids;
 		size = ARRAY_SIZE(adls_rpls_revids);
 	} else if (IS_ALDERLAKE_S(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 034454233d87..4318785b940f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3562,7 +3562,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
-		} else if (IS_ADLP_RPLU(dev_priv)) {
+		} else if (IS_ALDERLAKE_RPLU(dev_priv)) {
 			dev_priv->display.cdclk.table = rplu_cdclk_table;
 			dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
 		} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1dad0c9b4f30..c6ad78381dd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -591,7 +591,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_ALDERLAKE_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
 				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/119380/
State : warning

== Summary ==

Error: dim checkpatch failed
7403e3359af6 drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:665:
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
a14c9d1d9832 drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
-:372: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#372: FILE: drivers/gpu/drm/i915/i915_drv.h:691:
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))

-:377: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#377: FILE: drivers/gpu/drm/i915/i915_drv.h:695:
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))

-:382: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#382: FILE: drivers/gpu/drm/i915/i915_drv.h:699:
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))

total: 0 errors, 0 warnings, 3 checks, 306 lines checked
2957fedb5d37 drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#34: FILE: drivers/gpu/drm/i915/i915_drv.h:669:
+#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 16 lines checked
30a243ada797 drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
-:321: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#321: FILE: drivers/gpu/drm/i915/i915_drv.h:566:
+#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
 				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))

-:333: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#333: FILE: drivers/gpu/drm/i915/i915_drv.h:660:
+#define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_GRAPHICS_STEP(p, since, until))

-:335: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#335: FILE: drivers/gpu/drm/i915/i915_drv.h:662:
+#define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 3 checks, 278 lines checked
8bc8ff090e7e drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
-:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#92: FILE: drivers/gpu/drm/i915/i915_drv.h:627:
+#define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)

-:95: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#95: FILE: drivers/gpu/drm/i915/i915_drv.h:629:
+#define IS_KABYLAKE_GT3(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)

-:104: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#104: FILE: drivers/gpu/drm/i915/i915_drv.h:655:
+#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))

-:107: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#107: FILE: drivers/gpu/drm/i915/i915_drv.h:657:
+#define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))

total: 0 errors, 0 warnings, 4 checks, 90 lines checked
4e0e5a343950 drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#59: FILE: drivers/gpu/drm/i915/i915_drv.h:621:
+#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)

-:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#62: FILE: drivers/gpu/drm/i915/i915_drv.h:623:
+#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)

-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/i915_drv.h:625:
+#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)

-:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/i915_drv.h:653:
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))

-:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#74: FILE: drivers/gpu/drm/i915/i915_drv.h:653:
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))

total: 0 errors, 1 warnings, 4 checks, 59 lines checked
1617167bacb7 drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
-:7: WARNING:TYPO_SPELLING: 'platfrom' may be misspelled - perhaps 'platform'?
#7: 
Driver refers to the platfrom Alderlake P as ADLP in places
                     ^^^^^^^^

-:111: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#111: FILE: drivers/gpu/drm/i915/i915_drv.h:680:
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))

-:116: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#116: FILE: drivers/gpu/drm/i915/i915_drv.h:684:
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))

total: 0 errors, 1 warnings, 2 checks, 77 lines checked
9ffb57cf3d69 drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
eed866c75eb9 drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
2cfe542c1561 drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
-:7: WARNING:TYPO_SPELLING: 'platfrom' may be misspelled - perhaps 'platform'?
#7: 
Driver refers to the platfrom Alderlake S as ADLS in places
                     ^^^^^^^^

-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_drv.h:672:
+#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))

-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#63: FILE: drivers/gpu/drm/i915/i915_drv.h:676:
+#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))

total: 0 errors, 1 warnings, 2 checks, 45 lines checked
d984a3c236a4 drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/119380/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Replace acronym with full platform name in defines.

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8394 bytes --]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/119380/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13274 -> Patchwork_119380v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/index.html

Participating hosts (41 -> 41)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_119380v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_module_load@load:
    - bat-adlp-11:        [PASS][3] -> [ABORT][4] ([i915#4423])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-adlp-11/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-adlp-11/igt@i915_module_load@load.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#7913])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
    - fi-kbl-soraka:      NOTRUN -> [ABORT][6] ([i915#7913])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-2:         [PASS][7] -> [DMESG-WARN][8] ([i915#6367])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-rpls-2/igt@i915_selftest@live@slpc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-rpls-2/igt@i915_selftest@live@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271]) +14 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
    - bat-dg2-8:          [PASS][10] -> [FAIL][11] ([i915#7932])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/fi-kbl-soraka/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_mocs:
    - bat-mtlp-6:         [DMESG-FAIL][13] ([i915#7059]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@guc:
    - bat-rpls-2:         [DMESG-WARN][15] ([i915#7852]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-rpls-2/igt@i915_selftest@live@guc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-rpls-2/igt@i915_selftest@live@guc.html

  * igt@i915_selftest@live@migrate:
    - bat-mtlp-8:         [DMESG-FAIL][17] ([i915#7699]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-mtlp-8/igt@i915_selftest@live@migrate.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-mtlp-8/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [DMESG-FAIL][19] ([i915#6763]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
    - bat-dg2-8:          [FAIL][21] ([i915#7932]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html

  
#### Warnings ####

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-rpls-2:         [ABORT][23] ([i915#6687]) -> [ABORT][24] ([i915#6687] / [i915#8668])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_psr@primary_mmap_gtt:
    - bat-rplp-1:         [SKIP][25] ([i915#1072]) -> [ABORT][26] ([i915#8442])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668


Build changes
-------------

  * Linux: CI_DRM_13274 -> Patchwork_119380v1

  CI-20190529: 20190529
  CI_DRM_13274: 134d180cacae82fadbc5ee32f86014cc290f5e0c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7331: 4604cc18a2e7af126996d3b56ad0168e7258e8e9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_119380v1: 134d180cacae82fadbc5ee32f86014cc290f5e0c @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

c951a5b87f53 drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
6bd6a4619416 drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
a7447b3a7a91 drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
b1d67bef969c drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
2ad2cd2509ad drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
62baadfb1c9d drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
0fa48a165435 drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
d26299fcad66 drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
ea82b46bb58a drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
895794b00d93 drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
89a5cf0a25d2 drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/index.html

[-- Attachment #2: Type: text/html, Size: 9864 bytes --]

Re: [Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Thursday, June 15, 2023 2:54 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Subject: [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and
> subplatform defines
> 
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> Driver refers to the platfrom Alderlake S as ADLS in places and ALDERLAKE_S in
			^^^ same typo again!

Anusha 
> some. Making the consistent change to avoid confusion of the right naming
> convention for the platform.
> 
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c               | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h                     | 6 +++---
>  drivers/gpu/drm/i915/intel_step.c                   | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 3fd30e7f0062..f3090b8afc60 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -797,7 +797,7 @@ void intel_display_device_info_runtime_init(struct
> drm_i915_private *i915)
>  	enum pipe pipe;
> 
>  	/* Wa_14011765242: adl-s A0,A1 */
> -	if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
> +	if (IS_ALDERLAKE_S_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
>  		for_each_pipe(i915, pipe)
>  			display_runtime->num_scalers[pipe] = 0;
>  	else if (DISPLAY_VER(i915) >= 11) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 18250fb64bd8..eb28705b88bd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
>  	}
> 
>  	/* Intermediate platforms are HuC authentication only */
> -	if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
> +	if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) {
>  		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
>  		return;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d3ce6ed3be86..1dad0c9b4f30 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -585,7 +585,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> #define IS_DG2_G12(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) -
> #define IS_ADLS_RPLS(i915) \
> +#define IS_ALDERLAKE_S_RPLS(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S,
> INTEL_SUBPLATFORM_RPL)  #define IS_ALDERLAKE_P_N(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_N) @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const
> struct drm_i915_private *i915,  #define IS_ROCKETLAKE_DISPLAY_STEP(p, since,
> until) \
>  	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> 
> -#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_S(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_S(__i915) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index fe447063a064..f410aa2a8077 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ALDERLAKE_P(i915)) {
>  		revids = adlp_revids;
>  		size = ARRAY_SIZE(adlp_revids);
> -	} else if (IS_ADLS_RPLS(i915)) {
> +	} else if (IS_ALDERLAKE_S_RPLS(i915)) {
>  		revids = adls_rpls_revids;
>  		size = ARRAY_SIZE(adls_rpls_revids);
>  	} else if (IS_ALDERLAKE_S(i915)) {
> --
> 2.34.1

[Intel-gfx] ✓ Fi.CI.IGT: success for Replace acronym with full platform name in defines.

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 16095 bytes --]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/119380/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13274_full -> Patchwork_119380v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_119380v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([i915#2842])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_lmem_swapping@basic:
    - shard-apl:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@gem_lmem_swapping@basic.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglu:         [PASS][6] -> [FAIL][7] ([i915#3989] / [i915#454])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-tglu-4/igt@i915_pm_dc@dc6-dpms.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-tglu-7/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][8] -> [SKIP][9] ([i915#1397])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-3/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#8502]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][12] ([i915#3804] / [i915#4579])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][13] -> [FAIL][14] ([i915#4767])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-apl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +5 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#4579] / [i915#6953] / [i915#8228])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [FAIL][17] ([i915#4573]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#5176]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#4579] / [i915#5176]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][20] ([fdo#109271]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-snb1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4579]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-snb1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-dp-1:
    - shard-apl:          NOTRUN -> [SKIP][22] ([fdo#109271]) +56 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-dp-1.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
    - shard-apl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#658])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl6/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [FAIL][24] ([i915#7742]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
    - {shard-dg1}:        [ABORT][26] ([i915#6333] / [i915#7461] / [i915#8234]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-dg1-13/igt@gem_barrier_race@remote-request@rcs0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-dg1-15/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-rkl:          [FAIL][28] ([i915#6268]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@hibernate:
    - {shard-dg1}:        [ABORT][30] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-dg1-14/igt@gem_eio@hibernate.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-dg1-17/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-rkl:          [FAIL][32] ([i915#2842]) -> [PASS][33] +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][34] ([i915#4281]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-tglu-7/igt@i915_pm_dc@dc9-dpms.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - {shard-dg1}:        [SKIP][36] ([i915#1397]) -> [PASS][37] +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - {shard-dg1}:        [FAIL][38] ([i915#3743] / [i915#7959]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-dg1-19/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-dg1-15/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-apl:          [FAIL][40] ([i915#2346]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@forked-move@pipe-b:
    - {shard-dg1}:        [INCOMPLETE][42] ([i915#8011] / [i915#8347]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-dg1-19/igt@kms_cursor_legacy@forked-move@pipe-b.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-dg1-15/igt@kms_cursor_legacy@forked-move@pipe-b.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][44] ([i915#79]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html

  
#### Warnings ####

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][46] ([i915#3955]) -> [SKIP][47] ([fdo#110189] / [i915#3955])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13274/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6333]: https://gitlab.freedesktop.org/drm/intel/issues/6333
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7959]: https://gitlab.freedesktop.org/drm/intel/issues/7959
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502


Build changes
-------------

  * Linux: CI_DRM_13274 -> Patchwork_119380v1

  CI-20190529: 20190529
  CI_DRM_13274: 134d180cacae82fadbc5ee32f86014cc290f5e0c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7331: 4604cc18a2e7af126996d3b56ad0168e7258e8e9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_119380v1: 134d180cacae82fadbc5ee32f86014cc290f5e0c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119380v1/index.html

[-- Attachment #2: Type: text/html, Size: 16105 bytes --]

[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Dnyaneshwar Bhadane]

Replace all occurences of MTL with METEORLAKE, ADL with ALDERLAKE, 
TGL with TIGERLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, 
KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform
defines. This way there is a consistent pattern to how platforms 
are referred. While the change is minor and could be combined to 
have lesser patches, splitting to per subpaltform for easier 
cherrypicks, if needed.

v2:
 - Reordered patches by incrementing platform generations.

Anusha Srivatsa (5):
  drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
  drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
  drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
  drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
  drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

Dnyaneshwar Bhadane (6):
  drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
  drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines
  drm/i915/tgl: s/RKL/ROCKETLAKE for platform/subplatform defines
  drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines
  drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines
  drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
 .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
 .../drm/i915/display/skl_universal_plane.c    | 10 +--
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
 drivers/gpu/drm/i915/intel_step.c             | 10 +--
 drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
 34 files changed, 143 insertions(+), 143 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 01/11] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace SKL with
SKYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 14 +++++++-------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..13a2c364b8eb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
-	} else if (IS_SKL_ULX(i915)) {
+	} else if (IS_SKYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = skl_y_get_buf_trans;
-	} else if (IS_SKL_ULT(i915)) {
+	} else if (IS_SKYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = skl_u_get_buf_trans;
 	} else if (IS_SKYLAKE(i915)) {
 		encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..38ecbe793ea4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+	if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4cf6f0f636d..71dd1d80dc97 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KBL_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KBL_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
 #define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KBL_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
-	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+	(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
-- 
2.34.1

[Intel-gfx] [PATCH 02/11] drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace KBL with
KABYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h                    | 12 ++++++------
 drivers/gpu/drm/i915/intel_clock_gating.c          |  4 ++--
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 13a2c364b8eb..cd6915e9e138 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1718,9 +1718,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 			encoder->get_buf_trans = icl_get_mg_buf_trans;
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		encoder->get_buf_trans = bxt_get_buf_trans;
-	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KABYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = kbl_y_get_buf_trans;
-	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KABYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca..3173e811463d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
 			vf_flush_wa = true;
 
 		/* WaForGAMHang:kbl */
-		if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+		if (IS_KABYLAKE_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
 			dc_flush_wa = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 38ecbe793ea4..bb948ffc95ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -584,7 +584,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	gen9_ctx_workarounds_init(engine, wal);
 
 	/* WaToEnableHwFixForPushConstHWBug:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
 		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 			     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
@@ -1185,7 +1185,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	gen9_gt_workarounds_init(gt, wal);
 
 	/* WaDisableDynamicCreditSharing:kbl */
-	if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
 		wa_write_or(wal,
 			    GAMT_CHKN_BIT_REG,
 			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2933,7 +2933,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
 		wa_write(wal,
 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
 			 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71dd1d80dc97..6102b127fe4d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -614,9 +614,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_SKYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -624,9 +624,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
-#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT3(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_CFL_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
@@ -652,9 +652,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
-#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
+#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
-#define IS_KBL_DISPLAY_STEP(i915, since, until) \
+#define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a27600bc5976..bb349043522c 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -456,12 +456,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
 	/* WaDisableSDEUnitClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
 				 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableGamClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-- 
2.34.1

[Intel-gfx] [PATCH 03/11] drm/i915/tgl: s/RKL/ROCKETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace RKL with
ROCKETLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index db5437043904..c65505b82065 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1586,7 +1586,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	    IS_ROCKETLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6102b127fe4d..feddd9d32dce 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -666,7 +666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
+#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-- 
2.34.1

[Intel-gfx] [PATCH 04/11] drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c         |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c     |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c       |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +++++++++---------
 drivers/gpu/drm/i915/display/intel_hdmi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c       |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                | 10 +++++-----
 drivers/gpu/drm/i915/intel_step.c              |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c           |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
 		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+		if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
 			intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 		}
 	}
 
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		for_each_dsi_phy(phy, intel_dsi->phys)
 			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (dev_priv->display.cdclk.hw.ref == 24000)
 			dev_priv->display.cdclk.max_cdclk_freq = 552000;
 		else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 
 	if (IS_ALDERLAKE_S(i915))
 		return phy == PHY_A;
-	else if (IS_JSL_EHL(i915) ||
+	else if (IS_JASPERLAKE_EHL(i915) ||
 		 IS_ROCKETLAKE(i915) ||
 		 IS_DG1(i915))
 		return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-		if (IS_JSL_EHL(dev_priv)) {
+		if (IS_JASPERLAKE_EHL(dev_priv)) {
 			if (ehl_vbt_ddi_d_present(dev_priv))
 				expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * "internal" child devices.
 		 */
 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
 			val &= ~ICL_PHY_MISC_MUX_DDID;
 
 			if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 090f242e610c..106387ff3658 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3582,7 +3582,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 {
 	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
-	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
+	else if (IS_JASPERLAKE_EHL(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 3;
 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
@@ -4801,7 +4801,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->disable_clock = dg1_ddi_disable_clock;
 		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
 		encoder->get_config = dg1_ddi_get_config;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (intel_ddi_is_tc(dev_priv, port)) {
 			encoder->enable_clock = jsl_ddi_tc_enable_clock;
 			encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4872,7 +4872,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d8533603ad05..e659f8abaec8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1750,7 +1750,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 		return phy <= PHY_E;
 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		return phy <= PHY_C;
 	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
 		return phy <= PHY_B;
@@ -1802,7 +1802,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 		return PHY_B + port - PORT_TC1;
 	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
-	else if (IS_JSL_EHL(i915) && port == PORT_D)
+	else if (IS_JASPERLAKE_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
 	return PHY_A + port - PORT_A;
@@ -7440,7 +7440,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_TC5);
 		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 09dc6c88ad28..da9962b914f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -500,7 +500,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 			max_rate = 810000;
-		else if (IS_JSL_EHL(dev_priv))
+		else if (IS_JASPERLAKE_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..c6d376d414b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -191,7 +191,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 {
 	if (IS_DG1(i915))
 		return DG1_DPLL_ENABLE(pll->info->id);
-	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+	else if (IS_JASPERLAKE_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
 	return ICL_DPLL_ENABLE(pll->info->id);
@@ -2461,7 +2461,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
+		 IS_JASPERLAKE_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->display.dpll.ref_clks.nssc == 38400;
 }
@@ -3226,7 +3226,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv) && port != PORT_A) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3567,7 +3567,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
 		}
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			hw_state->cfgcr0 = intel_de_read(dev_priv,
 							 ICL_DPLL_CFGCR0(4));
 			hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3623,7 +3623,7 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 		div0_reg = TGL_DPLL0_DIV0(id);
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
 		} else {
@@ -3806,7 +3806,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 {
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 
 		/*
@@ -3914,7 +3914,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
 					pll->wakeref);
@@ -4150,7 +4150,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 		dpll_mgr = &rkl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
@@ -4335,7 +4335,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 
 	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
 
-	if (IS_JSL_EHL(i915) && pll->on &&
+	if (IS_JASPERLAKE_EHL(i915) && pll->on &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 		pll->wakeref = intel_display_power_get(i915,
 						       POWER_DOMAIN_DC_OFF);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..4e557594ba62 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2903,7 +2903,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
 		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d58ed9b62e67..46f6469ad4d8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -963,7 +963,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 
 	/* JSL and EHL only supports eDP 1.3 */
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 97ac6fb37958..0b34518d051c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -226,7 +226,7 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
 	 * it, but since i915 takes the stance of always zeroing memory before
 	 * handing it to userspace, we need to prevent this.
 	 */
-	return IS_JSL_EHL(i915);
+	return IS_JASPERLAKE_EHL(i915);
 }
 
 static void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 1141f875f5bd..6945a0bc9778 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -302,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	u8 eu_en;
 	u8 s_en;
 
-	if (IS_JSL_EHL(gt->i915))
+	if (IS_JASPERLAKE_EHL(gt->i915))
 		intel_sseu_set_info(sseu, 1, 4, 8);
 	else
 		intel_sseu_set_info(sseu, 1, 8, 8);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bb948ffc95ca..2337bc52d9f1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1441,7 +1441,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
+	    IS_JASPERLAKE_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    GEN11_SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index feddd9d32dce..b6a720ac48bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
 #define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
-#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
 				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
 #define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
@@ -657,10 +657,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
-#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
-#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 8a9ff6227e53..3469d912e83e 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -219,7 +219,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
-	} else if (IS_JSL_EHL(i915)) {
+	} else if (IS_JASPERLAKE_EHL(i915)) {
 		revids = jsl_ehl_revids;
 		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index ba9843cb1b13..2e78b17843da 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_ICP;
 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* MCC is TGP compatible */
 		return PCH_TGP;
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
@@ -127,7 +127,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_TGP;
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* JSP is ICP compatible */
 		return PCH_ICP;
 	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
@@ -177,7 +177,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
 		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
 	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
-- 
2.34.1

[Intel-gfx] [PATCH 05/11] drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace TGL with
TIGERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 drivers/gpu/drm/i915/intel_step.c                  | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cd6915e9e138..ab84d003232c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (crtc_state->port_clock > 270000) {
-		if (IS_TGL_UY(dev_priv)) {
+		if (IS_TIGERLAKE_UY(dev_priv)) {
 			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
 						   n_entries);
 		} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..26def9cb86e4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 
 	/* Wa_14010477008 */
 	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
-	    IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+	    IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6a720ac48bf..865977d69f7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_WITH_PORT_F(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 #define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -662,7 +662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
 	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 3469d912e83e..847c7de50e1f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ROCKETLAKE(i915)) {
 		revids = rkl_revids;
 		size = ARRAY_SIZE(rkl_revids);
-	} else if (IS_TGL_UY(i915)) {
+	} else if (IS_TIGERLAKE_UY(i915)) {
 		revids = tgl_uy_revids;
 		size = ARRAY_SIZE(tgl_uy_revids);
 	} else if (IS_TIGERLAKE(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 06/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platform Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2acfa0435675..034454233d87 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		/* Wa_22011320316:adl-p[a0] */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6d376d414b8..47fe8311067e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 {
 	u32 val;
 
-	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+	if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 46f6469ad4d8..cf82cc295319 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	/* Wa_22012278275:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
 			1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	/* Wa_16011303918:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return;
 
 	/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 		return false;
 	}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
-	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	    IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 26def9cb86e4..636a88827a8f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 865977d69f7e..691ed3f0258b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-- 
2.34.1

[Intel-gfx] [PATCH 07/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_step.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 691ed3f0258b..819e72a39ba6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -589,7 +589,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 847c7de50e1f..9072f4ccd3c1 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ADLP_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
-	} else if (IS_ADLP_RPLP(i915)) {
+	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
 		revids = adlp_rplp_revids;
 		size = ARRAY_SIZE(adlp_rplp_revids);
 	} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 08/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 034454233d87..4318785b940f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3562,7 +3562,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
-		} else if (IS_ADLP_RPLU(dev_priv)) {
+		} else if (IS_ALDERLAKE_RPLU(dev_priv)) {
 			dev_priv->display.cdclk.table = rplu_cdclk_table;
 			dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
 		} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 819e72a39ba6..aa9689a1683f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -591,7 +591,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_ALDERLAKE_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
 				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-- 
2.34.1

[Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c        | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                 | 2 +-
 drivers/gpu/drm/i915/intel_step.c               | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-	if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
 		return true;
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
 		return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d408856ae4c0..dfb2837a3ed4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -279,7 +279,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 	 * ADL-S, otherwise the GuC might attempt to fetch a config table that
 	 * does not exist.
 	 */
-	if (IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P_N(i915))
 		p = INTEL_ALDERLAKE_S;
 
 	GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aa9689a1683f..6dee940e6913 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -587,7 +587,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 9072f4ccd3c1..fe447063a064 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_XEHPSDV(i915)) {
 		revids = xehpsdv_revids;
 		size = ARRAY_SIZE(xehpsdv_revids);
-	} else if (IS_ADLP_N(i915)) {
+	} else if (IS_ALDERLAKE_P_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
 	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platform Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c               | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                     | 6 +++---
 drivers/gpu/drm/i915/intel_step.c                   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 3fd30e7f0062..f3090b8afc60 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -797,7 +797,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 	enum pipe pipe;
 
 	/* Wa_14011765242: adl-s A0,A1 */
-	if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+	if (IS_ALDERLAKE_S_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
 		for_each_pipe(i915, pipe)
 			display_runtime->num_scalers[pipe] = 0;
 	else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..eb28705b88bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
 	}
 
 	/* Intermediate platforms are HuC authentication only */
-	if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+	if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) {
 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6dee940e6913..ef828e7de2ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -585,7 +585,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_ALDERLAKE_S_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index fe447063a064..f410aa2a8077 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_P(i915)) {
 		revids = adlp_revids;
 		size = ARRAY_SIZE(adlp_revids);
-	} else if (IS_ADLS_RPLS(i915)) {
+	} else if (IS_ALDERLAKE_S_RPLS(i915)) {
 		revids = adls_rpls_revids;
 		size = ARRAY_SIZE(adls_rpls_revids);
 	} else if (IS_ALDERLAKE_S(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               |  6 +--
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cf82cc295319..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 636a88827a8f..2458a9ea25ba 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3173e811463d..ec0771dc662a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..f9af6b1a7c01 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2ebd937f3b4c..901ecd59afbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_engine_wait_for_pending_mi_fw(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..1dc7180eeb27 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..cd9a76f048f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..cc8b09b8a7fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2337bc52d9f1..10a4e0fc23ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 
 	mtl_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..3af0fcd7dd57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
@@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(gt->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 		flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..5914c7348aba 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
 		intel_engine_stop_cs(engine);
@@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef828e7de2ec..c6ad78381dd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a111b281578..e943ffbaecbc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
 		struct intel_gt *gt;
 		int i;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
> Follow consistent naming convention. Replace MTL with
> METEORLAKE
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>   drivers/gpu/drm/i915/i915_drv.h               |  6 +--
>   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>   15 files changed, 51 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7f8b2d7713c7..6358a8b26172 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>   
>   	/* Wa_14016291713 */
>   	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>   	    crtc_state->has_psr) {
>   		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
>   		return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f7608d363634..8c3158b188ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>   				     &pmdemand_state->base,
>   				     &intel_pmdemand_funcs);
>   
> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>   		/* Wa_14016740474 */
>   		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cf82cc295319..00c98c2b4324 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
>   	bool set_wa_bit = false;
>   
>   	/* Wa_14015648006 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>   	    IS_DISPLAY_VER(dev_priv, 11, 13))
>   		set_wa_bit |= crtc_state->wm_level_disabled;
>   
> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>   		 * All supported adlp panels have 1-based X granularity, this may
>   		 * cause issues if non-supported panels are used.
>   		 */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>   			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>   				     ADLP_1_BASED_X_GRANULARITY);
>   		else if (IS_ALDERLAKE_P(dev_priv))
> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>   				     ADLP_1_BASED_X_GRANULARITY);
>   
>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>   			intel_de_rmw(dev_priv,
>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
>   				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>   
>   	if (intel_dp->psr.psr2_enabled) {
>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>   			intel_de_rmw(dev_priv,
>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>   				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
> @@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   		goto skip_sel_fetch_set_loop;
>   
>   	/* Wa_14014971492 */
> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>   	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>   	    crtc_state->splitter.enable)
>   		pipe_clip.y1 = 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 636a88827a8f..2458a9ea25ba 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>   				 enum pipe pipe, enum plane_id plane_id)
>   {
>   	/* Wa_14017240301 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

Reading this casually, the amount of the checks exactly like the above 
smells like we could easily add a "is mtl graphics step" helper which 
does not care about the subplatform variant and make the source and 
binary more compact. Might as well while churning the codebase.

Something like:

#define IS_ANY_MTL_GRAPHICS_STEP(__i915, since, until) \
	(IS_METEORLAKE(__i915) && \
	 IS_GRAPHICS_STEP(__i915, since, until))

?

MTL_ANY, ANY_MTL, or a 3rd option I don't know.

Regards,

Tvrtko

>   		return false;
>   
>   	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 3173e811463d..ec0771dc662a 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
>   static int mtl_dummy_pipe_control(struct i915_request *rq)
>   {
>   	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>   		u32 *cs;
>   
>   		/* dummy PIPE_CONTROL + depth flush */
> @@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>   		     PIPE_CONTROL_FLUSH_ENABLE);
>   
>   	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>   		/* dummy PIPE_CONTROL + depth flush */
>   		cs = gen12_emit_pipe_control(cs, 0,
>   					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0aff5bb13c53..f9af6b1a7c01 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
>   	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>   	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>   	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>   		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2ebd937f3b4c..901ecd59afbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
>   	 * Wa_22011802037: In addition to stopping the cs, we need
>   	 * to wait for any pending mi force wakeups
>   	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>   		intel_engine_wait_for_pending_mi_fw(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..1dc7180eeb27 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>   		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>   		/* Wa_14016747170 */
> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>   					     intel_uncore_read(gt->uncore,
>   							       MTL_GT_ACTIVITY_FACTOR));
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a4ec20aaafe2..cd9a76f048f3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>   					      cs, GEN12_GFX_CCS_AUX_NV);
>   
>   	/* Wa_16014892111 */
> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>   	    IS_DG2(ce->engine->i915))
>   		cs = dg2_emit_draw_watermark_setting(cs);
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 58bb1c55294c..cc8b09b8a7fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>   		return false;
>   	}
>   
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>   	    gt->type == GT_MEDIA) {
>   		drm_notice(&i915->drm,
>   			   "Media RC6 disabled on A step\n");
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2337bc52d9f1..10a4e0fc23ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>   
>   	dg2_ctx_gt_tuning_init(engine, wal);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>   }
>   
> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   
>   	mtl_ctx_gt_tuning_init(engine, wal);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>   		/* Wa_14014947963 */
>   		wa_masked_field_set(wal, VF_PREEMPTION,
>   				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   	/* Wa_22016670082 */
>   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>   
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>   		/* Wa_14014830051 */
>   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>   
> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>   		/* Wa_22014600077 */
>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>   		/* Wa_1509727124 */
> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   
>   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>   		/* Wa_22012856258 */
>   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>   				 GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>   		/* Wa_14017856879 */
>   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>   		/*
>   		 * Wa_14017066071
>   		 * Wa_14017654203
> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>   				 MTL_DISABLE_SAMPLER_SC_OOO);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>   		/* Wa_22015279794 */
>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>   				 DISABLE_PREFETCH_INTO_IC);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>   		/* Wa_22013037850 */
> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   				DISABLE_128B_EVICTION_COMMAND_UDW);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>   	    IS_PONTEVECCHIO(i915) ||
>   	    IS_DG2(i915)) {
>   		/* Wa_22014226127 */
>   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>   	    IS_DG2(i915)) {
>   		/* Wa_18017747507 */
>   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2eb891b270ae..3af0fcd7dd57 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>   		flags |= GUC_WA_GAM_CREDITS;
>   
>   	/* Wa_14014475959 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>   	    IS_DG2(gt->i915))
>   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>   
> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>   		flags |= GUC_WA_DUAL_QUEUE;
>   
>   	/* Wa_22011802037: graphics version 11/12 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>   	    (GRAPHICS_VER(gt->i915) >= 11 &&
>   	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>   		flags |= GUC_WA_PRE_PARSER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..5914c7348aba 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
>   	 * Wa_22011802037: In addition to stopping the cs, we need
>   	 * to wait for any pending mi force wakeups
>   	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>   	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>   		intel_engine_stop_cs(engine);
> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>   
>   	/* Wa_14014475959:dg2 */
>   	if (engine->class == COMPUTE_CLASS)
> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>   		    IS_DG2(engine->i915))
>   			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ef828e7de2ec..c6ad78381dd1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>   
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>   	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
>   	 IS_GRAPHICS_STEP(__i915, since, until))
>   
> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>   	(IS_METEORLAKE(__i915) && \
>   	 IS_DISPLAY_STEP(__i915, since, until))
>   
> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>   	(IS_METEORLAKE(__i915) && \
>   	 IS_MEDIA_STEP(__i915, since, until))
>   
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 0a111b281578..e943ffbaecbc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
>   	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
>   	 * does not work as expected.
>   	 */
> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>   	    props->engine->oa_group->type == TYPE_OAM &&
>   	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>   		drm_dbg(&perf->i915->drm,
> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
>   	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>   	 * to indicate that OA media is not supported.
>   	 */
> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>   		struct intel_gt *gt;
>   		int i;
>   

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 16/06/2023 13:05, Tvrtko Ursulin wrote:
> 
> On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
>> Follow consistent naming convention. Replace MTL with
>> METEORLAKE
>>
>> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>   drivers/gpu/drm/i915/i915_drv.h               |  6 +--
>>   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>   15 files changed, 51 insertions(+), 51 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index 7f8b2d7713c7..6358a8b26172 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
>> intel_atomic_state *state,
>>       /* Wa_14016291713 */
>>       if ((IS_DISPLAY_VER(i915, 12, 13) ||
>> -         IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>> +         IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>           crtc_state->has_psr) {
>>           plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
>>           return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> index f7608d363634..8c3158b188ef 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>>                        &pmdemand_state->base,
>>                        &intel_pmdemand_funcs);
>> -    if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>> +    if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>           /* Wa_14016740474 */
>>           intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
>> DMD_RSP_TIMEOUT_DISABLE);
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index cf82cc295319..00c98c2b4324 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp 
>> *intel_dp,
>>       bool set_wa_bit = false;
>>       /* Wa_14015648006 */
>> -    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>           IS_DISPLAY_VER(dev_priv, 11, 13))
>>           set_wa_bit |= crtc_state->wm_level_disabled;
>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct 
>> intel_dp *intel_dp,
>>            * All supported adlp panels have 1-based X granularity, 
>> this may
>>            * cause issues if non-supported panels are used.
>>            */
>> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>               intel_de_rmw(dev_priv, 
>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>                        ADLP_1_BASED_X_GRANULARITY);
>>           else if (IS_ALDERLAKE_P(dev_priv))
>> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct 
>> intel_dp *intel_dp,
>>                        ADLP_1_BASED_X_GRANULARITY);
>>           /* Wa_16012604467:adlp,mtl[a0,b0] */
>> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>               intel_de_rmw(dev_priv,
>>                        MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
>>                        MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct 
>> intel_dp *intel_dp)
>>       if (intel_dp->psr.psr2_enabled) {
>>           /* Wa_16012604467:adlp,mtl[a0,b0] */
>> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>               intel_de_rmw(dev_priv,
>>                        MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>                        MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
>> @@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct 
>> intel_atomic_state *state,
>>           goto skip_sel_fetch_set_loop;
>>       /* Wa_14014971492 */
>> -    if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +    if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>            IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>           crtc_state->splitter.enable)
>>           pipe_clip.y1 = 0;
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 636a88827a8f..2458a9ea25ba 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct 
>> drm_i915_private *i915,
>>                    enum pipe pipe, enum plane_id plane_id)
>>   {
>>       /* Wa_14017240301 */
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> 
> Reading this casually, the amount of the checks exactly like the above 
> smells like we could easily add a "is mtl graphics step" helper which 
> does not care about the subplatform variant and make the source and 
> binary more compact. Might as well while churning the codebase.
> 
> Something like:
> 
> #define IS_ANY_MTL_GRAPHICS_STEP(__i915, since, until) \
>      (IS_METEORLAKE(__i915) && \
>       IS_GRAPHICS_STEP(__i915, since, until))
> 
> ?
> 
> MTL_ANY, ANY_MTL, or a 3rd option I don't know.

Sorry forgot to say.. or make existing IS_MTL_GRAPHICS_STEP not care 
about the platform and introduce like IS_MTL_P/M_GRAPHICS_STEP. That 
would align more with IS_ADLS_GRAPHICS_STEP and IS_ADLP_DISPLAY_STEP even.

> 
> Regards,
> 
> Tvrtko
> 
>>           return false;
>>       /* Wa_22011186057 */
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 3173e811463d..ec0771dc662a 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, 
>> u32 *cs, const i915_reg_t inv
>>   static int mtl_dummy_pipe_control(struct i915_request *rq)
>>   {
>>       /* Wa_14016712196 */
>> -    if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, 
>> STEP_B0)) {
>>           u32 *cs;
>>           /* dummy PIPE_CONTROL + depth flush */
>> @@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct 
>> i915_request *rq, u32 *cs)
>>                PIPE_CONTROL_FLUSH_ENABLE);
>>       /* Wa_14016712196 */
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>           /* dummy PIPE_CONTROL + depth flush */
>>           cs = gen12_emit_pipe_control(cs, 0,
>>                            PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 0aff5bb13c53..f9af6b1a7c01 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct 
>> intel_engine_cs *engine,
>>        * Wa_22011802037: Prior to doing a reset, ensure CS is
>>        * stopped, set ring stop bit and prefetch disable bit to halt CS
>>        */
>> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>>           (GRAPHICS_VER(engine->i915) >= 11 &&
>>           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>           intel_uncore_write_fw(uncore, 
>> RING_MODE_GEN7(engine->mmio_base),
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 2ebd937f3b4c..901ecd59afbc 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct 
>> intel_engine_cs *engine)
>>        * Wa_22011802037: In addition to stopping the cs, we need
>>        * to wait for any pending mi force wakeups
>>        */
>> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>>           (GRAPHICS_VER(engine->i915) >= 11 &&
>>           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>           intel_engine_wait_for_pending_mi_fw(engine);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> index 0b414eae1683..1dc7180eeb27 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>           gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>>       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>           /* Wa_14016747170 */
>> -        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +        if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +            IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>               fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>                            intel_uncore_read(gt->uncore,
>>                                      MTL_GT_ACTIVITY_FACTOR));
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index a4ec20aaafe2..cd9a76f048f3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct 
>> intel_context *ce, u32 *cs)
>>                             cs, GEN12_GFX_CCS_AUX_NV);
>>       /* Wa_16014892111 */
>> -    if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, 
>> STEP_B0) ||
>>           IS_DG2(ce->engine->i915))
>>           cs = dg2_emit_draw_watermark_setting(cs);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> index 58bb1c55294c..cc8b09b8a7fa 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>           return false;
>>       }
>> -    if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>> +    if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>           gt->type == GT_MEDIA) {
>>           drm_notice(&i915->drm,
>>                  "Media RC6 disabled on A step\n");
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 2337bc52d9f1..10a4e0fc23ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct 
>> intel_engine_cs *engine,
>>       dg2_ctx_gt_tuning_init(engine, wal);
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>           wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>   }
>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct 
>> intel_engine_cs *engine,
>>       mtl_ctx_gt_tuning_init(engine, wal);
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>           /* Wa_14014947963 */
>>           wa_masked_field_set(wal, VF_PREEMPTION,
>>                       PREEMPTION_VERTEX_COUNT, 0x4000);
>> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, 
>> struct i915_wa_list *wal)
>>       /* Wa_22016670082 */
>>       wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>           /* Wa_14014830051 */
>>           wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs 
>> *engine, struct i915_wa_list *wal)
>>   {
>>       struct drm_i915_private *i915 = engine->i915;
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>           /* Wa_22014600077 */
>>           wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>                    ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>       }
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>           IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>           IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>           /* Wa_1509727124 */
>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs 
>> *engine, struct i915_wa_list *wal)
>>       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>           IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>           /* Wa_22012856258 */
>>           wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>                    GEN12_DISABLE_READ_SUPPRESSION);
>> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct 
>> intel_engine_cs *engine, struct i915_wa_li
>>                    GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>       }
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>           /* Wa_14017856879 */
>>           wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, 
>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>           /*
>>            * Wa_14017066071
>>            * Wa_14017654203
>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct 
>> intel_engine_cs *engine, struct i915_wa_li
>>           wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>                    MTL_DISABLE_SAMPLER_SC_OOO);
>> -    if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>           /* Wa_22015279794 */
>>           wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>                    DISABLE_PREFETCH_INTO_IC);
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>           IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>           IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>           /* Wa_22013037850 */
>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct 
>> intel_engine_cs *engine, struct i915_wa_li
>>                   DISABLE_128B_EVICTION_COMMAND_UDW);
>>       }
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>           IS_PONTEVECCHIO(i915) ||
>>           IS_DG2(i915)) {
>>           /* Wa_22014226127 */
>>           wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 
>> DISABLE_D8_D16_COASLESCE);
>>       }
>> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>           IS_DG2(i915)) {
>>           /* Wa_18017747507 */
>>           wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, 
>> POLYGON_TRIFAN_LINELOOP_DISABLE);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 2eb891b270ae..3af0fcd7dd57 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>           flags |= GUC_WA_GAM_CREDITS;
>>       /* Wa_14014475959 */
>> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>           IS_DG2(gt->i915))
>>           flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>           flags |= GUC_WA_DUAL_QUEUE;
>>       /* Wa_22011802037: graphics version 11/12 */
>> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>           (GRAPHICS_VER(gt->i915) >= 11 &&
>>           GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>           flags |= GUC_WA_PRE_PARSER;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index a0e3ef1c65d2..5914c7348aba 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct 
>> intel_engine_cs *engine)
>>        * Wa_22011802037: In addition to stopping the cs, we need
>>        * to wait for any pending mi force wakeups
>>        */
>> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>>           (GRAPHICS_VER(engine->i915) >= 11 &&
>>            GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>           intel_engine_stop_cs(engine);
>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct 
>> intel_engine_cs *engine)
>>       /* Wa_14014475959:dg2 */
>>       if (engine->class == COMPUTE_CLASS)
>> -        if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +        if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, 
>> STEP_B0) ||
>>               IS_DG2(engine->i915))
>>               engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index ef828e7de2ec..c6ad78381dd1 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>       (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>>       (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, 
>> INTEL_SUBPLATFORM_##variant) && \
>>        IS_GRAPHICS_STEP(__i915, since, until))
>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>       (IS_METEORLAKE(__i915) && \
>>        IS_DISPLAY_STEP(__i915, since, until))
>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>       (IS_METEORLAKE(__i915) && \
>>        IS_MEDIA_STEP(__i915, since, until))
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 0a111b281578..e943ffbaecbc 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct 
>> i915_perf *perf,
>>        * C6 disable in BIOS. Fail if Media C6 is enabled on steppings 
>> where OAM
>>        * does not work as expected.
>>        */
>> -    if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>> +    if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, 
>> STEP_C0) &&
>>           props->engine->oa_group->type == TYPE_OAM &&
>>           intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>           drm_dbg(&perf->i915->drm,
>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct 
>> drm_i915_private *i915)
>>        * C6 disable in BIOS. If Media C6 is enabled in BIOS, return 
>> version 6
>>        * to indicate that OA media is not supported.
>>        */
>> -    if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>> +    if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>           struct intel_gt *gt;
>>           int i;

Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

[Jani Nikula]

On Thu, 15 Jun 2023, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> wrote:
> Follow consistent naming convention. Replace JSL with
> JASPERLAKE.
>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

> -#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> +#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
>  				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))

The new name for this is just dumb. This matches two platforms, JSL and
EHL, and there's no point in one of them being an acronym and the other
one not.

And IS_JASPERLAKE_ELKHARTLAKE() would be too long.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Monday, June 19, 2023 1:46 AM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for
> platform/subplatform defines
> 
> On Thu, 15 Jun 2023, Dnyaneshwar Bhadane
> <dnyaneshwar.bhadane@intel.com> wrote:
> > Follow consistent naming convention. Replace JSL with JASPERLAKE.
> >
> > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> 
> > -#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> > +#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915,
> INTEL_JASPERLAKE) || \
> >  				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
> 
> The new name for this is just dumb. This matches two platforms, JSL and EHL,
> and there's no point in one of them being an acronym and the other one not.
> 
> And IS_JASPERLAKE_ELKHARTLAKE() would be too long.
> 
Agreed on the long name.
Given that we are not touching Elkhartlake in this series, we can probably skip jasperlake too?

Anusha
> BR,
> Jani.
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Jani Nikula]

On Thu, 15 Jun 2023, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> wrote:
> Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, 
> MTL with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, 
> KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform
> defines. This way there is a consistent pattern to how platforms 
> are referred. While the change is minor and could be combined to 
> have lesser patches, splitting to per subpaltform for easier 
> cherrypicks, if needed.

First of all, I'll note that changes like these need maintainer acks
before merging. Simple review for correctness is not enough!

While discussing this, there was perhaps a slight preference for moving
towards acronyms for brevity instead of expanding all of them to full
names. It can get a bit unwieldy.

For background, the reasons for having IS_<TLA>_DISPLAY_STEP() are
two-fold: the steppings used to be platform specific, so it made sense
to tie platform and stepping together, and IS_<LONG_NAME>_DISPLAY_STEP()
was considered too long combined.

Nowadays, we've abstracted steppings in code to be independent of
platforms, so we could use IS_<LONG_NAME>() && IS_DISPLAY_STEP(), and
throw out all the IS_<TLA>_DISPLAY_STEP() macros. They're orthogonal
things, and it actually bugs me to have so many platform specific
wrappers for the combos.

If in addition we moved to acronyms, we could have IS_<TLA>() &&
IS_DISPLAY_STEP(), and it would be pretty short and nice.

That said, all of these changes are a lot of churn, so I'd rather not
make them lightly.


BR,
Jani.




>
> v2:
>  - Fix the checkpatch warning.
>
> Anusha Srivatsa (5):
>   drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
>   drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
>   drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
>   drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
>   drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
>
> Dnyaneshwar Bhadane (6):
>   drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
>   drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
>   drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
>   drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
>   drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
>   drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
>
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
>  .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
>  .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
>  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
>  .../drm/i915/display/intel_display_device.c   |  2 +-
>  .../drm/i915/display/intel_display_power.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
>  .../drm/i915/display/skl_universal_plane.c    | 10 +--
>  drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
>  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
>  drivers/gpu/drm/i915/intel_step.c             | 10 +--
>  drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
>  34 files changed, 143 insertions(+), 143 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Tvrtko Ursulin]

On 20/06/2023 17:30, Jani Nikula wrote:
> On Thu, 15 Jun 2023, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> wrote:
>> Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE,
>> MTL with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE,
>> KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform
>> defines. This way there is a consistent pattern to how platforms
>> are referred. While the change is minor and could be combined to
>> have lesser patches, splitting to per subpaltform for easier
>> cherrypicks, if needed.
> 
> First of all, I'll note that changes like these need maintainer acks
> before merging. Simple review for correctness is not enough!
> 
> While discussing this, there was perhaps a slight preference for moving
> towards acronyms for brevity instead of expanding all of them to full
> names. It can get a bit unwieldy.
> 
> For background, the reasons for having IS_<TLA>_DISPLAY_STEP() are
> two-fold: the steppings used to be platform specific, so it made sense
> to tie platform and stepping together, and IS_<LONG_NAME>_DISPLAY_STEP()
> was considered too long combined.
> 
> Nowadays, we've abstracted steppings in code to be independent of
> platforms, so we could use IS_<LONG_NAME>() && IS_DISPLAY_STEP(), and
> throw out all the IS_<TLA>_DISPLAY_STEP() macros. They're orthogonal
> things, and it actually bugs me to have so many platform specific
> wrappers for the combos.
> 
> If in addition we moved to acronyms, we could have IS_<TLA>() &&
> IS_DISPLAY_STEP(), and it would be pretty short and nice.
> 
> That said, all of these changes are a lot of churn, so I'd rather not
> make them lightly.

I don't have a strong opinion on whether to churn or not. Or for the TLA vs LONG_NAME. As long as we do not mix the two. I think this translates to "If you do something, make it consistent, make it readable and make it tidy.". :)

Historically we were not avoiding churn if we could sense a real gain. In this case we could drop some combo macros, as Jani points out, gain some consistency, what else?

As minimum compact the numerous pointlessly expanded(*) MTL checks into a single platform check. But that is even orthogonal to the renames. Like:

	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))

Into possibly:

	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))

But that could also be:

	if (IS_MTL_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))

Regards,

Tvrtko

Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Jani Nikula]

On Wed, 21 Jun 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> Historically we were not avoiding churn if we could sense a real
> gain.

I tried but failed to say, if we're going to churn, let's at least go
through this properly instead of churning, and then churning again, and
again.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, June 20, 2023 9:31 AM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; Srivatsa,
> Anusha <anusha.srivatsa@intel.com>; Tvrtko Ursulin
> <tvrtko.ursulin@linux.intel.com>; Joonas Lahtinen
> <joonas.lahtinen@linux.intel.com>
> Subject: Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name
> in defines.
> 
> On Thu, 15 Jun 2023, Dnyaneshwar Bhadane
> <dnyaneshwar.bhadane@intel.com> wrote:
> > Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, MTL
> > with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, KBL with
> > KABYLAKE and SKL with SKYLAKE in platform and subplatform defines.
> > This way there is a consistent pattern to how platforms are referred.
> > While the change is minor and could be combined to have lesser
> > patches, splitting to per subpaltform for easier cherrypicks, if
> > needed.
> 
> First of all, I'll note that changes like these need maintainer acks before merging.
> Simple review for correctness is not enough!
> 
> While discussing this, there was perhaps a slight preference for moving towards
> acronyms for brevity instead of expanding all of them to full names. It can get a
> bit unwieldy.

Yes there was. The main reason being the acronym was more brief/compact. Having said that, thinking out loud it felt having platform defines have full name would make it more clear and readable?  For anyone new wanting to contribute, there will be less confusion.

> 
> For background, the reasons for having IS_<TLA>_DISPLAY_STEP() are
> two-fold: the steppings used to be platform specific, so it made sense to tie
> platform and stepping together, and IS_<LONG_NAME>_DISPLAY_STEP() was
> considered too long combined.
> 
> Nowadays, we've abstracted steppings in code to be independent of platforms,
> so we could use IS_<LONG_NAME>() && IS_DISPLAY_STEP(), and throw out all
> the IS_<TLA>_DISPLAY_STEP() macros. They're orthogonal things, and it actually
> bugs me to have so many platform specific wrappers for the combos.
> 
> If in addition we moved to acronyms, we could have IS_<TLA>() &&
> IS_DISPLAY_STEP(), and it would be pretty short and nice.
> 
> That said, all of these changes are a lot of churn, so I'd rather not make them
> lightly.
Agreed.

Anusha
> 
> BR,
> Jani.
> 
> 
> 
> 
> >
> > v2:
> >  - Fix the checkpatch warning.
> >
> > Anusha Srivatsa (5):
> >   drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
> >   drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
> >   drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
> >   drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
> >   drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
> >
> > Dnyaneshwar Bhadane (6):
> >   drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
> >   drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
> >   drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
> >   drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
> >   drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
> >   drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
> >
> >  drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
> >  drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
> >  .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
> >  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
> >  .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
> >  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
> >  .../drm/i915/display/intel_display_device.c   |  2 +-
> >  .../drm/i915/display/intel_display_power.c    |  2 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
> >  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >  drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
> >  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
> >  .../drm/i915/display/skl_universal_plane.c    | 10 +--
> >  drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
> >  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
> >  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
> >  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >  .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
> >  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
> >  drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
> >  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >  drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
> >  drivers/gpu/drm/i915/intel_step.c             | 10 +--
> >  drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
> >  34 files changed, 143 insertions(+), 143 deletions(-)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Matt Roper]

On Fri, Jun 16, 2023 at 01:05:08PM +0100, Tvrtko Ursulin wrote:
> 
> On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
> > Follow consistent naming convention. Replace MTL with
> > METEORLAKE
> > 
> > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
> >   .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >   drivers/gpu/drm/i915/i915_drv.h               |  6 +--
> >   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >   15 files changed, 51 insertions(+), 51 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 7f8b2d7713c7..6358a8b26172 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
> >   	/* Wa_14016291713 */
> >   	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> > -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> > +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >   	    crtc_state->has_psr) {
> >   		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
> >   		return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > index f7608d363634..8c3158b188ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
> >   				     &pmdemand_state->base,
> >   				     &intel_pmdemand_funcs);
> > -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >   		/* Wa_14016740474 */
> >   		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index cf82cc295319..00c98c2b4324 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
> >   	bool set_wa_bit = false;
> >   	/* Wa_14015648006 */
> > -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >   	    IS_DISPLAY_VER(dev_priv, 11, 13))
> >   		set_wa_bit |= crtc_state->wm_level_disabled;
> > @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >   		 * All supported adlp panels have 1-based X granularity, this may
> >   		 * cause issues if non-supported panels are used.
> >   		 */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >   			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >   				     ADLP_1_BASED_X_GRANULARITY);
> >   		else if (IS_ALDERLAKE_P(dev_priv))
> > @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >   				     ADLP_1_BASED_X_GRANULARITY);
> >   		/* Wa_16012604467:adlp,mtl[a0,b0] */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >   			intel_de_rmw(dev_priv,
> >   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> >   				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> > @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> >   	if (intel_dp->psr.psr2_enabled) {
> >   		/* Wa_16012604467:adlp,mtl[a0,b0] */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >   			intel_de_rmw(dev_priv,
> >   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >   				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
> > @@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >   		goto skip_sel_fetch_set_loop;
> >   	/* Wa_14014971492 */
> > -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >   	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> >   	    crtc_state->splitter.enable)
> >   		pipe_clip.y1 = 0;
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 636a88827a8f..2458a9ea25ba 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> >   				 enum pipe pipe, enum plane_id plane_id)
> >   {
> >   	/* Wa_14017240301 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> 
> Reading this casually, the amount of the checks exactly like the above
> smells like we could easily add a "is mtl graphics step" helper which does
> not care about the subplatform variant and make the source and binary more
> compact. Might as well while churning the codebase.
> 
> Something like:
> 
> #define IS_ANY_MTL_GRAPHICS_STEP(__i915, since, until) \
> 	(IS_METEORLAKE(__i915) && \
> 	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> ?
> 
> MTL_ANY, ANY_MTL, or a 3rd option I don't know.

I'm not sure I agree with this; the hardware design forked, meaning that
even though some workarounds will be common between both branches of the
hardware design, each branch is also expected to have its own unique
workarounds as well.  The steppings for the "common" workarounds may or
may not be the same between branches (it's mostly luck that they happen
to align for the A steppings of these two variants).  This is basically
the same situation as DG2's G10/G11/G12 variants, although for MTL is
seems the timing for the forks made it more common for the stepping
bounds to wind up being the same; there's no real expectation that that
will continue to hold true for future workarounds, or for future
variants of this IP that might show up in the future.

Actually what we really need to do is disassociate workaround like this
from the platform ("MTL") entirely and tie them solely to the IP's
version/stepping.  Given how graphics, media, and display IP have been
separated in a more fundamental manner at the hardware level, it's very
possible that some future platform could directly re-use one of the IP
versions we currently associate with "MTL," but provide different IP
versions for the other IP blocks.  Ultimately we want workarounds for
GMDID-based platforms something more along the lines of

   if (IS_GMDID_GRAPHICS_STEP(IP_VER(12, 71), STEP_B0, STEP_D0))
           ...

That way if a platform has graphics version 12.71 hardware in the listed
stepping range, then the workaround applies.  It doesn't matter whether
the platform containing that IP version is one of today's Meteor Lake
platforms, or some future "FooBar Lake" that happens to re-use the same
chiplet in an otherwise new design.

Of course changes to workaround bound handling is probably something for
a separate patch series; it's a bit beyond the scope of the direct
renaming that Dnyaneshwar's series is focused on.


Matt

> 
> Regards,
> 
> Tvrtko
> 
> >   		return false;
> >   	/* Wa_22011186057 */
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3173e811463d..ec0771dc662a 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> >   static int mtl_dummy_pipe_control(struct i915_request *rq)
> >   {
> >   	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> >   		u32 *cs;
> >   		/* dummy PIPE_CONTROL + depth flush */
> > @@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >   		     PIPE_CONTROL_FLUSH_ENABLE);
> >   	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >   		/* dummy PIPE_CONTROL + depth flush */
> >   		cs = gen12_emit_pipe_control(cs, 0,
> >   					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 0aff5bb13c53..f9af6b1a7c01 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> >   	 * Wa_22011802037: Prior to doing a reset, ensure CS is
> >   	 * stopped, set ring stop bit and prefetch disable bit to halt CS
> >   	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >   	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >   		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 2ebd937f3b4c..901ecd59afbc 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> >   	 * Wa_22011802037: In addition to stopping the cs, we need
> >   	 * to wait for any pending mi force wakeups
> >   	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >   	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >   		intel_engine_wait_for_pending_mi_fw(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 0b414eae1683..1dc7180eeb27 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >   		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> >   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >   		/* Wa_14016747170 */
> > -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >   					     intel_uncore_read(gt->uncore,
> >   							       MTL_GT_ACTIVITY_FACTOR));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index a4ec20aaafe2..cd9a76f048f3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> >   					      cs, GEN12_GFX_CCS_AUX_NV);
> >   	/* Wa_16014892111 */
> > -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> >   	    IS_DG2(ce->engine->i915))
> >   		cs = dg2_emit_draw_watermark_setting(cs);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > index 58bb1c55294c..cc8b09b8a7fa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> >   		return false;
> >   	}
> > -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> > +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >   	    gt->type == GT_MEDIA) {
> >   		drm_notice(&i915->drm,
> >   			   "Media RC6 disabled on A step\n");
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 2337bc52d9f1..10a4e0fc23ec 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> >   	dg2_ctx_gt_tuning_init(engine, wal);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> >   }
> > @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   	mtl_ctx_gt_tuning_init(engine, wal);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >   		/* Wa_14014947963 */
> >   		wa_masked_field_set(wal, VF_PREEMPTION,
> >   				    PREEMPTION_VERTEX_COUNT, 0x4000);
> > @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >   	/* Wa_22016670082 */
> >   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> >   		/* Wa_14014830051 */
> >   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> > @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >   		/* Wa_22014600077 */
> >   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >   		/* Wa_1509727124 */
> > @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> >   		/* Wa_22012856258 */
> >   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >   				 GEN12_DISABLE_READ_SUPPRESSION);
> > @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >   		/* Wa_14017856879 */
> >   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >   		/*
> >   		 * Wa_14017066071
> >   		 * Wa_14017654203
> > @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >   				 MTL_DISABLE_SAMPLER_SC_OOO);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >   		/* Wa_22015279794 */
> >   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >   				 DISABLE_PREFETCH_INTO_IC);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >   		/* Wa_22013037850 */
> > @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   				DISABLE_128B_EVICTION_COMMAND_UDW);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >   	    IS_PONTEVECCHIO(i915) ||
> >   	    IS_DG2(i915)) {
> >   		/* Wa_22014226127 */
> >   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >   	    IS_DG2(i915)) {
> >   		/* Wa_18017747507 */
> >   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 2eb891b270ae..3af0fcd7dd57 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >   		flags |= GUC_WA_GAM_CREDITS;
> >   	/* Wa_14014475959 */
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >   	    IS_DG2(gt->i915))
> >   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> > @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >   		flags |= GUC_WA_DUAL_QUEUE;
> >   	/* Wa_22011802037: graphics version 11/12 */
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >   	    (GRAPHICS_VER(gt->i915) >= 11 &&
> >   	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> >   		flags |= GUC_WA_PRE_PARSER;
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index a0e3ef1c65d2..5914c7348aba 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> >   	 * Wa_22011802037: In addition to stopping the cs, we need
> >   	 * to wait for any pending mi force wakeups
> >   	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >   	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >   	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> >   		intel_engine_stop_cs(engine);
> > @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> >   	/* Wa_14014475959:dg2 */
> >   	if (engine->class == COMPUTE_CLASS)
> > -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >   		    IS_DG2(engine->i915))
> >   			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index ef828e7de2ec..c6ad78381dd1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
> >   	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> >   	 IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> >   	(IS_METEORLAKE(__i915) && \
> >   	 IS_DISPLAY_STEP(__i915, since, until))
> > -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> >   	(IS_METEORLAKE(__i915) && \
> >   	 IS_MEDIA_STEP(__i915, since, until))
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index 0a111b281578..e943ffbaecbc 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
> >   	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
> >   	 * does not work as expected.
> >   	 */
> > -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> > +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> >   	    props->engine->oa_group->type == TYPE_OAM &&
> >   	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> >   		drm_dbg(&perf->i915->drm,
> > @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
> >   	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> >   	 * to indicate that OA media is not supported.
> >   	 */
> > -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> > +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >   		struct intel_gt *gt;
> >   		int i;

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 21/06/2023 22:11, Matt Roper wrote:
> On Fri, Jun 16, 2023 at 01:05:08PM +0100, Tvrtko Ursulin wrote:
>>
>> On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
>>> Follow consistent naming convention. Replace MTL with
>>> METEORLAKE
>>>
>>> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>>    drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>>    drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>>    .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>>    drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>>    drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>>    .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>>    drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>>    drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>>    drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>>>    drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>>    .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>>    drivers/gpu/drm/i915/i915_drv.h               |  6 +--
>>>    drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>>    15 files changed, 51 insertions(+), 51 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> index 7f8b2d7713c7..6358a8b26172 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>>>    	/* Wa_14016291713 */
>>>    	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>    	    crtc_state->has_psr) {
>>>    		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
>>>    		return 0;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> index f7608d363634..8c3158b188ef 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>>>    				     &pmdemand_state->base,
>>>    				     &intel_pmdemand_funcs);
>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>    		/* Wa_14016740474 */
>>>    		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index cf82cc295319..00c98c2b4324 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
>>>    	bool set_wa_bit = false;
>>>    	/* Wa_14015648006 */
>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>    	    IS_DISPLAY_VER(dev_priv, 11, 13))
>>>    		set_wa_bit |= crtc_state->wm_level_disabled;
>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>>>    		 * All supported adlp panels have 1-based X granularity, this may
>>>    		 * cause issues if non-supported panels are used.
>>>    		 */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>    			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>>    				     ADLP_1_BASED_X_GRANULARITY);
>>>    		else if (IS_ALDERLAKE_P(dev_priv))
>>> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>>>    				     ADLP_1_BASED_X_GRANULARITY);
>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>    			intel_de_rmw(dev_priv,
>>>    				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
>>>    				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>    	if (intel_dp->psr.psr2_enabled) {
>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>    			intel_de_rmw(dev_priv,
>>>    				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>    				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
>>> @@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>>    		goto skip_sel_fetch_set_loop;
>>>    	/* Wa_14014971492 */
>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>    	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>>    	    crtc_state->splitter.enable)
>>>    		pipe_clip.y1 = 0;
>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> index 636a88827a8f..2458a9ea25ba 100644
>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>>>    				 enum pipe pipe, enum plane_id plane_id)
>>>    {
>>>    	/* Wa_14017240301 */
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>
>> Reading this casually, the amount of the checks exactly like the above
>> smells like we could easily add a "is mtl graphics step" helper which does
>> not care about the subplatform variant and make the source and binary more
>> compact. Might as well while churning the codebase.
>>
>> Something like:
>>
>> #define IS_ANY_MTL_GRAPHICS_STEP(__i915, since, until) \
>> 	(IS_METEORLAKE(__i915) && \
>> 	 IS_GRAPHICS_STEP(__i915, since, until))
>>
>> ?
>>
>> MTL_ANY, ANY_MTL, or a 3rd option I don't know.
> 
> I'm not sure I agree with this; the hardware design forked, meaning that
> even though some workarounds will be common between both branches of the
> hardware design, each branch is also expected to have its own unique
> workarounds as well.  The steppings for the "common" workarounds may or
> may not be the same between branches (it's mostly luck that they happen
> to align for the A steppings of these two variants).  This is basically
> the same situation as DG2's G10/G11/G12 variants, although for MTL is
> seems the timing for the forks made it more common for the stepping
> bounds to wind up being the same; there's no real expectation that that
> will continue to hold true for future workarounds, or for future
> variants of this IP that might show up in the future.

Hmm quick grep shows that currently we have 15 call sites of 
IS_MTL_GRAPHICS_STEP which are 100% duplicated for M and P variants. And 
only 8 call sites which apply to one platform only. And a bunch of them 
have STEP_FOREVER as the end point. Which suggests the design was forked 
well into the design life and is not expected to diverge further, no?

So for MTL I am not sure what exactly would be the disadvantage of 
taking the pragmatic approach and consolidating?

It is not the most important thing in the grand scheme of things, I just 
found it unsightly...

> Actually what we really need to do is disassociate workaround like this
> from the platform ("MTL") entirely and tie them solely to the IP's
> version/stepping.  Given how graphics, media, and display IP have been
> separated in a more fundamental manner at the hardware level, it's very
> possible that some future platform could directly re-use one of the IP
> versions we currently associate with "MTL," but provide different IP
> versions for the other IP blocks.  Ultimately we want workarounds for
> GMDID-based platforms something more along the lines of
> 
>     if (IS_GMDID_GRAPHICS_STEP(IP_VER(12, 71), STEP_B0, STEP_D0))
>             ...

On i915 I'd say only if we expect significant number of new platforms to 
be added. Otherwise I'd see no benefit to the churn and it would most 
likely just add lines of source and inflate the binary size. Unless it 
could be shown it would make some strange conditionals much easier to 
understand.

Regards,

Tvrtko

> That way if a platform has graphics version 12.71 hardware in the listed
> stepping range, then the workaround applies.  It doesn't matter whether
> the platform containing that IP version is one of today's Meteor Lake
> platforms, or some future "FooBar Lake" that happens to re-use the same
> chiplet in an otherwise new design.
> 
> Of course changes to workaround bound handling is probably something for
> a separate patch series; it's a bit beyond the scope of the direct
> renaming that Dnyaneshwar's series is focused on.
> 
> 
> Matt
> 
>>
>> Regards,
>>
>> Tvrtko
>>
>>>    		return false;
>>>    	/* Wa_22011186057 */
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> index 3173e811463d..ec0771dc662a 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
>>>    static int mtl_dummy_pipe_control(struct i915_request *rq)
>>>    {
>>>    	/* Wa_14016712196 */
>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>>    		u32 *cs;
>>>    		/* dummy PIPE_CONTROL + depth flush */
>>> @@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>    		     PIPE_CONTROL_FLUSH_ENABLE);
>>>    	/* Wa_14016712196 */
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>    		/* dummy PIPE_CONTROL + depth flush */
>>>    		cs = gen12_emit_pipe_control(cs, 0,
>>>    					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> index 0aff5bb13c53..f9af6b1a7c01 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
>>>    	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>>>    	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>>>    	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>    		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index 2ebd937f3b4c..901ecd59afbc 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
>>>    	 * to wait for any pending mi force wakeups
>>>    	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>    		intel_engine_wait_for_pending_mi_fw(engine);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> index 0b414eae1683..1dc7180eeb27 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>    		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>>>    	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>    		/* Wa_14016747170 */
>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>    			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>    					     intel_uncore_read(gt->uncore,
>>>    							       MTL_GT_ACTIVITY_FACTOR));
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index a4ec20aaafe2..cd9a76f048f3 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>>>    					      cs, GEN12_GFX_CCS_AUX_NV);
>>>    	/* Wa_16014892111 */
>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>>    	    IS_DG2(ce->engine->i915))
>>>    		cs = dg2_emit_draw_watermark_setting(cs);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> index 58bb1c55294c..cc8b09b8a7fa 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>>    		return false;
>>>    	}
>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>    	    gt->type == GT_MEDIA) {
>>>    		drm_notice(&i915->drm,
>>>    			   "Media RC6 disabled on A step\n");
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 2337bc52d9f1..10a4e0fc23ec 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>>    	dg2_ctx_gt_tuning_init(engine, wal);
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>>    }
>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>    	mtl_ctx_gt_tuning_init(engine, wal);
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>    		/* Wa_14014947963 */
>>>    		wa_masked_field_set(wal, VF_PREEMPTION,
>>>    				    PREEMPTION_VERTEX_COUNT, 0x4000);
>>> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>>    	/* Wa_22016670082 */
>>>    	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>>    		/* Wa_14014830051 */
>>>    		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>    {
>>>    	struct drm_i915_private *i915 = engine->i915;
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>    		/* Wa_22014600077 */
>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>    				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>    	}
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>    		/* Wa_1509727124 */
>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>    	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>>    		/* Wa_22012856258 */
>>>    		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>    				 GEN12_DISABLE_READ_SUPPRESSION);
>>> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>    				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>    	}
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>    		/* Wa_14017856879 */
>>>    		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>    		/*
>>>    		 * Wa_14017066071
>>>    		 * Wa_14017654203
>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>    		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>    				 MTL_DISABLE_SAMPLER_SC_OOO);
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>    		/* Wa_22015279794 */
>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>    				 DISABLE_PREFETCH_INTO_IC);
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>    		/* Wa_22013037850 */
>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>    				DISABLE_128B_EVICTION_COMMAND_UDW);
>>>    	}
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>    	    IS_PONTEVECCHIO(i915) ||
>>>    	    IS_DG2(i915)) {
>>>    		/* Wa_22014226127 */
>>>    		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>>>    	}
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>    	    IS_DG2(i915)) {
>>>    		/* Wa_18017747507 */
>>>    		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> index 2eb891b270ae..3af0fcd7dd57 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>    		flags |= GUC_WA_GAM_CREDITS;
>>>    	/* Wa_14014475959 */
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>    	    IS_DG2(gt->i915))
>>>    		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>    		flags |= GUC_WA_DUAL_QUEUE;
>>>    	/* Wa_22011802037: graphics version 11/12 */
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>    	    (GRAPHICS_VER(gt->i915) >= 11 &&
>>>    	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>>    		flags |= GUC_WA_PRE_PARSER;
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index a0e3ef1c65d2..5914c7348aba 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
>>>    	 * to wait for any pending mi force wakeups
>>>    	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>    	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>>    		intel_engine_stop_cs(engine);
>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>>>    	/* Wa_14014475959:dg2 */
>>>    	if (engine->class == COMPUTE_CLASS)
>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>    		    IS_DG2(engine->i915))
>>>    			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index ef828e7de2ec..c6ad78381dd1 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>    #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>    	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>>>    	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
>>>    	 IS_GRAPHICS_STEP(__i915, since, until))
>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>>    	(IS_METEORLAKE(__i915) && \
>>>    	 IS_DISPLAY_STEP(__i915, since, until))
>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>>    	(IS_METEORLAKE(__i915) && \
>>>    	 IS_MEDIA_STEP(__i915, since, until))
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>>> index 0a111b281578..e943ffbaecbc 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
>>>    	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
>>>    	 * does not work as expected.
>>>    	 */
>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>>>    	    props->engine->oa_group->type == TYPE_OAM &&
>>>    	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>>    		drm_dbg(&perf->i915->drm,
>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
>>>    	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>>>    	 * to indicate that OA media is not supported.
>>>    	 */
>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>    		struct intel_gt *gt;
>>>    		int i;
> 

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Sent: Friday, June 16, 2023 5:37 PM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> 
> On 16/06/2023 13:05, Tvrtko Ursulin wrote:
> >
> > On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
> >> Follow consistent naming convention. Replace MTL with METEORLAKE
> >>
> >> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
> >>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
> >>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >>   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44
> >> +++++++++----------
> >>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >>   drivers/gpu/drm/i915/i915_drv.h               |  6 +--
> >>   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >>   15 files changed, 51 insertions(+), 51 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> >> b/drivers/gpu/drm/i915/display/intel_fbc.c
> >> index 7f8b2d7713c7..6358a8b26172 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> >> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> >> intel_atomic_state *state,
> >>       /* Wa_14016291713 */
> >>       if ((IS_DISPLAY_VER(i915, 12, 13) ||
> >> -         IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >> +         IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>           crtc_state->has_psr) {
> >>           plane_state->no_fbc_reason = "PSR1 enabled
> >> (Wa_14016291713)";
> >>           return 0;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> index f7608d363634..8c3158b188ef 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private
> >> *i915)
> >>                        &pmdemand_state->base,
> >>                        &intel_pmdemand_funcs);
> >> -    if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >> +    if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>           /* Wa_14016740474 */
> >>           intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> >> DMD_RSP_TIMEOUT_DISABLE); diff --git
> >> a/drivers/gpu/drm/i915/display/intel_psr.c
> >> b/drivers/gpu/drm/i915/display/intel_psr.c
> >> index cf82cc295319..00c98c2b4324 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> >> *intel_dp,
> >>       bool set_wa_bit = false;
> >>       /* Wa_14015648006 */
> >> -    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>           IS_DISPLAY_VER(dev_priv, 11, 13))
> >>           set_wa_bit |= crtc_state->wm_level_disabled; @@ -1320,7
> >> +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> >> *intel_dp,
> >>            * All supported adlp panels have 1-based X granularity,
> >> this may
> >>            * cause issues if non-supported panels are used.
> >>            */
> >> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>               intel_de_rmw(dev_priv,
> >> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >>                        ADLP_1_BASED_X_GRANULARITY);
> >>           else if (IS_ALDERLAKE_P(dev_priv)) @@ -1328,7 +1328,7 @@
> >> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >>                        ADLP_1_BASED_X_GRANULARITY);
> >>           /* Wa_16012604467:adlp,mtl[a0,b0] */
> >> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>               intel_de_rmw(dev_priv,
> >>                        MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> >>                        MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> >> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct
> >> intel_dp *intel_dp)
> >>       if (intel_dp->psr.psr2_enabled) {
> >>           /* Wa_16012604467:adlp,mtl[a0,b0] */
> >> -        if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> +        if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>               intel_de_rmw(dev_priv,
> >>                        MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >>                        MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@
> >> -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct
> >> intel_atomic_state *state,
> >>           goto skip_sel_fetch_set_loop;
> >>       /* Wa_14014971492 */
> >> -    if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >> +    if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>            IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> >>           crtc_state->splitter.enable)
> >>           pipe_clip.y1 = 0;
> >> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> index 636a88827a8f..2458a9ea25ba 100644
> >> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> >> drm_i915_private *i915,
> >>                    enum pipe pipe, enum plane_id plane_id)
> >>   {
> >>       /* Wa_14017240301 */
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >
> > Reading this casually, the amount of the checks exactly like the above
> > smells like we could easily add a "is mtl graphics step" helper which
> > does not care about the subplatform variant and make the source and
> > binary more compact. Might as well while churning the codebase.
> >
> > Something like:
> >
> > #define IS_ANY_MTL_GRAPHICS_STEP(__i915, since, until) \
> >      (IS_METEORLAKE(__i915) && \
> >       IS_GRAPHICS_STEP(__i915, since, until))
> >
> > ?
> >
> > MTL_ANY, ANY_MTL, or a 3rd option I don't know.
> 
> Sorry forgot to say.. or make existing IS_MTL_GRAPHICS_STEP not care about
> the platform and introduce like IS_MTL_P/M_GRAPHICS_STEP. That would align
> more with IS_ADLS_GRAPHICS_STEP and IS_ADLP_DISPLAY_STEP even.

Hi Tvrtko /Jani,

I am adding IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP
For that will replace all the occurrence IS_MTL_GRAPHICS_STEP. This way we don’t 
need to supply 'P' or 'M' explicitly. 

#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
	(IS_METEORLAKE_P(__i915) && \
	 IS_GRAPHICS_STEP(__i915, since, until))

#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
	(IS_METEORLAKE_M(__i915) && \
	 IS_GRAPHICS_STEP(__i915, since, until))

Apart from MTL for SKL/KBL/ RKL /TGL platform we can user IS_FULL_PLATFORM_PLATFORM() 
&& IS_GRAPHICS_STEP removing the wrapper for them IS_PLATOFORM_GRAPHICS_STEP.

For the MTL there are multiple occurrences of check like 
i.e.
if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

Replacing It with IS_FULL_PLATFORM_NAME () && IS_GRAPHICS_STEP format(Jani's suggestion) 
will become untidy for MTL.

Regards,
Dnyaneshwar 

> 
> >
> > Regards,
> >
> > Tvrtko
> >
> >>           return false;
> >>       /* Wa_22011186057 */
> >> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >> index 3173e811463d..ec0771dc662a 100644
> >> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
> >> *gt,
> >> u32 *cs, const i915_reg_t inv
> >>   static int mtl_dummy_pipe_control(struct i915_request *rq)
> >>   {
> >>       /* Wa_14016712196 */
> >> -    if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0)
> >> ||
> >> -        IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))
> >> {
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0,
> >> STEP_B0)) {
> >>           u32 *cs;
> >>           /* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8 @@
> >> u32 *gen12_emit_fini_breadcrumb_rcs(struct
> >> i915_request *rq, u32 *cs)
> >>                PIPE_CONTROL_FLUSH_ENABLE);
> >>       /* Wa_14016712196 */
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>           /* dummy PIPE_CONTROL + depth flush */
> >>           cs = gen12_emit_pipe_control(cs, 0,
> >>                            PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff
> >> --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> index 0aff5bb13c53..f9af6b1a7c01 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> >> intel_engine_cs *engine,
> >>        * Wa_22011802037: Prior to doing a reset, ensure CS is
> >>        * stopped, set ring stop bit and prefetch disable bit to halt
> >> CS
> >>        */
> >> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >>           (GRAPHICS_VER(engine->i915) >= 11 &&
> >>           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>           intel_uncore_write_fw(uncore,
> >> RING_MODE_GEN7(engine->mmio_base),
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >> index 2ebd937f3b4c..901ecd59afbc 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> >> intel_engine_cs *engine)
> >>        * Wa_22011802037: In addition to stopping the cs, we need
> >>        * to wait for any pending mi force wakeups
> >>        */
> >> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >>           (GRAPHICS_VER(engine->i915) >= 11 &&
> >>           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>           intel_engine_wait_for_pending_mi_fw(engine);
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >> index 0b414eae1683..1dc7180eeb27 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >>           gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> >>       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >>           /* Wa_14016747170 */
> >> -        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >> +        if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)
> >> +||
> >> +            IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>               fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >>                            intel_uncore_read(gt->uncore,
> >>                                      MTL_GT_ACTIVITY_FACTOR)); diff
> >> --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> index a4ec20aaafe2..cd9a76f048f3 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> >> intel_context *ce, u32 *cs)
> >>                             cs, GEN12_GFX_CCS_AUX_NV);
> >>       /* Wa_16014892111 */
> >> -    if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0)
> >> ||
> >> -        IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0)
> >> ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0,
> >> STEP_B0) ||
> >>           IS_DG2(ce->engine->i915))
> >>           cs = dg2_emit_draw_watermark_setting(cs);
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >> index 58bb1c55294c..cc8b09b8a7fa 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> >>           return false;
> >>       }
> >> -    if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >> +    if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >>           gt->type == GT_MEDIA) {
> >>           drm_notice(&i915->drm,
> >>                  "Media RC6 disabled on A step\n"); diff --git
> >> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> index 2337bc52d9f1..10a4e0fc23ec 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct
> >> intel_engine_cs *engine,
> >>       dg2_ctx_gt_tuning_init(engine, wal);
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER)
> >> +||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>           wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> >>   }
> >> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> >> intel_engine_cs *engine,
> >>       mtl_ctx_gt_tuning_init(engine, wal);
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>           /* Wa_14014947963 */
> >>           wa_masked_field_set(wal, VF_PREEMPTION,
> >>                       PREEMPTION_VERTEX_COUNT, 0x4000); @@ -1716,8
> >> +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> >> i915_wa_list *wal)
> >>       /* Wa_22016670082 */
> >>       wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> >> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0)
> >> +||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
> >> +{
> >>           /* Wa_14014830051 */
> >>           wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); @@
> >> -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs
> >> *engine, struct i915_wa_list *wal)
> >>   {
> >>       struct drm_i915_private *i915 = engine->i915;
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>           /* Wa_22014600077 */
> >>           wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>                    ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >>       }
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>           IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>           IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>           /* Wa_1509727124 */
> >> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> >> *engine, struct i915_wa_list *wal)
> >>       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>           IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> >>           /* Wa_22012856258 */
> >>           wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >>                    GEN12_DISABLE_READ_SUPPRESSION); @@ -3016,13
> >> +3016,13 @@ general_render_compute_wa_init(struct
> >> intel_engine_cs *engine, struct i915_wa_li
> >>                    GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >>       }
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER)
> >> +||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>           /* Wa_14017856879 */
> >>           wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> >> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>           /*
> >>            * Wa_14017066071
> >>            * Wa_14017654203
> >> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> >> intel_engine_cs *engine, struct i915_wa_li
> >>           wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >>                    MTL_DISABLE_SAMPLER_SC_OOO);
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>           /* Wa_22015279794 */
> >>           wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>                    DISABLE_PREFETCH_INTO_IC);
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>           IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>           IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>           /* Wa_22013037850 */
> >> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> >> intel_engine_cs *engine, struct i915_wa_li
> >>                   DISABLE_128B_EVICTION_COMMAND_UDW);
> >>       }
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>           IS_PONTEVECCHIO(i915) ||
> >>           IS_DG2(i915)) {
> >>           /* Wa_22014226127 */
> >>           wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> >> DISABLE_D8_D16_COASLESCE);
> >>       }
> >> -    if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> -        IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >> +        IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>           IS_DG2(i915)) {
> >>           /* Wa_18017747507 */
> >>           wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> >> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> >> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >> index 2eb891b270ae..3af0fcd7dd57 100644
> >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
> >> *guc)
> >>           flags |= GUC_WA_GAM_CREDITS;
> >>       /* Wa_14014475959 */
> >> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0)
> >> +||
> >>           IS_DG2(gt->i915))
> >>           flags |= GUC_WA_HOLD_CCS_SWITCHOUT; @@ -292,7 +292,7 @@
> >> static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >>           flags |= GUC_WA_DUAL_QUEUE;
> >>       /* Wa_22011802037: graphics version 11/12 */
> >> -    if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0)
> >> +||
> >>           (GRAPHICS_VER(gt->i915) >= 11 &&
> >>           GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> >>           flags |= GUC_WA_PRE_PARSER; diff --git
> >> a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >> index a0e3ef1c65d2..5914c7348aba 100644
> >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> >> intel_engine_cs *engine)
> >>        * Wa_22011802037: In addition to stopping the cs, we need
> >>        * to wait for any pending mi force wakeups
> >>        */
> >> -    if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >>           (GRAPHICS_VER(engine->i915) >= 11 &&
> >>            GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> >>           intel_engine_stop_cs(engine); @@ -4267,7 +4267,7 @@ static
> >> void guc_default_vfuncs(struct intel_engine_cs *engine)
> >>       /* Wa_14014475959:dg2 */
> >>       if (engine->class == COMPUTE_CLASS)
> >> -        if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0)
> >> ||
> >> +        if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >> STEP_B0) ||
> >>               IS_DG2(engine->i915))
> >>               engine->flags |=
> >> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h index ef828e7de2ec..c6ad78381dd1
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private
> >> *i915,
> >>   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >>       (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> >> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
> >>       (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> >> INTEL_SUBPLATFORM_##variant) && \
> >>        IS_GRAPHICS_STEP(__i915, since, until)) -#define
> >> IS_MTL_DISPLAY_STEP(__i915, since, until) \
> >> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> >>       (IS_METEORLAKE(__i915) && \
> >>        IS_DISPLAY_STEP(__i915, since, until)) -#define
> >> IS_MTL_MEDIA_STEP(__i915, since, until) \
> >> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> >>       (IS_METEORLAKE(__i915) && \
> >>        IS_MEDIA_STEP(__i915, since, until)) diff --git
> >> a/drivers/gpu/drm/i915/i915_perf.c
> >> b/drivers/gpu/drm/i915/i915_perf.c
> >> index 0a111b281578..e943ffbaecbc 100644
> >> --- a/drivers/gpu/drm/i915/i915_perf.c
> >> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct
> >> i915_perf *perf,
> >>        * C6 disable in BIOS. Fail if Media C6 is enabled on steppings
> >> where OAM
> >>        * does not work as expected.
> >>        */
> >> -    if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> >> +    if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> >> STEP_C0) &&
> >>           props->engine->oa_group->type == TYPE_OAM &&
> >>           intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> >>           drm_dbg(&perf->i915->drm,
> >> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct
> >> drm_i915_private *i915)
> >>        * C6 disable in BIOS. If Media C6 is enabled in BIOS, return
> >> version 6
> >>        * to indicate that OA media is not supported.
> >>        */
> >> -    if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >> +    if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >>           struct intel_gt *gt;
> >>           int i;

[Intel-gfx] [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace MTL with
METEORLAKE. Added defines that are replacing IS_MTL_GRAPHICS_STEP with
IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.

v2:
- Replace IS_MLT_GRAPHICS_STEP with IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
- Changed subject prefix mtl with MTL (Anusha)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 15 files changed, 60 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 62151abe4748..ecd4e36119b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 636a88827a8f..cf1bcc6bff08 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3173e811463d..26656d4be61e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0, STEP_B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..df4883764ad4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2ebd937f3b4c..802b31ad982e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_engine_wait_for_pending_mi_fw(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..e30b56be0cb8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..80608090fb1e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..cc8b09b8a7fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bb948ffc95ca..f840376f107f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 
 	mtl_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..c8e2a110b833 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
@@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(gt->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 		flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..6f0e07c4488e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
 		intel_engine_stop_cs(engine);
@@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index deb5b9064621..8b4cc3f4df1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
+#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
+	(IS_METEORLAKE_P(__i915) && \
+	 IS_GRAPHICS_STEP(__i915, since, until))
+
+#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
+	(IS_METEORLAKE_M(__i915) && \
+	 IS_GRAPHICS_STEP(__i915, since, until))
+
+
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a111b281578..e943ffbaecbc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
 		struct intel_gt *gt;
 		int i;
 
-- 
2.34.1

Re: [Intel-gfx] [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Friday, June 30, 2023 4:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; jani.nikula@linux.intel.com;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
> defines
> 
> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
> defines that are replacing IS_MTL_GRAPHICS_STEP with
> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.

The patch also changes MTL_MEDIA macros. That should be mentioned in the commit message.

> v2:
> - Replace IS_MLT_GRAPHICS_STEP with
	Typo ^ s/MLT/MTL
> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> - Changed subject prefix mtl with MTL (Anusha)
	Rewording:"mtl instead of MTL" or "use lower case instead of upper case"


Anusha
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>  .../drm/i915/display/skl_universal_plane.c    |  4 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>  15 files changed, 60 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7f8b2d7713c7..6358a8b26172 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> 
>  	/* Wa_14016291713 */
>  	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>  	    crtc_state->has_psr) {
>  		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
>  		return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f7608d363634..8c3158b188ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>  				     &pmdemand_state->base,
>  				     &intel_pmdemand_funcs);
> 
> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>  		/* Wa_14016740474 */
>  		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 62151abe4748..ecd4e36119b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> *intel_dp,
>  	bool set_wa_bit = false;
> 
>  	/* Wa_14015648006 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	    IS_DISPLAY_VER(dev_priv, 11, 13))
>  		set_wa_bit |= crtc_state->wm_level_disabled;
> 
> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  		 * All supported adlp panels have 1-based X granularity, this may
>  		 * cause issues if non-supported panels are used.
>  		 */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>  				     ADLP_1_BASED_X_GRANULARITY);
>  		else if (IS_ALDERLAKE_P(dev_priv))
> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  				     ADLP_1_BASED_X_GRANULARITY);
> 
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 0,
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> 
>  	if (intel_dp->psr.psr2_enabled) {
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		goto skip_sel_fetch_set_loop;
> 
>  	/* Wa_14014971492 */
> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>  	    crtc_state->splitter.enable)
>  		pipe_clip.y1 = 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 636a88827a8f..cf1bcc6bff08 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
>  				 enum pipe pipe, enum plane_id plane_id)  {
>  	/* Wa_14017240301 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 3173e811463d..26656d4be61e 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
> i915_request *rq)  {
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> STEP_B0))
> +{
>  		u32 *cs;
> 
>  		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>  		     PIPE_CONTROL_FLUSH_ENABLE);
> 
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/* dummy PIPE_CONTROL + depth flush */
>  		cs = gen12_emit_pipe_control(cs, 0,
> 
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0aff5bb13c53..df4883764ad4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> intel_engine_cs *engine,
>  	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>  	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >mmio_base),
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2ebd937f3b4c..802b31ad982e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_engine_wait_for_pending_mi_fw(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..e30b56be0cb8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>  		gt->steering_table[OADDRM] =
> xelpmp_oaddrm_steering_table;
>  	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>  		/* Wa_14016747170 */
> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
> STEP_B0) ||
> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
> STEP_B0))
>  			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>  					     intel_uncore_read(gt->uncore,
> 
> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a4ec20aaafe2..80608090fb1e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> intel_context *ce, u32 *cs)
>  					      cs, GEN12_GFX_CCS_AUX_NV);
> 
>  	/* Wa_16014892111 */
> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> STEP_B0)
> +||
>  	    IS_DG2(ce->engine->i915))
>  		cs = dg2_emit_draw_watermark_setting(cs);
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 58bb1c55294c..cc8b09b8a7fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>  		return false;
>  	}
> 
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>  	    gt->type == GT_MEDIA) {
>  		drm_notice(&i915->drm,
>  			   "Media RC6 disabled on A step\n"); diff --git
> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index bb948ffc95ca..f840376f107f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
> *engine,
> 
>  	dg2_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>  		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
> false);  }
> 
> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> 
>  	mtl_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_14014947963 */
>  		wa_masked_field_set(wal, VF_PREEMPTION,
>  				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  	/* Wa_22016670082 */
>  	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> 
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
>  		/* Wa_14014830051 */
>  		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> 
> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)  {
>  	struct drm_i915_private *i915 = engine->i915;
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_22014600077 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_1509727124 */
> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> 
>  	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_22012856258 */
>  		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>  				 GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
> 
> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>  		/* Wa_14017856879 */
>  		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/*
>  		 * Wa_14017066071
>  		 * Wa_14017654203
> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>  				 MTL_DISABLE_SAMPLER_SC_OOO);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/* Wa_22015279794 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 DISABLE_PREFETCH_INTO_IC);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_22013037850 */
> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  				DISABLE_128B_EVICTION_COMMAND_UDW);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_PONTEVECCHIO(i915) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_22014226127 */
>  		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> DISABLE_D8_D16_COASLESCE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_18017747507 */
>  		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2eb891b270ae..c8e2a110b833 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_GAM_CREDITS;
> 
>  	/* Wa_14014475959 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2(gt->i915))
>  		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> 
> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_DUAL_QUEUE;
> 
>  	/* Wa_22011802037: graphics version 11/12 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>  	    (GRAPHICS_VER(gt->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>  		flags |= GUC_WA_PRE_PARSER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..6f0e07c4488e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>  		intel_engine_stop_cs(engine);
> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
> *engine)
> 
>  	/* Wa_14014475959:dg2 */
>  	if (engine->class == COMPUTE_CLASS)
> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
> STEP_A0, STEP_B0) ||
>  		    IS_DG2(engine->i915))
>  			engine->flags |=
> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index deb5b9064621..8b4cc3f4df1f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>  	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_##variant) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> +	(IS_METEORLAKE_P(__i915) && \
> +	 IS_GRAPHICS_STEP(__i915, since, until))
> +
> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
> +	(IS_METEORLAKE_M(__i915) && \
> +	 IS_GRAPHICS_STEP(__i915, since, until))
> +
> +
> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_MEDIA_STEP(__i915, since, until))
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 0a111b281578..e943ffbaecbc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
> *perf,
>  	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
> OAM
>  	 * does not work as expected.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> STEP_C0) &&
>  	    props->engine->oa_group->type == TYPE_OAM &&
>  	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>  		drm_dbg(&perf->i915->drm,
> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
> *i915)
>  	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>  	 * to indicate that OA media is not supported.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>  		struct intel_gt *gt;
>  		int i;
> 
> --
> 2.34.1

[Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace MTL with
METEORLAKE. Added defines that are replacing IS_MTL_GRAPHICS_STEP with
IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP and
IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.

v2:
- Replace IS_MTL_GRAPHICS_STEP with IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
- Changed subject prefix mtl instead of MTL (Anusha)
v3:
- Updated the commit message. (Anusha)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 15 files changed, 60 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 62151abe4748..ecd4e36119b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 636a88827a8f..cf1bcc6bff08 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3173e811463d..26656d4be61e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0, STEP_B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..df4883764ad4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2ebd937f3b4c..802b31ad982e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_engine_wait_for_pending_mi_fw(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..e30b56be0cb8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..80608090fb1e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..cc8b09b8a7fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bb948ffc95ca..f840376f107f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 
 	mtl_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..c8e2a110b833 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
@@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(gt->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 		flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..6f0e07c4488e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
 		intel_engine_stop_cs(engine);
@@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index deb5b9064621..8b4cc3f4df1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
+#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
+	(IS_METEORLAKE_P(__i915) && \
+	 IS_GRAPHICS_STEP(__i915, since, until))
+
+#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
+	(IS_METEORLAKE_M(__i915) && \
+	 IS_GRAPHICS_STEP(__i915, since, until))
+
+
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a111b281578..e943ffbaecbc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
 		struct intel_gt *gt;
 		int i;
 
-- 
2.34.1

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Monday, July 10, 2023 4:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; jani.nikula@linux.intel.com;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
> defines
> 
> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
> defines that are replacing IS_MTL_GRAPHICS_STEP with
> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
> Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP
> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
> 
Hi Tvrtko,
Could you please give the feedback on this ? or suggestion regarding the approach.

> v2:
> - Replace IS_MTL_GRAPHICS_STEP with
> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> - Changed subject prefix mtl instead of MTL (Anusha)
> v3:
> - Updated the commit message. (Anusha)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>  .../drm/i915/display/skl_universal_plane.c    |  4 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>  15 files changed, 60 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7f8b2d7713c7..6358a8b26172 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> 
>  	/* Wa_14016291713 */
>  	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>  	    crtc_state->has_psr) {
>  		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
>  		return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f7608d363634..8c3158b188ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>  				     &pmdemand_state->base,
>  				     &intel_pmdemand_funcs);
> 
> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>  		/* Wa_14016740474 */
>  		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 62151abe4748..ecd4e36119b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> *intel_dp,
>  	bool set_wa_bit = false;
> 
>  	/* Wa_14015648006 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	    IS_DISPLAY_VER(dev_priv, 11, 13))
>  		set_wa_bit |= crtc_state->wm_level_disabled;
> 
> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  		 * All supported adlp panels have 1-based X granularity, this may
>  		 * cause issues if non-supported panels are used.
>  		 */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>  				     ADLP_1_BASED_X_GRANULARITY);
>  		else if (IS_ALDERLAKE_P(dev_priv))
> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  				     ADLP_1_BASED_X_GRANULARITY);
> 
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 0,
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> 
>  	if (intel_dp->psr.psr2_enabled) {
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		goto skip_sel_fetch_set_loop;
> 
>  	/* Wa_14014971492 */
> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>  	    crtc_state->splitter.enable)
>  		pipe_clip.y1 = 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 636a88827a8f..cf1bcc6bff08 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
>  				 enum pipe pipe, enum plane_id plane_id)  {
>  	/* Wa_14017240301 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 3173e811463d..26656d4be61e 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
> i915_request *rq)  {
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> STEP_B0))
> +{
>  		u32 *cs;
> 
>  		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>  		     PIPE_CONTROL_FLUSH_ENABLE);
> 
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/* dummy PIPE_CONTROL + depth flush */
>  		cs = gen12_emit_pipe_control(cs, 0,
> 
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0aff5bb13c53..df4883764ad4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> intel_engine_cs *engine,
>  	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>  	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >mmio_base),
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2ebd937f3b4c..802b31ad982e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_engine_wait_for_pending_mi_fw(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..e30b56be0cb8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>  		gt->steering_table[OADDRM] =
> xelpmp_oaddrm_steering_table;
>  	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>  		/* Wa_14016747170 */
> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
> STEP_B0) ||
> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
> STEP_B0))
>  			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>  					     intel_uncore_read(gt->uncore,
> 
> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a4ec20aaafe2..80608090fb1e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> intel_context *ce, u32 *cs)
>  					      cs, GEN12_GFX_CCS_AUX_NV);
> 
>  	/* Wa_16014892111 */
> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> STEP_B0)
> +||
>  	    IS_DG2(ce->engine->i915))
>  		cs = dg2_emit_draw_watermark_setting(cs);
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 58bb1c55294c..cc8b09b8a7fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>  		return false;
>  	}
> 
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>  	    gt->type == GT_MEDIA) {
>  		drm_notice(&i915->drm,
>  			   "Media RC6 disabled on A step\n"); diff --git
> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index bb948ffc95ca..f840376f107f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
> *engine,
> 
>  	dg2_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>  		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
> false);  }
> 
> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> 
>  	mtl_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_14014947963 */
>  		wa_masked_field_set(wal, VF_PREEMPTION,
>  				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  	/* Wa_22016670082 */
>  	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> 
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
>  		/* Wa_14014830051 */
>  		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> 
> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)  {
>  	struct drm_i915_private *i915 = engine->i915;
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_22014600077 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_1509727124 */
> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> 
>  	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>  		/* Wa_22012856258 */
>  		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>  				 GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
> 
> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>  		/* Wa_14017856879 */
>  		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/*
>  		 * Wa_14017066071
>  		 * Wa_14017654203
> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>  				 MTL_DISABLE_SAMPLER_SC_OOO);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		/* Wa_22015279794 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 DISABLE_PREFETCH_INTO_IC);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_22013037850 */
> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  				DISABLE_128B_EVICTION_COMMAND_UDW);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_PONTEVECCHIO(i915) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_22014226127 */
>  		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> DISABLE_D8_D16_COASLESCE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_18017747507 */
>  		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2eb891b270ae..c8e2a110b833 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_GAM_CREDITS;
> 
>  	/* Wa_14014475959 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>  	    IS_DG2(gt->i915))
>  		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> 
> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_DUAL_QUEUE;
> 
>  	/* Wa_22011802037: graphics version 11/12 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>  	    (GRAPHICS_VER(gt->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>  		flags |= GUC_WA_PRE_PARSER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..6f0e07c4488e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>  		intel_engine_stop_cs(engine);
> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
> *engine)
> 
>  	/* Wa_14014475959:dg2 */
>  	if (engine->class == COMPUTE_CLASS)
> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
> STEP_A0, STEP_B0) ||
>  		    IS_DG2(engine->i915))
>  			engine->flags |=
> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index deb5b9064621..8b4cc3f4df1f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>  	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_##variant) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> +	(IS_METEORLAKE_P(__i915) && \
> +	 IS_GRAPHICS_STEP(__i915, since, until))
> +
> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
> +	(IS_METEORLAKE_M(__i915) && \
> +	 IS_GRAPHICS_STEP(__i915, since, until))
> +
> +
> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_MEDIA_STEP(__i915, since, until))
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 0a111b281578..e943ffbaecbc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
> *perf,
>  	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
> OAM
>  	 * does not work as expected.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> STEP_C0) &&
>  	    props->engine->oa_group->type == TYPE_OAM &&
>  	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>  		drm_dbg(&perf->i915->drm,
> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
> *i915)
>  	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>  	 * to indicate that OA media is not supported.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>  		struct intel_gt *gt;
>  		int i;
> 
> --
> 2.34.1

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines. (rev3)

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines. (rev3)
URL   : https://patchwork.freedesktop.org/series/119380/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/119380/revisions/3/mbox/ not applied
Applying: drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines
Applying: drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_fbc.c
M	drivers/gpu/drm/i915/display/intel_pmdemand.c
M	drivers/gpu/drm/i915/display/intel_psr.c
M	drivers/gpu/drm/i915/display/skl_universal_plane.c
M	drivers/gpu/drm/i915/gt/gen8_engine_cs.c
M	drivers/gpu/drm/i915/gt/intel_engine_cs.c
M	drivers/gpu/drm/i915/gt/intel_execlists_submission.c
M	drivers/gpu/drm/i915/gt/intel_gt_mcr.c
M	drivers/gpu/drm/i915/gt/intel_lrc.c
M	drivers/gpu/drm/i915/gt/intel_rc6.c
M	drivers/gpu/drm/i915/gt/intel_workarounds.c
M	drivers/gpu/drm/i915/gt/uc/intel_guc.c
M	drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_perf.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_perf.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/uc/intel_guc.c
Auto-merging drivers/gpu/drm/i915/gt/intel_workarounds.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_workarounds.c
Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_lrc.c
Auto-merging drivers/gpu/drm/i915/gt/intel_gt_mcr.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_gt_mcr.c
Auto-merging drivers/gpu/drm/i915/gt/intel_execlists_submission.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Auto-merging drivers/gpu/drm/i915/gt/intel_engine_cs.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_engine_cs.c
Auto-merging drivers/gpu/drm/i915/gt/gen8_engine_cs.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/gen8_engine_cs.c
Auto-merging drivers/gpu/drm/i915/display/skl_universal_plane.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/skl_universal_plane.c
Auto-merging drivers/gpu/drm/i915/display/intel_psr.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Srivatsa, Anusha]

I Like the acronym replacement approach - despite making the macro names longer, it is consistent with how platform is referred everywhere in the driver.

For that,

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Monday, July 10, 2023 6:44 AM
> To: intel-gfx@lists.freedesktop.org; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> Cc: jani.nikula@linux.intel.com; Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Subject: RE: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
> defines
> 
> 
> 
> > -----Original Message-----
> > From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> > Sent: Monday, July 10, 2023 4:28 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> > jani.nikula@linux.intel.com; Srivatsa, Anusha
> > <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> > <dnyaneshwar.bhadane@intel.com>
> > Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
> > defines
> >
> > Follow consistent naming convention. Replace MTL with METEORLAKE.
> > Added defines that are replacing IS_MTL_GRAPHICS_STEP with
> > IS_METEORLAKE_P_GRAPHICS_STEP and
> IS_METEORLAKE_M_GRAPHICS_STEP.
> > Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP
> > and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
> >
> Hi Tvrtko,
> Could you please give the feedback on this ? or suggestion regarding the
> approach.
> 
> > v2:
> > - Replace IS_MTL_GRAPHICS_STEP with
> > IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> > - Changed subject prefix mtl instead of MTL (Anusha)
> > v3:
> > - Updated the commit message. (Anusha)
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
> > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
> >  .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
> >  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
> >  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >  drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
> >  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >  15 files changed, 60 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 7f8b2d7713c7..6358a8b26172 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> > intel_atomic_state *state,
> >
> >  	/* Wa_14016291713 */
> >  	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> > -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> > +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >  	    crtc_state->has_psr) {
> >  		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> >  		return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > index f7608d363634..8c3158b188ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
> >  				     &pmdemand_state->base,
> >  				     &intel_pmdemand_funcs);
> >
> > -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >  		/* Wa_14016740474 */
> >  		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> > DMD_RSP_TIMEOUT_DISABLE);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 62151abe4748..ecd4e36119b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> > *intel_dp,
> >  	bool set_wa_bit = false;
> >
> >  	/* Wa_14015648006 */
> > -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >  	    IS_DISPLAY_VER(dev_priv, 11, 13))
> >  		set_wa_bit |= crtc_state->wm_level_disabled;
> >
> > @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  		 * All supported adlp panels have 1-based X granularity, this may
> >  		 * cause issues if non-supported panels are used.
> >  		 */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> > STEP_B0))
> >  			intel_de_rmw(dev_priv,
> > MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >  				     ADLP_1_BASED_X_GRANULARITY);
> >  		else if (IS_ALDERLAKE_P(dev_priv))
> > @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  				     ADLP_1_BASED_X_GRANULARITY);
> >
> >  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> > STEP_B0))
> >  			intel_de_rmw(dev_priv,
> >  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> > 0,
> >
> > MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> > @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct
> > intel_dp
> > *intel_dp)
> >
> >  	if (intel_dp->psr.psr2_enabled) {
> >  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> > -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> > STEP_B0))
> >  			intel_de_rmw(dev_priv,
> >  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >
> > MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7
> @@ int
> > intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >  		goto skip_sel_fetch_set_loop;
> >
> >  	/* Wa_14014971492 */
> > -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >  	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> >  	    crtc_state->splitter.enable)
> >  		pipe_clip.y1 = 0;
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 636a88827a8f..cf1bcc6bff08 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> > drm_i915_private *i915,
> >  				 enum pipe pipe, enum plane_id plane_id)  {
> >  	/* Wa_14017240301 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >  		return false;
> >
> >  	/* Wa_22011186057 */
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3173e811463d..26656d4be61e 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt,
> > u32 *cs, const i915_reg_t inv  static int
> > mtl_dummy_pipe_control(struct i915_request *rq)  {
> >  	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> > STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> > STEP_B0))
> > +{
> >  		u32 *cs;
> >
> >  		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32
> > *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >  		     PIPE_CONTROL_FLUSH_ENABLE);
> >
> >  	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >  		/* dummy PIPE_CONTROL + depth flush */
> >  		cs = gen12_emit_pipe_control(cs, 0,
> >
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> > a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 0aff5bb13c53..df4883764ad4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> > intel_engine_cs *engine,
> >  	 * Wa_22011802037: Prior to doing a reset, ensure CS is
> >  	 * stopped, set ring stop bit and prefetch disable bit to halt CS
> >  	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> > STEP_B0) ||
> >  	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >  		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> > >mmio_base),
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 2ebd937f3b4c..802b31ad982e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> > intel_engine_cs *engine)
> >  	 * Wa_22011802037: In addition to stopping the cs, we need
> >  	 * to wait for any pending mi force wakeups
> >  	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> > STEP_B0) ||
> >  	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >  		intel_engine_wait_for_pending_mi_fw(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 0b414eae1683..e30b56be0cb8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >  		gt->steering_table[OADDRM] =
> > xelpmp_oaddrm_steering_table;
> >  	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >  		/* Wa_14016747170 */
> > -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
> > STEP_B0) ||
> > +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
> > STEP_B0))
> >  			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >  					     intel_uncore_read(gt->uncore,
> >
> > MTL_GT_ACTIVITY_FACTOR)); diff --git
> > a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index a4ec20aaafe2..80608090fb1e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> > intel_context *ce, u32 *cs)
> >  					      cs, GEN12_GFX_CCS_AUX_NV);
> >
> >  	/* Wa_16014892111 */
> > -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> > STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> > STEP_B0)
> > +||
> >  	    IS_DG2(ce->engine->i915))
> >  		cs = dg2_emit_draw_watermark_setting(cs);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > index 58bb1c55294c..cc8b09b8a7fa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> >  		return false;
> >  	}
> >
> > -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> > +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >  	    gt->type == GT_MEDIA) {
> >  		drm_notice(&i915->drm,
> >  			   "Media RC6 disabled on A step\n"); diff --git
> > a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index bb948ffc95ca..f840376f107f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct
> > intel_engine_cs *engine,
> >
> >  	dg2_ctx_gt_tuning_init(engine, wal);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> > ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
> >  		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
> false);  }
> >
> > @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> > intel_engine_cs *engine,
> >
> >  	mtl_ctx_gt_tuning_init(engine, wal);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >  		/* Wa_14014947963 */
> >  		wa_masked_field_set(wal, VF_PREEMPTION,
> >  				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@
> > xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> > *wal)
> >  	/* Wa_22016670082 */
> >  	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
> >  		/* Wa_14014830051 */
> >  		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> >
> > @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)  {
> >  	struct drm_i915_private *i915 = engine->i915;
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >  		/* Wa_22014600077 */
> >  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >  	}
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >  		/* Wa_1509727124 */
> > @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)
> >
> >  	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >  	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >  		/* Wa_22012856258 */
> >  		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >  				 GEN12_DISABLE_READ_SUPPRESSION); @@ -
> 3016,13 +3016,13 @@
> > general_render_compute_wa_init(struct
> > intel_engine_cs *engine, struct i915_wa_li
> >
> > GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >  	}
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
> > ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
> >  		/* Wa_14017856879 */
> >  		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> > MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >  		/*
> >  		 * Wa_14017066071
> >  		 * Wa_14017654203
> > @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> > intel_engine_cs *engine, struct i915_wa_li
> >  		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >  				 MTL_DISABLE_SAMPLER_SC_OOO);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >  		/* Wa_22015279794 */
> >  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >  				 DISABLE_PREFETCH_INTO_IC);
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >  		/* Wa_22013037850 */
> > @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> > intel_engine_cs *engine, struct i915_wa_li
> >  				DISABLE_128B_EVICTION_COMMAND_UDW);
> >  	}
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >  	    IS_PONTEVECCHIO(i915) ||
> >  	    IS_DG2(i915)) {
> >  		/* Wa_22014226127 */
> >  		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> DISABLE_D8_D16_COASLESCE);
> >  	}
> >
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >  	    IS_DG2(i915)) {
> >  		/* Wa_18017747507 */
> >  		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> > POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> > a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 2eb891b270ae..c8e2a110b833 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >  		flags |= GUC_WA_GAM_CREDITS;
> >
> >  	/* Wa_14014475959 */
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
> >  	    IS_DG2(gt->i915))
> >  		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> >
> > @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >  		flags |= GUC_WA_DUAL_QUEUE;
> >
> >  	/* Wa_22011802037: graphics version 11/12 */
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
> >  	    (GRAPHICS_VER(gt->i915) >= 11 &&
> >  	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> >  		flags |= GUC_WA_PRE_PARSER;
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index a0e3ef1c65d2..6f0e07c4488e 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> > intel_engine_cs *engine)
> >  	 * Wa_22011802037: In addition to stopping the cs, we need
> >  	 * to wait for any pending mi force wakeups
> >  	 */
> > -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> > STEP_B0) ||
> >  	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >  	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> >  		intel_engine_stop_cs(engine);
> > @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct
> > intel_engine_cs
> > *engine)
> >
> >  	/* Wa_14014475959:dg2 */
> >  	if (engine->class == COMPUTE_CLASS)
> > -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> > STEP_B0) ||
> > +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
> > STEP_A0, STEP_B0) ||
> >  		    IS_DG2(engine->i915))
> >  			engine->flags |=
> > I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index deb5b9064621..8b4cc3f4df1f
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
> >  	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> > INTEL_SUBPLATFORM_##variant) && \
> >  	 IS_GRAPHICS_STEP(__i915, since, until))
> >
> > -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> > +	(IS_METEORLAKE_P(__i915) && \
> > +	 IS_GRAPHICS_STEP(__i915, since, until))
> > +
> > +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
> > +	(IS_METEORLAKE_M(__i915) && \
> > +	 IS_GRAPHICS_STEP(__i915, since, until))
> > +
> > +
> > +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> >  	(IS_METEORLAKE(__i915) && \
> >  	 IS_DISPLAY_STEP(__i915, since, until))
> >
> > -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> > +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> >  	(IS_METEORLAKE(__i915) && \
> >  	 IS_MEDIA_STEP(__i915, since, until))
> >
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 0a111b281578..e943ffbaecbc 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct
> > i915_perf *perf,
> >  	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings
> > where OAM
> >  	 * does not work as expected.
> >  	 */
> > -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> > +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> > STEP_C0) &&
> >  	    props->engine->oa_group->type == TYPE_OAM &&
> >  	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> >  		drm_dbg(&perf->i915->drm,
> > @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct
> > drm_i915_private
> > *i915)
> >  	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> >  	 * to indicate that OA media is not supported.
> >  	 */
> > -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> > +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >  		struct intel_gt *gt;
> >  		int i;
> >
> > --
> > 2.34.1

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>> -----Original Message-----
>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>> Sent: Monday, July 10, 2023 4:28 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; jani.nikula@linux.intel.com;
>> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>> <dnyaneshwar.bhadane@intel.com>
>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
>> defines
>>
>> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
>> defines that are replacing IS_MTL_GRAPHICS_STEP with
>> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP
>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
>>
> Hi Tvrtko,
> Could you please give the feedback on this ? or suggestion regarding the approach.

It's a step in the right direction I just wish we could do all churning 
in one go.

Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any other I 
am missing?

What have we concluded on Jani's suggestion to split it all to 
IS_<platform> && IS_<subsys>?

If you have a) captured all IS_<tla> and b) Jani acks the series too, I 
guess go ahead.

Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?

Regards,

Tvrtko

P.S.
I still think these suck though:

	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))

I am not convinced we get anything (apart more source code and more 
binary) by having duplicated conditions. I guess I will have to send 
that cleanup later.

>> v2:
>> - Replace IS_MTL_GRAPHICS_STEP with
>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
>> - Changed subject prefix mtl instead of MTL (Anusha)
>> v3:
>> - Updated the commit message. (Anusha)
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
>> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>   drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>>   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>   15 files changed, 60 insertions(+), 51 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index 7f8b2d7713c7..6358a8b26172 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
>> intel_atomic_state *state,
>>
>>   	/* Wa_14016291713 */
>>   	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>   	    crtc_state->has_psr) {
>>   		plane_state->no_fbc_reason = "PSR1 enabled
>> (Wa_14016291713)";
>>   		return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> index f7608d363634..8c3158b188ef 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>>   				     &pmdemand_state->base,
>>   				     &intel_pmdemand_funcs);
>>
>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>   		/* Wa_14016740474 */
>>   		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
>> DMD_RSP_TIMEOUT_DISABLE);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 62151abe4748..ecd4e36119b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
>> *intel_dp,
>>   	bool set_wa_bit = false;
>>
>>   	/* Wa_14015648006 */
>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>   	    IS_DISPLAY_VER(dev_priv, 11, 13))
>>   		set_wa_bit |= crtc_state->wm_level_disabled;
>>
>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
>> *intel_dp,
>>   		 * All supported adlp panels have 1-based X granularity, this may
>>   		 * cause issues if non-supported panels are used.
>>   		 */
>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>> STEP_B0))
>>   			intel_de_rmw(dev_priv,
>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>   				     ADLP_1_BASED_X_GRANULARITY);
>>   		else if (IS_ALDERLAKE_P(dev_priv))
>> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
>> *intel_dp,
>>   				     ADLP_1_BASED_X_GRANULARITY);
>>
>>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>> STEP_B0))
>>   			intel_de_rmw(dev_priv,
>>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>> 0,
>>
>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
>> *intel_dp)
>>
>>   	if (intel_dp->psr.psr2_enabled) {
>>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>> STEP_B0))
>>   			intel_de_rmw(dev_priv,
>>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>
>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>   		goto skip_sel_fetch_set_loop;
>>
>>   	/* Wa_14014971492 */
>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>   	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>   	    crtc_state->splitter.enable)
>>   		pipe_clip.y1 = 0;
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 636a88827a8f..cf1bcc6bff08 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
>> drm_i915_private *i915,
>>   				 enum pipe pipe, enum plane_id plane_id)  {
>>   	/* Wa_14017240301 */
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>   		return false;
>>
>>   	/* Wa_22011186057 */
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 3173e811463d..26656d4be61e 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
>> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
>> i915_request *rq)  {
>>   	/* Wa_14016712196 */
>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>> STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>> STEP_B0))
>> +{
>>   		u32 *cs;
>>
>>   		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
>> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>   		     PIPE_CONTROL_FLUSH_ENABLE);
>>
>>   	/* Wa_14016712196 */
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>   		/* dummy PIPE_CONTROL + depth flush */
>>   		cs = gen12_emit_pipe_control(cs, 0,
>>
>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 0aff5bb13c53..df4883764ad4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
>> intel_engine_cs *engine,
>>   	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>>   	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>>   	 */
>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>> STEP_B0) ||
>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>   		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
>>> mmio_base),
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 2ebd937f3b4c..802b31ad982e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
>> intel_engine_cs *engine)
>>   	 * Wa_22011802037: In addition to stopping the cs, we need
>>   	 * to wait for any pending mi force wakeups
>>   	 */
>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>> STEP_B0) ||
>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>   		intel_engine_wait_for_pending_mi_fw(engine);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> index 0b414eae1683..e30b56be0cb8 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>   		gt->steering_table[OADDRM] =
>> xelpmp_oaddrm_steering_table;
>>   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>   		/* Wa_14016747170 */
>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
>> STEP_B0) ||
>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
>> STEP_B0))
>>   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>   					     intel_uncore_read(gt->uncore,
>>
>> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index a4ec20aaafe2..80608090fb1e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
>> intel_context *ce, u32 *cs)
>>   					      cs, GEN12_GFX_CCS_AUX_NV);
>>
>>   	/* Wa_16014892111 */
>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>> STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>> STEP_B0)
>> +||
>>   	    IS_DG2(ce->engine->i915))
>>   		cs = dg2_emit_draw_watermark_setting(cs);
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> index 58bb1c55294c..cc8b09b8a7fa 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>   		return false;
>>   	}
>>
>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>   	    gt->type == GT_MEDIA) {
>>   		drm_notice(&i915->drm,
>>   			   "Media RC6 disabled on A step\n"); diff --git
>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index bb948ffc95ca..f840376f107f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
>> *engine,
>>
>>   	dg2_ctx_gt_tuning_init(engine, wal);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>> ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
>> false);  }
>>
>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
>> intel_engine_cs *engine,
>>
>>   	mtl_ctx_gt_tuning_init(engine, wal);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>   		/* Wa_14014947963 */
>>   		wa_masked_field_set(wal, VF_PREEMPTION,
>>   				    PREEMPTION_VERTEX_COUNT, 0x4000);
>> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
>> i915_wa_list *wal)
>>   	/* Wa_22016670082 */
>>   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
>>   		/* Wa_14014830051 */
>>   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>
>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal)  {
>>   	struct drm_i915_private *i915 = engine->i915;
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>   		/* Wa_22014600077 */
>>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>   	}
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>   		/* Wa_1509727124 */
>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal)
>>
>>   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>   		/* Wa_22012856258 */
>>   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>   				 GEN12_DISABLE_READ_SUPPRESSION);
>> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
>> intel_engine_cs *engine, struct i915_wa_li
>>
>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>   	}
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>> ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>   		/* Wa_14017856879 */
>>   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>   		/*
>>   		 * Wa_14017066071
>>   		 * Wa_14017654203
>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
>> intel_engine_cs *engine, struct i915_wa_li
>>   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>   				 MTL_DISABLE_SAMPLER_SC_OOO);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>   		/* Wa_22015279794 */
>>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>   				 DISABLE_PREFETCH_INTO_IC);
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>   		/* Wa_22013037850 */
>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
>> intel_engine_cs *engine, struct i915_wa_li
>>   				DISABLE_128B_EVICTION_COMMAND_UDW);
>>   	}
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>   	    IS_PONTEVECCHIO(i915) ||
>>   	    IS_DG2(i915)) {
>>   		/* Wa_22014226127 */
>>   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
>> DISABLE_D8_D16_COASLESCE);
>>   	}
>>
>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>   	    IS_DG2(i915)) {
>>   		/* Wa_18017747507 */
>>   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 2eb891b270ae..c8e2a110b833 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>   		flags |= GUC_WA_GAM_CREDITS;
>>
>>   	/* Wa_14014475959 */
>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>   	    IS_DG2(gt->i915))
>>   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>
>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>   		flags |= GUC_WA_DUAL_QUEUE;
>>
>>   	/* Wa_22011802037: graphics version 11/12 */
>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>   	    (GRAPHICS_VER(gt->i915) >= 11 &&
>>   	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>   		flags |= GUC_WA_PRE_PARSER;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index a0e3ef1c65d2..6f0e07c4488e 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
>> intel_engine_cs *engine)
>>   	 * Wa_22011802037: In addition to stopping the cs, we need
>>   	 * to wait for any pending mi force wakeups
>>   	 */
>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>> STEP_B0) ||
>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>   	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>   		intel_engine_stop_cs(engine);
>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
>> *engine)
>>
>>   	/* Wa_14014475959:dg2 */
>>   	if (engine->class == COMPUTE_CLASS)
>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
>> STEP_B0) ||
>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
>> STEP_A0, STEP_B0) ||
>>   		    IS_DG2(engine->i915))
>>   			engine->flags |=
>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index deb5b9064621..8b4cc3f4df1f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>
>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>>   	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
>> INTEL_SUBPLATFORM_##variant) && \
>>   	 IS_GRAPHICS_STEP(__i915, since, until))
>>
>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
>> +	(IS_METEORLAKE_P(__i915) && \
>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>> +
>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
>> +	(IS_METEORLAKE_M(__i915) && \
>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>> +
>> +
>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>   	(IS_METEORLAKE(__i915) && \
>>   	 IS_DISPLAY_STEP(__i915, since, until))
>>
>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>   	(IS_METEORLAKE(__i915) && \
>>   	 IS_MEDIA_STEP(__i915, since, until))
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 0a111b281578..e943ffbaecbc 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
>> *perf,
>>   	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
>> OAM
>>   	 * does not work as expected.
>>   	 */
>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
>> STEP_C0) &&
>>   	    props->engine->oa_group->type == TYPE_OAM &&
>>   	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>   		drm_dbg(&perf->i915->drm,
>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
>> *i915)
>>   	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>>   	 * to indicate that OA media is not supported.
>>   	 */
>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>   		struct intel_gt *gt;
>>   		int i;
>>
>> --
>> 2.34.1
> 

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Jani Nikula]

On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>> -----Original Message-----
>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>>> Sent: Monday, July 10, 2023 4:28 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; jani.nikula@linux.intel.com;
>>> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>>> <dnyaneshwar.bhadane@intel.com>
>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
>>> defines
>>>
>>> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
>>> defines that are replacing IS_MTL_GRAPHICS_STEP with
>>> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP
>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
>>>
>> Hi Tvrtko,
>> Could you please give the feedback on this ? or suggestion regarding the approach.
>
> It's a step in the right direction I just wish we could do all churning 
> in one go.
>
> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any other I 
> am missing?
>
> What have we concluded on Jani's suggestion to split it all to 
> IS_<platform> && IS_<subsys>?

IS_<platform> && IS_<step> is what I was after.

> If you have a) captured all IS_<tla> and b) Jani acks the series too, I 
> guess go ahead.
>
> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?

For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.

>
> Regards,
>
> Tvrtko
>
> P.S.
> I still think these suck though:
>
> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))

I still find it appealing to a) go towards shorter acronyms instead of
long names, and b) to separate platform and stepping checks because
they're orthogonal. They're only bundled together for historical
reasons, and to keep the conditions shorter.

The above could be:

	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))


BR,
Jani.


>
> I am not convinced we get anything (apart more source code and more 
> binary) by having duplicated conditions. I guess I will have to send 
> that cleanup later.
>
>>> v2:
>>> - Replace IS_MTL_GRAPHICS_STEP with
>>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
>>> - Changed subject prefix mtl instead of MTL (Anusha)
>>> v3:
>>> - Updated the commit message. (Anusha)
>>>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
>>> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>>   drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>>>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>>   drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>>>   drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>>   15 files changed, 60 insertions(+), 51 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> index 7f8b2d7713c7..6358a8b26172 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
>>> intel_atomic_state *state,
>>>
>>>   	/* Wa_14016291713 */
>>>   	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>   	    crtc_state->has_psr) {
>>>   		plane_state->no_fbc_reason = "PSR1 enabled
>>> (Wa_14016291713)";
>>>   		return 0;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> index f7608d363634..8c3158b188ef 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>>>   				     &pmdemand_state->base,
>>>   				     &intel_pmdemand_funcs);
>>>
>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>   		/* Wa_14016740474 */
>>>   		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
>>> DMD_RSP_TIMEOUT_DISABLE);
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 62151abe4748..ecd4e36119b2 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
>>> *intel_dp,
>>>   	bool set_wa_bit = false;
>>>
>>>   	/* Wa_14015648006 */
>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>   	    IS_DISPLAY_VER(dev_priv, 11, 13))
>>>   		set_wa_bit |= crtc_state->wm_level_disabled;
>>>
>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
>>> *intel_dp,
>>>   		 * All supported adlp panels have 1-based X granularity, this may
>>>   		 * cause issues if non-supported panels are used.
>>>   		 */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>> STEP_B0))
>>>   			intel_de_rmw(dev_priv,
>>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>>   				     ADLP_1_BASED_X_GRANULARITY);
>>>   		else if (IS_ALDERLAKE_P(dev_priv))
>>> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
>>> *intel_dp,
>>>   				     ADLP_1_BASED_X_GRANULARITY);
>>>
>>>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>> STEP_B0))
>>>   			intel_de_rmw(dev_priv,
>>>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>> 0,
>>>
>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
>>> *intel_dp)
>>>
>>>   	if (intel_dp->psr.psr2_enabled) {
>>>   		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>> STEP_B0))
>>>   			intel_de_rmw(dev_priv,
>>>   				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>
>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
>>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>>   		goto skip_sel_fetch_set_loop;
>>>
>>>   	/* Wa_14014971492 */
>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>   	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>>   	    crtc_state->splitter.enable)
>>>   		pipe_clip.y1 = 0;
>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> index 636a88827a8f..cf1bcc6bff08 100644
>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
>>> drm_i915_private *i915,
>>>   				 enum pipe pipe, enum plane_id plane_id)  {
>>>   	/* Wa_14017240301 */
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>   		return false;
>>>
>>>   	/* Wa_22011186057 */
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> index 3173e811463d..26656d4be61e 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
>>> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
>>> i915_request *rq)  {
>>>   	/* Wa_14016712196 */
>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>> STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>> STEP_B0))
>>> +{
>>>   		u32 *cs;
>>>
>>>   		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
>>> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>   		     PIPE_CONTROL_FLUSH_ENABLE);
>>>
>>>   	/* Wa_14016712196 */
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>   		/* dummy PIPE_CONTROL + depth flush */
>>>   		cs = gen12_emit_pipe_control(cs, 0,
>>>
>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
>>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> index 0aff5bb13c53..df4883764ad4 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
>>> intel_engine_cs *engine,
>>>   	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>>>   	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>>>   	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>> STEP_B0) ||
>>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>   		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
>>>> mmio_base),
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index 2ebd937f3b4c..802b31ad982e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
>>> intel_engine_cs *engine)
>>>   	 * Wa_22011802037: In addition to stopping the cs, we need
>>>   	 * to wait for any pending mi force wakeups
>>>   	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>> STEP_B0) ||
>>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>   	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>   		intel_engine_wait_for_pending_mi_fw(engine);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> index 0b414eae1683..e30b56be0cb8 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>   		gt->steering_table[OADDRM] =
>>> xelpmp_oaddrm_steering_table;
>>>   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>   		/* Wa_14016747170 */
>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
>>> STEP_B0) ||
>>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
>>> STEP_B0))
>>>   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>   					     intel_uncore_read(gt->uncore,
>>>
>>> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index a4ec20aaafe2..80608090fb1e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
>>> intel_context *ce, u32 *cs)
>>>   					      cs, GEN12_GFX_CCS_AUX_NV);
>>>
>>>   	/* Wa_16014892111 */
>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>> STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>> STEP_B0)
>>> +||
>>>   	    IS_DG2(ce->engine->i915))
>>>   		cs = dg2_emit_draw_watermark_setting(cs);
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> index 58bb1c55294c..cc8b09b8a7fa 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>>   		return false;
>>>   	}
>>>
>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>   	    gt->type == GT_MEDIA) {
>>>   		drm_notice(&i915->drm,
>>>   			   "Media RC6 disabled on A step\n"); diff --git
>>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index bb948ffc95ca..f840376f107f 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
>>> *engine,
>>>
>>>   	dg2_ctx_gt_tuning_init(engine, wal);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>>> ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>>   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
>>> false);  }
>>>
>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
>>> intel_engine_cs *engine,
>>>
>>>   	mtl_ctx_gt_tuning_init(engine, wal);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>   		/* Wa_14014947963 */
>>>   		wa_masked_field_set(wal, VF_PREEMPTION,
>>>   				    PREEMPTION_VERTEX_COUNT, 0x4000);
>>> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
>>> i915_wa_list *wal)
>>>   	/* Wa_22016670082 */
>>>   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
>>>   		/* Wa_14014830051 */
>>>   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>>
>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>>> struct i915_wa_list *wal)  {
>>>   	struct drm_i915_private *i915 = engine->i915;
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>   		/* Wa_22014600077 */
>>>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>   	}
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>   		/* Wa_1509727124 */
>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>>> struct i915_wa_list *wal)
>>>
>>>   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>   		/* Wa_22012856258 */
>>>   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>   				 GEN12_DISABLE_READ_SUPPRESSION);
>>> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
>>> intel_engine_cs *engine, struct i915_wa_li
>>>
>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>   	}
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>>> ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>>   		/* Wa_14017856879 */
>>>   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>   		/*
>>>   		 * Wa_14017066071
>>>   		 * Wa_14017654203
>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
>>> intel_engine_cs *engine, struct i915_wa_li
>>>   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>   				 MTL_DISABLE_SAMPLER_SC_OOO);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>   		/* Wa_22015279794 */
>>>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>   				 DISABLE_PREFETCH_INTO_IC);
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>   		/* Wa_22013037850 */
>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
>>> intel_engine_cs *engine, struct i915_wa_li
>>>   				DISABLE_128B_EVICTION_COMMAND_UDW);
>>>   	}
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>   	    IS_PONTEVECCHIO(i915) ||
>>>   	    IS_DG2(i915)) {
>>>   		/* Wa_22014226127 */
>>>   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
>>> DISABLE_D8_D16_COASLESCE);
>>>   	}
>>>
>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>   	    IS_DG2(i915)) {
>>>   		/* Wa_18017747507 */
>>>   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
>>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
>>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> index 2eb891b270ae..c8e2a110b833 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>   		flags |= GUC_WA_GAM_CREDITS;
>>>
>>>   	/* Wa_14014475959 */
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>>   	    IS_DG2(gt->i915))
>>>   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>>
>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>   		flags |= GUC_WA_DUAL_QUEUE;
>>>
>>>   	/* Wa_22011802037: graphics version 11/12 */
>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>>   	    (GRAPHICS_VER(gt->i915) >= 11 &&
>>>   	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>>   		flags |= GUC_WA_PRE_PARSER;
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index a0e3ef1c65d2..6f0e07c4488e 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
>>> intel_engine_cs *engine)
>>>   	 * Wa_22011802037: In addition to stopping the cs, we need
>>>   	 * to wait for any pending mi force wakeups
>>>   	 */
>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>> STEP_B0) ||
>>>   	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>   	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>>   		intel_engine_stop_cs(engine);
>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
>>> *engine)
>>>
>>>   	/* Wa_14014475959:dg2 */
>>>   	if (engine->class == COMPUTE_CLASS)
>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
>>> STEP_B0) ||
>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
>>> STEP_A0, STEP_B0) ||
>>>   		    IS_DG2(engine->i915))
>>>   			engine->flags |=
>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index deb5b9064621..8b4cc3f4df1f 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
>>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>>
>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>>>   	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
>>> INTEL_SUBPLATFORM_##variant) && \
>>>   	 IS_GRAPHICS_STEP(__i915, since, until))
>>>
>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
>>> +	(IS_METEORLAKE_P(__i915) && \
>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>> +
>>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
>>> +	(IS_METEORLAKE_M(__i915) && \
>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>> +
>>> +
>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>>   	(IS_METEORLAKE(__i915) && \
>>>   	 IS_DISPLAY_STEP(__i915, since, until))
>>>
>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>>   	(IS_METEORLAKE(__i915) && \
>>>   	 IS_MEDIA_STEP(__i915, since, until))
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>> b/drivers/gpu/drm/i915/i915_perf.c
>>> index 0a111b281578..e943ffbaecbc 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
>>> *perf,
>>>   	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
>>> OAM
>>>   	 * does not work as expected.
>>>   	 */
>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
>>> STEP_C0) &&
>>>   	    props->engine->oa_group->type == TYPE_OAM &&
>>>   	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>>   		drm_dbg(&perf->i915->drm,
>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
>>> *i915)
>>>   	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>>>   	 * to indicate that OA media is not supported.
>>>   	 */
>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>   		struct intel_gt *gt;
>>>   		int i;
>>>
>>> --
>>> 2.34.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 13/07/2023 10:39, Jani Nikula wrote:
> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>>> -----Original Message-----
>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>>>> Sent: Monday, July 10, 2023 4:28 PM
>>>> To: intel-gfx@lists.freedesktop.org
>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; jani.nikula@linux.intel.com;
>>>> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>>>> <dnyaneshwar.bhadane@intel.com>
>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
>>>> defines
>>>>
>>>> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
>>>> defines that are replacing IS_MTL_GRAPHICS_STEP with
>>>> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of IS_MTL_MEDIA_STEP
>>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
>>>>
>>> Hi Tvrtko,
>>> Could you please give the feedback on this ? or suggestion regarding the approach.
>>
>> It's a step in the right direction I just wish we could do all churning
>> in one go.
>>
>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any other I
>> am missing?
>>
>> What have we concluded on Jani's suggestion to split it all to
>> IS_<platform> && IS_<subsys>?
> 
> IS_<platform> && IS_<step> is what I was after.

Yeah I mistyped. I liked that to so would get my ack.

>> If you have a) captured all IS_<tla> and b) Jani acks the series too, I
>> guess go ahead.
>>
>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
> 
> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.

IS_ELKHARTLAKE would indeed work and platform/subplatform can be hidden 
implementation detail.

>> P.S.
>> I still think these suck though:
>>
>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> 
> I still find it appealing to a) go towards shorter acronyms instead of
> long names, and b) to separate platform and stepping checks because
> they're orthogonal. They're only bundled together for historical
> reasons, and to keep the conditions shorter.
> 
> The above could be:
> 
> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))

I'd be super pleased with that.

Regards,

Tvrtko

> 
> 
> BR,
> Jani.
> 
> 
>>
>> I am not convinced we get anything (apart more source code and more
>> binary) by having duplicated conditions. I guess I will have to send
>> that cleanup later.
>>
>>>> v2:
>>>> - Replace IS_MTL_GRAPHICS_STEP with
>>>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
>>>> - Changed subject prefix mtl instead of MTL (Anusha)
>>>> v3:
>>>> - Updated the commit message. (Anusha)
>>>>
>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
>>>> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>>>    drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>>>    drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>>>    .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>>>    drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>>>    drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>>>    .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>>>    drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>>>    drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>>>    drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>>>>    drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>>>    .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>>>    drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>>>>    drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>>>    15 files changed, 60 insertions(+), 51 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>>>> index 7f8b2d7713c7..6358a8b26172 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
>>>> intel_atomic_state *state,
>>>>
>>>>    	/* Wa_14016291713 */
>>>>    	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>>    	    crtc_state->has_psr) {
>>>>    		plane_state->no_fbc_reason = "PSR1 enabled
>>>> (Wa_14016291713)";
>>>>    		return 0;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>> index f7608d363634..8c3158b188ef 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>>>>    				     &pmdemand_state->base,
>>>>    				     &intel_pmdemand_funcs);
>>>>
>>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>>    		/* Wa_14016740474 */
>>>>    		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
>>>> DMD_RSP_TIMEOUT_DISABLE);
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>>> index 62151abe4748..ecd4e36119b2 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
>>>> *intel_dp,
>>>>    	bool set_wa_bit = false;
>>>>
>>>>    	/* Wa_14015648006 */
>>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>    	    IS_DISPLAY_VER(dev_priv, 11, 13))
>>>>    		set_wa_bit |= crtc_state->wm_level_disabled;
>>>>
>>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
>>>> *intel_dp,
>>>>    		 * All supported adlp panels have 1-based X granularity, this may
>>>>    		 * cause issues if non-supported panels are used.
>>>>    		 */
>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>> STEP_B0))
>>>>    			intel_de_rmw(dev_priv,
>>>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>>>    				     ADLP_1_BASED_X_GRANULARITY);
>>>>    		else if (IS_ALDERLAKE_P(dev_priv))
>>>> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
>>>> *intel_dp,
>>>>    				     ADLP_1_BASED_X_GRANULARITY);
>>>>
>>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>> STEP_B0))
>>>>    			intel_de_rmw(dev_priv,
>>>>    				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>> 0,
>>>>
>>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
>>>> *intel_dp)
>>>>
>>>>    	if (intel_dp->psr.psr2_enabled) {
>>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>> STEP_B0))
>>>>    			intel_de_rmw(dev_priv,
>>>>    				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>>
>>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
>>>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>>>    		goto skip_sel_fetch_set_loop;
>>>>
>>>>    	/* Wa_14014971492 */
>>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>    	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>>>    	    crtc_state->splitter.enable)
>>>>    		pipe_clip.y1 = 0;
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 636a88827a8f..cf1bcc6bff08 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
>>>> drm_i915_private *i915,
>>>>    				 enum pipe pipe, enum plane_id plane_id)  {
>>>>    	/* Wa_14017240301 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>    		return false;
>>>>
>>>>    	/* Wa_22011186057 */
>>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> index 3173e811463d..26656d4be61e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
>>>> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
>>>> i915_request *rq)  {
>>>>    	/* Wa_14016712196 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>>> STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>>> STEP_B0))
>>>> +{
>>>>    		u32 *cs;
>>>>
>>>>    		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
>>>> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>>    		     PIPE_CONTROL_FLUSH_ENABLE);
>>>>
>>>>    	/* Wa_14016712196 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>    		/* dummy PIPE_CONTROL + depth flush */
>>>>    		cs = gen12_emit_pipe_control(cs, 0,
>>>>
>>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
>>>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>> index 0aff5bb13c53..df4883764ad4 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
>>>> intel_engine_cs *engine,
>>>>    	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>>>>    	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>>>>    	 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>> STEP_B0) ||
>>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>>    		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
>>>>> mmio_base),
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>> index 2ebd937f3b4c..802b31ad982e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
>>>> intel_engine_cs *engine)
>>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
>>>>    	 * to wait for any pending mi force wakeups
>>>>    	 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>> STEP_B0) ||
>>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>>    		intel_engine_wait_for_pending_mi_fw(engine);
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> index 0b414eae1683..e30b56be0cb8 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>>    		gt->steering_table[OADDRM] =
>>>> xelpmp_oaddrm_steering_table;
>>>>    	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>>    		/* Wa_14016747170 */
>>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
>>>> STEP_B0) ||
>>>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
>>>> STEP_B0))
>>>>    			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>>    					     intel_uncore_read(gt->uncore,
>>>>
>>>> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> index a4ec20aaafe2..80608090fb1e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
>>>> intel_context *ce, u32 *cs)
>>>>    					      cs, GEN12_GFX_CCS_AUX_NV);
>>>>
>>>>    	/* Wa_16014892111 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>>> STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>>> STEP_B0)
>>>> +||
>>>>    	    IS_DG2(ce->engine->i915))
>>>>    		cs = dg2_emit_draw_watermark_setting(cs);
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>> index 58bb1c55294c..cc8b09b8a7fa 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>>>    		return false;
>>>>    	}
>>>>
>>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>>    	    gt->type == GT_MEDIA) {
>>>>    		drm_notice(&i915->drm,
>>>>    			   "Media RC6 disabled on A step\n"); diff --git
>>>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> index bb948ffc95ca..f840376f107f 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
>>>> *engine,
>>>>
>>>>    	dg2_ctx_gt_tuning_init(engine, wal);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>>>> ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>>>    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
>>>> false);  }
>>>>
>>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
>>>> intel_engine_cs *engine,
>>>>
>>>>    	mtl_ctx_gt_tuning_init(engine, wal);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>    		/* Wa_14014947963 */
>>>>    		wa_masked_field_set(wal, VF_PREEMPTION,
>>>>    				    PREEMPTION_VERTEX_COUNT, 0x4000);
>>>> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
>>>> i915_wa_list *wal)
>>>>    	/* Wa_22016670082 */
>>>>    	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0)) {
>>>>    		/* Wa_14014830051 */
>>>>    		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>>>
>>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>>>> struct i915_wa_list *wal)  {
>>>>    	struct drm_i915_private *i915 = engine->i915;
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>    		/* Wa_22014600077 */
>>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>    				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>>    	}
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>    		/* Wa_1509727124 */
>>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
>>>> struct i915_wa_list *wal)
>>>>
>>>>    	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>    		/* Wa_22012856258 */
>>>>    		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>>    				 GEN12_DISABLE_READ_SUPPRESSION);
>>>> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>
>>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>    	}
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)
>>>> ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER))
>>>>    		/* Wa_14017856879 */
>>>>    		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
>>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>    		/*
>>>>    		 * Wa_14017066071
>>>>    		 * Wa_14017654203
>>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>    		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>>    				 MTL_DISABLE_SAMPLER_SC_OOO);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>    		/* Wa_22015279794 */
>>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>    				 DISABLE_PREFETCH_INTO_IC);
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>    		/* Wa_22013037850 */
>>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>    				DISABLE_128B_EVICTION_COMMAND_UDW);
>>>>    	}
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>    	    IS_PONTEVECCHIO(i915) ||
>>>>    	    IS_DG2(i915)) {
>>>>    		/* Wa_22014226127 */
>>>>    		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
>>>> DISABLE_D8_D16_COASLESCE);
>>>>    	}
>>>>
>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>    	    IS_DG2(i915)) {
>>>>    		/* Wa_18017747507 */
>>>>    		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
>>>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
>>>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> index 2eb891b270ae..c8e2a110b833 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>>    		flags |= GUC_WA_GAM_CREDITS;
>>>>
>>>>    	/* Wa_14014475959 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>>>    	    IS_DG2(gt->i915))
>>>>    		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>>>
>>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>>    		flags |= GUC_WA_DUAL_QUEUE;
>>>>
>>>>    	/* Wa_22011802037: graphics version 11/12 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0) ||
>>>>    	    (GRAPHICS_VER(gt->i915) >= 11 &&
>>>>    	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>>>    		flags |= GUC_WA_PRE_PARSER;
>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> index a0e3ef1c65d2..6f0e07c4488e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
>>>> intel_engine_cs *engine)
>>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
>>>>    	 * to wait for any pending mi force wakeups
>>>>    	 */
>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>> STEP_B0) ||
>>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>    	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>>>    		intel_engine_stop_cs(engine);
>>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
>>>> *engine)
>>>>
>>>>    	/* Wa_14014475959:dg2 */
>>>>    	if (engine->class == COMPUTE_CLASS)
>>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
>>>> STEP_B0) ||
>>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
>>>> STEP_A0, STEP_B0) ||
>>>>    		    IS_DG2(engine->i915))
>>>>    			engine->flags |=
>>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index deb5b9064621..8b4cc3f4df1f 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct drm_i915_private
>>>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>>    	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>>>
>>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>>>>    	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
>>>> INTEL_SUBPLATFORM_##variant) && \
>>>>    	 IS_GRAPHICS_STEP(__i915, since, until))
>>>>
>>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
>>>> +	(IS_METEORLAKE_P(__i915) && \
>>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>>> +
>>>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
>>>> +	(IS_METEORLAKE_M(__i915) && \
>>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>>> +
>>>> +
>>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>>>    	(IS_METEORLAKE(__i915) && \
>>>>    	 IS_DISPLAY_STEP(__i915, since, until))
>>>>
>>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>>>    	(IS_METEORLAKE(__i915) && \
>>>>    	 IS_MEDIA_STEP(__i915, since, until))
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>>> b/drivers/gpu/drm/i915/i915_perf.c
>>>> index 0a111b281578..e943ffbaecbc 100644
>>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
>>>> *perf,
>>>>    	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
>>>> OAM
>>>>    	 * does not work as expected.
>>>>    	 */
>>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
>>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
>>>> STEP_C0) &&
>>>>    	    props->engine->oa_group->type == TYPE_OAM &&
>>>>    	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>>>    		drm_dbg(&perf->i915->drm,
>>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
>>>> *i915)
>>>>    	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>>>>    	 * to indicate that OA media is not supported.
>>>>    	 */
>>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>>    		struct intel_gt *gt;
>>>>    		int i;
>>>>
>>>> --
>>>> 2.34.1
>>>
> 

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Sent: Thursday, July 13, 2023 5:26 PM
> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> 
> On 13/07/2023 10:39, Jani Nikula wrote:
> > On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> >> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
> >>>> -----Original Message-----
> >>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> >>>> Sent: Monday, July 10, 2023 4:28 PM
> >>>> To: intel-gfx@lists.freedesktop.org
> >>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> >>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
> >>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> >>>> <dnyaneshwar.bhadane@intel.com>
> >>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> >>>> platform/subplatform defines
> >>>>
> >>>> Follow consistent naming convention. Replace MTL with METEORLAKE.
> >>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
> >>>> IS_METEORLAKE_P_GRAPHICS_STEP and
> IS_METEORLAKE_M_GRAPHICS_STEP.
> >>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
> IS_MTL_MEDIA_STEP
> >>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
> >>>>
> >>> Hi Tvrtko,
> >>> Could you please give the feedback on this ? or suggestion regarding the
> approach.
> >>
> >> It's a step in the right direction I just wish we could do all
> >> churning in one go.
> >>
> >> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
> >> other I am missing?
> >>
> >> What have we concluded on Jani's suggestion to split it all to
> >> IS_<platform> && IS_<subsys>?
> >
> > IS_<platform> && IS_<step> is what I was after.
> 
> Yeah I mistyped. I liked that to so would get my ack.
> 
> >> If you have a) captured all IS_<tla> and b) Jani acks the series too,
> >> I guess go ahead.
> >>
> >> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
> >
> > For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
> 
> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
> hidden implementation detail.
> 
> >> P.S.
> >> I still think these suck though:
> >>
> >> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >
> > I still find it appealing to a) go towards shorter acronyms instead of
> > long names, and b) to separate platform and stepping checks because
> > they're orthogonal. They're only bundled together for historical
> > reasons, and to keep the conditions shorter.
> >
> > The above could be:
> >
> > 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> 
> I'd be super pleased with that.

Could we use the above suggestion for MTL variants for P/M? also replacing MTL with METEORLAKE.

Using the format:  IS_FULL_PLATFORM_NAME && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0).

It will change to : 
	For M:	IS_METEORLAKE_M(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)
	For P:	IS_METEORLAKE_P(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)

Regards ,
Dnyaneshwar
> 
> Regards,
> 
> Tvrtko
> 
> >
> >
> > BR,
> > Jani.
> >
> >
> >>
> >> I am not convinced we get anything (apart more source code and more
> >> binary) by having duplicated conditions. I guess I will have to send
> >> that cleanup later.
> >>
> >>>> v2:
> >>>> - Replace IS_MTL_GRAPHICS_STEP with
> >>>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> >>>> - Changed subject prefix mtl instead of MTL (Anusha)
> >>>> v3:
> >>>> - Updated the commit message. (Anusha)
> >>>>
> >>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >>>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
> >>>> Signed-off-by: Dnyaneshwar Bhadane
> <dnyaneshwar.bhadane@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >>>>    drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >>>>    drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
> >>>>    .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
> >>>>    drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >>>>    .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++-------
> ---
> >>>>    drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >>>>    .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >>>>    drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
> >>>>    drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >>>>    15 files changed, 60 insertions(+), 51 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> index 7f8b2d7713c7..6358a8b26172 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> >>>> intel_atomic_state *state,
> >>>>
> >>>>    	/* Wa_14016291713 */
> >>>>    	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> >>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>>>    	    crtc_state->has_psr) {
> >>>>    		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> >>>>    		return 0;
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> index f7608d363634..8c3158b188ef 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private
> *i915)
> >>>>    				     &pmdemand_state->base,
> >>>>    				     &intel_pmdemand_funcs);
> >>>>
> >>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>>>    		/* Wa_14016740474 */
> >>>>    		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> >>>> DMD_RSP_TIMEOUT_DISABLE);
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> b/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> index 62151abe4748..ecd4e36119b2 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct
> >>>> intel_dp *intel_dp,
> >>>>    	bool set_wa_bit = false;
> >>>>
> >>>>    	/* Wa_14015648006 */
> >>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DISPLAY_VER(dev_priv, 11, 13))
> >>>>    		set_wa_bit |= crtc_state->wm_level_disabled;
> >>>>
> >>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct
> >>>> intel_dp *intel_dp,
> >>>>    		 * All supported adlp panels have 1-based X granularity, this
> may
> >>>>    		 * cause issues if non-supported panels are used.
> >>>>    		 */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >>>>    				     ADLP_1_BASED_X_GRANULARITY);
> >>>>    		else if (IS_ALDERLAKE_P(dev_priv)) @@ -1328,7 +1328,7 @@
> >>>> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >>>>    				     ADLP_1_BASED_X_GRANULARITY);
> >>>>
> >>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >>>> 0,
> >>>>
> >>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> >>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct
> >>>> intel_dp
> >>>> *intel_dp)
> >>>>
> >>>>    	if (intel_dp->psr.psr2_enabled) {
> >>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >>>>
> >>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7
> +1963,7 @@
> >>>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >>>>    		goto skip_sel_fetch_set_loop;
> >>>>
> >>>>    	/* Wa_14014971492 */
> >>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>>    	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> >>>>    	    crtc_state->splitter.enable)
> >>>>    		pipe_clip.y1 = 0;
> >>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> index 636a88827a8f..cf1bcc6bff08 100644
> >>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> >>>> drm_i915_private *i915,
> >>>>    				 enum pipe pipe, enum plane_id plane_id)  {
> >>>>    	/* Wa_14017240301 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		return false;
> >>>>
> >>>>    	/* Wa_22011186057 */
> >>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> index 3173e811463d..26656d4be61e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
> >>>> *gt, u32 *cs, const i915_reg_t inv  static int
> >>>> mtl_dummy_pipe_control(struct i915_request *rq)  {
> >>>>    	/* Wa_14016712196 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
> STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))
> {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> >>>> STEP_B0))
> >>>> +{
> >>>>    		u32 *cs;
> >>>>
> >>>>    		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32
> >>>> *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >>>>    		     PIPE_CONTROL_FLUSH_ENABLE);
> >>>>
> >>>>    	/* Wa_14016712196 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/* dummy PIPE_CONTROL + depth flush */
> >>>>    		cs = gen12_emit_pipe_control(cs, 0,
> >>>>
> >>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> index 0aff5bb13c53..df4883764ad4 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> >>>> intel_engine_cs *engine,
> >>>>    	 * Wa_22011802037: Prior to doing a reset, ensure CS is
> >>>>    	 * stopped, set ring stop bit and prefetch disable bit to halt CS
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>>>    		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >>>>> mmio_base),
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> index 2ebd937f3b4c..802b31ad982e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> >>>> intel_engine_cs *engine)
> >>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
> >>>>    	 * to wait for any pending mi force wakeups
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>>>    		intel_engine_wait_for_pending_mi_fw(engine);
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> index 0b414eae1683..e30b56be0cb8 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >>>>    		gt->steering_table[OADDRM] =
> >>>> xelpmp_oaddrm_steering_table;
> >>>>    	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >>>>    		/* Wa_14016747170 */
> >>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
> >>>> STEP_B0))
> >>>>    			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >>>>    					     intel_uncore_read(gt->uncore,
> >>>>
> >>>> MTL_GT_ACTIVITY_FACTOR)); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> index a4ec20aaafe2..80608090fb1e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> >>>> intel_context *ce, u32 *cs)
> >>>>    					      cs, GEN12_GFX_CCS_AUX_NV);
> >>>>
> >>>>    	/* Wa_16014892111 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
> STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0)
> ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> >>>> STEP_B0)
> >>>> +||
> >>>>    	    IS_DG2(ce->engine->i915))
> >>>>    		cs = dg2_emit_draw_watermark_setting(cs);
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> index 58bb1c55294c..cc8b09b8a7fa 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> >>>>    		return false;
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >>>>    	    gt->type == GT_MEDIA) {
> >>>>    		drm_notice(&i915->drm,
> >>>>    			   "Media RC6 disabled on A step\n"); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> index bb948ffc95ca..f840376f107f 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct
> >>>> intel_engine_cs *engine,
> >>>>
> >>>>    	dg2_ctx_gt_tuning_init(engine, wal);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER)
> >>>> ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER))
> >>>>    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF,
> 0, false);  }
> >>>>
> >>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> >>>> intel_engine_cs *engine,
> >>>>
> >>>>    	mtl_ctx_gt_tuning_init(engine, wal);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_14014947963 */
> >>>>    		wa_masked_field_set(wal, VF_PREEMPTION,
> >>>>    				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@
> >>>> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> >>>> *wal)
> >>>>    	/* Wa_22016670082 */
> >>>>    	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0))
> {
> >>>>    		/* Wa_14014830051 */
> >>>>    		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> >>>>
> >>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs
> >>>> *engine, struct i915_wa_list *wal)  {
> >>>>    	struct drm_i915_private *i915 = engine->i915;
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_22014600077 */
> >>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>>>    				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>>>    		/* Wa_1509727124 */
> >>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> >>>> *engine, struct i915_wa_list *wal)
> >>>>
> >>>>    	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> >>>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_22012856258 */
> >>>>    		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >>>>    				 GEN12_DISABLE_READ_SUPPRESSION); @@
> -3016,13 +3016,13 @@
> >>>> general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>
> >>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER)
> >>>> ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER))
> >>>>    		/* Wa_14017856879 */
> >>>>    		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> >>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/*
> >>>>    		 * Wa_14017066071
> >>>>    		 * Wa_14017654203
> >>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>    		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >>>>    				 MTL_DISABLE_SAMPLER_SC_OOO);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/* Wa_22015279794 */
> >>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>>>    				 DISABLE_PREFETCH_INTO_IC);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>>>    		/* Wa_22013037850 */
> >>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>
> 	DISABLE_128B_EVICTION_COMMAND_UDW);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_PONTEVECCHIO(i915) ||
> >>>>    	    IS_DG2(i915)) {
> >>>>    		/* Wa_22014226127 */
> >>>>    		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> >>>> DISABLE_D8_D16_COASLESCE);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2(i915)) {
> >>>>    		/* Wa_18017747507 */
> >>>>    		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> >>>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> index 2eb891b270ae..c8e2a110b833 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
> *guc)
> >>>>    		flags |= GUC_WA_GAM_CREDITS;
> >>>>
> >>>>    	/* Wa_14014475959 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>>    	    IS_DG2(gt->i915))
> >>>>    		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> >>>>
> >>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
> *guc)
> >>>>    		flags |= GUC_WA_DUAL_QUEUE;
> >>>>
> >>>>    	/* Wa_22011802037: graphics version 11/12 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(gt->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> >>>>    		flags |= GUC_WA_PRE_PARSER;
> >>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> index a0e3ef1c65d2..6f0e07c4488e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> >>>> intel_engine_cs *engine)
> >>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
> >>>>    	 * to wait for any pending mi force wakeups
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> >>>>    		intel_engine_stop_cs(engine);
> >>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct
> >>>> intel_engine_cs
> >>>> *engine)
> >>>>
> >>>>    	/* Wa_14014475959:dg2 */
> >>>>    	if (engine->class == COMPUTE_CLASS)
> >>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
> >>>> STEP_A0, STEP_B0) ||
> >>>>    		    IS_DG2(engine->i915))
> >>>>    			engine->flags |=
> >>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>>> b/drivers/gpu/drm/i915/i915_drv.h index deb5b9064621..8b4cc3f4df1f
> >>>> 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> >>>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >>>>    	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> >>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since,
> until)
> >>>> +\
> >>>>    	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> >>>> INTEL_SUBPLATFORM_##variant) && \
> >>>>    	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> >>>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> >>>> +	(IS_METEORLAKE_P(__i915) && \
> >>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>> +
> >>>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
> >>>> +	(IS_METEORLAKE_M(__i915) && \
> >>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>> +
> >>>> +
> >>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> >>>>    	(IS_METEORLAKE(__i915) && \
> >>>>    	 IS_DISPLAY_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> >>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> >>>>    	(IS_METEORLAKE(__i915) && \
> >>>>    	 IS_MEDIA_STEP(__i915, since, until))
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> >>>> b/drivers/gpu/drm/i915/i915_perf.c
> >>>> index 0a111b281578..e943ffbaecbc 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_perf.c
> >>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct
> >>>> i915_perf *perf,
> >>>>    	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings
> >>>> where OAM
> >>>>    	 * does not work as expected.
> >>>>    	 */
> >>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0)
> &&
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> >>>> STEP_C0) &&
> >>>>    	    props->engine->oa_group->type == TYPE_OAM &&
> >>>>    	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> >>>>    		drm_dbg(&perf->i915->drm,
> >>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct
> >>>> drm_i915_private
> >>>> *i915)
> >>>>    	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> >>>>    	 * to indicate that OA media is not supported.
> >>>>    	 */
> >>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >>>>    		struct intel_gt *gt;
> >>>>    		int i;
> >>>>
> >>>> --
> >>>> 2.34.1
> >>>
> >

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 13/07/2023 13:12, Bhadane, Dnyaneshwar wrote:
> 
> 
>> -----Original Message-----
>> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Sent: Thursday, July 13, 2023 5:26 PM
>> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
>> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
>> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
>> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>> platform/subplatform defines
>>
>>
>> On 13/07/2023 10:39, Jani Nikula wrote:
>>> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>>>>> -----Original Message-----
>>>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>>>>>> Sent: Monday, July 10, 2023 4:28 PM
>>>>>> To: intel-gfx@lists.freedesktop.org
>>>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
>>>>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
>>>>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>>>>>> <dnyaneshwar.bhadane@intel.com>
>>>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>>>>>> platform/subplatform defines
>>>>>>
>>>>>> Follow consistent naming convention. Replace MTL with METEORLAKE.
>>>>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
>>>>>> IS_METEORLAKE_P_GRAPHICS_STEP and
>> IS_METEORLAKE_M_GRAPHICS_STEP.
>>>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
>> IS_MTL_MEDIA_STEP
>>>>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
>>>>>>
>>>>> Hi Tvrtko,
>>>>> Could you please give the feedback on this ? or suggestion regarding the
>> approach.
>>>>
>>>> It's a step in the right direction I just wish we could do all
>>>> churning in one go.
>>>>
>>>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
>>>> other I am missing?
>>>>
>>>> What have we concluded on Jani's suggestion to split it all to
>>>> IS_<platform> && IS_<subsys>?
>>>
>>> IS_<platform> && IS_<step> is what I was after.
>>
>> Yeah I mistyped. I liked that to so would get my ack.
>>
>>>> If you have a) captured all IS_<tla> and b) Jani acks the series too,
>>>> I guess go ahead.
>>>>
>>>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
>>>
>>> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
>>
>> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
>> hidden implementation detail.
>>
>>>> P.S.
>>>> I still think these suck though:
>>>>
>>>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>
>>> I still find it appealing to a) go towards shorter acronyms instead of
>>> long names, and b) to separate platform and stepping checks because
>>> they're orthogonal. They're only bundled together for historical
>>> reasons, and to keep the conditions shorter.
>>>
>>> The above could be:
>>>
>>> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>
>> I'd be super pleased with that.
> 
> Could we use the above suggestion for MTL variants for P/M? also replacing MTL with METEORLAKE.
> 
> Using the format:  IS_FULL_PLATFORM_NAME && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0).
> 
> It will change to :
> 	For M:	IS_METEORLAKE_M(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)
> 	For P:	IS_METEORLAKE_P(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)

You could, but you'd only get a meh from me. :) Why you'd insist to keep 
the two checks? Are we expecting IS_METEROLAKE_<X> at some point?

Regards,

Tvrtko

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Sent: Thursday, July 13, 2023 5:55 PM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; intel-gfx@lists.freedesktop.org; Ursulin,
> Tvrtko <tvrtko.ursulin@intel.com>
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> 
> On 13/07/2023 13:12, Bhadane, Dnyaneshwar wrote:
> >
> >
> >> -----Original Message-----
> >> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> >> Sent: Thursday, July 13, 2023 5:26 PM
> >> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
> >> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
> >> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> >> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> >> platform/subplatform defines
> >>
> >>
> >> On 13/07/2023 10:39, Jani Nikula wrote:
> >>> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> wrote:
> >>>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> >>>>>> Sent: Monday, July 10, 2023 4:28 PM
> >>>>>> To: intel-gfx@lists.freedesktop.org
> >>>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> >>>>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
> >>>>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> >>>>>> <dnyaneshwar.bhadane@intel.com>
> >>>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> >>>>>> platform/subplatform defines
> >>>>>>
> >>>>>> Follow consistent naming convention. Replace MTL with
> METEORLAKE.
> >>>>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
> >>>>>> IS_METEORLAKE_P_GRAPHICS_STEP and
> >> IS_METEORLAKE_M_GRAPHICS_STEP.
> >>>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
> >> IS_MTL_MEDIA_STEP
> >>>>>> and IS_METEORLAKE_DISPLAY_STEP instead of
> IS_MTL_DISPLAY_STEP.
> >>>>>>
> >>>>> Hi Tvrtko,
> >>>>> Could you please give the feedback on this ? or suggestion
> >>>>> regarding the
> >> approach.
> >>>>
> >>>> It's a step in the right direction I just wish we could do all
> >>>> churning in one go.
> >>>>
> >>>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
> >>>> other I am missing?
> >>>>
> >>>> What have we concluded on Jani's suggestion to split it all to
> >>>> IS_<platform> && IS_<subsys>?
> >>>
> >>> IS_<platform> && IS_<step> is what I was after.
> >>
> >> Yeah I mistyped. I liked that to so would get my ack.
> >>
> >>>> If you have a) captured all IS_<tla> and b) Jani acks the series
> >>>> too, I guess go ahead.
> >>>>
> >>>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
> >>>
> >>> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
> >>
> >> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
> >> hidden implementation detail.
> >>
> >>>> P.S.
> >>>> I still think these suck though:
> >>>>
> >>>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>
> >>> I still find it appealing to a) go towards shorter acronyms instead
> >>> of long names, and b) to separate platform and stepping checks
> >>> because they're orthogonal. They're only bundled together for
> >>> historical reasons, and to keep the conditions shorter.
> >>>
> >>> The above could be:
> >>>
> >>> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>
> >> I'd be super pleased with that.
> >
> > Could we use the above suggestion for MTL variants for P/M? also
> replacing MTL with METEORLAKE.
> >
> > Using the format:  IS_FULL_PLATFORM_NAME &&
> IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0).
> >
> > It will change to :
> > 	For M:	IS_METEORLAKE_M(i915) && IS_GRAPHICS_STEP(i915,
> STEP_A0, STEP_B0)
> > 	For P:	IS_METEORLAKE_P(i915) && IS_GRAPHICS_STEP(i915,
> STEP_A0, STEP_B0)
> 
> You could, but you'd only get a meh from me. :) Why you'd insist to keep the
> two checks? Are we expecting IS_METEROLAKE_<X> at some point?

For example FILE PATH:  drivers/gpu/drm/i915/gt/intel_workarounds.c

Multiple occurrences of IS_MTL_GRAPHICS_STEP(i915, M/P, STEP_B0, STEP_FOREVER)
Where P and M are passed explicitly. That why we can not check IS_METEORLAKE()
as single check.
IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))

The IS_GRAPHICS_STEP is generic macro and used by other platforms also. 
On changing the IS_GRAPHICS_STEP  only  for MTL variants is lead to affect the other 
platform. The IS_METEORLAKE_P(i915) or IS_METEORLAKE_M(i915) solves the problem. 
to differentiate the MTL platform variant.

Regards, 
Dnyaneshwar.
> 
> Regards,
> 
> Tvrtko

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Jani Nikula]

On Thu, 13 Jul 2023, "Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> wrote:
>> -----Original Message-----
>> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Sent: Thursday, July 13, 2023 5:55 PM
>> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; Jani Nikula
>> <jani.nikula@linux.intel.com>; intel-gfx@lists.freedesktop.org; Ursulin,
>> Tvrtko <tvrtko.ursulin@intel.com>
>> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>> platform/subplatform defines
>> 
>> 
>> On 13/07/2023 13:12, Bhadane, Dnyaneshwar wrote:
>> >
>> >
>> >> -----Original Message-----
>> >> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> >> Sent: Thursday, July 13, 2023 5:26 PM
>> >> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
>> >> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
>> >> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
>> >> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>> >> platform/subplatform defines
>> >>
>> >>
>> >> On 13/07/2023 10:39, Jani Nikula wrote:
>> >>> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> wrote:
>> >>>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>> >>>>>> -----Original Message-----
>> >>>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>> >>>>>> Sent: Monday, July 10, 2023 4:28 PM
>> >>>>>> To: intel-gfx@lists.freedesktop.org
>> >>>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
>> >>>>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
>> >>>>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>> >>>>>> <dnyaneshwar.bhadane@intel.com>
>> >>>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>> >>>>>> platform/subplatform defines
>> >>>>>>
>> >>>>>> Follow consistent naming convention. Replace MTL with
>> METEORLAKE.
>> >>>>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
>> >>>>>> IS_METEORLAKE_P_GRAPHICS_STEP and
>> >> IS_METEORLAKE_M_GRAPHICS_STEP.
>> >>>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
>> >> IS_MTL_MEDIA_STEP
>> >>>>>> and IS_METEORLAKE_DISPLAY_STEP instead of
>> IS_MTL_DISPLAY_STEP.
>> >>>>>>
>> >>>>> Hi Tvrtko,
>> >>>>> Could you please give the feedback on this ? or suggestion
>> >>>>> regarding the
>> >> approach.
>> >>>>
>> >>>> It's a step in the right direction I just wish we could do all
>> >>>> churning in one go.
>> >>>>
>> >>>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
>> >>>> other I am missing?
>> >>>>
>> >>>> What have we concluded on Jani's suggestion to split it all to
>> >>>> IS_<platform> && IS_<subsys>?
>> >>>
>> >>> IS_<platform> && IS_<step> is what I was after.
>> >>
>> >> Yeah I mistyped. I liked that to so would get my ack.
>> >>
>> >>>> If you have a) captured all IS_<tla> and b) Jani acks the series
>> >>>> too, I guess go ahead.
>> >>>>
>> >>>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
>> >>>
>> >>> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
>> >>
>> >> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
>> >> hidden implementation detail.
>> >>
>> >>>> P.S.
>> >>>> I still think these suck though:
>> >>>>
>> >>>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>> >>>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>> >>>
>> >>> I still find it appealing to a) go towards shorter acronyms instead
>> >>> of long names, and b) to separate platform and stepping checks
>> >>> because they're orthogonal. They're only bundled together for
>> >>> historical reasons, and to keep the conditions shorter.
>> >>>
>> >>> The above could be:
>> >>>
>> >>> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>> >>
>> >> I'd be super pleased with that.
>> >
>> > Could we use the above suggestion for MTL variants for P/M? also
>> replacing MTL with METEORLAKE.
>> >
>> > Using the format:  IS_FULL_PLATFORM_NAME &&
>> IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0).
>> >
>> > It will change to :
>> > 	For M:	IS_METEORLAKE_M(i915) && IS_GRAPHICS_STEP(i915,
>> STEP_A0, STEP_B0)
>> > 	For P:	IS_METEORLAKE_P(i915) && IS_GRAPHICS_STEP(i915,
>> STEP_A0, STEP_B0)
>> 
>> You could, but you'd only get a meh from me. :) Why you'd insist to keep the
>> two checks? Are we expecting IS_METEROLAKE_<X> at some point?
>
> For example FILE PATH:  drivers/gpu/drm/i915/gt/intel_workarounds.c
>
> Multiple occurrences of IS_MTL_GRAPHICS_STEP(i915, M/P, STEP_B0, STEP_FOREVER)
> Where P and M are passed explicitly. That why we can not check IS_METEORLAKE()
> as single check.
> IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>
> The IS_GRAPHICS_STEP is generic macro and used by other platforms also. 
> On changing the IS_GRAPHICS_STEP  only  for MTL variants is lead to affect the other 
> platform. The IS_METEORLAKE_P(i915) or IS_METEORLAKE_M(i915) solves the problem. 
> to differentiate the MTL platform variant.

I've been trying to say all along that we've abstracted the stepping
checks, and we no longer need macros that capture *both* the platform
and the step ranges. They're orthogonal.

If the stepping ranges to check are the same, you don't need to separate
between MTL subplatforms. They'll both match MTL. They'll both match the
stepping ranges, and you can use the generic stepping check.

You'll need to do if
	((IS_MTL_M() && IS_GRAPHICS_STEP(a,b)) ||
	  IS_MTL_P() && IS_GRAPHICS_STEP(c,d))

if a != c && b != d.


BR,
Jani.




>
> Regards, 
> Dnyaneshwar.
>> 
>> Regards,
>> 
>> Tvrtko

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Jani Nikula]

On Thu, 13 Jul 2023, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 13 Jul 2023, "Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> wrote:
>>> -----Original Message-----
>>> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> Sent: Thursday, July 13, 2023 5:55 PM
>>> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>; Jani Nikula
>>> <jani.nikula@linux.intel.com>; intel-gfx@lists.freedesktop.org; Ursulin,
>>> Tvrtko <tvrtko.ursulin@intel.com>
>>> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Shankar, Uma
>>> <uma.shankar@intel.com>
>>> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>>> platform/subplatform defines
>>> 
>>> 
>>> On 13/07/2023 13:12, Bhadane, Dnyaneshwar wrote:
>>> >
>>> >
>>> >> -----Original Message-----
>>> >> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> >> Sent: Thursday, July 13, 2023 5:26 PM
>>> >> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
>>> >> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
>>> >> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
>>> >> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>>> >> platform/subplatform defines
>>> >>
>>> >>
>>> >> On 13/07/2023 10:39, Jani Nikula wrote:
>>> >>> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> wrote:
>>> >>>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>> >>>>>> -----Original Message-----
>>> >>>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>>> >>>>>> Sent: Monday, July 10, 2023 4:28 PM
>>> >>>>>> To: intel-gfx@lists.freedesktop.org
>>> >>>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
>>> >>>>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
>>> >>>>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>>> >>>>>> <dnyaneshwar.bhadane@intel.com>
>>> >>>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>>> >>>>>> platform/subplatform defines
>>> >>>>>>
>>> >>>>>> Follow consistent naming convention. Replace MTL with
>>> METEORLAKE.
>>> >>>>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
>>> >>>>>> IS_METEORLAKE_P_GRAPHICS_STEP and
>>> >> IS_METEORLAKE_M_GRAPHICS_STEP.
>>> >>>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
>>> >> IS_MTL_MEDIA_STEP
>>> >>>>>> and IS_METEORLAKE_DISPLAY_STEP instead of
>>> IS_MTL_DISPLAY_STEP.
>>> >>>>>>
>>> >>>>> Hi Tvrtko,
>>> >>>>> Could you please give the feedback on this ? or suggestion
>>> >>>>> regarding the
>>> >> approach.
>>> >>>>
>>> >>>> It's a step in the right direction I just wish we could do all
>>> >>>> churning in one go.
>>> >>>>
>>> >>>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
>>> >>>> other I am missing?
>>> >>>>
>>> >>>> What have we concluded on Jani's suggestion to split it all to
>>> >>>> IS_<platform> && IS_<subsys>?
>>> >>>
>>> >>> IS_<platform> && IS_<step> is what I was after.
>>> >>
>>> >> Yeah I mistyped. I liked that to so would get my ack.
>>> >>
>>> >>>> If you have a) captured all IS_<tla> and b) Jani acks the series
>>> >>>> too, I guess go ahead.
>>> >>>>
>>> >>>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
>>> >>>
>>> >>> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
>>> >>
>>> >> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
>>> >> hidden implementation detail.
>>> >>
>>> >>>> P.S.
>>> >>>> I still think these suck though:
>>> >>>>
>>> >>>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>> >>>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>> >>>
>>> >>> I still find it appealing to a) go towards shorter acronyms instead
>>> >>> of long names, and b) to separate platform and stepping checks
>>> >>> because they're orthogonal. They're only bundled together for
>>> >>> historical reasons, and to keep the conditions shorter.
>>> >>>
>>> >>> The above could be:
>>> >>>
>>> >>> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>> >>
>>> >> I'd be super pleased with that.
>>> >
>>> > Could we use the above suggestion for MTL variants for P/M? also
>>> replacing MTL with METEORLAKE.
>>> >
>>> > Using the format:  IS_FULL_PLATFORM_NAME &&
>>> IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0).
>>> >
>>> > It will change to :
>>> > 	For M:	IS_METEORLAKE_M(i915) && IS_GRAPHICS_STEP(i915,
>>> STEP_A0, STEP_B0)
>>> > 	For P:	IS_METEORLAKE_P(i915) && IS_GRAPHICS_STEP(i915,
>>> STEP_A0, STEP_B0)
>>> 
>>> You could, but you'd only get a meh from me. :) Why you'd insist to keep the
>>> two checks? Are we expecting IS_METEROLAKE_<X> at some point?
>>
>> For example FILE PATH:  drivers/gpu/drm/i915/gt/intel_workarounds.c
>>
>> Multiple occurrences of IS_MTL_GRAPHICS_STEP(i915, M/P, STEP_B0, STEP_FOREVER)
>> Where P and M are passed explicitly. That why we can not check IS_METEORLAKE()
>> as single check.
>> IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>
>> The IS_GRAPHICS_STEP is generic macro and used by other platforms also. 
>> On changing the IS_GRAPHICS_STEP  only  for MTL variants is lead to affect the other 
>> platform. The IS_METEORLAKE_P(i915) or IS_METEORLAKE_M(i915) solves the problem. 
>> to differentiate the MTL platform variant.
>
> I've been trying to say all along that we've abstracted the stepping
> checks, and we no longer need macros that capture *both* the platform
> and the step ranges. They're orthogonal.
>
> If the stepping ranges to check are the same, you don't need to separate
> between MTL subplatforms. They'll both match MTL. They'll both match the
> stepping ranges, and you can use the generic stepping check.
>
> You'll need to do if
> 	((IS_MTL_M() && IS_GRAPHICS_STEP(a,b)) ||
> 	  IS_MTL_P() && IS_GRAPHICS_STEP(c,d))
>
> if a != c && b != d.

There are some cases where only _M or _P is needed, but then you'd use
the relevant subplatform check.

BR,
Jani.

>
>
> BR,
> Jani.
>
>
>
>
>>
>> Regards, 
>> Dnyaneshwar.
>>> 
>>> Regards,
>>> 
>>> Tvrtko

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Sent: Thursday, July 13, 2023 5:26 PM
> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> 
> On 13/07/2023 10:39, Jani Nikula wrote:
> > On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> >> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
> >>>> -----Original Message-----
> >>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> >>>> Sent: Monday, July 10, 2023 4:28 PM
> >>>> To: intel-gfx@lists.freedesktop.org
> >>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> >>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
> >>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> >>>> <dnyaneshwar.bhadane@intel.com>
> >>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> >>>> platform/subplatform defines
> >>>>
> >>>> Follow consistent naming convention. Replace MTL with METEORLAKE.
> >>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
> >>>> IS_METEORLAKE_P_GRAPHICS_STEP and
> IS_METEORLAKE_M_GRAPHICS_STEP.
> >>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
> IS_MTL_MEDIA_STEP
> >>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
> >>>>
> >>> Hi Tvrtko,
> >>> Could you please give the feedback on this ? or suggestion regarding the
> approach.
> >>
> >> It's a step in the right direction I just wish we could do all
> >> churning in one go.
> >>
> >> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
> >> other I am missing?
> >>
> >> What have we concluded on Jani's suggestion to split it all to
> >> IS_<platform> && IS_<subsys>?
> >
> > IS_<platform> && IS_<step> is what I was after.
> 
> Yeah I mistyped. I liked that to so would get my ack.
> 
> >> If you have a) captured all IS_<tla> and b) Jani acks the series too,
> >> I guess go ahead.
> >>
> >> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
> >
> > For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
> 
> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
> hidden implementation detail.
> 
> >> P.S.
> >> I still think these suck though:
> >>
> >> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >
> > I still find it appealing to a) go towards shorter acronyms instead of
> > long names, and b) to separate platform and stepping checks because
> > they're orthogonal. They're only bundled together for historical
> > reasons, and to keep the conditions shorter.

Changing to acronyms in i915 driver means we need to make all these changes in XE driver as well.
That is why we are insisting to go for full name approach.
https://gitlab.freedesktop.org/drm/xe/kernel/-/blob/drm-xe-next/drivers/gpu/drm/xe/xe_platform_types.h

> >
> > The above could be:
> >
> > 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> 
> I'd be super pleased with that.
> 
> Regards,
> 
> Tvrtko
> 
> >
> >
> > BR,
> > Jani.
> >
> >
> >>
> >> I am not convinced we get anything (apart more source code and more
> >> binary) by having duplicated conditions. I guess I will have to send
> >> that cleanup later.
> >>
> >>>> v2:
> >>>> - Replace IS_MTL_GRAPHICS_STEP with
> >>>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> >>>> - Changed subject prefix mtl instead of MTL (Anusha)
> >>>> v3:
> >>>> - Updated the commit message. (Anusha)
> >>>>
> >>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >>>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
> >>>> Signed-off-by: Dnyaneshwar Bhadane
> <dnyaneshwar.bhadane@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
> >>>>    drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >>>>    drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
> >>>>    .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
> >>>>    drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
> >>>>    .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
> >>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++-------
> ---
> >>>>    drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
> >>>>    .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >>>>    drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
> >>>>    drivers/gpu/drm/i915/i915_perf.c              |  4 +-
> >>>>    15 files changed, 60 insertions(+), 51 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> index 7f8b2d7713c7..6358a8b26172 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> >>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> >>>> intel_atomic_state *state,
> >>>>
> >>>>    	/* Wa_14016291713 */
> >>>>    	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> >>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>>>    	    crtc_state->has_psr) {
> >>>>    		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> >>>>    		return 0;
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> index f7608d363634..8c3158b188ef 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private
> *i915)
> >>>>    				     &pmdemand_state->base,
> >>>>    				     &intel_pmdemand_funcs);
> >>>>
> >>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>>>    		/* Wa_14016740474 */
> >>>>    		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> >>>> DMD_RSP_TIMEOUT_DISABLE);
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> b/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> index 62151abe4748..ecd4e36119b2 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct
> >>>> intel_dp *intel_dp,
> >>>>    	bool set_wa_bit = false;
> >>>>
> >>>>    	/* Wa_14015648006 */
> >>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DISPLAY_VER(dev_priv, 11, 13))
> >>>>    		set_wa_bit |= crtc_state->wm_level_disabled;
> >>>>
> >>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct
> >>>> intel_dp *intel_dp,
> >>>>    		 * All supported adlp panels have 1-based X granularity, this
> may
> >>>>    		 * cause issues if non-supported panels are used.
> >>>>    		 */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >>>>    				     ADLP_1_BASED_X_GRANULARITY);
> >>>>    		else if (IS_ALDERLAKE_P(dev_priv)) @@ -1328,7 +1328,7 @@
> >>>> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >>>>    				     ADLP_1_BASED_X_GRANULARITY);
> >>>>
> >>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >>>> 0,
> >>>>
> >>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> >>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct
> >>>> intel_dp
> >>>> *intel_dp)
> >>>>
> >>>>    	if (intel_dp->psr.psr2_enabled) {
> >>>>    		/* Wa_16012604467:adlp,mtl[a0,b0] */
> >>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> >>>> STEP_B0))
> >>>>    			intel_de_rmw(dev_priv,
> >>>>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >>>>
> >>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7
> +1963,7 @@
> >>>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >>>>    		goto skip_sel_fetch_set_loop;
> >>>>
> >>>>    	/* Wa_14014971492 */
> >>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>>>    	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> >>>>    	    crtc_state->splitter.enable)
> >>>>    		pipe_clip.y1 = 0;
> >>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> index 636a88827a8f..cf1bcc6bff08 100644
> >>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> >>>> drm_i915_private *i915,
> >>>>    				 enum pipe pipe, enum plane_id plane_id)  {
> >>>>    	/* Wa_14017240301 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		return false;
> >>>>
> >>>>    	/* Wa_22011186057 */
> >>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> index 3173e811463d..26656d4be61e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> >>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
> >>>> *gt, u32 *cs, const i915_reg_t inv  static int
> >>>> mtl_dummy_pipe_control(struct i915_request *rq)  {
> >>>>    	/* Wa_14016712196 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
> STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))
> {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
> >>>> STEP_B0))
> >>>> +{
> >>>>    		u32 *cs;
> >>>>
> >>>>    		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32
> >>>> *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >>>>    		     PIPE_CONTROL_FLUSH_ENABLE);
> >>>>
> >>>>    	/* Wa_14016712196 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/* dummy PIPE_CONTROL + depth flush */
> >>>>    		cs = gen12_emit_pipe_control(cs, 0,
> >>>>
> >>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> index 0aff5bb13c53..df4883764ad4 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> >>>> intel_engine_cs *engine,
> >>>>    	 * Wa_22011802037: Prior to doing a reset, ensure CS is
> >>>>    	 * stopped, set ring stop bit and prefetch disable bit to halt CS
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>>>    		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >>>>> mmio_base),
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> index 2ebd937f3b4c..802b31ad982e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> >>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> >>>> intel_engine_cs *engine)
> >>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
> >>>>    	 * to wait for any pending mi force wakeups
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> >>>>    		intel_engine_wait_for_pending_mi_fw(engine);
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> index 0b414eae1683..e30b56be0cb8 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> >>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >>>>    		gt->steering_table[OADDRM] =
> >>>> xelpmp_oaddrm_steering_table;
> >>>>    	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >>>>    		/* Wa_14016747170 */
> >>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
> >>>> STEP_B0))
> >>>>    			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >>>>    					     intel_uncore_read(gt->uncore,
> >>>>
> >>>> MTL_GT_ACTIVITY_FACTOR)); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> index a4ec20aaafe2..80608090fb1e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> >>>> intel_context *ce, u32 *cs)
> >>>>    					      cs, GEN12_GFX_CCS_AUX_NV);
> >>>>
> >>>>    	/* Wa_16014892111 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
> STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0)
> ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
> >>>> STEP_B0)
> >>>> +||
> >>>>    	    IS_DG2(ce->engine->i915))
> >>>>    		cs = dg2_emit_draw_watermark_setting(cs);
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> index 58bb1c55294c..cc8b09b8a7fa 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> >>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> >>>>    		return false;
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> >>>>    	    gt->type == GT_MEDIA) {
> >>>>    		drm_notice(&i915->drm,
> >>>>    			   "Media RC6 disabled on A step\n"); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> index bb948ffc95ca..f840376f107f 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct
> >>>> intel_engine_cs *engine,
> >>>>
> >>>>    	dg2_ctx_gt_tuning_init(engine, wal);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER)
> >>>> ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER))
> >>>>    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF,
> 0, false);  }
> >>>>
> >>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> >>>> intel_engine_cs *engine,
> >>>>
> >>>>    	mtl_ctx_gt_tuning_init(engine, wal);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_14014947963 */
> >>>>    		wa_masked_field_set(wal, VF_PREEMPTION,
> >>>>    				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@
> >>>> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> >>>> *wal)
> >>>>    	/* Wa_22016670082 */
> >>>>    	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0))
> {
> >>>>    		/* Wa_14014830051 */
> >>>>    		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> >>>>
> >>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs
> >>>> *engine, struct i915_wa_list *wal)  {
> >>>>    	struct drm_i915_private *i915 = engine->i915;
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_22014600077 */
> >>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>>>    				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>>>    		/* Wa_1509727124 */
> >>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> >>>> *engine, struct i915_wa_list *wal)
> >>>>
> >>>>    	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> >>>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> >>>>    		/* Wa_22012856258 */
> >>>>    		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >>>>    				 GEN12_DISABLE_READ_SUPPRESSION); @@
> -3016,13 +3016,13 @@
> >>>> general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>
> >>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER)
> >>>> ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
> STEP_FOREVER))
> >>>>    		/* Wa_14017856879 */
> >>>>    		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> >>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/*
> >>>>    		 * Wa_14017066071
> >>>>    		 * Wa_14017654203
> >>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>    		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >>>>    				 MTL_DISABLE_SAMPLER_SC_OOO);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> >>>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> >>>>    		/* Wa_22015279794 */
> >>>>    		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >>>>    				 DISABLE_PREFETCH_INTO_IC);
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >>>>    	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >>>>    		/* Wa_22013037850 */
> >>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> >>>> intel_engine_cs *engine, struct i915_wa_li
> >>>>
> 	DISABLE_128B_EVICTION_COMMAND_UDW);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_PONTEVECCHIO(i915) ||
> >>>>    	    IS_DG2(i915)) {
> >>>>    		/* Wa_22014226127 */
> >>>>    		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> >>>> DISABLE_D8_D16_COASLESCE);
> >>>>    	}
> >>>>
> >>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> >>>>    	    IS_DG2(i915)) {
> >>>>    		/* Wa_18017747507 */
> >>>>    		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> >>>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> >>>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> index 2eb891b270ae..c8e2a110b833 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
> *guc)
> >>>>    		flags |= GUC_WA_GAM_CREDITS;
> >>>>
> >>>>    	/* Wa_14014475959 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>>    	    IS_DG2(gt->i915))
> >>>>    		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> >>>>
> >>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
> *guc)
> >>>>    		flags |= GUC_WA_DUAL_QUEUE;
> >>>>
> >>>>    	/* Wa_22011802037: graphics version 11/12 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(gt->i915) >= 11 &&
> >>>>    	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> >>>>    		flags |= GUC_WA_PRE_PARSER;
> >>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> index a0e3ef1c65d2..6f0e07c4488e 100644
> >>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> >>>> intel_engine_cs *engine)
> >>>>    	 * Wa_22011802037: In addition to stopping the cs, we need
> >>>>    	 * to wait for any pending mi force wakeups
> >>>>    	 */
> >>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> >>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
> >>>> STEP_B0) ||
> >>>>    	    (GRAPHICS_VER(engine->i915) >= 11 &&
> >>>>    	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
> >>>>    		intel_engine_stop_cs(engine);
> >>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct
> >>>> intel_engine_cs
> >>>> *engine)
> >>>>
> >>>>    	/* Wa_14014475959:dg2 */
> >>>>    	if (engine->class == COMPUTE_CLASS)
> >>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> >>>> STEP_B0) ||
> >>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
> >>>> STEP_A0, STEP_B0) ||
> >>>>    		    IS_DG2(engine->i915))
> >>>>    			engine->flags |=
> >>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>>> b/drivers/gpu/drm/i915/i915_drv.h index deb5b9064621..8b4cc3f4df1f
> >>>> 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> >>>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >>>>    	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> >>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since,
> until)
> >>>> +\
> >>>>    	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> >>>> INTEL_SUBPLATFORM_##variant) && \
> >>>>    	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> >>>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> >>>> +	(IS_METEORLAKE_P(__i915) && \
> >>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>> +
> >>>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
> >>>> +	(IS_METEORLAKE_M(__i915) && \
> >>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
> >>>> +
> >>>> +
> >>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
> >>>>    	(IS_METEORLAKE(__i915) && \
> >>>>    	 IS_DISPLAY_STEP(__i915, since, until))
> >>>>
> >>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> >>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
> >>>>    	(IS_METEORLAKE(__i915) && \
> >>>>    	 IS_MEDIA_STEP(__i915, since, until))
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> >>>> b/drivers/gpu/drm/i915/i915_perf.c
> >>>> index 0a111b281578..e943ffbaecbc 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_perf.c
> >>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct
> >>>> i915_perf *perf,
> >>>>    	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings
> >>>> where OAM
> >>>>    	 * does not work as expected.
> >>>>    	 */
> >>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0)
> &&
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> >>>> STEP_C0) &&
> >>>>    	    props->engine->oa_group->type == TYPE_OAM &&
> >>>>    	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> >>>>    		drm_dbg(&perf->i915->drm,
> >>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct
> >>>> drm_i915_private
> >>>> *i915)
> >>>>    	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> >>>>    	 * to indicate that OA media is not supported.
> >>>>    	 */
> >>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> >>>>    		struct intel_gt *gt;
> >>>>    		int i;
> >>>>
> >>>> --
> >>>> 2.34.1
> >>>
> >

Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

[Tvrtko Ursulin]

On 17/07/2023 07:42, Bhadane, Dnyaneshwar wrote:
>> -----Original Message-----
>> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Sent: Thursday, July 13, 2023 5:26 PM
>> To: Jani Nikula <jani.nikula@linux.intel.com>; Bhadane, Dnyaneshwar
>> <dnyaneshwar.bhadane@intel.com>; intel-gfx@lists.freedesktop.org;
>> Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
>> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>> platform/subplatform defines
>>
>>
>> On 13/07/2023 10:39, Jani Nikula wrote:
>>> On Thu, 13 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>>> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>>>>> -----Original Message-----
>>>>>> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
>>>>>> Sent: Monday, July 10, 2023 4:28 PM
>>>>>> To: intel-gfx@lists.freedesktop.org
>>>>>> Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
>>>>>> jani.nikula@linux.intel.com; Srivatsa, Anusha
>>>>>> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
>>>>>> <dnyaneshwar.bhadane@intel.com>
>>>>>> Subject: [v3] drm/i915/mtl: s/MTL/METEORLAKE for
>>>>>> platform/subplatform defines
>>>>>>
>>>>>> Follow consistent naming convention. Replace MTL with METEORLAKE.
>>>>>> Added defines that are replacing IS_MTL_GRAPHICS_STEP with
>>>>>> IS_METEORLAKE_P_GRAPHICS_STEP and
>> IS_METEORLAKE_M_GRAPHICS_STEP.
>>>>>> Also replaced IS_METEORLAKE_MEDIA_STEP instead of
>> IS_MTL_MEDIA_STEP
>>>>>> and IS_METEORLAKE_DISPLAY_STEP instead of IS_MTL_DISPLAY_STEP.
>>>>>>
>>>>> Hi Tvrtko,
>>>>> Could you please give the feedback on this ? or suggestion regarding the
>> approach.
>>>>
>>>> It's a step in the right direction I just wish we could do all
>>>> churning in one go.
>>>>
>>>> Have you captured IS_CFL and IS_CML in the series? ICL? HSW? Any
>>>> other I am missing?
>>>>
>>>> What have we concluded on Jani's suggestion to split it all to
>>>> IS_<platform> && IS_<subsys>?
>>>
>>> IS_<platform> && IS_<step> is what I was after.
>>
>> Yeah I mistyped. I liked that to so would get my ack.
>>
>>>> If you have a) captured all IS_<tla> and b) Jani acks the series too,
>>>> I guess go ahead.
>>>>
>>>> Hm.. what have we concluded to do with IS_JASPERLAKE_EHL?
>>>
>>> For sure it can't be *that*. It's JSL *or* EHL. Not subplatform.
>>
>> IS_ELKHARTLAKE would indeed work and platform/subplatform can be
>> hidden implementation detail.
>>
>>>> P.S.
>>>> I still think these suck though:
>>>>
>>>> 	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>> 	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>
>>> I still find it appealing to a) go towards shorter acronyms instead of
>>> long names, and b) to separate platform and stepping checks because
>>> they're orthogonal. They're only bundled together for historical
>>> reasons, and to keep the conditions shorter.
> 
> Changing to acronyms in i915 driver means we need to make all these changes in XE driver as well.
> That is why we are insisting to go for full name approach.
> https://gitlab.freedesktop.org/drm/xe/kernel/-/blob/drm-xe-next/drivers/gpu/drm/xe/xe_platform_types.h

I didn't get this - platform enum vs macro names?

But anyway, I am okay with long names too. Just want to see _all_ of 
them converted, no overly long IS_JASPERLAKE_ELKHARTLAKE but change to 
IS_ELKHARTLAKE, and the conversion to "IS_METEORLAKE && 
IS_<something>_STEP".

Regards,

Tvrtko

> 
>>>
>>> The above could be:
>>>
>>> 	if (IS_MTL(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>
>> I'd be super pleased with that.
>>
>> Regards,
>>
>> Tvrtko
>>
>>>
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>>>
>>>> I am not convinced we get anything (apart more source code and more
>>>> binary) by having duplicated conditions. I guess I will have to send
>>>> that cleanup later.
>>>>
>>>>>> v2:
>>>>>> - Replace IS_MTL_GRAPHICS_STEP with
>>>>>> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
>>>>>> - Changed subject prefix mtl instead of MTL (Anusha)
>>>>>> v3:
>>>>>> - Updated the commit message. (Anusha)
>>>>>>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>>> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
>>>>>> Signed-off-by: Dnyaneshwar Bhadane
>> <dnyaneshwar.bhadane@intel.com>
>>>>>> ---
>>>>>>     drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>>>>>>     drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>>>>>>     drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>>>>>>     .../drm/i915/display/skl_universal_plane.c    |  4 +-
>>>>>>     drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>>>>>>     drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>>>>>>     .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>>>>>>     drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>>>>>>     drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>>>>>>     drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>>>>>>     drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++-------
>> ---
>>>>>>     drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>>>>>>     .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>>>>>>     drivers/gpu/drm/i915/i915_drv.h               | 15 +++++--
>>>>>>     drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>>>>>>     15 files changed, 60 insertions(+), 51 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>>>>>> index 7f8b2d7713c7..6358a8b26172 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>>>>>> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
>>>>>> intel_atomic_state *state,
>>>>>>
>>>>>>     	/* Wa_14016291713 */
>>>>>>     	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>>>>>> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>>>> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>>>>>>     	    crtc_state->has_psr) {
>>>>>>     		plane_state->no_fbc_reason = "PSR1 enabled
>> (Wa_14016291713)";
>>>>>>     		return 0;
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>>>> index f7608d363634..8c3158b188ef 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>>>>>> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private
>> *i915)
>>>>>>     				     &pmdemand_state->base,
>>>>>>     				     &intel_pmdemand_funcs);
>>>>>>
>>>>>> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>>>> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>>>>>>     		/* Wa_14016740474 */
>>>>>>     		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
>>>>>> DMD_RSP_TIMEOUT_DISABLE);
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>>> index 62151abe4748..ecd4e36119b2 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>>> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct
>>>>>> intel_dp *intel_dp,
>>>>>>     	bool set_wa_bit = false;
>>>>>>
>>>>>>     	/* Wa_14015648006 */
>>>>>> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>>>     	    IS_DISPLAY_VER(dev_priv, 11, 13))
>>>>>>     		set_wa_bit |= crtc_state->wm_level_disabled;
>>>>>>
>>>>>> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct
>>>>>> intel_dp *intel_dp,
>>>>>>     		 * All supported adlp panels have 1-based X granularity, this
>> may
>>>>>>     		 * cause issues if non-supported panels are used.
>>>>>>     		 */
>>>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>>>> STEP_B0))
>>>>>>     			intel_de_rmw(dev_priv,
>>>>>> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>>>>>>     				     ADLP_1_BASED_X_GRANULARITY);
>>>>>>     		else if (IS_ALDERLAKE_P(dev_priv)) @@ -1328,7 +1328,7 @@
>>>>>> static void intel_psr_enable_source(struct intel_dp *intel_dp,
>>>>>>     				     ADLP_1_BASED_X_GRANULARITY);
>>>>>>
>>>>>>     		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>>>> STEP_B0))
>>>>>>     			intel_de_rmw(dev_priv,
>>>>>>
>> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>>>> 0,
>>>>>>
>>>>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>>>>>> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct
>>>>>> intel_dp
>>>>>> *intel_dp)
>>>>>>
>>>>>>     	if (intel_dp->psr.psr2_enabled) {
>>>>>>     		/* Wa_16012604467:adlp,mtl[a0,b0] */
>>>>>> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>>>>> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
>>>>>> STEP_B0))
>>>>>>     			intel_de_rmw(dev_priv,
>>>>>>
>> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>>>>>>
>>>>>> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7
>> +1963,7 @@
>>>>>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>>>>>     		goto skip_sel_fetch_set_loop;
>>>>>>
>>>>>>     	/* Wa_14014971492 */
>>>>>> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>>> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>>>>>>     	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>>>>>>     	    crtc_state->splitter.enable)
>>>>>>     		pipe_clip.y1 = 0;
>>>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> index 636a88827a8f..cf1bcc6bff08 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
>>>>>> drm_i915_private *i915,
>>>>>>     				 enum pipe pipe, enum plane_id plane_id)  {
>>>>>>     	/* Wa_14017240301 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>>>     		return false;
>>>>>>
>>>>>>     	/* Wa_22011186057 */
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>>> index 3173e811463d..26656d4be61e 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
>>>>>> *gt, u32 *cs, const i915_reg_t inv  static int
>>>>>> mtl_dummy_pipe_control(struct i915_request *rq)  {
>>>>>>     	/* Wa_14016712196 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
>> STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))
>> {
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(rq->engine->i915, STEP_A0,
>>>>>> STEP_B0))
>>>>>> +{
>>>>>>     		u32 *cs;
>>>>>>
>>>>>>     		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
>> @@ u32
>>>>>> *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>>>>     		     PIPE_CONTROL_FLUSH_ENABLE);
>>>>>>
>>>>>>     	/* Wa_14016712196 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>>>     		/* dummy PIPE_CONTROL + depth flush */
>>>>>>     		cs = gen12_emit_pipe_control(cs, 0,
>>>>>>
>>>>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
>>>>>> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>>>> index 0aff5bb13c53..df4883764ad4 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>>>>> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
>>>>>> intel_engine_cs *engine,
>>>>>>     	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>>>>>>     	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>>>>>>     	 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>>     	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>>>     	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>>>>     		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
>>>>>>> mmio_base),
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>>>> index 2ebd937f3b4c..802b31ad982e 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>>>>> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
>>>>>> intel_engine_cs *engine)
>>>>>>     	 * Wa_22011802037: In addition to stopping the cs, we need
>>>>>>     	 * to wait for any pending mi force wakeups
>>>>>>     	 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>>     	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>>>     	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>>>>>>     		intel_engine_wait_for_pending_mi_fw(engine);
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>>> index 0b414eae1683..e30b56be0cb8 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>>>>     		gt->steering_table[OADDRM] =
>>>>>> xelpmp_oaddrm_steering_table;
>>>>>>     	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>>>>     		/* Wa_14016747170 */
>>>>>> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>> +		    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0,
>>>>>> STEP_B0))
>>>>>>     			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>>>>     					     intel_uncore_read(gt->uncore,
>>>>>>
>>>>>> MTL_GT_ACTIVITY_FACTOR)); diff --git
>>>>>> a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>> index a4ec20aaafe2..80608090fb1e 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
>>>>>> intel_context *ce, u32 *cs)
>>>>>>     					      cs, GEN12_GFX_CCS_AUX_NV);
>>>>>>
>>>>>>     	/* Wa_16014892111 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
>> STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0)
>> ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(ce->engine->i915, STEP_A0,
>>>>>> STEP_B0)
>>>>>> +||
>>>>>>     	    IS_DG2(ce->engine->i915))
>>>>>>     		cs = dg2_emit_draw_watermark_setting(cs);
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>>>> index 58bb1c55294c..cc8b09b8a7fa 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>>>>> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>>>>>>     		return false;
>>>>>>     	}
>>>>>>
>>>>>> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>>>> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>>>>>     	    gt->type == GT_MEDIA) {
>>>>>>     		drm_notice(&i915->drm,
>>>>>>     			   "Media RC6 disabled on A step\n"); diff --git
>>>>>> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> index bb948ffc95ca..f840376f107f 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct
>>>>>> intel_engine_cs *engine,
>>>>>>
>>>>>>     	dg2_ctx_gt_tuning_init(engine, wal);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
>> STEP_FOREVER)
>>>>>> ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
>> STEP_FOREVER))
>>>>>>     		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF,
>> 0, false);  }
>>>>>>
>>>>>> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
>>>>>> intel_engine_cs *engine,
>>>>>>
>>>>>>     	mtl_ctx_gt_tuning_init(engine, wal);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>>>     		/* Wa_14014947963 */
>>>>>>     		wa_masked_field_set(wal, VF_PREEMPTION,
>>>>>>     				    PREEMPTION_VERTEX_COUNT, 0x4000);
>> @@ -1716,8 +1716,8 @@
>>>>>> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
>>>>>> *wal)
>>>>>>     	/* Wa_22016670082 */
>>>>>>     	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
>> STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_B0))
>> {
>>>>>>     		/* Wa_14014830051 */
>>>>>>     		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>>>>>
>>>>>> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>>>> *engine, struct i915_wa_list *wal)  {
>>>>>>     	struct drm_i915_private *i915 = engine->i915;
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>>>     		/* Wa_22014600077 */
>>>>>>     		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>>>     				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>>>>     	}
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>>     	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>>>     	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>>>     		/* Wa_1509727124 */
>>>>>> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>>>> *engine, struct i915_wa_list *wal)
>>>>>>
>>>>>>     	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>>>     	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>>>>> +	    IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
>>>>>>     		/* Wa_22012856258 */
>>>>>>     		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>>>>     				 GEN12_DISABLE_READ_SUPPRESSION); @@
>> -3016,13 +3016,13 @@
>>>>>> general_render_compute_wa_init(struct
>>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>>>
>>>>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>>>     	}
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_B0,
>> STEP_FOREVER)
>>>>>> ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_B0,
>> STEP_FOREVER))
>>>>>>     		/* Wa_14017856879 */
>>>>>>     		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
>>>>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>>>     		/*
>>>>>>     		 * Wa_14017066071
>>>>>>     		 * Wa_14017654203
>>>>>> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
>>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>>>     		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>>>>     				 MTL_DISABLE_SAMPLER_SC_OOO);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>>> +	if (IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>>>>>>     		/* Wa_22015279794 */
>>>>>>     		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>>>     				 DISABLE_PREFETCH_INTO_IC);
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>>     	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>>>     	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>>>     		/* Wa_22013037850 */
>>>>>> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
>>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>>>
>> 	DISABLE_128B_EVICTION_COMMAND_UDW);
>>>>>>     	}
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>>     	    IS_PONTEVECCHIO(i915) ||
>>>>>>     	    IS_DG2(i915)) {
>>>>>>     		/* Wa_22014226127 */
>>>>>>     		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
>>>>>> DISABLE_D8_D16_COASLESCE);
>>>>>>     	}
>>>>>>
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>>> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>> +	    IS_METEORLAKE_P_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
>>>>>>     	    IS_DG2(i915)) {
>>>>>>     		/* Wa_18017747507 */
>>>>>>     		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
>>>>>> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
>>>>>> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>>> index 2eb891b270ae..c8e2a110b833 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
>> *guc)
>>>>>>     		flags |= GUC_WA_GAM_CREDITS;
>>>>>>
>>>>>>     	/* Wa_14014475959 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
>> STEP_B0) ||
>>>>>>     	    IS_DG2(gt->i915))
>>>>>>     		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>>>>>
>>>>>> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc
>> *guc)
>>>>>>     		flags |= GUC_WA_DUAL_QUEUE;
>>>>>>
>>>>>>     	/* Wa_22011802037: graphics version 11/12 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(gt->i915, STEP_A0,
>> STEP_B0) ||
>>>>>>     	    (GRAPHICS_VER(gt->i915) >= 11 &&
>>>>>>     	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>>>>>>     		flags |= GUC_WA_PRE_PARSER;
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>>> index a0e3ef1c65d2..6f0e07c4488e 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>>> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
>>>>>> intel_engine_cs *engine)
>>>>>>     	 * Wa_22011802037: In addition to stopping the cs, we need
>>>>>>     	 * to wait for any pending mi force wakeups
>>>>>>     	 */
>>>>>> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>>>> +	if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>>     	    (GRAPHICS_VER(engine->i915) >= 11 &&
>>>>>>     	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>>>>>>     		intel_engine_stop_cs(engine);
>>>>>> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct
>>>>>> intel_engine_cs
>>>>>> *engine)
>>>>>>
>>>>>>     	/* Wa_14014475959:dg2 */
>>>>>>     	if (engine->class == COMPUTE_CLASS)
>>>>>> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
>>>>>> STEP_B0) ||
>>>>>> +		if (IS_METEORLAKE_M_GRAPHICS_STEP(engine->i915,
>>>>>> STEP_A0, STEP_B0) ||
>>>>>>     		    IS_DG2(engine->i915))
>>>>>>     			engine->flags |=
>>>>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>>>> b/drivers/gpu/drm/i915/i915_drv.h index deb5b9064621..8b4cc3f4df1f
>>>>>> 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>>> @@ -688,15 +688,24 @@ IS_SUBPLATFORM(const struct
>> drm_i915_private
>>>>>> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>>>>     	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>>>>>
>>>>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>>>>> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since,
>> until)
>>>>>> +\
>>>>>>     	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
>>>>>> INTEL_SUBPLATFORM_##variant) && \
>>>>>>     	 IS_GRAPHICS_STEP(__i915, since, until))
>>>>>>
>>>>>> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>>>>> +#define IS_METEORLAKE_P_GRAPHICS_STEP(__i915, since, until) \
>>>>>> +	(IS_METEORLAKE_P(__i915) && \
>>>>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>>>>> +
>>>>>> +#define IS_METEORLAKE_M_GRAPHICS_STEP(__i915, since, until) \
>>>>>> +	(IS_METEORLAKE_M(__i915) && \
>>>>>> +	 IS_GRAPHICS_STEP(__i915, since, until))
>>>>>> +
>>>>>> +
>>>>>> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>>>>>>     	(IS_METEORLAKE(__i915) && \
>>>>>>     	 IS_DISPLAY_STEP(__i915, since, until))
>>>>>>
>>>>>> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>>>>>> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>>>>>>     	(IS_METEORLAKE(__i915) && \
>>>>>>     	 IS_MEDIA_STEP(__i915, since, until))
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>>>>> b/drivers/gpu/drm/i915/i915_perf.c
>>>>>> index 0a111b281578..e943ffbaecbc 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>>>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>>>>> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct
>>>>>> i915_perf *perf,
>>>>>>     	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings
>>>>>> where OAM
>>>>>>     	 * does not work as expected.
>>>>>>     	 */
>>>>>> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0)
>> &&
>>>>>> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
>>>>>> STEP_C0) &&
>>>>>>     	    props->engine->oa_group->type == TYPE_OAM &&
>>>>>>     	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>>>>>>     		drm_dbg(&perf->i915->drm,
>>>>>> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct
>>>>>> drm_i915_private
>>>>>> *i915)
>>>>>>     	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>>>>>>     	 * to indicate that OA media is not supported.
>>>>>>     	 */
>>>>>> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>>>> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>>>>>>     		struct intel_gt *gt;
>>>>>>     		int i;
>>>>>>
>>>>>> --
>>>>>> 2.34.1
>>>>>
>>>