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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/psr: Include some basic PSR information in the state dump
Date: Thu, 23 Nov 2023 07:15:53 +0000	[thread overview]
Message-ID: <8927fdf7bd10cc90486f01f0ac214ad64a7d6593.camel@intel.com> (raw)
In-Reply-To: <20231122093137.1509-2-ville.syrjala@linux.intel.com>

On Wed, 2023-11-22 at 11:31 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently no one can figure out what the PSR code is doing since
> we're including any of it in the basic state dump. Add at least the
> bare minimum there.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 2d15e82c0b3d..5bcdbf083281 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -262,6 +262,11 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
>                 drm_dbg_kms(&i915->drm, "fec: %s, enhanced framing:
> %s\n",
>                             str_enabled_disabled(pipe_config-
> >fec_enable),
>                             str_enabled_disabled(pipe_config-
> >enhanced_framing));
> +
> +               drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, selective
> fetch: %s\n",
> +                           str_enabled_disabled(pipe_config-
> >has_psr),
> +                           str_enabled_disabled(pipe_config-
> >has_psr2),
> +                           str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));

Maybe you could add pipe_config->has_panel_replay here as well?

BR,

Jouni Högander
 
>         }
>  
>         drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing
> delay: %d\n",


  reply	other threads:[~2023-11-23  7:16 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-22  9:31 [Intel-gfx] [PATCH 1/4] drm/i915/psr: Don't send a NULL VSC SDP Ville Syrjala
2023-11-22  9:31 ` [Intel-gfx] [PATCH 2/4] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
2023-11-23  7:15   ` Hogander, Jouni [this message]
2023-11-22  9:31 ` [Intel-gfx] [PATCH 3/4] drm/i915: Stop printing pipe name as hex Ville Syrjala
2023-11-23  7:16   ` Hogander, Jouni
2023-11-22  9:31 ` [Intel-gfx] [PATCH 4/4] drm/i915: Move the SDP split debug spew to the correct place Ville Syrjala
2023-11-23  7:18   ` Hogander, Jouni
2023-11-23  0:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/psr: Don't send a NULL VSC SDP Patchwork
2023-11-23  0:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-23  7:14 ` [Intel-gfx] [PATCH 1/4] " Hogander, Jouni
2023-11-24  8:32   ` Ville Syrjälä
2023-11-24  0:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork

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