[Intel-gfx] [PATCH v3 00/15] drm/i915: Clean up the DDI clock routing mess

[Intel-gfx] [PATCH v3 00/15] drm/i915: Clean up the DDI clock routing mess

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Sorry for spamming the same series again and again.
v2 still had some issues around FDI, and to fix those
I had to stick a fresh patch to the start of the series.
Hopefully it's now solid.

I have a few more patches already cooked up on top to
clean up the readout side too. But I'm going to try
land this part first.

Ville Syrjälä (15):
  drm/i915: Use intel_ddi_clk_select() for FDI
  drm/i915: Introduce .{enable,disable}_clock() encoder vfuncs
  drm/i915: Extract hsw_ddi_{enable,disable}_clock()
  drm/i915: Extract skl_ddi_{enable,disable}_clock()
  drm/i195: Extract cnl_ddi_{enable,disable}_clock()
  drm/i915: Convert DG1 over to .{enable,disable}_clock()
  drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
  drm/i915: Use intel_de_rmw() for DDI clock routing
  drm/i915: Sprinkle a few missing locks around shared DDI clock
    registers
  drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
  drm/i915: Extract _cnl_ddi_{enable,disable}_clock()
  drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()
  drm/i915: Use .disable_clock() for pll sanitation
  drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
  drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing

 drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 578 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_ddi.h      |   6 +-
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_fdi.c      |   7 +-
 6 files changed, 326 insertions(+), 274 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to put all DDI clock routing code into one place.
Unify the FDI enable sequence to use the standard function
instead of hand rolling its own. The disable sequence already
uses the normal thing.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++-
 drivers/gpu/drm/i915/display/intel_fdi.c | 7 +++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 28877a31adc0..dbef228555a0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -184,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 			port_name(port));
 }
 
-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 {
 	switch (pll->info->id) {
 	case DPLL_ID_WRPLL1:
@@ -1845,8 +1845,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
 }
 
-static void intel_ddi_clk_select(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *crtc_state)
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f9a916cad7e7..e618e1c80252 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -28,7 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				struct intel_encoder *intel_encoder,
 				const struct intel_crtc_state *old_crtc_state,
 				const struct drm_connector_state *old_conn_state);
-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll);
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state);
 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 77df675e607e..dbd6be3342c0 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 temp, i, rx_ctl_val, ddi_pll_sel;
+	u32 temp, i, rx_ctl_val;
 	int n_entries;
 
 	intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
@@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
 	/* Configure Port Clock Select */
-	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
-	intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
-	drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
+	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
+	intel_ddi_clk_select(encoder, crtc_state);
 
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
-- 
2.26.2

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Re: [Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI

[Lucas De Marchi]

On Fri, Feb 05, 2021 at 11:46:20PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>We want to put all DDI clock routing code into one place.
>Unify the FDI enable sequence to use the standard function
>instead of hand rolling its own. The disable sequence already
>uses the normal thing.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_fdi.c | 7 +++----
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 28877a31adc0..dbef228555a0 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -184,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> 			port_name(port));
> }
>
>-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
>+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> {
> 	switch (pll->info->id) {
> 	case DPLL_ID_WRPLL1:
>@@ -1845,8 +1845,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
> }
>
>-static void intel_ddi_clk_select(struct intel_encoder *encoder,
>-				 const struct intel_crtc_state *crtc_state)
>+void intel_ddi_clk_select(struct intel_encoder *encoder,
>+			  const struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
>index f9a916cad7e7..e618e1c80252 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.h
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
>@@ -28,7 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
> 				struct intel_encoder *intel_encoder,
> 				const struct intel_crtc_state *old_crtc_state,
> 				const struct drm_connector_state *old_conn_state);
>-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll);
>+void intel_ddi_clk_select(struct intel_encoder *encoder,
>+			  const struct intel_crtc_state *crtc_state);
> void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> 				  const struct intel_crtc_state *crtc_state);
> void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
>index 77df675e607e..dbd6be3342c0 100644
>--- a/drivers/gpu/drm/i915/display/intel_fdi.c
>+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>@@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> {
> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	u32 temp, i, rx_ctl_val, ddi_pll_sel;
>+	u32 temp, i, rx_ctl_val;
> 	int n_entries;
>
> 	intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
>@@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>
> 	/* Configure Port Clock Select */
>-	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);

you can also unexport hsw_pll_to_ddi_pll_sel() now that it's only used
in intel_ddi.c

with that,


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>-	intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
>-	drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
>+	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
>+	intel_ddi_clk_select(encoder, crtc_state);
>
> 	/* Start the training iterating through available voltages and emphasis,
> 	 * testing each value twice. */
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI

[Ville Syrjälä]

On Sat, Feb 13, 2021 at 09:33:36AM -0800, Lucas De Marchi wrote:
> On Fri, Feb 05, 2021 at 11:46:20PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >We want to put all DDI clock routing code into one place.
> >Unify the FDI enable sequence to use the standard function
> >instead of hand rolling its own. The disable sequence already
> >uses the normal thing.
> >
> >Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
> > drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++-
> > drivers/gpu/drm/i915/display/intel_fdi.c | 7 +++----
> > 3 files changed, 8 insertions(+), 8 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index 28877a31adc0..dbef228555a0 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -184,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> > 			port_name(port));
> > }
> >
> >-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> >+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > {
> > 	switch (pll->info->id) {
> > 	case DPLL_ID_WRPLL1:
> >@@ -1845,8 +1845,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> > 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
> > }
> >
> >-static void intel_ddi_clk_select(struct intel_encoder *encoder,
> >-				 const struct intel_crtc_state *crtc_state)
> >+void intel_ddi_clk_select(struct intel_encoder *encoder,
> >+			  const struct intel_crtc_state *crtc_state)
> > {
> > 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > 	enum port port = encoder->port;
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> >index f9a916cad7e7..e618e1c80252 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.h
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> >@@ -28,7 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
> > 				struct intel_encoder *intel_encoder,
> > 				const struct intel_crtc_state *old_crtc_state,
> > 				const struct drm_connector_state *old_conn_state);
> >-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll);
> >+void intel_ddi_clk_select(struct intel_encoder *encoder,
> >+			  const struct intel_crtc_state *crtc_state);
> > void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> > 				  const struct intel_crtc_state *crtc_state);
> > void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> >diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> >index 77df675e607e..dbd6be3342c0 100644
> >--- a/drivers/gpu/drm/i915/display/intel_fdi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> >@@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > {
> > 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >-	u32 temp, i, rx_ctl_val, ddi_pll_sel;
> >+	u32 temp, i, rx_ctl_val;
> > 	int n_entries;
> >
> > 	intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
> >@@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
> >
> > 	/* Configure Port Clock Select */
> >-	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
> 
> you can also unexport hsw_pll_to_ddi_pll_sel() now that it's only used
> in intel_ddi.c

I guess you skipped reading the other hunks?

> 
> with that,
> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Thanks. Pushed the series. Now on to readout...

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 02/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.

We leave them initially unimplemented, falling back to the old
if-else approach.

v2: Convert the FDI enable sequence

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> #v2
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 29 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_ddi.h      |  4 +--
 .../drm/i915/display/intel_display_types.h    |  6 ++++
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 4 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dbef228555a0..ebfbd68b8e82 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1927,6 +1927,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	}
 }
 
+void intel_ddi_enable_clock(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state)
+{
+	if (encoder->enable_clock)
+		encoder->enable_clock(encoder, crtc_state);
+	else
+		intel_ddi_clk_select(encoder, crtc_state);
+}
+
+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	if (encoder->disable_clock)
+		encoder->disable_clock(encoder);
+	else
+		intel_ddi_clk_disable(encoder);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
@@ -2171,7 +2188,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
 	 * configure the PLL to port mapping here.
 	 */
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
 	if (!intel_phy_is_tc(dev_priv, phy) ||
@@ -2292,7 +2309,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
 	intel_pps_on(intel_dp);
 
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	if (!intel_phy_is_tc(dev_priv, phy) ||
 	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
@@ -2367,7 +2384,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 	dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
@@ -2519,7 +2536,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 					dig_port->ddi_io_power_domain,
 					fetch_and_zero(&dig_port->ddi_io_wakeref));
 
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 }
 
 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
@@ -2542,7 +2559,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
 				dig_port->ddi_io_power_domain,
 				fetch_and_zero(&dig_port->ddi_io_wakeref));
 
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 }
@@ -2642,7 +2659,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
 
 	intel_disable_ddi_buf(encoder, old_crtc_state);
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 
 	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index e618e1c80252..1aa0eedbf342 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -28,8 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				struct intel_encoder *intel_encoder,
 				const struct intel_crtc_state *old_crtc_state,
 				const struct drm_connector_state *old_conn_state);
-void intel_ddi_clk_select(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state);
+void intel_ddi_enable_clock(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state);
 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 307ff4b771f4..3f00c328d188 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -219,6 +219,12 @@ struct intel_encoder {
 	 * encoders have been disabled and suspended.
 	 */
 	void (*shutdown)(struct intel_encoder *encoder);
+	/*
+	 * Enable/disable the clock to the port.
+	 */
+	void (*enable_clock)(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state);
+	void (*disable_clock)(struct intel_encoder *encoder);
 	enum hpd_pin hpd_pin;
 	enum intel_display_power_domain power_domain;
 	/* for communication with audio component; protected by av_mutex */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index dbd6be3342c0..60b29110099a 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -596,7 +596,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 
 	/* Configure Port Clock Select */
 	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
-- 
2.26.2

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[Intel-gfx] [PATCH v3 03/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.

v2: s/dev_priv/i915/ (Lucas)
v3: Deal with FDI

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> #v2
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c |  2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_ddi.h |  3 +++
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 077ebc7e6396..91a8a42b4aa2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1076,6 +1076,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
 		crt->base.enable = hsw_enable_crt;
 		crt->base.disable = hsw_disable_crt;
 		crt->base.post_disable = hsw_post_disable_crt;
+		crt->base.enable_clock = hsw_ddi_enable_clock;
+		crt->base.disable_clock = hsw_ddi_disable_clock;
 	} else {
 		if (HAS_PCH_SPLIT(dev_priv)) {
 			crt->base.compute_config = pch_crt_compute_config;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ebfbd68b8e82..806712020530 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1896,9 +1896,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		intel_de_write(dev_priv, DPLL_CTRL2, val);
 
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       hsw_pll_to_ddi_pll_sel(pll));
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -1921,12 +1918,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	} else if (IS_GEN9_BC(dev_priv)) {
 		intel_de_write(dev_priv, DPLL_CTRL2,
 			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       PORT_CLK_SEL_NONE);
 	}
 }
 
+void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+}
+
+void hsw_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+}
+
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state)
 {
@@ -4073,6 +4088,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
+	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+		encoder->enable_clock = hsw_ddi_enable_clock;
+		encoder->disable_clock = hsw_ddi_disable_clock;
+	}
+
 	if (IS_DG1(dev_priv))
 		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
 	else if (IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 1aa0eedbf342..4a0c1d5c85e7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -30,6 +30,9 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				const struct drm_connector_state *old_conn_state);
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
+void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state);
+void hsw_ddi_disable_clock(struct intel_encoder *encoder);
 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-- 
2.26.2

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[Intel-gfx] [PATCH v3 04/15] drm/i915: Extract skl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DDI clock routing clode for skl/derivatives
into the new encoder vfuncs.

v2: s/dev_priv/i915/ (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 53 +++++++++++++++++-------
 1 file changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 806712020530..3bd7dd28a4fc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1885,17 +1885,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
 		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
-	} else if (IS_GEN9_BC(dev_priv)) {
-		/* DDI -> PLL mapping  */
-		val = intel_de_read(dev_priv, DPLL_CTRL2);
-
-		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-		intel_de_write(dev_priv, DPLL_CTRL2, val);
-
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -1915,12 +1904,43 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		intel_de_write(dev_priv, DPCLKA_CFGCR0,
 			       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-	} else if (IS_GEN9_BC(dev_priv)) {
-		intel_de_write(dev_priv, DPLL_CTRL2,
-			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
 	}
 }
 
+static void skl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+	u32 val;
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	mutex_lock(&i915->dpll.lock);
+
+	val = intel_de_read(i915, DPLL_CTRL2);
+
+	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
+		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
+	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
+
+	intel_de_write(i915, DPLL_CTRL2, val);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
+static void skl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(i915, DPLL_CTRL2,
+		       intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+}
+
 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
 			  const struct intel_crtc_state *crtc_state)
 {
@@ -4088,7 +4108,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv)) {
+		encoder->enable_clock = skl_ddi_enable_clock;
+		encoder->disable_clock = skl_ddi_disable_clock;
+	} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
 		encoder->enable_clock = hsw_ddi_enable_clock;
 		encoder->disable_clock = hsw_ddi_disable_clock;
 	}
-- 
2.26.2

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[Intel-gfx] [PATCH v3 05/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DDI clock routing for CNL into the new vfuncs.

v2: s/dev_priv/i915/ (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 62 ++++++++++++++++--------
 1 file changed, 42 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3bd7dd28a4fc..5c6cd71557a4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1851,7 +1851,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
-	u32 val;
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
@@ -1870,21 +1869,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 			 */
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       DDI_CLK_SEL_MG);
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
-		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
-
-		/*
-		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
-		 * This step and the step before must be done with separate
-		 * register writes.
-		 */
-		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -1901,12 +1885,47 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       DDI_CLK_SEL_NONE);
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		intel_de_write(dev_priv, DPCLKA_CFGCR0,
-			       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 	}
 }
 
+static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+	u32 val;
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	mutex_lock(&i915->dpll.lock);
+
+	val = intel_de_read(i915, DPCLKA_CFGCR0);
+	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	intel_de_write(i915, DPCLKA_CFGCR0, val);
+
+	/*
+	 * "This step and the step before must be
+	 *  done with separate register writes."
+	 */
+	val = intel_de_read(i915, DPCLKA_CFGCR0);
+	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	intel_de_write(i915, DPCLKA_CFGCR0, val);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
+static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(i915, DPCLKA_CFGCR0,
+		       intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+}
+
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -4108,7 +4127,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		encoder->enable_clock = cnl_ddi_enable_clock;
+		encoder->disable_clock = cnl_ddi_disable_clock;
+	} else if (IS_GEN9_BC(dev_priv)) {
 		encoder->enable_clock = skl_ddi_enable_clock;
 		encoder->disable_clock = skl_ddi_disable_clock;
 	} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 06/15] drm/i915: Convert DG1 over to .{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5c6cd71557a4..94df5e897d19 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1597,8 +1597,8 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *crtc_state)
+static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -1631,6 +1631,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -1683,19 +1696,6 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
-}
-
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2477,9 +2477,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (IS_DG1(dev_priv))
-		dg1_map_plls_to_ports(encoder, crtc_state);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_map_plls_to_ports(encoder, crtc_state);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -2680,9 +2678,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (IS_DG1(dev_priv))
-		dg1_unmap_plls_to_ports(encoder);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_unmap_plls_to_ports(encoder);
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
@@ -4127,7 +4123,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		encoder->enable_clock = dg1_ddi_enable_clock;
+		encoder->disable_clock = dg1_ddi_disable_clock;
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		encoder->enable_clock = cnl_ddi_enable_clock;
 		encoder->disable_clock = cnl_ddi_disable_clock;
 	} else if (IS_GEN9_BC(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 07/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
   -> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
   and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
   -> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
   -> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
   the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
   -> these use both TC and combo DDIs with combo PHYs, however they
   always use the full combo style clock selection as per
   icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
   thus get treated the same as 2)

We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here

v2: s/dev_priv/i915/ (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 163 ++++++++++++++---------
 1 file changed, 102 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 94df5e897d19..d6f94a1e320e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1644,8 +1644,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void icl_map_plls_to_ports(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *crtc_state)
+static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -1673,22 +1673,20 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	drm_WARN_ON(&dev_priv->drm,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
-	if (intel_phy_is_combo(dev_priv, phy)) {
-		/*
-		 * Even though this register references DDIs, note that we
-		 * want to pass the PHY rather than the port (DDI).  For
-		 * ICL, port=phy in all cases so it doesn't matter, but for
-		 * EHL the bspec notes the following:
-		 *
-		 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-		 *   Clock Select chooses the PLL for both DDIA and DDID and
-		 *   drives port A in all cases."
-		 */
-		val &= ~mask;
-		val |= sel;
-		intel_de_write(dev_priv, reg, val);
-		intel_de_posting_read(dev_priv, reg);
-	}
+	/*
+	 * Even though this register references DDIs, note that we
+	 * want to pass the PHY rather than the port (DDI).  For
+	 * ICL, port=phy in all cases so it doesn't matter, but for
+	 * EHL the bspec notes the following:
+	 *
+	 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+	 *   Clock Select chooses the PLL for both DDIA and DDID and
+	 *   drives port A in all cases."
+	 */
+	val &= ~mask;
+	val |= sel;
+	intel_de_write(dev_priv, reg, val);
+	intel_de_posting_read(dev_priv, reg);
 
 	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	intel_de_write(dev_priv, reg, val);
@@ -1696,7 +1694,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
+static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
@@ -1845,47 +1843,71 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
 }
 
-void intel_ddi_clk_select(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state)
+static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	/*
+	 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
+	 *  MG does not exist, but the programming is required to ungate DDIC and DDID."
+	 */
+	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
+
+	icl_ddi_combo_enable_clock(encoder, crtc_state);
+}
+
+static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	icl_ddi_combo_disable_clock(encoder);
+
+	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+}
+
+static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
+	enum port port = encoder->port;
 
-	if (drm_WARN_ON(&dev_priv->drm, !pll))
+	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_phy_is_combo(dev_priv, phy))
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
-		else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
-			/*
-			 * MG does not exist but the programming is required
-			 * to ungate DDIC and DDID
-			 */
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       DDI_CLK_SEL_MG);
-	}
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	intel_de_write(i915, DDI_CLK_SEL(port),
+		       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
+
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
+		     ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
+
+	mutex_unlock(&i915->dpll.lock);
 }
 
-static void intel_ddi_clk_disable(struct intel_encoder *encoder)
+static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
 	enum port port = encoder->port;
-	enum phy phy = intel_port_to_phy(dev_priv, port);
-
-	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_phy_is_combo(dev_priv, phy) ||
-		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       DDI_CLK_SEL_NONE);
-	}
+
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
+		     0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
+
+	mutex_unlock(&i915->dpll.lock);
+
+	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 }
 
 static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1986,16 +2008,12 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
 {
 	if (encoder->enable_clock)
 		encoder->enable_clock(encoder, crtc_state);
-	else
-		intel_ddi_clk_select(encoder, crtc_state);
 }
 
 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
 {
 	if (encoder->disable_clock)
 		encoder->disable_clock(encoder);
-	else
-		intel_ddi_clk_disable(encoder);
 }
 
 static void
@@ -2477,9 +2495,6 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
-		icl_map_plls_to_ports(encoder, crtc_state);
-
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -2678,9 +2693,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
-		icl_unmap_plls_to_ports(encoder);
-
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
 		intel_display_power_put(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port),
@@ -4019,6 +4031,16 @@ static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
 	return HPD_PORT_A + port - PORT_A;
 }
 
+static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
+{
+	if (INTEL_GEN(i915) >= 12)
+		return port >= PORT_TC1;
+	else if (INTEL_GEN(i915) >= 11)
+		return port >= PORT_C;
+	else
+		return false;
+}
+
 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
 
@@ -4123,9 +4145,28 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+		encoder->enable_clock = icl_ddi_combo_enable_clock;
+		encoder->disable_clock = icl_ddi_combo_disable_clock;
+	} else if (IS_DG1(dev_priv)) {
 		encoder->enable_clock = dg1_ddi_enable_clock;
 		encoder->disable_clock = dg1_ddi_disable_clock;
+	} else if (IS_JSL_EHL(dev_priv)) {
+		if (intel_ddi_is_tc(dev_priv, port)) {
+			encoder->enable_clock = jsl_ddi_tc_enable_clock;
+			encoder->disable_clock = jsl_ddi_tc_disable_clock;
+		} else {
+			encoder->enable_clock = icl_ddi_combo_enable_clock;
+			encoder->disable_clock = icl_ddi_combo_disable_clock;
+		}
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		if (intel_ddi_is_tc(dev_priv, port)) {
+			encoder->enable_clock = icl_ddi_tc_enable_clock;
+			encoder->disable_clock = icl_ddi_tc_disable_clock;
+		} else {
+			encoder->enable_clock = icl_ddi_combo_enable_clock;
+			encoder->disable_clock = icl_ddi_combo_disable_clock;
+		}
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		encoder->enable_clock = cnl_ddi_enable_clock;
 		encoder->disable_clock = cnl_ddi_disable_clock;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 08/15] drm/i915: Use intel_de_rmw() for DDI clock routing

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 77 +++++++++---------------
 1 file changed, 28 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d6f94a1e320e..0cb20163fb1f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1603,7 +1603,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
@@ -1616,17 +1615,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
 
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-	val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -1638,8 +1632,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -1650,7 +1644,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val, mask, sel;
+	u32 mask, sel;
 	i915_reg_t reg;
 
 	if (IS_ALDERLAKE_S(dev_priv)) {
@@ -1669,10 +1663,6 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
-
 	/*
 	 * Even though this register references DDIs, note that we
 	 * want to pass the PHY rather than the port (DDI).  For
@@ -1683,13 +1673,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	 *   Clock Select chooses the PLL for both DDIA and DDID and
 	 *   drives port A in all cases."
 	 */
-	val &= ~mask;
-	val |= sel;
-	intel_de_write(dev_priv, reg, val);
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_rmw(dev_priv, reg, mask, sel);
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -1698,7 +1685,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 	i915_reg_t reg;
 
 	mutex_lock(&dev_priv->dpll.lock);
@@ -1708,10 +1694,10 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	else
 		reg = ICL_DPCLKA_CFGCR0;
 
-	val = intel_de_read(dev_priv, reg);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
+	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -1916,25 +1902,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
 	mutex_lock(&i915->dpll.lock);
 
-	val = intel_de_read(i915, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-	intel_de_write(i915, DPCLKA_CFGCR0, val);
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
 
 	/*
 	 * "This step and the step before must be
 	 *  done with separate register writes."
 	 */
-	val = intel_de_read(i915, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	intel_de_write(i915, DPCLKA_CFGCR0, val);
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
 
 	mutex_unlock(&i915->dpll.lock);
 }
@@ -1944,8 +1927,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(i915, DPCLKA_CFGCR0,
-		       intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1954,21 +1937,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
 	mutex_lock(&i915->dpll.lock);
 
-	val = intel_de_read(i915, DPLL_CTRL2);
-
-	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-	intel_de_write(i915, DPLL_CTRL2, val);
+	intel_de_rmw(i915, DPLL_CTRL2,
+		     DPLL_CTRL2_DDI_CLK_OFF(port) |
+		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
+		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
 	mutex_unlock(&i915->dpll.lock);
 }
@@ -1978,8 +1957,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(i915, DPLL_CTRL2,
-		       intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+	intel_de_rmw(i915, DPLL_CTRL2,
+		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
 }
 
 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH v3 09/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code attempts to protect the RMWs into global
clock routing registers with a mutex, but forgets to do so
in a few places. Let's remedy that.

Note that at the moment we serialize all modesets onto single
wq, so this shouldn't actually matter. But maybe one day we
wish to attempt parallel modesets again...

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0cb20163fb1f..bd1eac282033 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1927,8 +1927,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&i915->dpll.lock);
+
 	intel_de_rmw(i915, DPCLKA_CFGCR0,
 		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+
+	mutex_unlock(&i915->dpll.lock);
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1957,8 +1961,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&i915->dpll.lock);
+
 	intel_de_rmw(i915, DPLL_CTRL2,
 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
+
+	mutex_unlock(&i915->dpll.lock);
 }
 
 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH v3 10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the shared_dpll code (not sure it wouldn't
oops elsewhere though). So let's unify it all and sprinkle in
the missing WARNs for icl/dg1.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bd1eac282033..c98bdf456958 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1604,6 +1604,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
 	 * used by first 2 phys and last 2 PLLs by last phys
@@ -1661,6 +1664,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
 
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
 	mutex_lock(&dev_priv->dpll.lock);
 
 	/*
-- 
2.26.2

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[Intel-gfx] [PATCH v3 11/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the DPCLKA_CFGCR handling follows a common pattern. Let's
extract that to a small helper that just takes a few parameters
each caller can customize.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 108 +++++++++--------------
 1 file changed, 44 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c98bdf456958..8b7ef5f3ba03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1597,11 +1597,37 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
+{
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
+
+	/*
+	 * "This step and the step before must be
+	 *  done with separate register writes."
+	 */
+	intel_de_rmw(i915, reg, clk_off, 0);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
+static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+				   u32 clk_off)
+{
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, reg, 0, clk_off);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
@@ -1616,16 +1642,10 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
@@ -1633,19 +1653,15 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 mask, sel;
 	i915_reg_t reg;
@@ -1667,24 +1683,8 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	/*
-	 * Even though this register references DDIs, note that we
-	 * want to pass the PHY rather than the port (DDI).  For
-	 * ICL, port=phy in all cases so it doesn't matter, but for
-	 * EHL the bspec notes the following:
-	 *
-	 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-	 *   Clock Select chooses the PLL for both DDIA and DDID and
-	 *   drives port A in all cases."
-	 */
-	intel_de_rmw(dev_priv, reg, mask, sel);
-
-	intel_de_rmw(dev_priv, reg,
-		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_enable_clock(dev_priv, reg, mask, sel,
+			      icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 }
 
 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
@@ -1693,19 +1693,13 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
 	if (IS_ALDERLAKE_S(dev_priv))
 		reg = ADLS_DPCLKA_CFGCR(phy);
 	else
 		reg = ICL_DPCLKA_CFGCR0;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, reg,
-		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_disable_clock(dev_priv, reg,
+			       icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 }
 
 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
@@ -1912,20 +1906,10 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	mutex_lock(&i915->dpll.lock);
-
-	intel_de_rmw(i915, DPCLKA_CFGCR0,
-		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
-		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
-
-	/*
-	 * "This step and the step before must be
-	 *  done with separate register writes."
-	 */
-	intel_de_rmw(i915, DPCLKA_CFGCR0,
-		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
-
-	mutex_unlock(&i915->dpll.lock);
+	_cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,
+			      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+			      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
+			      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
@@ -1933,12 +1917,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	mutex_lock(&i915->dpll.lock);
-
-	intel_de_rmw(i915, DPCLKA_CFGCR0,
-		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-
-	mutex_unlock(&i915->dpll.lock);
+	_cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,
+			       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH v3 12/15] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
have if-ladders inside them. Just provide specialized version for adl-s
and rkl so we don't need any of that.

v2: s/dev_priv/i915/ (Lucas)
    Fix typos in platform names (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 91 ++++++++++++++++--------
 1 file changed, 62 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8b7ef5f3ba03..89962e412f18 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1623,6 +1623,56 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
 	mutex_unlock(&i915->dpll.lock);
 }
 
+static void adls_ddi_enable_clock(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	_cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
+			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void adls_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+	_cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
+			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -1663,43 +1713,23 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 mask, sel;
-	i915_reg_t reg;
-
-	if (IS_ALDERLAKE_S(dev_priv)) {
-		reg = ADLS_DPCLKA_CFGCR(phy);
-		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
-		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
-	} else if (IS_ROCKETLAKE(dev_priv)) {
-		reg = ICL_DPCLKA_CFGCR0;
-		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	} else {
-		reg = ICL_DPCLKA_CFGCR0;
-		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	}
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(dev_priv, reg, mask, sel,
-			      icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
+	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	i915_reg_t reg;
 
-	if (IS_ALDERLAKE_S(dev_priv))
-		reg = ADLS_DPCLKA_CFGCR(phy);
-	else
-		reg = ICL_DPCLKA_CFGCR0;
-
-	_cnl_ddi_disable_clock(dev_priv, reg,
-			       icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
+	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
@@ -4118,9 +4148,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
-		encoder->enable_clock = icl_ddi_combo_enable_clock;
-		encoder->disable_clock = icl_ddi_combo_disable_clock;
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		encoder->enable_clock = adls_ddi_enable_clock;
+		encoder->disable_clock = adls_ddi_disable_clock;
+	} else if (IS_ROCKETLAKE(dev_priv)) {
+		encoder->enable_clock = rkl_ddi_enable_clock;
+		encoder->disable_clock = rkl_ddi_disable_clock;
 	} else if (IS_DG1(dev_priv)) {
 		encoder->enable_clock = dg1_ddi_enable_clock;
 		encoder->disable_clock = dg1_ddi_disable_clock;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 13/15] drm/i915: Use .disable_clock() for pll sanitation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Instead of every new platform having yet another masive
copy of the whole PLL sanitation code, let's just reuse the
.disable_clock() hook for this purpose. We do need to plug
this into the ICL+ DSI code for that, but fortunately it
already has a suitable function we can use.

We do lose the debug message though on account of not bothering
to check if the clock is actually enabled or not before turning
it off. We could introduce yet another vfunc to query the current
state, but not sure it's worth the hassle?

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c   |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c | 92 +-----------------------
 2 files changed, 3 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9d245a689323..a7edfaa09035 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1940,6 +1940,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->pipe_mask = ~0;
 	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
 	encoder->get_power_domains = gen11_dsi_get_power_domains;
+	encoder->disable_clock = gen11_dsi_gate_clocks;
 
 	/* register DSI connector with DRM subsystem */
 	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 89962e412f18..967871c2bf1e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1580,23 +1580,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
-static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-				     enum phy phy)
-{
-	if (IS_ROCKETLAKE(dev_priv)) {
-		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	} else if (intel_phy_is_combo(dev_priv, phy)) {
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	} else if (intel_phy_is_tc(dev_priv, phy)) {
-		enum tc_port tc_port = intel_port_to_tc(dev_priv,
-							(enum port)phy);
-
-		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
-	}
-
-	return 0;
-}
-
 static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
 				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
 {
@@ -1732,75 +1715,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
-static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
-				      u32 port_mask, bool ddi_clk_needed)
-{
-	enum port port;
-	u32 val;
-
-	for_each_port_masked(port, port_mask) {
-		enum phy phy = intel_port_to_phy(dev_priv, port);
-		bool ddi_clk_off;
-
-		val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-		ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-
-		if (ddi_clk_needed == !ddi_clk_off)
-			continue;
-
-		/*
-		 * Punt on the case now where clock is gated, but it would
-		 * be needed by the port. Something else is really broken then.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
-			continue;
-
-		drm_notice(&dev_priv->drm,
-			   "PHY %c is disabled with an ungated DDI clock, gate it\n",
-			   phy_name(phy));
-		val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-		intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	}
-}
-
-static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
-				      u32 port_mask, bool ddi_clk_needed)
-{
-	enum port port;
-	bool ddi_clk_off;
-	u32 val;
-	i915_reg_t reg;
-
-	for_each_port_masked(port, port_mask) {
-		enum phy phy = intel_port_to_phy(dev_priv, port);
-
-		if (IS_ALDERLAKE_S(dev_priv))
-			reg = ADLS_DPCLKA_CFGCR(phy);
-		else
-			reg = ICL_DPCLKA_CFGCR0;
-
-		val = intel_de_read(dev_priv, reg);
-		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
-							      phy);
-
-		if (ddi_clk_needed == !ddi_clk_off)
-			continue;
-
-		/*
-		 * Punt on the case now where clock is gated, but it would
-		 * be needed by the port. Something else is really broken then.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
-			continue;
-
-		drm_notice(&dev_priv->drm,
-			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
-			   phy_name(phy));
-		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-		intel_de_write(dev_priv, reg, val);
-	}
-}
-
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1853,10 +1767,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		ddi_clk_needed = false;
 	}
 
-	if (IS_DG1(dev_priv))
-		dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
-	else
-		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+	if (!ddi_clk_needed && encoder->disable_clock)
+		encoder->disable_clock(encoder);
 }
 
 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH v3 14/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move icl_sanitize_encoder_pll_mapping() out from the middle
of the .{enable,disable}_clock() functions.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++++++++++------------
 1 file changed, 56 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 967871c2bf1e..d4b9410110fd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1715,62 +1715,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
-void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u32 port_mask;
-	bool ddi_clk_needed;
-
-	/*
-	 * In case of DP MST, we sanitize the primary encoder only, not the
-	 * virtual ones.
-	 */
-	if (encoder->type == INTEL_OUTPUT_DP_MST)
-		return;
-
-	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
-		u8 pipe_mask;
-		bool is_mst;
-
-		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
-		/*
-		 * In the unlikely case that BIOS enables DP in MST mode, just
-		 * warn since our MST HW readout is incomplete.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, is_mst))
-			return;
-	}
-
-	port_mask = BIT(encoder->port);
-	ddi_clk_needed = encoder->base.crtc;
-
-	if (encoder->type == INTEL_OUTPUT_DSI) {
-		struct intel_encoder *other_encoder;
-
-		port_mask = intel_dsi_encoder_ports(encoder);
-		/*
-		 * Sanity check that we haven't incorrectly registered another
-		 * encoder using any of the ports of this DSI encoder.
-		 */
-		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
-			if (other_encoder == encoder)
-				continue;
-
-			if (drm_WARN_ON(&dev_priv->drm,
-					port_mask & BIT(other_encoder->port)))
-				return;
-		}
-		/*
-		 * For DSI we keep the ddi clocks gated
-		 * except during enable/disable sequence.
-		 */
-		ddi_clk_needed = false;
-	}
-
-	if (!ddi_clk_needed && encoder->disable_clock)
-		encoder->disable_clock(encoder);
-}
-
 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -1931,6 +1875,62 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
 		encoder->disable_clock(encoder);
 }
 
+void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	u32 port_mask;
+	bool ddi_clk_needed;
+
+	/*
+	 * In case of DP MST, we sanitize the primary encoder only, not the
+	 * virtual ones.
+	 */
+	if (encoder->type == INTEL_OUTPUT_DP_MST)
+		return;
+
+	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
+		u8 pipe_mask;
+		bool is_mst;
+
+		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
+		/*
+		 * In the unlikely case that BIOS enables DP in MST mode, just
+		 * warn since our MST HW readout is incomplete.
+		 */
+		if (drm_WARN_ON(&dev_priv->drm, is_mst))
+			return;
+	}
+
+	port_mask = BIT(encoder->port);
+	ddi_clk_needed = encoder->base.crtc;
+
+	if (encoder->type == INTEL_OUTPUT_DSI) {
+		struct intel_encoder *other_encoder;
+
+		port_mask = intel_dsi_encoder_ports(encoder);
+		/*
+		 * Sanity check that we haven't incorrectly registered another
+		 * encoder using any of the ports of this DSI encoder.
+		 */
+		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
+			if (other_encoder == encoder)
+				continue;
+
+			if (drm_WARN_ON(&dev_priv->drm,
+					port_mask & BIT(other_encoder->port)))
+				return;
+		}
+		/*
+		 * For DSI we keep the ddi clocks gated
+		 * except during enable/disable sequence.
+		 */
+		ddi_clk_needed = false;
+	}
+
+	if (!ddi_clk_needed && encoder->disable_clock)
+		encoder->disable_clock(encoder);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 15/15] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Convert the remaining 'dev_priv's to 'i915's in the DDI
clock routing functions.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 38 ++++++++++++------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4b9410110fd..0f0e68c99589 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1659,23 +1659,23 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	if (drm_WARN_ON(&dev_priv->drm, !pll))
+	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
 	 * used by first 2 phys and last 2 PLLs by last phys
 	 */
-	if (drm_WARN_ON(&dev_priv->drm,
+	if (drm_WARN_ON(&i915->drm,
 			(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
 		return;
 
-	_cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+	_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1683,24 +1683,24 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 
 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+	_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
 			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	if (drm_WARN_ON(&dev_priv->drm, !pll))
+	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1708,10 +1708,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 
 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1877,7 +1877,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
 
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 port_mask;
 	bool ddi_clk_needed;
 
@@ -1897,7 +1897,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		 * In the unlikely case that BIOS enables DP in MST mode, just
 		 * warn since our MST HW readout is incomplete.
 		 */
-		if (drm_WARN_ON(&dev_priv->drm, is_mst))
+		if (drm_WARN_ON(&i915->drm, is_mst))
 			return;
 	}
 
@@ -1912,11 +1912,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		 * Sanity check that we haven't incorrectly registered another
 		 * encoder using any of the ports of this DSI encoder.
 		 */
-		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
+		for_each_intel_encoder(&i915->drm, other_encoder) {
 			if (other_encoder == encoder)
 				continue;
 
-			if (drm_WARN_ON(&dev_priv->drm,
+			if (drm_WARN_ON(&i915->drm,
 					port_mask & BIT(other_encoder->port)))
 				return;
 		}
-- 
2.26.2

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Re: [Intel-gfx] [PATCH v3 15/15] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing

[Lucas De Marchi]

On Fri, Feb 05, 2021 at 11:46:34PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Convert the remaining 'dev_priv's to 'i915's in the DDI
>clock routing functions.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

when merging you may probably need to update this due to conflicts,
though.


Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 38 ++++++++++++------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index d4b9410110fd..0f0e68c99589 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1659,23 +1659,23 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
> static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> 				 const struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	enum phy phy = intel_port_to_phy(i915, encoder->port);
>
>-	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+	if (drm_WARN_ON(&i915->drm, !pll))
> 		return;
>
> 	/*
> 	 * If we fail this, something went very wrong: first 2 PLLs should be
> 	 * used by first 2 phys and last 2 PLLs by last phys
> 	 */
>-	if (drm_WARN_ON(&dev_priv->drm,
>+	if (drm_WARN_ON(&i915->drm,
> 			(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
> 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
> 		return;
>
>-	_cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
>+	_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
> 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
> 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
> 			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>@@ -1683,24 +1683,24 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
>
> static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
> {
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>+	enum phy phy = intel_port_to_phy(i915, encoder->port);
>
>-	_cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
>+	_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
> 			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> 				       const struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	enum phy phy = intel_port_to_phy(i915, encoder->port);
>
>-	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+	if (drm_WARN_ON(&i915->drm, !pll))
> 		return;
>
>-	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
> 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
> 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
> 			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>@@ -1708,10 +1708,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
>
> static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
> {
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>+	enum phy phy = intel_port_to_phy(i915, encoder->port);
>
>-	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
> 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
>@@ -1877,7 +1877,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
>
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> {
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> 	u32 port_mask;
> 	bool ddi_clk_needed;
>
>@@ -1897,7 +1897,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> 		 * In the unlikely case that BIOS enables DP in MST mode, just
> 		 * warn since our MST HW readout is incomplete.
> 		 */
>-		if (drm_WARN_ON(&dev_priv->drm, is_mst))
>+		if (drm_WARN_ON(&i915->drm, is_mst))
> 			return;
> 	}
>
>@@ -1912,11 +1912,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> 		 * Sanity check that we haven't incorrectly registered another
> 		 * encoder using any of the ports of this DSI encoder.
> 		 */
>-		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
>+		for_each_intel_encoder(&i915->drm, other_encoder) {
> 			if (other_encoder == encoder)
> 				continue;
>
>-			if (drm_WARN_ON(&dev_priv->drm,
>+			if (drm_WARN_ON(&i915->drm,
> 					port_mask & BIT(other_encoder->port)))
> 				return;
> 		}
>-- 
>2.26.2
>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess (rev3)
URL   : https://patchwork.freedesktop.org/series/86544/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fb756117b976 drm/i915: Use intel_ddi_clk_select() for FDI
714543e726a1 drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
9d4d81c6506a drm/i915: Extract hsw_ddi_{enable, disable}_clock()
ee8eea416db2 drm/i915: Extract skl_ddi_{enable, disable}_clock()
00e920f321c9 drm/i195: Extract cnl_ddi_{enable, disable}_clock()
77273dccc0c5 drm/i915: Convert DG1 over to .{enable, disable}_clock()
2d0451ebdcae drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12: 
   and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()

total: 0 errors, 1 warnings, 0 checks, 232 lines checked
37115fc6c61d drm/i915: Use intel_de_rmw() for DDI clock routing
9b04986ef8f2 drm/i915: Sprinkle a few missing locks around shared DDI clock registers
f987335252b3 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
89983fc4363a drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
ecafbcddb924 drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock()
47f613addb9d drm/i915: Use .disable_clock() for pll sanitation
649993c52249 drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
418fa1f5fb93 drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up the DDI clock routing mess (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess (rev3)
URL   : https://patchwork.freedesktop.org/series/86544/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up the DDI clock routing mess (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 4408 bytes --]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess (rev3)
URL   : https://patchwork.freedesktop.org/series/86544/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9740 -> Patchwork_19613
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/index.html

Known issues
------------

  Here are the changes found in Patchwork_19613 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-byt-j1900:       NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-byt-j1900/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][2] -> [INCOMPLETE][3] ([i915#2940])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-byt-j1900:       NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-byt-j1900/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][5] ([i915#1436])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-bsw-nick/igt@runner@aborted.html

  * igt@vgem_basic@mmap:
    - fi-tgl-y:           [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/fi-tgl-y/igt@vgem_basic@mmap.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-tgl-y/igt@vgem_basic@mmap.html

  
#### Possible fixes ####

  * igt@prime_self_import@basic-with_one_bo_two_files:
    - fi-tgl-y:           [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 38)
------------------------------

  Additional (1): fi-byt-j1900 
  Missing    (6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9740 -> Patchwork_19613

  CI-20190529: 20190529
  CI_DRM_9740: d0d6b3dabc3c5f35990abedf7361eb27f7123f4d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5993: b1225ec25d5671a985c5bb48739111d2e8a723cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19613: 418fa1f5fb93cd720e9911ed4f809cdd22adeca4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

418fa1f5fb93 drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
649993c52249 drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
47f613addb9d drm/i915: Use .disable_clock() for pll sanitation
ecafbcddb924 drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock()
89983fc4363a drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
f987335252b3 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
9b04986ef8f2 drm/i915: Sprinkle a few missing locks around shared DDI clock registers
37115fc6c61d drm/i915: Use intel_de_rmw() for DDI clock routing
2d0451ebdcae drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
77273dccc0c5 drm/i915: Convert DG1 over to .{enable, disable}_clock()
00e920f321c9 drm/i195: Extract cnl_ddi_{enable, disable}_clock()
ee8eea416db2 drm/i915: Extract skl_ddi_{enable, disable}_clock()
9d4d81c6506a drm/i915: Extract hsw_ddi_{enable, disable}_clock()
714543e726a1 drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
fb756117b976 drm/i915: Use intel_ddi_clk_select() for FDI

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/index.html

[-- Attachment #1.2: Type: text/html, Size: 5396 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up the DDI clock routing mess (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30275 bytes --]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess (rev3)
URL   : https://patchwork.freedesktop.org/series/86544/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9740_full -> Patchwork_19613_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19613_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19613_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19613_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_persistence@many-contexts:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb3/igt@gem_ctx_persistence@many-contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb4/igt@gem_ctx_persistence@many-contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_19613_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb2/igt@feature_discovery@psr2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb6/igt@feature_discovery@psr2.html

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][5] ([i915#3002])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@clone:
    - shard-hsw:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw6/igt@gem_ctx_persistence@clone.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk6/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-glk:          [PASS][14] -> [DMESG-WARN][15] ([i915#118] / [i915#95])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk9/igt@gem_exec_whisper@basic-fds-priority.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk3/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-apl:          NOTRUN -> [SKIP][16] ([fdo#109271]) +39 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl7/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][17] ([i915#768]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [INCOMPLETE][18] ([i915#2502] / [i915#2667])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl7/igt@gem_userptr_blits@vma-merge.html
    - shard-kbl:          NOTRUN -> [INCOMPLETE][19] ([i915#2502] / [i915#2667])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_render_tiledy_blits:
    - shard-iclb:         NOTRUN -> [SKIP][20] ([fdo#109289])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([i915#1436] / [i915#716])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk1/igt@gen9_exec_parse@allowed-all.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk6/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl1/igt@gen9_exec_parse@allowed-single.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl10/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([fdo#112306])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [PASS][26] -> [INCOMPLETE][27] ([i915#2880])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         NOTRUN -> [WARN][28] ([i915#2681] / [i915#2684])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-kbl:          [PASS][31] -> [DMESG-WARN][32] ([i915#180])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl2/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2705])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl7/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_chamelium@hdmi-crc-nonplanar-formats:
    - shard-hsw:          NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw6/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
    - shard-skl:          NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl9/igt@kms_chamelium@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-kbl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl2/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color@pipe-c-ctm-0-75:
    - shard-iclb:         NOTRUN -> [FAIL][38] ([i915#1149] / [i915#315])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@kms_color@pipe-c-ctm-0-75.html

  * igt@kms_color@pipe-d-ctm-0-5:
    - shard-skl:          NOTRUN -> [SKIP][39] ([fdo#109271]) +85 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl8/igt@kms_color@pipe-d-ctm-0-5.html

  * igt@kms_color@pipe-d-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#1149])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@kms_color@pipe-d-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_content_protection@legacy:
    - shard-kbl:          NOTRUN -> [TIMEOUT][43] ([i915#1319]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl2/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          NOTRUN -> [FAIL][44] ([i915#2105])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl8/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([i915#54]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
    - shard-skl:          NOTRUN -> [FAIL][47] ([i915#54]) +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
    - shard-hsw:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533]) +4 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw6/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
    - shard-skl:          [PASS][49] -> [DMESG-WARN][50] ([i915#1982])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl8/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl4/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          NOTRUN -> [FAIL][51] ([i915#2346] / [i915#533])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [PASS][52] -> [FAIL][53] ([i915#2346])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [PASS][54] -> [INCOMPLETE][55] ([i915#155] / [i915#180] / [i915#636])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#109274])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([i915#79]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-tglb:         [PASS][59] -> [FAIL][60] ([i915#2598])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][61] ([i915#180])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-hsw:          [PASS][62] -> [INCOMPLETE][63] ([i915#2055])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw6/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][64] -> [FAIL][65] ([i915#2122]) +3 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2672])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
    - shard-skl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2672])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([fdo#109280]) +3 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271]) +70 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-apl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109278]) +5 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane@plane-position-hole-pipe-c-planes:
    - shard-skl:          [PASS][73] -> [FAIL][74] ([i915#2472])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl4/igt@kms_plane@plane-position-hole-pipe-c-planes.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl10/igt@kms_plane@plane-position-hole-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-skl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][77] -> [FAIL][78] ([fdo#108145] / [i915#265]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([i915#658])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][81] -> [SKIP][82] ([fdo#109441]) +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][83] ([IGT#2])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl7/igt@kms_sysfs_edid_timing.html

  * igt@perf@polling-small-buf:
    - shard-skl:          NOTRUN -> [FAIL][84] ([i915#1722])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl6/igt@perf@polling-small-buf.html

  * igt@prime_nv_pcopy@test3_4:
    - shard-iclb:         NOTRUN -> [SKIP][85] ([fdo#109291])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@prime_nv_pcopy@test3_4.html

  * igt@sysfs_clients@recycle:
    - shard-snb:          [PASS][86] -> [FAIL][87] ([i915#3028])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-snb5/igt@sysfs_clients@recycle.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-snb4/igt@sysfs_clients@recycle.html

  * igt@sysfs_heartbeat_interval@precise@vcs0:
    - shard-hsw:          NOTRUN -> [SKIP][88] ([fdo#109271]) +39 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw6/igt@sysfs_heartbeat_interval@precise@vcs0.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@smoketest:
    - shard-tglb:         [FAIL][89] ([i915#2896]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-tglb2/igt@gem_ctx_persistence@smoketest.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-tglb1/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [DMESG-WARN][91] ([i915#1037] / [i915#180]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl2/igt@gem_eio@in-flight-suspend.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@hang:
    - shard-iclb:         [INCOMPLETE][93] ([i915#1895] / [i915#2295] / [i915#3031]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb2/igt@gem_exec_balancer@hang.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb8/igt@gem_exec_balancer@hang.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][95] ([i915#2842]) -> [PASS][96] +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][97] ([i915#2842]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
    - shard-iclb:         [DMESG-WARN][99] ([i915#2803]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb1/igt@gem_exec_schedule@u-fairslice@rcs0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb1/igt@gem_exec_schedule@u-fairslice@rcs0.html

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-glk:          [DMESG-WARN][101] ([i915#118] / [i915#95]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk3/igt@gem_exec_whisper@basic-queues-priority.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk1/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][103] ([i915#180]) -> [PASS][104] +2 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_selftest@live@client:
    - shard-glk:          [DMESG-FAIL][105] ([i915#3047]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-glk9/igt@i915_selftest@live@client.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-glk3/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@hangcheck:
    - shard-hsw:          [INCOMPLETE][107] ([i915#2782]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw2/igt@i915_selftest@live@hangcheck.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw6/igt@i915_selftest@live@hangcheck.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
    - shard-skl:          [FAIL][109] ([i915#54]) -> [PASS][110] +8 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [FAIL][111] ([i915#96]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-hsw:          [FAIL][113] ([i915#2370]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-skl:          [FAIL][115] ([i915#2346]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [DMESG-WARN][117] ([i915#180]) -> [PASS][118] +3 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [INCOMPLETE][119] ([i915#155] / [i915#794]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
    - shard-skl:          [INCOMPLETE][121] ([i915#198] / [i915#1982]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][123] ([fdo#108145] / [i915#265]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][125] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][127] ([fdo#109441]) -> [PASS][128] +2 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  * igt@sysfs_clients@busy@vcs0:
    - shard-skl:          [FAIL][129] ([i915#3019]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-skl3/igt@sysfs_clients@busy@vcs0.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-skl5/igt@sysfs_clients@busy@vcs0.html

  * {igt@sysfs_clients@recycle-many}:
    - shard-hsw:          [FAIL][131] ([i915#3028]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw7/igt@sysfs_clients@recycle-many.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw2/igt@sysfs_clients@recycle-many.html

  
#### Warnings ####

  * igt@i915_pm_backlight@fade:
    - shard-hsw:          [SKIP][133] ([fdo#109271]) -> [SKIP][134] ([fdo#109271] / [i915#3012])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-hsw6/igt@i915_pm_backlight@fade.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-hsw1/igt@i915_pm_backlight@fade.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][135] ([i915#658]) -> [SKIP][136] ([i915#2920]) +1 similar issue
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][137] ([i915#2920]) -> [SKIP][138] ([i915#658]) +1 similar issue
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#3002] / [i915#602]) -> ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#2295] / [i915#2505] / [i915#3002] / [i915#92])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl2/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl7/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl2/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9740/shard-kbl7/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl6/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl3/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/shard-kbl7/igt@runner@abor

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19613/index.html

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