From: Andi Shyti <andi.shyti@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: Andi Shyti <andi@etezian.org>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Paulo Zanoni <paulo.r.zanoni@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
Andi Shyti <andi.shyti@linux.intel.com>
Subject: Re: [Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Date: Fri, 29 Oct 2021 02:16:10 +0200 [thread overview]
Message-ID: <YXs9Sq87Lukml5wr@intel.intel> (raw)
In-Reply-To: <20211028232053.GG602200@mdroper-desk1.amr.corp.intel.com>
Hi Matt,
> > > - dg1_master_intr_enable(uncore->regs);
> > > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> > > + dg1_master_intr_enable(dev_priv->gt.uncore->regs);
> > > + intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
> >
> > I guess this should also go under a for_each_gt()
>
> DG1_MSTR_TILE_INTR (0x190008) is the top-level, one-per-PCI device
> interrupt register; we always access it via tile0's MMIO . So in this
> case we do want to do this outside the loop since it's not a per-tile
> operation.
yes of course... we are writing to the master interrupt.
> We could probably simplify the dev_priv->gt.uncore parameter to just
> dev_priv->uncore to make this more obvious.
... it would be a nitpick, but nice to have.
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
next prev parent reply other threads:[~2021-10-29 0:16 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 21:56 [Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support Matt Roper
2021-10-08 21:56 ` [Intel-gfx] [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper
2021-10-27 6:22 ` Lucas De Marchi
2021-10-28 14:13 ` Andi Shyti
2021-10-08 21:56 ` [Intel-gfx] [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper
2021-10-27 6:26 ` Lucas De Marchi
2021-10-28 14:17 ` Andi Shyti
2021-10-08 21:56 ` [Intel-gfx] [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper
2021-10-13 12:12 ` Jani Nikula
2021-10-27 6:57 ` Lucas De Marchi
2021-10-27 7:58 ` Jani Nikula
2021-10-08 21:56 ` [Intel-gfx] [PATCH 04/11] drm/i915: Store backpointer to GT in uncore Matt Roper
2021-10-28 14:26 ` Andi Shyti
2021-10-08 21:56 ` [Intel-gfx] [PATCH 05/11] drm/i915: Prepare for multiple gts Matt Roper
2021-10-27 7:01 ` Lucas De Marchi
2021-10-08 21:56 ` [Intel-gfx] [PATCH 06/11] drm/i915: Initial support for per-tile uncore Matt Roper
2021-10-28 15:41 ` Andi Shyti
2021-10-08 21:56 ` [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper
2021-10-08 23:48 ` Matt Roper
2021-10-13 0:55 ` Andi Shyti
2021-10-27 7:13 ` Lucas De Marchi
2021-10-08 21:56 ` [Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper
2021-10-28 16:30 ` Andi Shyti
2021-10-28 23:20 ` Matt Roper
2021-10-29 0:16 ` Andi Shyti [this message]
2021-10-08 21:56 ` [Intel-gfx] [PATCH 09/11] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper
2021-10-08 21:56 ` [Intel-gfx] [PATCH 10/11] drm/i915: Release per-gt resources allocated Matt Roper
2021-10-28 16:33 ` Andi Shyti
2021-10-08 21:56 ` [Intel-gfx] [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper
2021-10-08 23:33 ` [Intel-gfx] [PATCH v2 " Matt Roper
2021-10-11 7:51 ` Tvrtko Ursulin
2021-10-12 23:11 ` Andi Shyti
2021-10-08 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support Patchwork
2021-10-08 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-09 0:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev2) Patchwork
2021-10-09 0:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-09 2:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial multi-tile support Patchwork
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