* [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-21 23:24 ` Radhakrishna Sripada
` (2 more replies)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout Mika Kahola
` (15 subsequent siblings)
16 siblings, 3 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 280 +++++++++++++++---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
.../drm/i915/display/intel_display_types.h | 15 +-
drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
5 files changed, 300 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 83180074b512..dd96bf5e179e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
__intel_cx0_write(i915, port, lane, addr, data, committed);
}
+static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u16 data)
+{
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool committed)
{
@@ -1415,6 +1427,207 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
+static bool intel_c20_use_mplla(u32 clock)
+{
+ /* 10G and 20G rates use MPLLA */
+ if (clock == 312500 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static u8 intel_c20_get_dp_rate(u32 clock)
+{
+ switch (clock) {
+ case 162000: /* 1.62 Gbps DP1.4 */
+ return 0;
+ case 270000: /* 2.7 Gbps DP1.4 */
+ return 1;
+ case 540000: /* 5.4 Gbps DP 1.4 */
+ return 2;
+ case 810000: /* 8.1 Gbps DP1.4 */
+ return 3;
+ case 216000: /* 2.16 Gbps eDP */
+ return 4;
+ case 243000: /* 2.43 Gbps eDP */
+ return 5;
+ case 324000: /* 3.24 Gbps eDP */
+ return 6;
+ case 432000: /* 4.32 Gbps eDP */
+ return 7;
+ case 312500: /* 10 Gbps DP2.0 */
+ return 8;
+ case 421875: /* 13.5 Gbps DP2.0 */
+ return 9;
+ case 625000: /* 20 Gbps DP2.0*/
+ return 10;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static u8 intel_c20_get_hdmi_rate(u32 clock)
+{
+ switch (clock) {
+ case 25175:
+ case 27000:
+ case 74250:
+ case 148500:
+ case 594000:
+ return 0;
+ case 166670: /* 3 Gbps */
+ case 333330: /* 6 Gbps */
+ case 666670: /* 12 Gbps */
+ return 1;
+ case 444440: /* 8 Gbps */
+ return 2;
+ case 555560: /* 10 Gbps */
+ return 3;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static bool is_dp2(u32 clock)
+{
+ /* DP2.0 clock rates */
+ if (clock == 312500 || clock == 421875 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static bool is_hdmi_frl(u32 clock)
+{
+ switch (clock) {
+ case 166670: /* 3 Gbps */
+ case 333330: /* 6 Gbps */
+ case 444440: /* 8 Gbps */
+ case 555560: /* 10 Gbps */
+ case 666670: /* 12 Gbps */
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+
+ /* banks should not be cleared for DPALT/USB4/TBT modes */
+ /* TODO: optimize re-calibration in legacy mode */
+ return intel_tc_port_in_legacy_mode(intel_dig_port);
+}
+
+static void intel_c20_pll_program(struct drm_i915_private *i915,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
+ bool dp = false;
+ int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+ bool cntx;
+ int i;
+
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ dp = true;
+
+ /* 1. Read current context selection */
+ cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
+ PHY_C20_CONTEXT_TOGGLE;
+
+ /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
+ * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA.
+ * Protocol switch is only applicable for MPLLA
+ */
+ if (intel_c20_protocol_switch_valid(encoder)) {
+ for (i = 0; i < 4; i++)
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
+ msleep(4);
+ }
+
+ /* 3. Write SRAM configuration context. If A in use, write configuration to B context */
+ /* 3.1 Tx configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
+ if (cntx)
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+ else
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+ }
+
+ /* 3.2 common configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
+ if (cntx)
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ else
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ }
+
+ /* 3.3 mpllb or mplla configuration */
+ if (intel_c20_use_mplla(pll_state->clock)) {
+ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
+ if (cntx)
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i),
+ pll_state->mplla[i]);
+ else
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i),
+ pll_state->mplla[i]);
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ if (cntx)
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i),
+ pll_state->mpllb[i]);
+ else
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i),
+ pll_state->mpllb[i]);
+ }
+ }
+
+ /* 4. Program custom width to match the link protocol */
+ if (dp) {
+ intel_cx0_write(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
+ is_dp2(pll_state->clock) ? 2 : 0,
+ MB_WRITE_COMMITTED);
+ } else if (is_hdmi_frl(pll_state->clock)) {
+ intel_cx0_write(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
+ 1, MB_WRITE_COMMITTED);
+ } else
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_WIDTH,
+ 0, MB_WRITE_COMMITTED);
+
+ /* 5. For DP or 6. For HDMI */
+ if (dp) {
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
+ BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
+ MB_WRITE_COMMITTED);
+ } else {
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ PHY_C20_IS_FRL,
+ is_hdmi_frl(pll_state->clock) ? 1 : 0,
+ MB_WRITE_COMMITTED);
+
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+ intel_c20_get_hdmi_rate(pll_state->clock),
+ MB_WRITE_COMMITTED);
+ }
+
+ /*
+ * 7. Write Vendor specific registers to toggle context setting to load
+ * the updated programming toggle context bit
+ */
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : 1, MB_WRITE_COMMITTED);
+}
+
int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10pll_state *pll_state)
{
@@ -1456,7 +1669,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+ if (is_hdmi_frl(crtc_state->port_clock))
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
+ else
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
/* TODO: HDMI FRL */
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
@@ -1612,7 +1829,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port po
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
}
-static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
+static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
struct intel_encoder *encoder, int lane_count,
bool lane_reversal)
{
@@ -1620,9 +1837,11 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
enum port port = encoder->port;
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- 0, C10_VDR_CTRL_MSGBUS_ACCESS,
- MB_WRITE_COMMITTED);
+ if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+ intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ PHY_C10_VDR_CONTROL(1), 0,
+ C10_VDR_CTRL_MSGBUS_ACCESS,
+ MB_WRITE_COMMITTED);
/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
@@ -1685,9 +1904,11 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
l1t2, MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- 0, C10_VDR_CTRL_UPDATE_CFG,
- MB_WRITE_COMMITTED);
+ if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+ intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ PHY_C10_VDR_CONTROL(1), 0,
+ C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
}
static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)
@@ -1712,8 +1933,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
return val;
}
-static void intel_c10pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -1721,6 +1942,7 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
+ intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/*
* 1. Program PORT_CLOCK_CTL REGISTER to configure
@@ -1739,13 +1961,16 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
CX0_P2_STATE_READY);
/* 4. Program PHY internal PLL internal registers. */
- intel_c10_pll_program(i915, crtc_state, encoder);
+ if (intel_is_c10phy(i915, phy))
+ intel_c10_pll_program(i915, crtc_state, encoder);
+ else
+ intel_c20_pll_program(i915, crtc_state, encoder);
/*
* 5. Program the enabled and disabled owned PHY lane
* transmitters over message bus
*/
- intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+ intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
/*
* 6. Follow the Display Voltage Frequency Switching - Sequence
@@ -1779,32 +2004,22 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
* 10. Follow the Display Voltage Frequency Switching Sequence After
* Frequency Change. We handle this step in bxt_set_cdclk().
*/
-}
-
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
- intel_wakeref_t wakeref;
-
- wakeref = intel_cx0_phy_transaction_begin(encoder);
-
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
- intel_c10pll_enable(encoder, crtc_state);
/* TODO: enable TBT-ALT mode */
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c10pll_disable(struct intel_encoder *encoder)
+void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ bool is_c10 = intel_is_c10phy(i915, phy);
+ intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Change owned PHY lane power to Disable state. */
intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
- CX0_P2PG_STATE_DISABLE);
+ is_c10 ? CX0_P2PG_STATE_DISABLE :
+ CX0_P4PG_STATE_DISABLE);
/*
* 2. Follow the Display Voltage Frequency Switching Sequence Before
@@ -1842,18 +2057,7 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
-}
-void intel_cx0pll_disable(struct intel_encoder *encoder)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
- intel_wakeref_t wakeref;
-
- wakeref = intel_cx0_phy_transaction_begin(encoder);
-
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
- intel_c10pll_disable(encoder);
intel_cx0_phy_transaction_end(encoder, wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 20024622d0eb..6fcb1680fb54 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -177,4 +177,36 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+/* C20 Registers */
+#define PHY_C20_WR_ADDRESS_L 0xC02
+#define PHY_C20_WR_ADDRESS_H 0xC03
+#define PHY_C20_WR_DATA_L 0xC04
+#define PHY_C20_WR_DATA_H 0xC05
+#define PHY_C20_RD_ADDRESS_L 0xC06
+#define PHY_C20_RD_ADDRESS_H 0xC07
+#define PHY_C20_RD_DATA_L 0xC08
+#define PHY_C20_RD_DATA_H 0xC09
+#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define PHY_C20_IS_FRL REG_BIT8(7)
+#define PHY_C20_VDR_HDMI_RATE 0xD01
+#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
+#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
+#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
+#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
+#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
+#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
+#define C20_MPLLA_FRACEN REG_BIT(14)
+#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
+#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
+#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
+#define C20_MPLLB_FRACEN REG_BIT(13)
+#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
+
+#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 29e4bfab4635..f445f2613adb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3359,7 +3359,8 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *slave_crtc;
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (!intel_phy_is_tc(i915, phy))
+ /* FIXME: Add MTL pll_mgr */
+ if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
return;
intel_update_active_dpll(state, crtc, encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 64b6a5ec4b81..c9927e12b95e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -996,8 +996,21 @@ struct intel_c10pll_state {
u8 pll[20];
};
+struct intel_c20pll_state {
+ u32 clock; /* in kHz */
+ u16 tx[3];
+ u16 cmn[4];
+ union {
+ u16 mplla[10];
+ u16 mpllb[11];
+ };
+};
+
struct intel_cx0pll_state {
- struct intel_c10pll_state c10;
+ union {
+ struct intel_c10pll_state c10;
+ struct intel_c20pll_state c20;
+ };
bool ssc_enabled;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1d28a2560ae0..4361c1ac65c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -53,6 +53,7 @@
#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"
@@ -423,7 +424,14 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
static int mtl_max_source_rate(struct intel_dp *intel_dp)
{
- return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (intel_is_c10phy(i915, phy))
+ return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+
+ return 2000000;
}
static int vbt_max_link_rate(struct intel_dp *intel_dp)
@@ -452,7 +460,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* The values must be in increasing order */
static const int mtl_rates[] = {
162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
- 810000,
+ 810000, 1000000, 1350000, 2000000,
};
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-20 12:40 ` [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming Mika Kahola
@ 2023-04-21 23:24 ` Radhakrishna Sripada
2023-04-24 8:39 ` Kahola, Mika
2023-04-27 3:22 ` Murthy, Arun R
2023-04-28 9:07 ` Andi Shyti
2 siblings, 1 reply; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-21 23:24 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
On Thu, Apr 20, 2023 at 03:40:38PM +0300, Mika Kahola wrote:
> C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
> 4 lane support for c20.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 280 +++++++++++++++---
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h | 15 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> 5 files changed, 300 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 83180074b512..dd96bf5e179e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
> __intel_cx0_write(i915, port, lane, addr, data, committed);
> }
>
> +static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u16 data)
> +{
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool committed)
> {
> @@ -1415,6 +1427,207 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
>
> +static bool intel_c20_use_mplla(u32 clock)
> +{
> + /* 10G and 20G rates use MPLLA */
> + if (clock == 312500 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static u8 intel_c20_get_dp_rate(u32 clock)
> +{
> + switch (clock) {
> + case 162000: /* 1.62 Gbps DP1.4 */
> + return 0;
> + case 270000: /* 2.7 Gbps DP1.4 */
> + return 1;
> + case 540000: /* 5.4 Gbps DP 1.4 */
> + return 2;
> + case 810000: /* 8.1 Gbps DP1.4 */
> + return 3;
> + case 216000: /* 2.16 Gbps eDP */
> + return 4;
> + case 243000: /* 2.43 Gbps eDP */
> + return 5;
> + case 324000: /* 3.24 Gbps eDP */
> + return 6;
> + case 432000: /* 4.32 Gbps eDP */
> + return 7;
> + case 312500: /* 10 Gbps DP2.0 */
> + return 8;
> + case 421875: /* 13.5 Gbps DP2.0 */
> + return 9;
> + case 625000: /* 20 Gbps DP2.0*/
> + return 10;
Worth adding the rate for 6.75 Gbps eDP.
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static u8 intel_c20_get_hdmi_rate(u32 clock)
> +{
> + switch (clock) {
> + case 25175:
> + case 27000:
> + case 74250:
> + case 148500:
> + case 594000:
> + return 0;
> + case 166670: /* 3 Gbps */
> + case 333330: /* 6 Gbps */
> + case 666670: /* 12 Gbps */
> + return 1;
> + case 444440: /* 8 Gbps */
> + return 2;
> + case 555560: /* 10 Gbps */
> + return 3;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static bool is_dp2(u32 clock)
> +{
> + /* DP2.0 clock rates */
> + if (clock == 312500 || clock == 421875 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static bool is_hdmi_frl(u32 clock)
> +{
> + switch (clock) {
> + case 166670: /* 3 Gbps */
> + case 333330: /* 6 Gbps */
> + case 444440: /* 8 Gbps */
> + case 555560: /* 10 Gbps */
> + case 666670: /* 12 Gbps */
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +
> + /* banks should not be cleared for DPALT/USB4/TBT modes */
> + /* TODO: optimize re-calibration in legacy mode */
> + return intel_tc_port_in_legacy_mode(intel_dig_port);
> +}
> +
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
> + bool dp = false;
> + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
The check here should be crtc_state->lane_count > 2 to accomodate 3 lanes for FRL.
> + bool cntx;
> + int i;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + dp = true;
> +
> + /* 1. Read current context selection */
> + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> + PHY_C20_CONTEXT_TOGGLE;
> +
> + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA.
> + * Protocol switch is only applicable for MPLLA
> + */
> + if (intel_c20_protocol_switch_valid(encoder)) {
> + for (i = 0; i < 4; i++)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> + msleep(4);
> + }
> +
> + /* 3. Write SRAM configuration context. If A in use, write configuration to B context */
> + /* 3.1 Tx configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
> + }
> +
> + /* 3.2 common configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> + }
> +
> + /* 3.3 mpllb or mplla configuration */
> + if (intel_c20_use_mplla(pll_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_MPLLA_CNTX_CFG(i),
> + pll_state->mplla[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_MPLLA_CNTX_CFG(i),
> + pll_state->mplla[i]);
> + }
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_MPLLB_CNTX_CFG(i),
> + pll_state->mpllb[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_MPLLB_CNTX_CFG(i),
> + pll_state->mpllb[i]);
> + }
> + }
> +
> + /* 4. Program custom width to match the link protocol */
> + if (dp) {
> + intel_cx0_write(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
> + is_dp2(pll_state->clock) ? 2 : 0,
> + MB_WRITE_COMMITTED);
> + } else if (is_hdmi_frl(pll_state->clock)) {
> + intel_cx0_write(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
> + 1, MB_WRITE_COMMITTED);
> + } else
> + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_WIDTH,
> + 0, MB_WRITE_COMMITTED);
Can we use intel_cx0_rmw above to not disturb the reserved bits?
Also can we consolidate the logic into a static function that gives custom width value taking
pll_state->clock, dp as inputs. Below is sample code.
static int intel_get_c20_custom_width(u32 clock, bool dp)
{
if (dp && is_dp2(clock))
return 2;
else if (is_hdmi_frl(clock))
return 1;
else
return 0
}
intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
C20_CUSTOM_WIDTH_MASK, intel_get_c20_custom_width(pll_state->clock, dp),
MB_WRITE_COMMITTED);
> +
> + /* 5. For DP or 6. For HDMI */
> + if (dp) {
> + intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> + BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
> + MB_WRITE_COMMITTED);
> + } else {
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
Should be lane instead of INTEL_CX0_BOTH_LANES.
> + PHY_C20_IS_FRL,
We need to clear PHY_C20_IS_FRL | PHY_C20_CUSTOM_SERDES_MASK here.
> + is_hdmi_frl(pll_state->clock) ? 1 : 0,
This should be is_hdmi_frl(pll_state->clock) ? PHY_C20_IS_FRL : 0
While at it PHY_C20_IS_FRL might not be an approprate name. Either we
can use BIT(7) like dp case or have a saner name for both DP and HDMI cases.
> + MB_WRITE_COMMITTED);
> +
> + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> + intel_c20_get_hdmi_rate(pll_state->clock),
> + MB_WRITE_COMMITTED);
> + }
> +
> + /*
> + * 7. Write Vendor specific registers to toggle context setting to load
> + * the updated programming toggle context bit
> + */
> + intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : 1, MB_WRITE_COMMITTED);
> +}
> +
> int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_c10pll_state *pll_state)
> {
> @@ -1456,7 +1669,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
>
> val |= XELPDP_FORWARD_CLOCK_UNGATE;
> - val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> +
> + if (is_hdmi_frl(crtc_state->port_clock))
> + val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> + else
> + val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
Add check for DP2.0 10G and 20G and enable SSC if required
XELPDP_SSC_ENABLE_PLLA.
- Radhakrishna(RK) Sripada
> @@ -1612,7 +1829,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port po
> phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> }
>
> -static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> +static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> struct intel_encoder *encoder, int lane_count,
> bool lane_reversal)
> {
> @@ -1620,9 +1837,11 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> enum port port = encoder->port;
>
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> - 0, C10_VDR_CTRL_MSGBUS_ACCESS,
> - MB_WRITE_COMMITTED);
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_MSGBUS_ACCESS,
> + MB_WRITE_COMMITTED);
>
> /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
> l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> @@ -1685,9 +1904,11 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
> l1t2, MB_WRITE_COMMITTED);
>
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> - 0, C10_VDR_CTRL_UPDATE_CFG,
> - MB_WRITE_COMMITTED);
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> }
>
> static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)
> @@ -1712,8 +1933,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> return val;
> }
>
> -static void intel_c10pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> @@ -1721,6 +1942,7 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> INTEL_CX0_LANE0;
> + intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> /*
> * 1. Program PORT_CLOCK_CTL REGISTER to configure
> @@ -1739,13 +1961,16 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> CX0_P2_STATE_READY);
>
> /* 4. Program PHY internal PLL internal registers. */
> - intel_c10_pll_program(i915, crtc_state, encoder);
> + if (intel_is_c10phy(i915, phy))
> + intel_c10_pll_program(i915, crtc_state, encoder);
> + else
> + intel_c20_pll_program(i915, crtc_state, encoder);
>
> /*
> * 5. Program the enabled and disabled owned PHY lane
> * transmitters over message bus
> */
> - intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
> + intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
>
> /*
> * 6. Follow the Display Voltage Frequency Switching - Sequence
> @@ -1779,32 +2004,22 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> * 10. Follow the Display Voltage Frequency Switching Sequence After
> * Frequency Change. We handle this step in bxt_set_cdclk().
> */
> -}
> -
> -void intel_cx0pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> - intel_wakeref_t wakeref;
> -
> - wakeref = intel_cx0_phy_transaction_begin(encoder);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> - intel_c10pll_enable(encoder, crtc_state);
>
> /* TODO: enable TBT-ALT mode */
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> -static void intel_c10pll_disable(struct intel_encoder *encoder)
> +void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + bool is_c10 = intel_is_c10phy(i915, phy);
> + intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> /* 1. Change owned PHY lane power to Disable state. */
> intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> - CX0_P2PG_STATE_DISABLE);
> + is_c10 ? CX0_P2PG_STATE_DISABLE :
> + CX0_P4PG_STATE_DISABLE);
>
> /*
> * 2. Follow the Display Voltage Frequency Switching Sequence Before
> @@ -1842,18 +2057,7 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
> XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
> -}
>
> -void intel_cx0pll_disable(struct intel_encoder *encoder)
> -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> - intel_wakeref_t wakeref;
> -
> - wakeref = intel_cx0_phy_transaction_begin(encoder);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> - intel_c10pll_disable(encoder);
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 20024622d0eb..6fcb1680fb54 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -177,4 +177,36 @@
> #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
> #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
>
> +/* C20 Registers */
> +#define PHY_C20_WR_ADDRESS_L 0xC02
> +#define PHY_C20_WR_ADDRESS_H 0xC03
> +#define PHY_C20_WR_DATA_L 0xC04
> +#define PHY_C20_WR_DATA_H 0xC05
> +#define PHY_C20_RD_ADDRESS_L 0xC06
> +#define PHY_C20_RD_ADDRESS_H 0xC07
> +#define PHY_C20_RD_DATA_L 0xC08
> +#define PHY_C20_RD_DATA_H 0xC09
> +#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> +#define PHY_C20_IS_FRL REG_BIT8(7)
> +#define PHY_C20_VDR_HDMI_RATE 0xD01
> +#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> +#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
> +#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
> +#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> +#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
> +#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
> +#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
> +#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
> +#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
> +#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
> +#define C20_MPLLA_FRACEN REG_BIT(14)
> +#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
> +#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
> +#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
> +#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
> +#define C20_MPLLB_FRACEN REG_BIT(13)
> +#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> +
> +#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
> +
> #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 29e4bfab4635..f445f2613adb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3359,7 +3359,8 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *slave_crtc;
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> - if (!intel_phy_is_tc(i915, phy))
> + /* FIXME: Add MTL pll_mgr */
> + if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
> return;
>
> intel_update_active_dpll(state, crtc, encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 64b6a5ec4b81..c9927e12b95e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -996,8 +996,21 @@ struct intel_c10pll_state {
> u8 pll[20];
> };
>
> +struct intel_c20pll_state {
> + u32 clock; /* in kHz */
> + u16 tx[3];
> + u16 cmn[4];
> + union {
> + u16 mplla[10];
> + u16 mpllb[11];
> + };
> +};
> +
> struct intel_cx0pll_state {
> - struct intel_c10pll_state c10;
> + union {
> + struct intel_c10pll_state c10;
> + struct intel_c20pll_state c20;
> + };
> bool ssc_enabled;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1d28a2560ae0..4361c1ac65c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -53,6 +53,7 @@
> #include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> @@ -423,7 +424,14 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
>
> static int mtl_max_source_rate(struct intel_dp *intel_dp)
> {
> - return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> +
> + return 2000000;
> }
>
> static int vbt_max_link_rate(struct intel_dp *intel_dp)
> @@ -452,7 +460,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* The values must be in increasing order */
> static const int mtl_rates[] = {
> 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> - 810000,
> + 810000, 1000000, 1350000, 2000000,
> };
> static const int icl_rates[] = {
> 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-21 23:24 ` Radhakrishna Sripada
@ 2023-04-24 8:39 ` Kahola, Mika
0 siblings, 0 replies; 47+ messages in thread
From: Kahola, Mika @ 2023-04-24 8:39 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Saturday, April 22, 2023 2:24 AM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> On Thu, Apr 20, 2023 at 03:40:38PM +0300, Mika Kahola wrote:
> > C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> > HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence.
> > add
> > 4 lane support for c20.
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 280
> > +++++++++++++++--- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 ++
> > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> > .../drm/i915/display/intel_display_types.h | 15 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> > 5 files changed, 300 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 83180074b512..dd96bf5e179e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private
> *i915, enum port port,
> > __intel_cx0_write(i915, port, lane, addr, data, committed); }
> >
> > +static void intel_c20_sram_write(struct drm_i915_private *i915, enum port
> port,
> > + int lane, u16 addr, u16 data)
> > +{
> > + assert_dc_off(i915);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8,
> 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff,
> > +0);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > +1); }
> > +
> > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > int lane, u16 addr, u8 clear, u8 set, bool committed) {
> @@
> > -1415,6 +1427,207 @@ void intel_c10pll_dump_hw_state(struct
> drm_i915_private *i915,
> > i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
> >
> > +static bool intel_c20_use_mplla(u32 clock) {
> > + /* 10G and 20G rates use MPLLA */
> > + if (clock == 312500 || clock == 625000)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > +static u8 intel_c20_get_dp_rate(u32 clock) {
> > + switch (clock) {
> > + case 162000: /* 1.62 Gbps DP1.4 */
> > + return 0;
> > + case 270000: /* 2.7 Gbps DP1.4 */
> > + return 1;
> > + case 540000: /* 5.4 Gbps DP 1.4 */
> > + return 2;
> > + case 810000: /* 8.1 Gbps DP1.4 */
> > + return 3;
> > + case 216000: /* 2.16 Gbps eDP */
> > + return 4;
> > + case 243000: /* 2.43 Gbps eDP */
> > + return 5;
> > + case 324000: /* 3.24 Gbps eDP */
> > + return 6;
> > + case 432000: /* 4.32 Gbps eDP */
> > + return 7;
> > + case 312500: /* 10 Gbps DP2.0 */
> > + return 8;
> > + case 421875: /* 13.5 Gbps DP2.0 */
> > + return 9;
> > + case 625000: /* 20 Gbps DP2.0*/
> > + return 10;
> Worth adding the rate for 6.75 Gbps eDP.
Definitely. As per BSPec it seems that we are missing also 6.48Gbps rate as well i.e. return value "11".
>
> > + default:
> > + MISSING_CASE(clock);
> > + return 0;
> > + }
> > +}
> > +
> > +static u8 intel_c20_get_hdmi_rate(u32 clock) {
> > + switch (clock) {
> > + case 25175:
> > + case 27000:
> > + case 74250:
> > + case 148500:
> > + case 594000:
> > + return 0;
> > + case 166670: /* 3 Gbps */
> > + case 333330: /* 6 Gbps */
> > + case 666670: /* 12 Gbps */
> > + return 1;
> > + case 444440: /* 8 Gbps */
> > + return 2;
> > + case 555560: /* 10 Gbps */
> > + return 3;
> > + default:
> > + MISSING_CASE(clock);
> > + return 0;
> > + }
> > +}
> > +
> > +static bool is_dp2(u32 clock)
> > +{
> > + /* DP2.0 clock rates */
> > + if (clock == 312500 || clock == 421875 || clock == 625000)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > +static bool is_hdmi_frl(u32 clock)
> > +{
> > + switch (clock) {
> > + case 166670: /* 3 Gbps */
> > + case 333330: /* 6 Gbps */
> > + case 444440: /* 8 Gbps */
> > + case 555560: /* 10 Gbps */
> > + case 666670: /* 12 Gbps */
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool intel_c20_protocol_switch_valid(struct intel_encoder
> > +*encoder) {
> > + struct intel_digital_port *intel_dig_port =
> > +enc_to_dig_port(encoder);
> > +
> > + /* banks should not be cleared for DPALT/USB4/TBT modes */
> > + /* TODO: optimize re-calibration in legacy mode */
> > + return intel_tc_port_in_legacy_mode(intel_dig_port);
> > +}
> > +
> > +static void intel_c20_pll_program(struct drm_i915_private *i915,
> > + const struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c20pll_state *pll_state = &crtc_state-
> >cx0pll_state.c20;
> > + bool dp = false;
> > + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES :
> > +INTEL_CX0_LANE0;
> The check here should be crtc_state->lane_count > 2 to accomodate 3 lanes for
> FRL.
>
> > + bool cntx;
> > + int i;
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + dp = true;
> > +
> > + /* 1. Read current context selection */
> > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> > + PHY_C20_CONTEXT_TOGGLE;
> > +
> > + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> > + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable
> MPLLA.
> > + * Protocol switch is only applicable for MPLLA
> > + */
> > + if (intel_c20_protocol_switch_valid(encoder)) {
> > + for (i = 0; i < 4; i++)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> > + msleep(4);
> > + }
> > +
> > + /* 3. Write SRAM configuration context. If A in use, write configuration
> to B context */
> > + /* 3.1 Tx configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> > + if (cntx)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
> > + else
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
> > + }
> > +
> > + /* 3.2 common configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> > + if (cntx)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> > + else
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> > + }
> > +
> > + /* 3.3 mpllb or mplla configuration */
> > + if (intel_c20_use_mplla(pll_state->clock)) {
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> > + if (cntx)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> > +
> PHY_C20_A_MPLLA_CNTX_CFG(i),
> > + pll_state->mplla[i]);
> > + else
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> > +
> PHY_C20_B_MPLLA_CNTX_CFG(i),
> > + pll_state->mplla[i]);
> > + }
> > + } else {
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> > + if (cntx)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> > +
> PHY_C20_A_MPLLB_CNTX_CFG(i),
> > + pll_state->mpllb[i]);
> > + else
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> > +
> PHY_C20_B_MPLLB_CNTX_CFG(i),
> > + pll_state->mpllb[i]);
> > + }
> > + }
> > +
> > + /* 4. Program custom width to match the link protocol */
> > + if (dp) {
> > + intel_cx0_write(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_WIDTH,
> > + is_dp2(pll_state->clock) ? 2 : 0,
> > + MB_WRITE_COMMITTED);
> > + } else if (is_hdmi_frl(pll_state->clock)) {
> > + intel_cx0_write(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_WIDTH,
> > + 1, MB_WRITE_COMMITTED);
> > + } else
> > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_CUSTOM_WIDTH,
> > + 0, MB_WRITE_COMMITTED);
> Can we use intel_cx0_rmw above to not disturb the reserved bits?
> Also can we consolidate the logic into a static function that gives custom width
> value taking pll_state->clock, dp as inputs. Below is sample code.
>
> static int intel_get_c20_custom_width(u32 clock, bool dp) {
> if (dp && is_dp2(clock))
> return 2;
> else if (is_hdmi_frl(clock))
> return 1;
> else
> return 0
>
> }
Yes, we could switch to use intel_cx0_rmw() just to make sure that bits are not disturbed. I will update this.
>
> intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_WIDTH,
> C20_CUSTOM_WIDTH_MASK,
> intel_get_c20_custom_width(pll_state->clock, dp),
> MB_WRITE_COMMITTED);
> > +
> > + /* 5. For DP or 6. For HDMI */
> > + if (dp) {
> > + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> > + BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> > + BIT(6) |
> PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
> > + MB_WRITE_COMMITTED);
> > + } else {
> > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > +PHY_C20_VDR_CUSTOM_SERDES_RATE,
> Should be lane instead of INTEL_CX0_BOTH_LANES.
> > + PHY_C20_IS_FRL,
> We need to clear PHY_C20_IS_FRL | PHY_C20_CUSTOM_SERDES_MASK here.
> > + is_hdmi_frl(pll_state->clock) ? 1 : 0,
> This should be is_hdmi_frl(pll_state->clock) ? PHY_C20_IS_FRL : 0 While at it
> PHY_C20_IS_FRL might not be an approprate name. Either we can use BIT(7) like
> dp case or have a saner name for both DP and HDMI cases.
Right, I think we could go with BIT(7) naming convention here as this approach is already used with dp case.
> > + MB_WRITE_COMMITTED);
> > +
> > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_HDMI_RATE,
> > + intel_c20_get_hdmi_rate(pll_state->clock),
> > + MB_WRITE_COMMITTED);
> > + }
> > +
> > + /*
> > + * 7. Write Vendor specific registers to toggle context setting to load
> > + * the updated programming toggle context bit
> > + */
> > + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> > + PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : 1,
> MB_WRITE_COMMITTED); }
> > +
> > int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> > const struct intel_c10pll_state *pll_state) {
> @@ -1456,7
> > +1669,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder
> *encoder,
> > val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
> >
> > val |= XELPDP_FORWARD_CLOCK_UNGATE;
> > - val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> > +
> > + if (is_hdmi_frl(crtc_state->port_clock))
> > + val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> > + else
> > + val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> >
> > /* TODO: HDMI FRL */
> > /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> Add check for DP2.0 10G and 20G and enable SSC if required
> XELPDP_SSC_ENABLE_PLLA.
>
Thanks for the review and comments!
-Mika-
> - Radhakrishna(RK) Sripada
> > @@ -1612,7 +1829,7 @@ static void intel_cx0_phy_lane_reset(struct
> drm_i915_private *i915, enum port po
> > phy_name(phy),
> XELPDP_PORT_RESET_END_TIMEOUT); }
> >
> > -static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> > +static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> > struct intel_encoder *encoder, int
> lane_count,
> > bool lane_reversal)
> > {
> > @@ -1620,9 +1837,11 @@ static void intel_c10_program_phy_lane(struct
> drm_i915_private *i915,
> > bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> > enum port port = encoder->port;
> >
> > - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > - 0, C10_VDR_CTRL_MSGBUS_ACCESS,
> > - MB_WRITE_COMMITTED);
> > + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> > + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> > + PHY_C10_VDR_CONTROL(1), 0,
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> > + MB_WRITE_COMMITTED);
> >
> > /* TODO: DP-alt MFD case where only one PHY lane should be
> programmed. */
> > l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> > PHY_CX0_TX_CONTROL(1, 2)); @@ -1685,9 +1904,11 @@ static void
> intel_c10_program_phy_lane(struct drm_i915_private *i915,
> > intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(2, 2),
> > l1t2, MB_WRITE_COMMITTED);
> >
> > - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > - 0, C10_VDR_CTRL_UPDATE_CFG,
> > - MB_WRITE_COMMITTED);
> > + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> > + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> > + PHY_C10_VDR_CONTROL(1), 0,
> > + C10_VDR_CTRL_UPDATE_CFG,
> > + MB_WRITE_COMMITTED);
> > }
> >
> > static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) @@ -1712,8
> > +1933,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> > return val;
> > }
> >
> > -static void intel_c10pll_enable(struct intel_encoder *encoder,
> > - const struct intel_crtc_state *crtc_state)
> > +void intel_cx0pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port); @@ -1721,6
> > +1942,7 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> > bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > INTEL_CX0_LANE0;
> > + intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
> >
> > /*
> > * 1. Program PORT_CLOCK_CTL REGISTER to configure @@ -1739,13
> > +1961,16 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> > CX0_P2_STATE_READY);
> >
> > /* 4. Program PHY internal PLL internal registers. */
> > - intel_c10_pll_program(i915, crtc_state, encoder);
> > + if (intel_is_c10phy(i915, phy))
> > + intel_c10_pll_program(i915, crtc_state, encoder);
> > + else
> > + intel_c20_pll_program(i915, crtc_state, encoder);
> >
> > /*
> > * 5. Program the enabled and disabled owned PHY lane
> > * transmitters over message bus
> > */
> > - intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count,
> lane_reversal);
> > + intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
> > +lane_reversal);
> >
> > /*
> > * 6. Follow the Display Voltage Frequency Switching - Sequence @@
> > -1779,32 +2004,22 @@ static void intel_c10pll_enable(struct intel_encoder
> *encoder,
> > * 10. Follow the Display Voltage Frequency Switching Sequence After
> > * Frequency Change. We handle this step in bxt_set_cdclk().
> > */
> > -}
> > -
> > -void intel_cx0pll_enable(struct intel_encoder *encoder,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - enum phy phy = intel_port_to_phy(i915, encoder->port);
> > - intel_wakeref_t wakeref;
> > -
> > - wakeref = intel_cx0_phy_transaction_begin(encoder);
> > -
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > - intel_c10pll_enable(encoder, crtc_state);
> >
> > /* TODO: enable TBT-ALT mode */
> > intel_cx0_phy_transaction_end(encoder, wakeref); }
> >
> > -static void intel_c10pll_disable(struct intel_encoder *encoder)
> > +void intel_cx0pll_disable(struct intel_encoder *encoder)
> > {
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > + bool is_c10 = intel_is_c10phy(i915, phy);
> > + intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
> >
> > /* 1. Change owned PHY lane power to Disable state. */
> > intel_cx0_powerdown_change_sequence(i915, encoder->port,
> INTEL_CX0_BOTH_LANES,
> > - CX0_P2PG_STATE_DISABLE);
> > + is_c10 ? CX0_P2PG_STATE_DISABLE :
> > + CX0_P4PG_STATE_DISABLE);
> >
> > /*
> > * 2. Follow the Display Voltage Frequency Switching Sequence Before
> > @@ -1842,18 +2057,7 @@ static void intel_c10pll_disable(struct
> intel_encoder *encoder)
> > XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > XELPDP_FORWARD_CLOCK_UNGATE, 0); -}
> >
> > -void intel_cx0pll_disable(struct intel_encoder *encoder) -{
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - enum phy phy = intel_port_to_phy(i915, encoder->port);
> > - intel_wakeref_t wakeref;
> > -
> > - wakeref = intel_cx0_phy_transaction_begin(encoder);
> > -
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > - intel_c10pll_disable(encoder);
> > intel_cx0_phy_transaction_end(encoder, wakeref); }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > index 20024622d0eb..6fcb1680fb54 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > @@ -177,4 +177,36 @@
> > #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 +
> (control))
> > #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
> >
> > +/* C20 Registers */
> > +#define PHY_C20_WR_ADDRESS_L 0xC02
> > +#define PHY_C20_WR_ADDRESS_H 0xC03
> > +#define PHY_C20_WR_DATA_L 0xC04
> > +#define PHY_C20_WR_DATA_H 0xC05
> > +#define PHY_C20_RD_ADDRESS_L 0xC06
> > +#define PHY_C20_RD_ADDRESS_H 0xC07
> > +#define PHY_C20_RD_DATA_L 0xC08
> > +#define PHY_C20_RD_DATA_H 0xC09
> > +#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> > +#define PHY_C20_IS_FRL REG_BIT8(7)
> > +#define PHY_C20_VDR_HDMI_RATE 0xD01
> > +#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> > +#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
> > +#define PHY_C20_CUSTOM_SERDES(val)
> REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
> > +#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> > +#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
> > +#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
> > +#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
> > +#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
> > +#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
> > +#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
> > +#define C20_MPLLA_FRACEN REG_BIT(14)
> > +#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
> > +#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
> > +#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
> > +#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
> > +#define C20_MPLLB_FRACEN REG_BIT(13)
> > +#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> > +
> > +#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D +
> (idx))
> > +
> > #endif /* __INTEL_CX0_REG_DEFS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 29e4bfab4635..f445f2613adb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3359,7 +3359,8 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
> > struct intel_crtc *slave_crtc;
> > enum phy phy = intel_port_to_phy(i915, encoder->port);
> >
> > - if (!intel_phy_is_tc(i915, phy))
> > + /* FIXME: Add MTL pll_mgr */
> > + if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
> > return;
> >
> > intel_update_active_dpll(state, crtc, encoder); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 64b6a5ec4b81..c9927e12b95e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -996,8 +996,21 @@ struct intel_c10pll_state {
> > u8 pll[20];
> > };
> >
> > +struct intel_c20pll_state {
> > + u32 clock; /* in kHz */
> > + u16 tx[3];
> > + u16 cmn[4];
> > + union {
> > + u16 mplla[10];
> > + u16 mpllb[11];
> > + };
> > +};
> > +
> > struct intel_cx0pll_state {
> > - struct intel_c10pll_state c10;
> > + union {
> > + struct intel_c10pll_state c10;
> > + struct intel_c20pll_state c20;
> > + };
> > bool ssc_enabled;
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1d28a2560ae0..4361c1ac65c3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -53,6 +53,7 @@
> > #include "intel_combo_phy_regs.h"
> > #include "intel_connector.h"
> > #include "intel_crtc.h"
> > +#include "intel_cx0_phy.h"
> > #include "intel_ddi.h"
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > @@ -423,7 +424,14 @@ static int ehl_max_source_rate(struct intel_dp
> > *intel_dp)
> >
> > static int mtl_max_source_rate(struct intel_dp *intel_dp) {
> > - return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> > +
> > + if (intel_is_c10phy(i915, phy))
> > + return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> > +
> > + return 2000000;
> > }
> >
> > static int vbt_max_link_rate(struct intel_dp *intel_dp) @@ -452,7
> > +460,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > /* The values must be in increasing order */
> > static const int mtl_rates[] = {
> > 162000, 216000, 243000, 270000, 324000, 432000, 540000,
> 675000,
> > - 810000,
> > + 810000, 1000000, 1350000, 2000000,
> > };
> > static const int icl_rates[] = {
> > 162000, 216000, 270000, 324000, 432000, 540000, 648000,
> 810000,
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-20 12:40 ` [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming Mika Kahola
2023-04-21 23:24 ` Radhakrishna Sripada
@ 2023-04-27 3:22 ` Murthy, Arun R
2023-04-28 9:07 ` Andi Shyti
2 siblings, 0 replies; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 3:22 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Souza, Jose
> <jose.souza@intel.com>; Modem, Bhanuprakash
> <bhanuprakash.modem@intel.com>; Deak, Imre <imre.deak@intel.com>;
> Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence.
> add
> 4 lane support for c20.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 280 +++++++++++++++---
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h | 15 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> 5 files changed, 300 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 83180074b512..dd96bf5e179e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private
> *i915, enum port port,
> __intel_cx0_write(i915, port, lane, addr, data, committed); }
>
> +static void intel_c20_sram_write(struct drm_i915_private *i915, enum port
> port,
> + int lane, u16 addr, u16 data)
> +{
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >>
> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr &
> 0xff,
> +0);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8,
> 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> 1);
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed) { @@ -1415,6 +1427,207 @@ void
> intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i +
> 3]); }
>
> +static bool intel_c20_use_mplla(u32 clock) {
> + /* 10G and 20G rates use MPLLA */
> + if (clock == 312500 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static u8 intel_c20_get_dp_rate(u32 clock) {
> + switch (clock) {
> + case 162000: /* 1.62 Gbps DP1.4 */
> + return 0;
> + case 270000: /* 2.7 Gbps DP1.4 */
> + return 1;
> + case 540000: /* 5.4 Gbps DP 1.4 */
> + return 2;
> + case 810000: /* 8.1 Gbps DP1.4 */
> + return 3;
> + case 216000: /* 2.16 Gbps eDP */
> + return 4;
> + case 243000: /* 2.43 Gbps eDP */
> + return 5;
> + case 324000: /* 3.24 Gbps eDP */
> + return 6;
> + case 432000: /* 4.32 Gbps eDP */
> + return 7;
> + case 312500: /* 10 Gbps DP2.0 */
> + return 8;
> + case 421875: /* 13.5 Gbps DP2.0 */
> + return 9;
> + case 625000: /* 20 Gbps DP2.0*/
> + return 10;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static u8 intel_c20_get_hdmi_rate(u32 clock) {
> + switch (clock) {
> + case 25175:
> + case 27000:
> + case 74250:
> + case 148500:
> + case 594000:
> + return 0;
> + case 166670: /* 3 Gbps */
> + case 333330: /* 6 Gbps */
> + case 666670: /* 12 Gbps */
> + return 1;
> + case 444440: /* 8 Gbps */
> + return 2;
> + case 555560: /* 10 Gbps */
> + return 3;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static bool is_dp2(u32 clock)
> +{
> + /* DP2.0 clock rates */
> + if (clock == 312500 || clock == 421875 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static bool is_hdmi_frl(u32 clock)
> +{
> + switch (clock) {
> + case 166670: /* 3 Gbps */
> + case 333330: /* 6 Gbps */
> + case 444440: /* 8 Gbps */
> + case 555560: /* 10 Gbps */
> + case 666670: /* 12 Gbps */
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool intel_c20_protocol_switch_valid(struct intel_encoder
> +*encoder) {
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +
> + /* banks should not be cleared for DPALT/USB4/TBT modes */
> + /* TODO: optimize re-calibration in legacy mode */
> + return intel_tc_port_in_legacy_mode(intel_dig_port);
> +}
> +
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state = &crtc_state-
> >cx0pll_state.c20;
> + bool dp = false;
> + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> + bool cntx;
> + int i;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + dp = true;
> +
> + /* 1. Read current context selection */
> + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> + PHY_C20_CONTEXT_TOGGLE;
> +
> + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates
> enable MPLLA.
> + * Protocol switch is only applicable for MPLLA
> + */
Multi line commenting style.
With this change
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> + if (intel_c20_protocol_switch_valid(encoder)) {
> + for (i = 0; i < 4; i++)
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> + msleep(4);
> + }
> +
> + /* 3. Write SRAM configuration context. If A in use, write
> configuration to B context */
> + /* 3.1 Tx configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
> + }
> +
> + /* 3.2 common configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
> + }
> +
> + /* 3.3 mpllb or mplla configuration */
> + if (intel_c20_use_mplla(pll_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> +
> PHY_C20_A_MPLLA_CNTX_CFG(i),
> + pll_state->mplla[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> +
> PHY_C20_B_MPLLA_CNTX_CFG(i),
> + pll_state->mplla[i]);
> + }
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> + if (cntx)
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> +
> PHY_C20_A_MPLLB_CNTX_CFG(i),
> + pll_state->mpllb[i]);
> + else
> + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0,
> +
> PHY_C20_B_MPLLB_CNTX_CFG(i),
> + pll_state->mpllb[i]);
> + }
> + }
> +
> + /* 4. Program custom width to match the link protocol */
> + if (dp) {
> + intel_cx0_write(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_WIDTH,
> + is_dp2(pll_state->clock) ? 2 : 0,
> + MB_WRITE_COMMITTED);
> + } else if (is_hdmi_frl(pll_state->clock)) {
> + intel_cx0_write(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_WIDTH,
> + 1, MB_WRITE_COMMITTED);
> + } else
> + intel_cx0_write(i915, encoder->port,
> INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_WIDTH,
> + 0, MB_WRITE_COMMITTED);
> +
> + /* 5. For DP or 6. For HDMI */
> + if (dp) {
> + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> + BIT(6) |
> PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
> + MB_WRITE_COMMITTED);
> + } else {
> + intel_cx0_rmw(i915, encoder->port,
> INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + PHY_C20_IS_FRL,
> + is_hdmi_frl(pll_state->clock) ? 1 : 0,
> + MB_WRITE_COMMITTED);
> +
> + intel_cx0_write(i915, encoder->port,
> INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> + intel_c20_get_hdmi_rate(pll_state->clock),
> + MB_WRITE_COMMITTED);
> + }
> +
> + /*
> + * 7. Write Vendor specific registers to toggle context setting to load
> + * the updated programming toggle context bit
> + */
> + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : 1,
> MB_WRITE_COMMITTED); }
> +
> int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_c10pll_state *pll_state) {
> @@ -1456,7 +1669,11 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
> val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
>
> val |= XELPDP_FORWARD_CLOCK_UNGATE;
> - val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> +
> + if (is_hdmi_frl(crtc_state->port_clock))
> + val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> + else
> + val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ @@ -1612,7
> +1829,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
> *i915, enum port po
> phy_name(phy),
> XELPDP_PORT_RESET_END_TIMEOUT); }
>
> -static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> +static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> struct intel_encoder *encoder, int
> lane_count,
> bool lane_reversal)
> {
> @@ -1620,9 +1837,11 @@ static void intel_c10_program_phy_lane(struct
> drm_i915_private *i915,
> bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> enum port port = encoder->port;
>
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> - 0, C10_VDR_CTRL_MSGBUS_ACCESS,
> - MB_WRITE_COMMITTED);
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_MSGBUS_ACCESS,
> + MB_WRITE_COMMITTED);
>
> /* TODO: DP-alt MFD case where only one PHY lane should be
> programmed. */
> l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2)); @@ -1685,9 +1904,11 @@ static void
> intel_c10_program_phy_lane(struct drm_i915_private *i915,
> intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(2, 2),
> l1t2, MB_WRITE_COMMITTED);
>
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> - 0, C10_VDR_CTRL_UPDATE_CFG,
> - MB_WRITE_COMMITTED);
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> }
>
> static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) @@ -1712,8
> +1933,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> return val;
> }
>
> -static void intel_c10pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port); @@ -
> 1721,6 +1942,7 @@ static void intel_c10pll_enable(struct intel_encoder
> *encoder,
> bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> INTEL_CX0_LANE0;
> + intel_wakeref_t wakeref =
> intel_cx0_phy_transaction_begin(encoder);
>
> /*
> * 1. Program PORT_CLOCK_CTL REGISTER to configure @@ -1739,13
> +1961,16 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
> CX0_P2_STATE_READY);
>
> /* 4. Program PHY internal PLL internal registers. */
> - intel_c10_pll_program(i915, crtc_state, encoder);
> + if (intel_is_c10phy(i915, phy))
> + intel_c10_pll_program(i915, crtc_state, encoder);
> + else
> + intel_c20_pll_program(i915, crtc_state, encoder);
>
> /*
> * 5. Program the enabled and disabled owned PHY lane
> * transmitters over message bus
> */
> - intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count,
> lane_reversal);
> + intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
> +lane_reversal);
>
> /*
> * 6. Follow the Display Voltage Frequency Switching - Sequence @@
> -1779,32 +2004,22 @@ static void intel_c10pll_enable(struct intel_encoder
> *encoder,
> * 10. Follow the Display Voltage Frequency Switching Sequence After
> * Frequency Change. We handle this step in bxt_set_cdclk().
> */
> -}
> -
> -void intel_cx0pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> - intel_wakeref_t wakeref;
> -
> - wakeref = intel_cx0_phy_transaction_begin(encoder);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> - intel_c10pll_enable(encoder, crtc_state);
>
> /* TODO: enable TBT-ALT mode */
> intel_cx0_phy_transaction_end(encoder, wakeref); }
>
> -static void intel_c10pll_disable(struct intel_encoder *encoder)
> +void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + bool is_c10 = intel_is_c10phy(i915, phy);
> + intel_wakeref_t wakeref =
> intel_cx0_phy_transaction_begin(encoder);
>
> /* 1. Change owned PHY lane power to Disable state. */
> intel_cx0_powerdown_change_sequence(i915, encoder->port,
> INTEL_CX0_BOTH_LANES,
> - CX0_P2PG_STATE_DISABLE);
> + is_c10 ? CX0_P2PG_STATE_DISABLE
> :
> + CX0_P4PG_STATE_DISABLE);
>
> /*
> * 2. Follow the Display Voltage Frequency Switching Sequence Before
> @@ -1842,18 +2057,7 @@ static void intel_c10pll_disable(struct
> intel_encoder *encoder)
> XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0); -}
>
> -void intel_cx0pll_disable(struct intel_encoder *encoder) -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> - intel_wakeref_t wakeref;
> -
> - wakeref = intel_cx0_phy_transaction_begin(encoder);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> - intel_c10pll_disable(encoder);
> intel_cx0_phy_transaction_end(encoder, wakeref); }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 20024622d0eb..6fcb1680fb54 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -177,4 +177,36 @@
> #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 +
> (control))
> #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
>
> +/* C20 Registers */
> +#define PHY_C20_WR_ADDRESS_L 0xC02
> +#define PHY_C20_WR_ADDRESS_H 0xC03
> +#define PHY_C20_WR_DATA_L 0xC04
> +#define PHY_C20_WR_DATA_H 0xC05
> +#define PHY_C20_RD_ADDRESS_L 0xC06
> +#define PHY_C20_RD_ADDRESS_H 0xC07
> +#define PHY_C20_RD_DATA_L 0xC08
> +#define PHY_C20_RD_DATA_H 0xC09
> +#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> +#define PHY_C20_IS_FRL REG_BIT8(7)
> +#define PHY_C20_VDR_HDMI_RATE 0xD01
> +#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> +#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
> +#define PHY_C20_CUSTOM_SERDES(val)
> REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
> +#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> +#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
> +#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
> +#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
> +#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
> +#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
> +#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
> +#define C20_MPLLA_FRACEN REG_BIT(14)
> +#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
> +#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
> +#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
> +#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
> +#define C20_MPLLB_FRACEN REG_BIT(13)
> +#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> +
> +#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D +
> (idx))
> +
> #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 29e4bfab4635..f445f2613adb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3359,7 +3359,8 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
> struct intel_crtc *slave_crtc;
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> - if (!intel_phy_is_tc(i915, phy))
> + /* FIXME: Add MTL pll_mgr */
> + if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
> return;
>
> intel_update_active_dpll(state, crtc, encoder); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 64b6a5ec4b81..c9927e12b95e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -996,8 +996,21 @@ struct intel_c10pll_state {
> u8 pll[20];
> };
>
> +struct intel_c20pll_state {
> + u32 clock; /* in kHz */
> + u16 tx[3];
> + u16 cmn[4];
> + union {
> + u16 mplla[10];
> + u16 mpllb[11];
> + };
> +};
> +
> struct intel_cx0pll_state {
> - struct intel_c10pll_state c10;
> + union {
> + struct intel_c10pll_state c10;
> + struct intel_c20pll_state c20;
> + };
> bool ssc_enabled;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1d28a2560ae0..4361c1ac65c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -53,6 +53,7 @@
> #include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> @@ -423,7 +424,14 @@ static int ehl_max_source_rate(struct intel_dp
> *intel_dp)
>
> static int mtl_max_source_rate(struct intel_dp *intel_dp) {
> - return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> +
> + return 2000000;
> }
>
> static int vbt_max_link_rate(struct intel_dp *intel_dp) @@ -452,7 +460,7
> @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* The values must be in increasing order */
> static const int mtl_rates[] = {
> 162000, 216000, 243000, 270000, 324000, 432000, 540000,
> 675000,
> - 810000,
> + 810000, 1000000, 1350000, 2000000,
> };
> static const int icl_rates[] = {
> 162000, 216000, 270000, 324000, 432000, 540000, 648000,
> 810000,
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-20 12:40 ` [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming Mika Kahola
2023-04-21 23:24 ` Radhakrishna Sripada
2023-04-27 3:22 ` Murthy, Arun R
@ 2023-04-28 9:07 ` Andi Shyti
2023-04-28 9:11 ` Kahola, Mika
2 siblings, 1 reply; 47+ messages in thread
From: Andi Shyti @ 2023-04-28 9:07 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
> + bool dp = false;
> + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
> + bool cntx;
> + int i;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + dp = true;
> +
> + /* 1. Read current context selection */
> + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> + PHY_C20_CONTEXT_TOGGLE;
> +
> + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA.
> + * Protocol switch is only applicable for MPLLA
> + */
> + if (intel_c20_protocol_switch_valid(encoder)) {
> + for (i = 0; i < 4; i++)
> + intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> + msleep(4);
can you use usleep_range() here?
Andi
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
2023-04-28 9:07 ` Andi Shyti
@ 2023-04-28 9:11 ` Kahola, Mika
0 siblings, 0 replies; 47+ messages in thread
From: Kahola, Mika @ 2023-04-28 9:11 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Friday, April 28, 2023 12:07 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> > +static void intel_c20_pll_program(struct drm_i915_private *i915,
> > + const struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c20pll_state *pll_state = &crtc_state-
> >cx0pll_state.c20;
> > + bool dp = false;
> > + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> > + bool cntx;
> > + int i;
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + dp = true;
> > +
> > + /* 1. Read current context selection */
> > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> > + PHY_C20_CONTEXT_TOGGLE;
> > +
> > + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> > + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable
> MPLLA.
> > + * Protocol switch is only applicable for MPLLA
> > + */
> > + if (intel_c20_protocol_switch_valid(encoder)) {
> > + for (i = 0; i < 4; i++)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> > + msleep(4);
>
> can you use usleep_range() here?
I think we should use usleep_range() here. If I remember right, the msleep() is not that accurate.
Thanks for spotting!
-Mika-
>
> Andi
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
2023-04-20 12:40 ` [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-24 20:56 ` Radhakrishna Sripada
` (2 more replies)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state Mika Kahola
` (14 subsequent siblings)
16 siblings, 3 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
6 files changed, 628 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dd96bf5e179e..61428c5145e5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -11,6 +11,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_tc.h"
@@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
}
+static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr)
+{
+ u16 val;
+
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
+
+ val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
+ val <<= 8;
+ val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
+
+ return val;
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool committed)
{
@@ -659,6 +677,199 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
NULL,
};
+/* C20 basic DP 1.4 tables */
+static const struct intel_c20pll_state mtl_c20_dp_rbr = {
+ .link_bit_rate = 162000,
+ .clock = 162000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x5800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x50a8, /* mpllb cfg0 */
+ 0x2120, /* mpllb cfg1 */
+ 0xcd9a, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x5ab8, /* mpllb cfg4 */
+ 0x4c34, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x6000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
+ .link_bit_rate = 270000,
+ .clock = 270000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x308c, /* mpllb cfg0 */
+ 0x2110, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x489a, /* mpllb cfg4 */
+ 0x3f81, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
+ .link_bit_rate = 540000,
+ .clock = 540000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x108c, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x489a, /* mpllb cfg4 */
+ 0x3f81, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
+ .link_bit_rate = 810000,
+ .clock = 810000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x10d2, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
+ 0x8d98, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x7166, /* mpllb cfg4 */
+ 0x5f42, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x7800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+/* C20 basic DP 2.0 tables */
+static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
+ .link_bit_rate = 1000000, /* 10 Gbps */
+ .clock = 312500,
+ .tx = { 0xbe21, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mplla = { 0x3104, /* mplla cfg0 */
+ 0xd105, /* mplla cfg1 */
+ 0xc025, /* mplla cfg2 */
+ 0xc025, /* mplla cfg3 */
+ 0xa6ab, /* mplla cfg4 */
+ 0x8c00, /* mplla cfg5 */
+ 0x4000, /* mplla cfg6 */
+ 0x0003, /* mplla cfg7 */
+ 0x3555, /* mplla cfg8 */
+ 0x0000, /* mplla cfg9 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
+ .link_bit_rate = 1350000, /* 13.5 Gbps */
+ .clock = 421875,
+ .tx = { 0xbea0, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x015f, /* mpllb cfg0 */
+ 0x2205, /* mpllb cfg1 */
+ 0x1b17, /* mpllb cfg2 */
+ 0xffc1, /* mpllb cfg3 */
+ 0xe100, /* mpllb cfg4 */
+ 0xbd00, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
+ .link_bit_rate = 2000000, /* 20 Gbps */
+ .clock = 625000,
+ .tx = { 0xbe20, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mplla = { 0x3104, /* mplla cfg0 */
+ 0xd105, /* mplla cfg1 */
+ 0xc025, /* mplla cfg2 */
+ 0xc025, /* mplla cfg3 */
+ 0xa6ab, /* mplla cfg4 */
+ 0x8c00, /* mplla cfg5 */
+ 0x4000, /* mplla cfg6 */
+ 0x0003, /* mplla cfg7 */
+ 0x3555, /* mplla cfg8 */
+ 0x0002, /* mplla cfg9 */
+ },
+};
+
+static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
+ &mtl_c20_dp_rbr,
+ &mtl_c20_dp_hbr1,
+ &mtl_c20_dp_hbr2,
+ &mtl_c20_dp_hbr3,
+ &mtl_c20_dp_uhbr10,
+ &mtl_c20_dp_uhbr13_5,
+ &mtl_c20_dp_uhbr20,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
NULL,
};
-int intel_c10_phy_check_hdmi_link_rate(int clock)
+static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
+ .link_bit_rate = 25175,
+ .clock = 25175,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0xa0d2, /* mpllb cfg0 */
+ 0x7d80, /* mpllb cfg1 */
+ 0x0906, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x0200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x0000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
+ .link_bit_rate = 27000,
+ .clock = 27000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0xa0e0, /* mpllb cfg0 */
+ 0x7d80, /* mpllb cfg1 */
+ 0x0906, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x8000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
+ .link_bit_rate = 74250,
+ .clock = 74250,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x609a, /* mpllb cfg0 */
+ 0x7d40, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
+ .link_bit_rate = 148500,
+ .clock = 148500,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x409a, /* mpllb cfg0 */
+ 0x7d20, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
+ .link_bit_rate = 594000,
+ .clock = 594000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x009a, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
+ .link_bit_rate = 3000000,
+ .clock = 166670,
+ .tx = { 0xbe98, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x209c, /* mpllb cfg0 */
+ 0x7d10, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x2000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
+ .link_bit_rate = 6000000,
+ .clock = 333330,
+ .tx = { 0xbe98, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x009c, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x2000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
+ .link_bit_rate = 8000000,
+ .clock = 444440,
+ .tx = { 0xbe98, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x00d0, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x4a06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0003, /* mpllb cfg7 */
+ 0x2aaa, /* mpllb cfg8 */
+ 0x0002, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
+ .link_bit_rate = 10000000,
+ .clock = 555560,
+ .tx = { 0xbe98, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x1104, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x0a06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0003, /* mpllb cfg7 */
+ 0x3555, /* mpllb cfg8 */
+ 0x0001, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
+ .link_bit_rate = 12000000,
+ .clock = 666670,
+ .tx = { 0xbe98, /* tx cfg0 */
+ 0x9800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = { 0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x0138, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x5486, /* mpllb cfg2 */
+ 0xfe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
+ &mtl_c20_hdmi_25_175,
+ &mtl_c20_hdmi_27_0,
+ &mtl_c20_hdmi_74_25,
+ &mtl_c20_hdmi_148_5,
+ &mtl_c20_hdmi_594,
+ &mtl_c20_hdmi_300,
+ &mtl_c20_hdmi_600,
+ &mtl_c20_hdmi_800,
+ &mtl_c20_hdmi_1000,
+ &mtl_c20_hdmi_1200,
+ NULL,
+};
+
+static int intel_c10_phy_check_hdmi_link_rate(int clock)
{
const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
int i;
@@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
-int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
- struct intel_encoder *encoder)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
-
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
-
- return intel_c10pll_calc_state(crtc_state, encoder);
-}
-
void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c10pll_state *pll_state)
{
@@ -1427,6 +1901,74 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
+static int intel_c20_phy_check_hdmi_link_rate(int clock)
+{
+ const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
+ int i;
+
+ for (i = 0; tables[i]; i++) {
+ if (clock == tables[i]->link_bit_rate)
+ return MODE_OK;
+ }
+
+ return MODE_CLOCK_RANGE;
+}
+
+int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
+{
+ struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
+ struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (intel_is_c10phy(i915, phy))
+ return intel_c10_phy_check_hdmi_link_rate(clock);
+ return intel_c20_phy_check_hdmi_link_rate(clock);
+}
+
+static const struct intel_c20pll_state * const *
+intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ return mtl_c20_dp_tables;
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return mtl_c20_hdmi_tables;
+
+ MISSING_CASE(encoder->type);
+ return NULL;
+}
+
+static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c20pll_state * const *tables;
+ int i;
+
+ tables = intel_c20_pll_tables_get(crtc_state, encoder);
+ if (!tables)
+ return -EINVAL;
+
+ for (i = 0; tables[i]; i++) {
+ if (crtc_state->port_clock == tables[i]->link_bit_rate) {
+ crtc_state->cx0pll_state.c20 = *tables[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ if (intel_is_c10phy(i915, phy))
+ return intel_c10pll_calc_state(crtc_state, encoder);
+ return intel_c20pll_calc_state(crtc_state, encoder);
+}
+
static bool intel_c20_use_mplla(u32 clock)
{
/* 10G and 20G rates use MPLLA */
@@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
return false;
}
+void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ bool cntx, use_mpllb;
+ u32 val;
+ int i;
+
+ /* 1. Read current context selection */
+ cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+
+ /* Read Tx configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
+ if (cntx)
+ pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(i));
+ else
+ pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(i));
+ }
+
+ /* Read common configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
+ if (cntx)
+ pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(i));
+ else
+ pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(i));
+ }
+
+ val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_MPLLA_CNTX_CFG(6));
+ use_mpllb = val & C20_MPLLB_FRACEN;
+
+ if (use_mpllb) {
+ /* MPLLA configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
+ if (cntx)
+ pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i));
+ else
+ pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i));
+ }
+ } else {
+ /* MPLLB configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ if (cntx)
+ pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i));
+ else
+ pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i));
+ }
+ }
+}
+
static u8 intel_c20_get_dp_rate(u32 clock)
{
switch (clock) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 509d1d12776e..9760c6292c81 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10pll_state *pll_state);
void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
+void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
-int intel_c10_phy_check_hdmi_link_rate(int clock);
-
+int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
+void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ u32 level);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f445f2613adb..44f07011245b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ if (intel_is_c10phy(i915, phy)) {
+ intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
+ intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
+ } else {
+ intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
+ }
- intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
- intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
intel_ddi_get_config(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c9927e12b95e..4eadf45c0a43 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -997,6 +997,7 @@ struct intel_c10pll_state {
};
struct intel_c20pll_state {
+ u32 link_bit_rate;
u32 clock; /* in kHz */
u16 tx[3];
u16 cmn[4];
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 8141d5184856..65a258507d62 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -58,7 +58,7 @@
#include "intel_panel.h"
#include "intel_snps_phy.h"
-static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
+inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
{
return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
}
@@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
* FIXME: We will hopefully get an algorithmic way of programming
* the MPLLB for HDMI in the future.
*/
- if (IS_METEORLAKE(dev_priv))
- return intel_c10_phy_check_hdmi_link_rate(clock);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
else if (IS_DG2(dev_priv))
return intel_snps_phy_check_hdmi_link_rate(clock);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 774dda2376ed..492bd3921385 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
int src_max_slices, int src_max_slice_width,
int hdmi_max_slices, int hdmi_throughput);
int intel_hdmi_dsc_get_slice_height(int vactive);
+struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi);
#endif /* __INTEL_HDMI_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-20 12:40 ` [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout Mika Kahola
@ 2023-04-24 20:56 ` Radhakrishna Sripada
2023-04-26 11:43 ` Kahola, Mika
2023-04-27 3:31 ` Murthy, Arun R
2023-04-28 9:14 ` Andi Shyti
2 siblings, 1 reply; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-24 20:56 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
> BSpec: 64568
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> 6 files changed, 628 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dd96bf5e179e..61428c5145e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -11,6 +11,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_hdmi.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_tc.h"
> @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
> intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
> }
>
> +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr)
> +{
> + u16 val;
> +
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
> +
> + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> + val <<= 8;
> + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> +
> + return val;
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool committed)
> {
> @@ -659,6 +677,199 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +/* C20 basic DP 1.4 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> + .link_bit_rate = 162000,
> + .clock = 162000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x5800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x50a8, /* mpllb cfg0 */
> + 0x2120, /* mpllb cfg1 */
> + 0xcd9a, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x5ab8, /* mpllb cfg4 */
> + 0x4c34, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x6000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> + .link_bit_rate = 270000,
> + .clock = 270000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x308c, /* mpllb cfg0 */
> + 0x2110, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> + .link_bit_rate = 540000,
> + .clock = 540000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x108c, /* mpllb cfg0 */
> + 0x2108, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> + .link_bit_rate = 810000,
> + .clock = 810000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x10d2, /* mpllb cfg0 */
> + 0x2108, /* mpllb cfg1 */
> + 0x8d98, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x7166, /* mpllb cfg4 */
> + 0x5f42, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x7800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +/* C20 basic DP 2.0 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> + .link_bit_rate = 1000000, /* 10 Gbps */
> + .clock = 312500,
> + .tx = { 0xbe21, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mplla = { 0x3104, /* mplla cfg0 */
> + 0xd105, /* mplla cfg1 */
> + 0xc025, /* mplla cfg2 */
> + 0xc025, /* mplla cfg3 */
> + 0xa6ab, /* mplla cfg4 */
This should be 0x8c00 ^ for mplla cfg4 according to the consolidated table.
> + 0x8c00, /* mplla cfg5 */
This should be 0x759a ^ for mplla cfg5 according to the consolidated table.
> + 0x4000, /* mplla cfg6 */
> + 0x0003, /* mplla cfg7 */
> + 0x3555, /* mplla cfg8 */
> + 0x0000, /* mplla cfg9 */
This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> + .link_bit_rate = 1350000, /* 13.5 Gbps */
> + .clock = 421875,
> + .tx = { 0xbea0, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x015f, /* mpllb cfg0 */
> + 0x2205, /* mpllb cfg1 */
> + 0x1b17, /* mpllb cfg2 */
> + 0xffc1, /* mpllb cfg3 */
> + 0xe100, /* mpllb cfg4 */
> + 0xbd00, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> + .link_bit_rate = 2000000, /* 20 Gbps */
> + .clock = 625000,
> + .tx = { 0xbe20, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mplla = { 0x3104, /* mplla cfg0 */
> + 0xd105, /* mplla cfg1 */
> + 0xc025, /* mplla cfg2 */
> + 0xc025, /* mplla cfg3 */
> + 0xa6ab, /* mplla cfg4 */
> + 0x8c00, /* mplla cfg5 */
> + 0x4000, /* mplla cfg6 */
> + 0x0003, /* mplla cfg7 */
> + 0x3555, /* mplla cfg8 */
> + 0x0002, /* mplla cfg9 */
This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
These are the suggested changes for now. I would need to check the HDMI tables.
- Radhakrishna(RK) Sripada
> + },
> +};
> +
> +static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> + &mtl_c20_dp_rbr,
> + &mtl_c20_dp_hbr1,
> + &mtl_c20_dp_hbr2,
> + &mtl_c20_dp_hbr3,
> + &mtl_c20_dp_uhbr10,
> + &mtl_c20_dp_uhbr13_5,
> + &mtl_c20_dp_uhbr20,
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
> NULL,
> };
>
> -int intel_c10_phy_check_hdmi_link_rate(int clock)
> +static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> + .link_bit_rate = 25175,
> + .clock = 25175,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0xa0d2, /* mpllb cfg0 */
> + 0x7d80, /* mpllb cfg1 */
> + 0x0906, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x0200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x0000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> + .link_bit_rate = 27000,
> + .clock = 27000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0xa0e0, /* mpllb cfg0 */
> + 0x7d80, /* mpllb cfg1 */
> + 0x0906, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x8000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> + .link_bit_rate = 74250,
> + .clock = 74250,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x609a, /* mpllb cfg0 */
> + 0x7d40, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> + .link_bit_rate = 148500,
> + .clock = 148500,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x409a, /* mpllb cfg0 */
> + 0x7d20, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> + .link_bit_rate = 594000,
> + .clock = 594000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x009a, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> + .link_bit_rate = 3000000,
> + .clock = 166670,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x209c, /* mpllb cfg0 */
> + 0x7d10, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x2000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> + .link_bit_rate = 6000000,
> + .clock = 333330,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x009c, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x2000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> + .link_bit_rate = 8000000,
> + .clock = 444440,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x00d0, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x4a06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0003, /* mpllb cfg7 */
> + 0x2aaa, /* mpllb cfg8 */
> + 0x0002, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> + .link_bit_rate = 10000000,
> + .clock = 555560,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x1104, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x0a06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0003, /* mpllb cfg7 */
> + 0x3555, /* mpllb cfg8 */
> + 0x0001, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> + .link_bit_rate = 12000000,
> + .clock = 666670,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x0138, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x5486, /* mpllb cfg2 */
> + 0xfe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> + &mtl_c20_hdmi_25_175,
> + &mtl_c20_hdmi_27_0,
> + &mtl_c20_hdmi_74_25,
> + &mtl_c20_hdmi_148_5,
> + &mtl_c20_hdmi_594,
> + &mtl_c20_hdmi_300,
> + &mtl_c20_hdmi_600,
> + &mtl_c20_hdmi_800,
> + &mtl_c20_hdmi_1000,
> + &mtl_c20_hdmi_1200,
> + NULL,
> +};
> +
> +static int intel_c10_phy_check_hdmi_link_rate(int clock)
> {
> const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> int i;
> @@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> - struct intel_encoder *encoder)
> -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> -
> - return intel_c10pll_calc_state(crtc_state, encoder);
> -}
> -
> void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c10pll_state *pll_state)
> {
> @@ -1427,6 +1901,74 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
>
> +static int intel_c20_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> + return MODE_OK;
> + }
> +
> + return MODE_CLOCK_RANGE;
> +}
> +
> +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
> +{
> + struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> + struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_c10_phy_check_hdmi_link_rate(clock);
> + return intel_c20_phy_check_hdmi_link_rate(clock);
> +}
> +
> +static const struct intel_c20pll_state * const *
> +intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + return mtl_c20_dp_tables;
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return mtl_c20_hdmi_tables;
> +
> + MISSING_CASE(encoder->type);
> + return NULL;
> +}
> +
> +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state * const *tables;
> + int i;
> +
> + tables = intel_c20_pll_tables_get(crtc_state, encoder);
> + if (!tables)
> + return -EINVAL;
> +
> + for (i = 0; tables[i]; i++) {
> + if (crtc_state->port_clock == tables[i]->link_bit_rate) {
> + crtc_state->cx0pll_state.c20 = *tables[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_c10pll_calc_state(crtc_state, encoder);
> + return intel_c20pll_calc_state(crtc_state, encoder);
> +}
> +
> static bool intel_c20_use_mplla(u32 clock)
> {
> /* 10G and 20G rates use MPLLA */
> @@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
> return false;
> }
>
> +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c20pll_state *pll_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + bool cntx, use_mpllb;
> + u32 val;
> + int i;
> +
> + /* 1. Read current context selection */
> + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> +
> + /* Read Tx configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> + if (cntx)
> + pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_TX_CNTX_CFG(i));
> + else
> + pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_TX_CNTX_CFG(i));
> + }
> +
> + /* Read common configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> + if (cntx)
> + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_CMN_CNTX_CFG(i));
> + else
> + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_CMN_CNTX_CFG(i));
> + }
> +
> + val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_MPLLA_CNTX_CFG(6));
> + use_mpllb = val & C20_MPLLB_FRACEN;
> +
> + if (use_mpllb) {
> + /* MPLLA configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> + if (cntx)
> + pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_MPLLA_CNTX_CFG(i));
> + else
> + pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_MPLLA_CNTX_CFG(i));
> + }
> + } else {
> + /* MPLLB configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> + if (cntx)
> + pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_B_MPLLB_CNTX_CFG(i));
> + else
> + pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> + PHY_C20_A_MPLLB_CNTX_CFG(i));
> + }
> + }
> +}
> +
> static u8 intel_c20_get_dp_rate(u32 clock)
> {
> switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 509d1d12776e..9760c6292c81 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_c10pll_state *pll_state);
> void intel_c10pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state);
> +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c20pll_state *pll_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> -int intel_c10_phy_check_hdmi_link_rate(int clock);
> -
> +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> +void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + u32 level);
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index f445f2613adb..44f07011245b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + if (intel_is_c10phy(i915, phy)) {
> + intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
> + intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> + } else {
> + intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
> + }
>
> - intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
> - intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
>
> intel_ddi_get_config(encoder, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c9927e12b95e..4eadf45c0a43 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -997,6 +997,7 @@ struct intel_c10pll_state {
> };
>
> struct intel_c20pll_state {
> + u32 link_bit_rate;
> u32 clock; /* in kHz */
> u16 tx[3];
> u16 cmn[4];
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 8141d5184856..65a258507d62 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -58,7 +58,7 @@
> #include "intel_panel.h"
> #include "intel_snps_phy.h"
>
> -static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
> +inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
> {
> return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
> }
> @@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> * FIXME: We will hopefully get an algorithmic way of programming
> * the MPLLB for HDMI in the future.
> */
> - if (IS_METEORLAKE(dev_priv))
> - return intel_c10_phy_check_hdmi_link_rate(clock);
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> else if (IS_DG2(dev_priv))
> return intel_snps_phy_check_hdmi_link_rate(clock);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index 774dda2376ed..492bd3921385 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
> int src_max_slices, int src_max_slice_width,
> int hdmi_max_slices, int hdmi_throughput);
> int intel_hdmi_dsc_get_slice_height(int vactive);
> +struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi);
>
> #endif /* __INTEL_HDMI_H__ */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-24 20:56 ` Radhakrishna Sripada
@ 2023-04-26 11:43 ` Kahola, Mika
2023-04-27 16:47 ` Sripada, Radhakrishna
0 siblings, 1 reply; 47+ messages in thread
From: Kahola, Mika @ 2023-04-26 11:43 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Monday, April 24, 2023 11:56 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > The PLL settings are based on table, not for algorithmic alternative.
> > For DP 1.4 only MPLLB is in use.
> >
> > Once register settings are done, we read back C20 HW state.
> >
> > BSpec: 64568
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > 6 files changed, 628 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index dd96bf5e179e..61428c5145e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -11,6 +11,7 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > +#include "intel_hdmi.h"
> > #include "intel_panel.h"
> > #include "intel_psr.h"
> > #include "intel_tc.h"
> > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> drm_i915_private *i915, enum port port,
> > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > 1); }
> >
> > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> port,
> > + int lane, u16 addr)
> > +{
> > + u16 val;
> > +
> > + assert_dc_off(i915);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8,
> 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff,
> > +1);
> > +
> > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > + val <<= 8;
> > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > +
> > + return val;
> > +}
> > +
> > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > int lane, u16 addr, u8 clear, u8 set, bool committed) {
> @@
> > -659,6 +677,199 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> > NULL,
> > };
> >
> > +/* C20 basic DP 1.4 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > + .link_bit_rate = 162000,
> > + .clock = 162000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x5800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > + 0x2120, /* mpllb cfg1 */
> > + 0xcd9a, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x5ab8, /* mpllb cfg4 */
> > + 0x4c34, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x6000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > + .link_bit_rate = 270000,
> > + .clock = 270000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x308c, /* mpllb cfg0 */
> > + 0x2110, /* mpllb cfg1 */
> > + 0xcc9c, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x489a, /* mpllb cfg4 */
> This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
Yes. Perhaps this has changed since the time of writing.
>
> > + 0x3f81, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > + .link_bit_rate = 540000,
> > + .clock = 540000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x108c, /* mpllb cfg0 */
> > + 0x2108, /* mpllb cfg1 */
> > + 0xcc9c, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x489a, /* mpllb cfg4 */
> This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
I will change this one too.
>
> > + 0x3f81, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > + .link_bit_rate = 810000,
> > + .clock = 810000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x10d2, /* mpllb cfg0 */
> > + 0x2108, /* mpllb cfg1 */
> > + 0x8d98, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x7166, /* mpllb cfg4 */
> > + 0x5f42, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x7800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +/* C20 basic DP 2.0 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > + .link_bit_rate = 1000000, /* 10 Gbps */
> > + .clock = 312500,
> > + .tx = { 0xbe21, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mplla = { 0x3104, /* mplla cfg0 */
> > + 0xd105, /* mplla cfg1 */
> > + 0xc025, /* mplla cfg2 */
> > + 0xc025, /* mplla cfg3 */
> > + 0xa6ab, /* mplla cfg4 */
> This should be 0x8c00 ^ for mplla cfg4 according to the consolidated table.
True. I will update this
>
> > + 0x8c00, /* mplla cfg5 */
> This should be 0x759a ^ for mplla cfg5 according to the consolidated table.
As well as this one.
>
> > + 0x4000, /* mplla cfg6 */
> > + 0x0003, /* mplla cfg7 */
> > + 0x3555, /* mplla cfg8 */
> > + 0x0000, /* mplla cfg9 */
> This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
This is bit controversial. The consolidated table indeed suggests that these mplla cfg9
values should be 0x0001 for both 10G and 20G rates. However, if we look at the table
definition "C20 MPLLA Programming for DP UHBR link rates (10G and 20G)" for mplla cfg9
it states for mplla_frac_rem parameter 0x0000 for 10G and 0x0002 for 20G. Now, which
one of these are the correct ones? Should we rely on values defined consolidated table?
>
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > + .link_bit_rate = 1350000, /* 13.5 Gbps */
> > + .clock = 421875,
> > + .tx = { 0xbea0, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x015f, /* mpllb cfg0 */
> > + 0x2205, /* mpllb cfg1 */
> > + 0x1b17, /* mpllb cfg2 */
> > + 0xffc1, /* mpllb cfg3 */
> > + 0xe100, /* mpllb cfg4 */
> > + 0xbd00, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x4800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > + .link_bit_rate = 2000000, /* 20 Gbps */
> > + .clock = 625000,
> > + .tx = { 0xbe20, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mplla = { 0x3104, /* mplla cfg0 */
> > + 0xd105, /* mplla cfg1 */
> > + 0xc025, /* mplla cfg2 */
> > + 0xc025, /* mplla cfg3 */
> > + 0xa6ab, /* mplla cfg4 */
> > + 0x8c00, /* mplla cfg5 */
> > + 0x4000, /* mplla cfg6 */
> > + 0x0003, /* mplla cfg7 */
> > + 0x3555, /* mplla cfg8 */
> > + 0x0002, /* mplla cfg9 */
> This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
>
> These are the suggested changes for now. I would need to check the HDMI
> tables.
Thanks for the review and comments!
-Mika-
>
> - Radhakrishna(RK) Sripada
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> > + &mtl_c20_dp_rbr,
> > + &mtl_c20_dp_hbr1,
> > + &mtl_c20_dp_hbr2,
> > + &mtl_c20_dp_hbr3,
> > + &mtl_c20_dp_uhbr10,
> > + &mtl_c20_dp_uhbr13_5,
> > + &mtl_c20_dp_uhbr20,
> > + NULL,
> > +};
> > +
> > /*
> > * HDMI link rates with 38.4 MHz reference clock.
> > */
> > @@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const
> mtl_c10_hdmi_tables[] = {
> > NULL,
> > };
> >
> > -int intel_c10_phy_check_hdmi_link_rate(int clock)
> > +static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> > + .link_bit_rate = 25175,
> > + .clock = 25175,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0xa0d2, /* mpllb cfg0 */
> > + 0x7d80, /* mpllb cfg1 */
> > + 0x0906, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x0200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x0000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> > + .link_bit_rate = 27000,
> > + .clock = 27000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0xa0e0, /* mpllb cfg0 */
> > + 0x7d80, /* mpllb cfg1 */
> > + 0x0906, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x8000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> > + .link_bit_rate = 74250,
> > + .clock = 74250,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x609a, /* mpllb cfg0 */
> > + 0x7d40, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> > + .link_bit_rate = 148500,
> > + .clock = 148500,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x409a, /* mpllb cfg0 */
> > + 0x7d20, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> > + .link_bit_rate = 594000,
> > + .clock = 594000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x009a, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > + .link_bit_rate = 3000000,
> > + .clock = 166670,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x209c, /* mpllb cfg0 */
> > + 0x7d10, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x2000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > + .link_bit_rate = 6000000,
> > + .clock = 333330,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x009c, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x2000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > + .link_bit_rate = 8000000,
> > + .clock = 444440,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x00d0, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x4a06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0003, /* mpllb cfg7 */
> > + 0x2aaa, /* mpllb cfg8 */
> > + 0x0002, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > + .link_bit_rate = 10000000,
> > + .clock = 555560,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x1104, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x0a06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0003, /* mpllb cfg7 */
> > + 0x3555, /* mpllb cfg8 */
> > + 0x0001, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > + .link_bit_rate = 12000000,
> > + .clock = 666670,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x0138, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x5486, /* mpllb cfg2 */
> > + 0xfe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x4000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> > + &mtl_c20_hdmi_25_175,
> > + &mtl_c20_hdmi_27_0,
> > + &mtl_c20_hdmi_74_25,
> > + &mtl_c20_hdmi_148_5,
> > + &mtl_c20_hdmi_594,
> > + &mtl_c20_hdmi_300,
> > + &mtl_c20_hdmi_600,
> > + &mtl_c20_hdmi_800,
> > + &mtl_c20_hdmi_1000,
> > + &mtl_c20_hdmi_1200,
> > + NULL,
> > +};
> > +
> > +static int intel_c10_phy_check_hdmi_link_rate(int clock)
> > {
> > const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> > int i;
> > @@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
> > return -EINVAL;
> > }
> >
> > -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > - struct intel_encoder *encoder)
> > -{
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - enum phy phy = intel_port_to_phy(i915, encoder->port);
> > -
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > -
> > - return intel_c10pll_calc_state(crtc_state, encoder);
> > -}
> > -
> > void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> > struct intel_c10pll_state *pll_state) { @@ -
> 1427,6 +1901,74
> > @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> > i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
> >
> > +static int intel_c20_phy_check_hdmi_link_rate(int clock) {
> > + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> > + int i;
> > +
> > + for (i = 0; tables[i]; i++) {
> > + if (clock == tables[i]->link_bit_rate)
> > + return MODE_OK;
> > + }
> > +
> > + return MODE_CLOCK_RANGE;
> > +}
> > +
> > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > +clock) {
> > + struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> > + struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
> > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> > +
> > + if (intel_is_c10phy(i915, phy))
> > + return intel_c10_phy_check_hdmi_link_rate(clock);
> > + return intel_c20_phy_check_hdmi_link_rate(clock);
> > +}
> > +
> > +static const struct intel_c20pll_state * const *
> > +intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + return mtl_c20_dp_tables;
> > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > + return mtl_c20_hdmi_tables;
> > +
> > + MISSING_CASE(encoder->type);
> > + return NULL;
> > +}
> > +
> > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder) {
> > + const struct intel_c20pll_state * const *tables;
> > + int i;
> > +
> > + tables = intel_c20_pll_tables_get(crtc_state, encoder);
> > + if (!tables)
> > + return -EINVAL;
> > +
> > + for (i = 0; tables[i]; i++) {
> > + if (crtc_state->port_clock == tables[i]->link_bit_rate) {
> > + crtc_state->cx0pll_state.c20 = *tables[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + if (intel_is_c10phy(i915, phy))
> > + return intel_c10pll_calc_state(crtc_state, encoder);
> > + return intel_c20pll_calc_state(crtc_state, encoder); }
> > +
> > static bool intel_c20_use_mplla(u32 clock) {
> > /* 10G and 20G rates use MPLLA */
> > @@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
> > return false;
> > }
> >
> > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c20pll_state *pll_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + bool cntx, use_mpllb;
> > + u32 val;
> > + int i;
> > +
> > + /* 1. Read current context selection */
> > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> > +
> > + /* Read Tx configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> > + if (cntx)
> > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> > +
> PHY_C20_B_TX_CNTX_CFG(i));
> > + else
> > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> > +
> PHY_C20_A_TX_CNTX_CFG(i));
> > + }
> > +
> > + /* Read common configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> > + if (cntx)
> > + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> > +
> PHY_C20_B_CMN_CNTX_CFG(i));
> > + else
> > + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> > +
> PHY_C20_A_CMN_CNTX_CFG(i));
> > + }
> > +
> > + val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_A_MPLLA_CNTX_CFG(6));
> > + use_mpllb = val & C20_MPLLB_FRACEN;
> > +
> > + if (use_mpllb) {
> > + /* MPLLA configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> > + if (cntx)
> > + pll_state->mplla[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> > +
> PHY_C20_B_MPLLA_CNTX_CFG(i));
> > + else
> > + pll_state->mplla[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> > +
> PHY_C20_A_MPLLA_CNTX_CFG(i));
> > + }
> > + } else {
> > + /* MPLLB configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> > + if (cntx)
> > + pll_state->mpllb[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> > +
> PHY_C20_B_MPLLB_CNTX_CFG(i));
> > + else
> > + pll_state->mpllb[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> > +
> PHY_C20_A_MPLLB_CNTX_CFG(i));
> > + }
> > + }
> > +}
> > +
> > static u8 intel_c20_get_dp_rate(u32 clock) {
> > switch (clock) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 509d1d12776e..9760c6292c81 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct intel_encoder
> *encoder,
> > const struct intel_c10pll_state *pll_state);
> void
> > intel_c10pll_state_verify(struct intel_atomic_state *state,
> > struct intel_crtc_state *new_crtc_state);
> > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c20pll_state *pll_state);
> > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state); -
> int
> > intel_c10_phy_check_hdmi_link_rate(int clock);
> > -
> > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > +clock); void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + u32 level);
> > #endif /* __INTEL_CX0_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index f445f2613adb..44f07011245b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct
> intel_encoder *encoder,
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port);
> >
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > + if (intel_is_c10phy(i915, phy)) {
> > + intel_c10pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c10);
> > + intel_c10pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c10);
> > + } else {
> > + intel_c20pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c20);
> > + }
> >
> > - intel_c10pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c10);
> > - intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> > &crtc_state->cx0pll_state.c10);
> >
> > intel_ddi_get_config(encoder, crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c9927e12b95e..4eadf45c0a43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -997,6 +997,7 @@ struct intel_c10pll_state { };
> >
> > struct intel_c20pll_state {
> > + u32 link_bit_rate;
> > u32 clock; /* in kHz */
> > u16 tx[3];
> > u16 cmn[4];
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 8141d5184856..65a258507d62 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -58,7 +58,7 @@
> > #include "intel_panel.h"
> > #include "intel_snps_phy.h"
> >
> > -static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > *intel_hdmi)
> > +inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > +*intel_hdmi)
> > {
> > return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
> > }
> > @@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > * FIXME: We will hopefully get an algorithmic way of programming
> > * the MPLLB for HDMI in the future.
> > */
> > - if (IS_METEORLAKE(dev_priv))
> > - return intel_c10_phy_check_hdmi_link_rate(clock);
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> > else if (IS_DG2(dev_priv))
> > return intel_snps_phy_check_hdmi_link_rate(clock);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > index 774dda2376ed..492bd3921385 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > @@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct
> intel_crtc_state *crtc_state,
> > int src_max_slices, int src_max_slice_width,
> > int hdmi_max_slices, int hdmi_throughput);
> int
> > intel_hdmi_dsc_get_slice_height(int vactive);
> > +struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > +*intel_hdmi);
> >
> > #endif /* __INTEL_HDMI_H__ */
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-26 11:43 ` Kahola, Mika
@ 2023-04-27 16:47 ` Sripada, Radhakrishna
0 siblings, 0 replies; 47+ messages in thread
From: Sripada, Radhakrishna @ 2023-04-27 16:47 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Wednesday, April 26, 2023 4:43 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -----Original Message-----
> > From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> > Sent: Monday, April 24, 2023 11:56 PM
> > To: Kahola, Mika <mika.kahola@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> >
> > On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> > > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > > The PLL settings are based on table, not for algorithmic alternative.
> > > For DP 1.4 only MPLLB is in use.
> > >
> > > Once register settings are done, we read back C20 HW state.
> > >
> > > BSpec: 64568
> > >
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > > .../drm/i915/display/intel_display_types.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > > 6 files changed, 628 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index dd96bf5e179e..61428c5145e5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -11,6 +11,7 @@
> > > #include "intel_de.h"
> > > #include "intel_display_types.h"
> > > #include "intel_dp.h"
> > > +#include "intel_hdmi.h"
> > > #include "intel_panel.h"
> > > #include "intel_psr.h"
> > > #include "intel_tc.h"
> > > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> > drm_i915_private *i915, enum port port,
> > > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > > 1); }
> > >
> > > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> > port,
> > > + int lane, u16 addr)
> > > +{
> > > + u16 val;
> > > +
> > > + assert_dc_off(i915);
> > > +
> > > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8,
> > 0);
> > > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff,
> > > +1);
> > > +
> > > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > > + val <<= 8;
> > > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > > +
> > > + return val;
> > > +}
> > > +
> > > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > > int lane, u16 addr, u8 clear, u8 set, bool committed) {
> > @@
> > > -659,6 +677,199 @@ static const struct intel_c10pll_state * const
> > mtl_c10_edp_tables[] = {
> > > NULL,
> > > };
> > >
> > > +/* C20 basic DP 1.4 tables */
> > > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > > + .link_bit_rate = 162000,
> > > + .clock = 162000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x5800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > > + 0x2120, /* mpllb cfg1 */
> > > + 0xcd9a, /* mpllb cfg2 */
> > > + 0xbfc1, /* mpllb cfg3 */
> > > + 0x5ab8, /* mpllb cfg4 */
> > > + 0x4c34, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x6000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0000, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > > + .link_bit_rate = 270000,
> > > + .clock = 270000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x308c, /* mpllb cfg0 */
> > > + 0x2110, /* mpllb cfg1 */
> > > + 0xcc9c, /* mpllb cfg2 */
> > > + 0xbfc1, /* mpllb cfg3 */
> > > + 0x489a, /* mpllb cfg4 */
> > This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
> Yes. Perhaps this has changed since the time of writing.
>
> >
> > > + 0x3f81, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x5000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0000, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > > + .link_bit_rate = 540000,
> > > + .clock = 540000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x108c, /* mpllb cfg0 */
> > > + 0x2108, /* mpllb cfg1 */
> > > + 0xcc9c, /* mpllb cfg2 */
> > > + 0xbfc1, /* mpllb cfg3 */
> > > + 0x489a, /* mpllb cfg4 */
> > This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
> I will change this one too.
>
> >
> > > + 0x3f81, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x5000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0000, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > > + .link_bit_rate = 810000,
> > > + .clock = 810000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x10d2, /* mpllb cfg0 */
> > > + 0x2108, /* mpllb cfg1 */
> > > + 0x8d98, /* mpllb cfg2 */
> > > + 0xbfc1, /* mpllb cfg3 */
> > > + 0x7166, /* mpllb cfg4 */
> > > + 0x5f42, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x7800, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0000, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +/* C20 basic DP 2.0 tables */
> > > +static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > > + .link_bit_rate = 1000000, /* 10 Gbps */
> > > + .clock = 312500,
> > > + .tx = { 0xbe21, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mplla = { 0x3104, /* mplla cfg0 */
> > > + 0xd105, /* mplla cfg1 */
> > > + 0xc025, /* mplla cfg2 */
> > > + 0xc025, /* mplla cfg3 */
> > > + 0xa6ab, /* mplla cfg4 */
> > This should be 0x8c00 ^ for mplla cfg4 according to the consolidated table.
> True. I will update this
> >
> > > + 0x8c00, /* mplla cfg5 */
> > This should be 0x759a ^ for mplla cfg5 according to the consolidated table.
> As well as this one.
> >
> > > + 0x4000, /* mplla cfg6 */
> > > + 0x0003, /* mplla cfg7 */
> > > + 0x3555, /* mplla cfg8 */
> > > + 0x0000, /* mplla cfg9 */
> > This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
> This is bit controversial. The consolidated table indeed suggests that these mplla
> cfg9
> values should be 0x0001 for both 10G and 20G rates. However, if we look at the
> table
> definition "C20 MPLLA Programming for DP UHBR link rates (10G and 20G)" for
> mplla cfg9
> it states for mplla_frac_rem parameter 0x0000 for 10G and 0x0002 for 20G.
> Now, which
> one of these are the correct ones? Should we rely on values defined
> consolidated table?
I was in discussion with HW Architects for some C10 phy issue. I was told that consolidated tables
are more accurate.
-Radhakrishna(RK) Sripada
>
> >
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > > + .link_bit_rate = 1350000, /* 13.5 Gbps */
> > > + .clock = 421875,
> > > + .tx = { 0xbea0, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x015f, /* mpllb cfg0 */
> > > + 0x2205, /* mpllb cfg1 */
> > > + 0x1b17, /* mpllb cfg2 */
> > > + 0xffc1, /* mpllb cfg3 */
> > > + 0xe100, /* mpllb cfg4 */
> > > + 0xbd00, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x4800, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0000, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > > + .link_bit_rate = 2000000, /* 20 Gbps */
> > > + .clock = 625000,
> > > + .tx = { 0xbe20, /* tx cfg0 */
> > > + 0x4800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mplla = { 0x3104, /* mplla cfg0 */
> > > + 0xd105, /* mplla cfg1 */
> > > + 0xc025, /* mplla cfg2 */
> > > + 0xc025, /* mplla cfg3 */
> > > + 0xa6ab, /* mplla cfg4 */
> > > + 0x8c00, /* mplla cfg5 */
> > > + 0x4000, /* mplla cfg6 */
> > > + 0x0003, /* mplla cfg7 */
> > > + 0x3555, /* mplla cfg8 */
> > > + 0x0002, /* mplla cfg9 */
> > This should be 0x0001 ^ for mplla cfg9 according to the consolidated table.
> >
> > These are the suggested changes for now. I would need to check the HDMI
> > tables.
>
> Thanks for the review and comments!
>
> -Mika-
> >
> > - Radhakrishna(RK) Sripada
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> > > + &mtl_c20_dp_rbr,
> > > + &mtl_c20_dp_hbr1,
> > > + &mtl_c20_dp_hbr2,
> > > + &mtl_c20_dp_hbr3,
> > > + &mtl_c20_dp_uhbr10,
> > > + &mtl_c20_dp_uhbr13_5,
> > > + &mtl_c20_dp_uhbr20,
> > > + NULL,
> > > +};
> > > +
> > > /*
> > > * HDMI link rates with 38.4 MHz reference clock.
> > > */
> > > @@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const
> > mtl_c10_hdmi_tables[] = {
> > > NULL,
> > > };
> > >
> > > -int intel_c10_phy_check_hdmi_link_rate(int clock)
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> > > + .link_bit_rate = 25175,
> > > + .clock = 25175,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0xa0d2, /* mpllb cfg0 */
> > > + 0x7d80, /* mpllb cfg1 */
> > > + 0x0906, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x0200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x0000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0001, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> > > + .link_bit_rate = 27000,
> > > + .clock = 27000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0xa0e0, /* mpllb cfg0 */
> > > + 0x7d80, /* mpllb cfg1 */
> > > + 0x0906, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x8000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0001, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> > > + .link_bit_rate = 74250,
> > > + .clock = 74250,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x609a, /* mpllb cfg0 */
> > > + 0x7d40, /* mpllb cfg1 */
> > > + 0xca06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x5800, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0001, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> > > + .link_bit_rate = 148500,
> > > + .clock = 148500,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x409a, /* mpllb cfg0 */
> > > + 0x7d20, /* mpllb cfg1 */
> > > + 0xca06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x5800, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0001, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> > > + .link_bit_rate = 594000,
> > > + .clock = 594000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x009a, /* mpllb cfg0 */
> > > + 0x7d08, /* mpllb cfg1 */
> > > + 0xca06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x5800, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0001, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > > + .link_bit_rate = 3000000,
> > > + .clock = 166670,
> > > + .tx = { 0xbe98, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x209c, /* mpllb cfg0 */
> > > + 0x7d10, /* mpllb cfg1 */
> > > + 0xca06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x2000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0004, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > > + .link_bit_rate = 6000000,
> > > + .clock = 333330,
> > > + .tx = { 0xbe98, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x009c, /* mpllb cfg0 */
> > > + 0x7d08, /* mpllb cfg1 */
> > > + 0xca06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x2000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0004, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > > + .link_bit_rate = 8000000,
> > > + .clock = 444440,
> > > + .tx = { 0xbe98, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x00d0, /* mpllb cfg0 */
> > > + 0x7d08, /* mpllb cfg1 */
> > > + 0x4a06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0003, /* mpllb cfg7 */
> > > + 0x2aaa, /* mpllb cfg8 */
> > > + 0x0002, /* mpllb cfg9 */
> > > + 0x0004, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > > + .link_bit_rate = 10000000,
> > > + .clock = 555560,
> > > + .tx = { 0xbe98, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x1104, /* mpllb cfg0 */
> > > + 0x7d08, /* mpllb cfg1 */
> > > + 0x0a06, /* mpllb cfg2 */
> > > + 0xbe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0003, /* mpllb cfg7 */
> > > + 0x3555, /* mpllb cfg8 */
> > > + 0x0001, /* mpllb cfg9 */
> > > + 0x0004, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > > + .link_bit_rate = 12000000,
> > > + .clock = 666670,
> > > + .tx = { 0xbe98, /* tx cfg0 */
> > > + 0x9800, /* tx cfg1 */
> > > + 0x0000, /* tx cfg2 */
> > > + },
> > > + .cmn = { 0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x0000, /* cmn cfg2 */
> > > + 0x0000, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x0138, /* mpllb cfg0 */
> > > + 0x7d08, /* mpllb cfg1 */
> > > + 0x5486, /* mpllb cfg2 */
> > > + 0xfe40, /* mpllb cfg3 */
> > > + 0x0000, /* mpllb cfg4 */
> > > + 0x0000, /* mpllb cfg5 */
> > > + 0x2200, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x4000, /* mpllb cfg8 */
> > > + 0x0000, /* mpllb cfg9 */
> > > + 0x0004, /* mpllb cfg10 */
> > > + },
> > > +};
> > > +
> > > +static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> > > + &mtl_c20_hdmi_25_175,
> > > + &mtl_c20_hdmi_27_0,
> > > + &mtl_c20_hdmi_74_25,
> > > + &mtl_c20_hdmi_148_5,
> > > + &mtl_c20_hdmi_594,
> > > + &mtl_c20_hdmi_300,
> > > + &mtl_c20_hdmi_600,
> > > + &mtl_c20_hdmi_800,
> > > + &mtl_c20_hdmi_1000,
> > > + &mtl_c20_hdmi_1200,
> > > + NULL,
> > > +};
> > > +
> > > +static int intel_c10_phy_check_hdmi_link_rate(int clock)
> > > {
> > > const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> > > int i;
> > > @@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> > > return -EINVAL;
> > > }
> > >
> > > -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > > - struct intel_encoder *encoder)
> > > -{
> > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > - enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > -
> > > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > > -
> > > - return intel_c10pll_calc_state(crtc_state, encoder);
> > > -}
> > > -
> > > void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> > > struct intel_c10pll_state *pll_state) { @@ -
> > 1427,6 +1901,74
> > > @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> > > i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> > }
> > >
> > > +static int intel_c20_phy_check_hdmi_link_rate(int clock) {
> > > + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> > > + int i;
> > > +
> > > + for (i = 0; tables[i]; i++) {
> > > + if (clock == tables[i]->link_bit_rate)
> > > + return MODE_OK;
> > > + }
> > > +
> > > + return MODE_CLOCK_RANGE;
> > > +}
> > > +
> > > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > > +clock) {
> > > + struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> > > + struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
> > > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> > > +
> > > + if (intel_is_c10phy(i915, phy))
> > > + return intel_c10_phy_check_hdmi_link_rate(clock);
> > > + return intel_c20_phy_check_hdmi_link_rate(clock);
> > > +}
> > > +
> > > +static const struct intel_c20pll_state * const *
> > > +intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> > > + struct intel_encoder *encoder)
> > > +{
> > > + if (intel_crtc_has_dp_encoder(crtc_state))
> > > + return mtl_c20_dp_tables;
> > > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > > + return mtl_c20_hdmi_tables;
> > > +
> > > + MISSING_CASE(encoder->type);
> > > + return NULL;
> > > +}
> > > +
> > > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > > + struct intel_encoder *encoder) {
> > > + const struct intel_c20pll_state * const *tables;
> > > + int i;
> > > +
> > > + tables = intel_c20_pll_tables_get(crtc_state, encoder);
> > > + if (!tables)
> > > + return -EINVAL;
> > > +
> > > + for (i = 0; tables[i]; i++) {
> > > + if (crtc_state->port_clock == tables[i]->link_bit_rate) {
> > > + crtc_state->cx0pll_state.c20 = *tables[i];
> > > + return 0;
> > > + }
> > > + }
> > > +
> > > + return -EINVAL;
> > > +}
> > > +
> > > +int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > > + struct intel_encoder *encoder)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > +
> > > + if (intel_is_c10phy(i915, phy))
> > > + return intel_c10pll_calc_state(crtc_state, encoder);
> > > + return intel_c20pll_calc_state(crtc_state, encoder); }
> > > +
> > > static bool intel_c20_use_mplla(u32 clock) {
> > > /* 10G and 20G rates use MPLLA */
> > > @@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
> > > return false;
> > > }
> > >
> > > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > > + struct intel_c20pll_state *pll_state) {
> > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > + bool cntx, use_mpllb;
> > > + u32 val;
> > > + int i;
> > > +
> > > + /* 1. Read current context selection */
> > > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> > > +PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> > > +
> > > + /* Read Tx configuration */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> > > + if (cntx)
> > > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_B_TX_CNTX_CFG(i));
> > > + else
> > > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_A_TX_CNTX_CFG(i));
> > > + }
> > > +
> > > + /* Read common configuration */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> > > + if (cntx)
> > > + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_B_CMN_CNTX_CFG(i));
> > > + else
> > > + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_A_CMN_CNTX_CFG(i));
> > > + }
> > > +
> > > + val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > PHY_C20_A_MPLLA_CNTX_CFG(6));
> > > + use_mpllb = val & C20_MPLLB_FRACEN;
> > > +
> > > + if (use_mpllb) {
> > > + /* MPLLA configuration */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> > > + if (cntx)
> > > + pll_state->mplla[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_B_MPLLA_CNTX_CFG(i));
> > > + else
> > > + pll_state->mplla[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_A_MPLLA_CNTX_CFG(i));
> > > + }
> > > + } else {
> > > + /* MPLLB configuration */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> > > + if (cntx)
> > > + pll_state->mpllb[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_B_MPLLB_CNTX_CFG(i));
> > > + else
> > > + pll_state->mpllb[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > > +
> > PHY_C20_A_MPLLB_CNTX_CFG(i));
> > > + }
> > > + }
> > > +}
> > > +
> > > static u8 intel_c20_get_dp_rate(u32 clock) {
> > > switch (clock) {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > index 509d1d12776e..9760c6292c81 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > @@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct intel_encoder
> > *encoder,
> > > const struct intel_c10pll_state *pll_state);
> > void
> > > intel_c10pll_state_verify(struct intel_atomic_state *state,
> > > struct intel_crtc_state *new_crtc_state);
> > > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > > + struct intel_c20pll_state *pll_state);
> > > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state); -
> > int
> > > intel_c10_phy_check_hdmi_link_rate(int clock);
> > > -
> > > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > > +clock); void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder
> > *encoder,
> > > + const struct intel_crtc_state *crtc_state,
> > > + u32 level);
> > > #endif /* __INTEL_CX0_PHY_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index f445f2613adb..44f07011245b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct
> > intel_encoder *encoder,
> > > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >
> > > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > > + if (intel_is_c10phy(i915, phy)) {
> > > + intel_c10pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c10);
> > > + intel_c10pll_dump_hw_state(i915, &crtc_state-
> > >cx0pll_state.c10);
> > > + } else {
> > > + intel_c20pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c20);
> > > + }
> > >
> > > - intel_c10pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c10);
> > > - intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> > > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> > > &crtc_state->cx0pll_state.c10);
> > >
> > > intel_ddi_get_config(encoder, crtc_state); diff --git
> > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c9927e12b95e..4eadf45c0a43 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -997,6 +997,7 @@ struct intel_c10pll_state { };
> > >
> > > struct intel_c20pll_state {
> > > + u32 link_bit_rate;
> > > u32 clock; /* in kHz */
> > > u16 tx[3];
> > > u16 cmn[4];
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index 8141d5184856..65a258507d62 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -58,7 +58,7 @@
> > > #include "intel_panel.h"
> > > #include "intel_snps_phy.h"
> > >
> > > -static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > > *intel_hdmi)
> > > +inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > > +*intel_hdmi)
> > > {
> > > return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
> > > }
> > > @@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > > * FIXME: We will hopefully get an algorithmic way of programming
> > > * the MPLLB for HDMI in the future.
> > > */
> > > - if (IS_METEORLAKE(dev_priv))
> > > - return intel_c10_phy_check_hdmi_link_rate(clock);
> > > + if (DISPLAY_VER(dev_priv) >= 14)
> > > + return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> > > else if (IS_DG2(dev_priv))
> > > return intel_snps_phy_check_hdmi_link_rate(clock);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > > b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > > index 774dda2376ed..492bd3921385 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > > @@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct
> > intel_crtc_state *crtc_state,
> > > int src_max_slices, int src_max_slice_width,
> > > int hdmi_max_slices, int hdmi_throughput);
> > int
> > > intel_hdmi_dsc_get_slice_height(int vactive);
> > > +struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > > +*intel_hdmi);
> > >
> > > #endif /* __INTEL_HDMI_H__ */
> > > --
> > > 2.34.1
> > >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-20 12:40 ` [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout Mika Kahola
2023-04-24 20:56 ` Radhakrishna Sripada
@ 2023-04-27 3:31 ` Murthy, Arun R
2023-04-27 10:25 ` Kahola, Mika
2023-04-28 9:14 ` Andi Shyti
2 siblings, 1 reply; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 3:31 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
> BSpec: 64568
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> 6 files changed, 628 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dd96bf5e179e..61428c5145e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -11,6 +11,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_hdmi.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_tc.h"
> @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> drm_i915_private *i915, enum port port,
> intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> 1); }
>
> +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> port,
> + int lane, u16 addr)
> +{
> + u16 val;
> +
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >>
> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr &
> 0xff,
> +1);
> +
> + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> + val <<= 8;
> + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> +
> + return val;
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed) { @@ -659,6 +677,199 @@ static const struct intel_c10pll_state
> * const mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +/* C20 basic DP 1.4 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> + .link_bit_rate = 162000,
> + .clock = 162000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x5800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x50a8, /* mpllb cfg0 */
> + 0x2120, /* mpllb cfg1 */
> + 0xcd9a, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x5ab8, /* mpllb cfg4 */
> + 0x4c34, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x6000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> + .link_bit_rate = 270000,
> + .clock = 270000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x308c, /* mpllb cfg0 */
> + 0x2110, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> + .link_bit_rate = 540000,
> + .clock = 540000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x108c, /* mpllb cfg0 */
> + 0x2108, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> + .link_bit_rate = 810000,
> + .clock = 810000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x10d2, /* mpllb cfg0 */
> + 0x2108, /* mpllb cfg1 */
> + 0x8d98, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x7166, /* mpllb cfg4 */
> + 0x5f42, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x7800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +/* C20 basic DP 2.0 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> + .link_bit_rate = 1000000, /* 10 Gbps */
> + .clock = 312500,
> + .tx = { 0xbe21, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mplla = { 0x3104, /* mplla cfg0 */
> + 0xd105, /* mplla cfg1 */
> + 0xc025, /* mplla cfg2 */
> + 0xc025, /* mplla cfg3 */
> + 0xa6ab, /* mplla cfg4 */
> + 0x8c00, /* mplla cfg5 */
> + 0x4000, /* mplla cfg6 */
> + 0x0003, /* mplla cfg7 */
> + 0x3555, /* mplla cfg8 */
> + 0x0000, /* mplla cfg9 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> + .link_bit_rate = 1350000, /* 13.5 Gbps */
> + .clock = 421875,
> + .tx = { 0xbea0, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x015f, /* mpllb cfg0 */
> + 0x2205, /* mpllb cfg1 */
> + 0x1b17, /* mpllb cfg2 */
> + 0xffc1, /* mpllb cfg3 */
> + 0xe100, /* mpllb cfg4 */
> + 0xbd00, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> + .link_bit_rate = 2000000, /* 20 Gbps */
> + .clock = 625000,
> + .tx = { 0xbe20, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mplla = { 0x3104, /* mplla cfg0 */
> + 0xd105, /* mplla cfg1 */
> + 0xc025, /* mplla cfg2 */
> + 0xc025, /* mplla cfg3 */
> + 0xa6ab, /* mplla cfg4 */
> + 0x8c00, /* mplla cfg5 */
> + 0x4000, /* mplla cfg6 */
> + 0x0003, /* mplla cfg7 */
> + 0x3555, /* mplla cfg8 */
> + 0x0002, /* mplla cfg9 */
> + },
> +};
> +
> +static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> + &mtl_c20_dp_rbr,
> + &mtl_c20_dp_hbr1,
> + &mtl_c20_dp_hbr2,
> + &mtl_c20_dp_hbr3,
> + &mtl_c20_dp_uhbr10,
> + &mtl_c20_dp_uhbr13_5,
> + &mtl_c20_dp_uhbr20,
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const
> mtl_c10_hdmi_tables[] = {
> NULL,
> };
>
> -int intel_c10_phy_check_hdmi_link_rate(int clock)
> +static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> + .link_bit_rate = 25175,
> + .clock = 25175,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0xa0d2, /* mpllb cfg0 */
> + 0x7d80, /* mpllb cfg1 */
> + 0x0906, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x0200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x0000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> + .link_bit_rate = 27000,
> + .clock = 27000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0xa0e0, /* mpllb cfg0 */
> + 0x7d80, /* mpllb cfg1 */
> + 0x0906, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x8000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> + .link_bit_rate = 74250,
> + .clock = 74250,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x609a, /* mpllb cfg0 */
> + 0x7d40, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> + .link_bit_rate = 148500,
> + .clock = 148500,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x409a, /* mpllb cfg0 */
> + 0x7d20, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> + .link_bit_rate = 594000,
> + .clock = 594000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x009a, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0001, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> + .link_bit_rate = 3000000,
> + .clock = 166670,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x209c, /* mpllb cfg0 */
> + 0x7d10, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x2000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> + .link_bit_rate = 6000000,
> + .clock = 333330,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x009c, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0xca06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x2000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> + .link_bit_rate = 8000000,
> + .clock = 444440,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x00d0, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x4a06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0003, /* mpllb cfg7 */
> + 0x2aaa, /* mpllb cfg8 */
> + 0x0002, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> + .link_bit_rate = 10000000,
> + .clock = 555560,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x1104, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x0a06, /* mpllb cfg2 */
> + 0xbe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0003, /* mpllb cfg7 */
> + 0x3555, /* mpllb cfg8 */
> + 0x0001, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> + .link_bit_rate = 12000000,
> + .clock = 666670,
> + .tx = { 0xbe98, /* tx cfg0 */
> + 0x9800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = { 0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x0138, /* mpllb cfg0 */
> + 0x7d08, /* mpllb cfg1 */
> + 0x5486, /* mpllb cfg2 */
> + 0xfe40, /* mpllb cfg3 */
> + 0x0000, /* mpllb cfg4 */
> + 0x0000, /* mpllb cfg5 */
> + 0x2200, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4000, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0004, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> + &mtl_c20_hdmi_25_175,
> + &mtl_c20_hdmi_27_0,
> + &mtl_c20_hdmi_74_25,
> + &mtl_c20_hdmi_148_5,
> + &mtl_c20_hdmi_594,
> + &mtl_c20_hdmi_300,
> + &mtl_c20_hdmi_600,
> + &mtl_c20_hdmi_800,
> + &mtl_c20_hdmi_1000,
> + &mtl_c20_hdmi_1200,
> + NULL,
> +};
> +
> +static int intel_c10_phy_check_hdmi_link_rate(int clock)
> {
> const struct intel_c10pll_state * const *tables =
> mtl_c10_hdmi_tables;
> int i;
> @@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> - struct intel_encoder *encoder)
> -{
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(i915, encoder->port);
> -
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> -
> - return intel_c10pll_calc_state(crtc_state, encoder);
> -}
> -
> void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c10pll_state *pll_state) { @@ -
> 1427,6 +1901,74 @@ void intel_c10pll_dump_hw_state(struct
> drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i +
> 3]); }
>
> +static int intel_c20_phy_check_hdmi_link_rate(int clock) {
> + const struct intel_c20pll_state * const *tables =
> mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> + return MODE_OK;
> + }
> +
> + return MODE_CLOCK_RANGE;
> +}
> +
> +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> +clock) {
> + struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> + struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_c10_phy_check_hdmi_link_rate(clock);
> + return intel_c20_phy_check_hdmi_link_rate(clock);
> +}
> +
> +static const struct intel_c20pll_state * const *
> +intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + return mtl_c20_dp_tables;
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return mtl_c20_hdmi_tables;
> +
> + MISSING_CASE(encoder->type);
> + return NULL;
> +}
> +
> +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state * const *tables;
> + int i;
> +
> + tables = intel_c20_pll_tables_get(crtc_state, encoder);
> + if (!tables)
> + return -EINVAL;
> +
> + for (i = 0; tables[i]; i++) {
> + if (crtc_state->port_clock == tables[i]->link_bit_rate) {
> + crtc_state->cx0pll_state.c20 = *tables[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_is_c10phy(i915, phy))
> + return intel_c10pll_calc_state(crtc_state, encoder);
> + return intel_c20pll_calc_state(crtc_state, encoder); }
> +
> static bool intel_c20_use_mplla(u32 clock) {
> /* 10G and 20G rates use MPLLA */
> @@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
> return false;
> }
>
> +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c20pll_state *pll_state) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + bool cntx, use_mpllb;
> + u32 val;
> + int i;
> +
> + /* 1. Read current context selection */
> + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> +PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> +
> + /* Read Tx configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> + if (cntx)
> + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> +
> PHY_C20_B_TX_CNTX_CFG(i));
> + else
> + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> >port, INTEL_CX0_LANE0,
> +
> PHY_C20_A_TX_CNTX_CFG(i));
> + }
> +
> + /* Read common configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> + if (cntx)
> + pll_state->cmn[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_B_CMN_CNTX_CFG(i));
> + else
> + pll_state->cmn[i] = intel_c20_sram_read(i915,
> encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_A_CMN_CNTX_CFG(i));
> + }
> +
> + val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_A_MPLLA_CNTX_CFG(6));
> + use_mpllb = val & C20_MPLLB_FRACEN;
> +
> + if (use_mpllb) {
If mpllb is in use why is it that the data read is copied to mplla of pll_state?
I assume that the change is for only context!
> + /* MPLLA configuration */
> + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> + if (cntx)
> + pll_state->mplla[i] =
> intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_B_MPLLA_CNTX_CFG(i));
> + else
> + pll_state->mplla[i] =
> intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_A_MPLLA_CNTX_CFG(i));
> + }
> + } else {
> + /* MPLLB configuration */
Same here, should this be mplla?
Thanks and Regards,
Arun R Murthy
--------------------
> + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> + if (cntx)
> + pll_state->mpllb[i] =
> intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_B_MPLLB_CNTX_CFG(i));
> + else
> + pll_state->mpllb[i] =
> intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> +
> PHY_C20_A_MPLLB_CNTX_CFG(i));
> + }
> + }
> +}
> +
> static u8 intel_c20_get_dp_rate(u32 clock) {
> switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 509d1d12776e..9760c6292c81 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct intel_encoder
> *encoder,
> const struct intel_c10pll_state *pll_state);
> void intel_c10pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state);
> +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c20pll_state *pll_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state); -
> int intel_c10_phy_check_hdmi_link_rate(int clock);
> -
> +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> +clock); void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
> + const struct intel_crtc_state *crtc_state,
> + u32 level);
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index f445f2613adb..44f07011245b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct
> intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + if (intel_is_c10phy(i915, phy)) {
> + intel_c10pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c10);
> + intel_c10pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c10);
> + } else {
> + intel_c20pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c20);
> + }
>
> - intel_c10pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c10);
> - intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> &crtc_state->cx0pll_state.c10);
>
> intel_ddi_get_config(encoder, crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c9927e12b95e..4eadf45c0a43 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -997,6 +997,7 @@ struct intel_c10pll_state { };
>
> struct intel_c20pll_state {
> + u32 link_bit_rate;
> u32 clock; /* in kHz */
> u16 tx[3];
> u16 cmn[4];
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 8141d5184856..65a258507d62 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -58,7 +58,7 @@
> #include "intel_panel.h"
> #include "intel_snps_phy.h"
>
> -static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> *intel_hdmi)
> +inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> +*intel_hdmi)
> {
> return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
> }
> @@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> * FIXME: We will hopefully get an algorithmic way of programming
> * the MPLLB for HDMI in the future.
> */
> - if (IS_METEORLAKE(dev_priv))
> - return intel_c10_phy_check_hdmi_link_rate(clock);
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> else if (IS_DG2(dev_priv))
> return intel_snps_phy_check_hdmi_link_rate(clock);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
> b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index 774dda2376ed..492bd3921385 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct
> intel_crtc_state *crtc_state,
> int src_max_slices, int src_max_slice_width,
> int hdmi_max_slices, int hdmi_throughput);
> int intel_hdmi_dsc_get_slice_height(int vactive);
> +struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> +*intel_hdmi);
>
> #endif /* __INTEL_HDMI_H__ */
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-27 3:31 ` Murthy, Arun R
@ 2023-04-27 10:25 ` Kahola, Mika
0 siblings, 0 replies; 47+ messages in thread
From: Kahola, Mika @ 2023-04-27 10:25 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@intel.com>
> Sent: Thursday, April 27, 2023 6:31 AM
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: RE: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -----Original Message-----
> > From: Kahola, Mika <mika.kahola@intel.com>
> > Sent: Thursday, April 20, 2023 6:11 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Kahola, Mika <mika.kahola@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Nautiyal, Ankit K
> > <ankit.k.nautiyal@intel.com>
> > Subject: [PATCH 02/13] drm/i915/mtl: C20 HW readout
> >
> > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > The PLL settings are based on table, not for algorithmic alternative.
> > For DP 1.4 only MPLLB is in use.
> >
> > Once register settings are done, we read back C20 HW state.
> >
> > BSpec: 64568
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > 6 files changed, 628 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index dd96bf5e179e..61428c5145e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -11,6 +11,7 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > +#include "intel_hdmi.h"
> > #include "intel_panel.h"
> > #include "intel_psr.h"
> > #include "intel_tc.h"
> > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> > drm_i915_private *i915, enum port port,
> > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > 1); }
> >
> > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum
> > +port
> > port,
> > + int lane, u16 addr)
> > +{
> > + u16 val;
> > +
> > + assert_dc_off(i915);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >>
> > 8, 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr &
> > 0xff,
> > +1);
> > +
> > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > + val <<= 8;
> > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > +
> > + return val;
> > +}
> > +
> > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > int lane, u16 addr, u8 clear, u8 set, bool
> > committed) { @@ -659,6 +677,199 @@ static const struct
> > intel_c10pll_state
> > * const mtl_c10_edp_tables[] = {
> > NULL,
> > };
> >
> > +/* C20 basic DP 1.4 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > + .link_bit_rate = 162000,
> > + .clock = 162000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x5800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > + 0x2120, /* mpllb cfg1 */
> > + 0xcd9a, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x5ab8, /* mpllb cfg4 */
> > + 0x4c34, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x6000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > + .link_bit_rate = 270000,
> > + .clock = 270000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x308c, /* mpllb cfg0 */
> > + 0x2110, /* mpllb cfg1 */
> > + 0xcc9c, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x489a, /* mpllb cfg4 */
> > + 0x3f81, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > + .link_bit_rate = 540000,
> > + .clock = 540000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x108c, /* mpllb cfg0 */
> > + 0x2108, /* mpllb cfg1 */
> > + 0xcc9c, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x489a, /* mpllb cfg4 */
> > + 0x3f81, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > + .link_bit_rate = 810000,
> > + .clock = 810000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x10d2, /* mpllb cfg0 */
> > + 0x2108, /* mpllb cfg1 */
> > + 0x8d98, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x7166, /* mpllb cfg4 */
> > + 0x5f42, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x7800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +/* C20 basic DP 2.0 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > + .link_bit_rate = 1000000, /* 10 Gbps */
> > + .clock = 312500,
> > + .tx = { 0xbe21, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mplla = { 0x3104, /* mplla cfg0 */
> > + 0xd105, /* mplla cfg1 */
> > + 0xc025, /* mplla cfg2 */
> > + 0xc025, /* mplla cfg3 */
> > + 0xa6ab, /* mplla cfg4 */
> > + 0x8c00, /* mplla cfg5 */
> > + 0x4000, /* mplla cfg6 */
> > + 0x0003, /* mplla cfg7 */
> > + 0x3555, /* mplla cfg8 */
> > + 0x0000, /* mplla cfg9 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > + .link_bit_rate = 1350000, /* 13.5 Gbps */
> > + .clock = 421875,
> > + .tx = { 0xbea0, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x015f, /* mpllb cfg0 */
> > + 0x2205, /* mpllb cfg1 */
> > + 0x1b17, /* mpllb cfg2 */
> > + 0xffc1, /* mpllb cfg3 */
> > + 0xe100, /* mpllb cfg4 */
> > + 0xbd00, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x4800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0000, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > + .link_bit_rate = 2000000, /* 20 Gbps */
> > + .clock = 625000,
> > + .tx = { 0xbe20, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mplla = { 0x3104, /* mplla cfg0 */
> > + 0xd105, /* mplla cfg1 */
> > + 0xc025, /* mplla cfg2 */
> > + 0xc025, /* mplla cfg3 */
> > + 0xa6ab, /* mplla cfg4 */
> > + 0x8c00, /* mplla cfg5 */
> > + 0x4000, /* mplla cfg6 */
> > + 0x0003, /* mplla cfg7 */
> > + 0x3555, /* mplla cfg8 */
> > + 0x0002, /* mplla cfg9 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> > + &mtl_c20_dp_rbr,
> > + &mtl_c20_dp_hbr1,
> > + &mtl_c20_dp_hbr2,
> > + &mtl_c20_dp_hbr3,
> > + &mtl_c20_dp_uhbr10,
> > + &mtl_c20_dp_uhbr13_5,
> > + &mtl_c20_dp_uhbr20,
> > + NULL,
> > +};
> > +
> > /*
> > * HDMI link rates with 38.4 MHz reference clock.
> > */
> > @@ -1243,7 +1454,281 @@ static const struct intel_c10pll_state * const
> > mtl_c10_hdmi_tables[] = {
> > NULL,
> > };
> >
> > -int intel_c10_phy_check_hdmi_link_rate(int clock)
> > +static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> > + .link_bit_rate = 25175,
> > + .clock = 25175,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0xa0d2, /* mpllb cfg0 */
> > + 0x7d80, /* mpllb cfg1 */
> > + 0x0906, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x0200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x0000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> > + .link_bit_rate = 27000,
> > + .clock = 27000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0xa0e0, /* mpllb cfg0 */
> > + 0x7d80, /* mpllb cfg1 */
> > + 0x0906, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x8000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> > + .link_bit_rate = 74250,
> > + .clock = 74250,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x609a, /* mpllb cfg0 */
> > + 0x7d40, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> > + .link_bit_rate = 148500,
> > + .clock = 148500,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x409a, /* mpllb cfg0 */
> > + 0x7d20, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> > + .link_bit_rate = 594000,
> > + .clock = 594000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x009a, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5800, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0001, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > + .link_bit_rate = 3000000,
> > + .clock = 166670,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x209c, /* mpllb cfg0 */
> > + 0x7d10, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x2000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > + .link_bit_rate = 6000000,
> > + .clock = 333330,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x009c, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0xca06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x2000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > + .link_bit_rate = 8000000,
> > + .clock = 444440,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x00d0, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x4a06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0003, /* mpllb cfg7 */
> > + 0x2aaa, /* mpllb cfg8 */
> > + 0x0002, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > + .link_bit_rate = 10000000,
> > + .clock = 555560,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x1104, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x0a06, /* mpllb cfg2 */
> > + 0xbe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0003, /* mpllb cfg7 */
> > + 0x3555, /* mpllb cfg8 */
> > + 0x0001, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > + .link_bit_rate = 12000000,
> > + .clock = 666670,
> > + .tx = { 0xbe98, /* tx cfg0 */
> > + 0x9800, /* tx cfg1 */
> > + 0x0000, /* tx cfg2 */
> > + },
> > + .cmn = { 0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x0000, /* cmn cfg2 */
> > + 0x0000, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x0138, /* mpllb cfg0 */
> > + 0x7d08, /* mpllb cfg1 */
> > + 0x5486, /* mpllb cfg2 */
> > + 0xfe40, /* mpllb cfg3 */
> > + 0x0000, /* mpllb cfg4 */
> > + 0x0000, /* mpllb cfg5 */
> > + 0x2200, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x4000, /* mpllb cfg8 */
> > + 0x0000, /* mpllb cfg9 */
> > + 0x0004, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> > + &mtl_c20_hdmi_25_175,
> > + &mtl_c20_hdmi_27_0,
> > + &mtl_c20_hdmi_74_25,
> > + &mtl_c20_hdmi_148_5,
> > + &mtl_c20_hdmi_594,
> > + &mtl_c20_hdmi_300,
> > + &mtl_c20_hdmi_600,
> > + &mtl_c20_hdmi_800,
> > + &mtl_c20_hdmi_1000,
> > + &mtl_c20_hdmi_1200,
> > + NULL,
> > +};
> > +
> > +static int intel_c10_phy_check_hdmi_link_rate(int clock)
> > {
> > const struct intel_c10pll_state * const *tables =
> > mtl_c10_hdmi_tables;
> > int i;
> > @@ -1319,17 +1804,6 @@ static int intel_c10pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> > return -EINVAL;
> > }
> >
> > -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > - struct intel_encoder *encoder)
> > -{
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - enum phy phy = intel_port_to_phy(i915, encoder->port);
> > -
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > -
> > - return intel_c10pll_calc_state(crtc_state, encoder);
> > -}
> > -
> > void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> > struct intel_c10pll_state *pll_state) { @@ -
> > 1427,6 +1901,74 @@ void intel_c10pll_dump_hw_state(struct
> > drm_i915_private *i915,
> > i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
> >
> > +static int intel_c20_phy_check_hdmi_link_rate(int clock) {
> > + const struct intel_c20pll_state * const *tables =
> > mtl_c20_hdmi_tables;
> > + int i;
> > +
> > + for (i = 0; tables[i]; i++) {
> > + if (clock == tables[i]->link_bit_rate)
> > + return MODE_OK;
> > + }
> > +
> > + return MODE_CLOCK_RANGE;
> > +}
> > +
> > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > +clock) {
> > + struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> > + struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
> > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> > +
> > + if (intel_is_c10phy(i915, phy))
> > + return intel_c10_phy_check_hdmi_link_rate(clock);
> > + return intel_c20_phy_check_hdmi_link_rate(clock);
> > +}
> > +
> > +static const struct intel_c20pll_state * const *
> > +intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + return mtl_c20_dp_tables;
> > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > + return mtl_c20_hdmi_tables;
> > +
> > + MISSING_CASE(encoder->type);
> > + return NULL;
> > +}
> > +
> > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder) {
> > + const struct intel_c20pll_state * const *tables;
> > + int i;
> > +
> > + tables = intel_c20_pll_tables_get(crtc_state, encoder);
> > + if (!tables)
> > + return -EINVAL;
> > +
> > + for (i = 0; tables[i]; i++) {
> > + if (crtc_state->port_clock == tables[i]->link_bit_rate) {
> > + crtc_state->cx0pll_state.c20 = *tables[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + if (intel_is_c10phy(i915, phy))
> > + return intel_c10pll_calc_state(crtc_state, encoder);
> > + return intel_c20pll_calc_state(crtc_state, encoder); }
> > +
> > static bool intel_c20_use_mplla(u32 clock) {
> > /* 10G and 20G rates use MPLLA */
> > @@ -1436,6 +1978,63 @@ static bool intel_c20_use_mplla(u32 clock)
> > return false;
> > }
> >
> > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c20pll_state *pll_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + bool cntx, use_mpllb;
> > + u32 val;
> > + int i;
> > +
> > + /* 1. Read current context selection */
> > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> > +
> > + /* Read Tx configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> > + if (cntx)
> > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_B_TX_CNTX_CFG(i));
> > + else
> > + pll_state->tx[i] = intel_c20_sram_read(i915, encoder-
> > >port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_A_TX_CNTX_CFG(i));
> > + }
> > +
> > + /* Read common configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> > + if (cntx)
> > + pll_state->cmn[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_B_CMN_CNTX_CFG(i));
> > + else
> > + pll_state->cmn[i] = intel_c20_sram_read(i915,
> > encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_A_CMN_CNTX_CFG(i));
> > + }
> > +
> > + val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > PHY_C20_A_MPLLA_CNTX_CFG(6));
> > + use_mpllb = val & C20_MPLLB_FRACEN;
> > +
> > + if (use_mpllb) {
>
> If mpllb is in use why is it that the data read is copied to mplla of pll_state?
> I assume that the change is for only context!
This should state use_mplla. This is a typo from the change that wasn't useful. Good catch, thanks!
I also noticed that we cannot use mplla_fracen as differentiator between mplla and mpllb. These both has fracen enabled. I was thinking that in this case the differentiator could be mpllx_fracn_quot i.e. tx[8]. For both 10G and 20G rates the franc_quot is 0x3555 which is not used for any other rate.
-Mika-
>
> > + /* MPLLA configuration */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> > + if (cntx)
> > + pll_state->mplla[i] =
> > intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_B_MPLLA_CNTX_CFG(i));
> > + else
> > + pll_state->mplla[i] =
> > intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_A_MPLLA_CNTX_CFG(i));
> > + }
> > + } else {
> > + /* MPLLB configuration */
>
>
> Same here, should this be mplla?
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
> > + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> > + if (cntx)
> > + pll_state->mpllb[i] =
> > intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_B_MPLLB_CNTX_CFG(i));
> > + else
> > + pll_state->mpllb[i] =
> > intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
> > +
> > PHY_C20_A_MPLLB_CNTX_CFG(i));
> > + }
> > + }
> > +}
> > +
> > static u8 intel_c20_get_dp_rate(u32 clock) {
> > switch (clock) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 509d1d12776e..9760c6292c81 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -30,8 +30,12 @@ int intel_c10pll_calc_port_clock(struct
> > intel_encoder *encoder,
> > const struct intel_c10pll_state *pll_state); void
> > intel_c10pll_state_verify(struct intel_atomic_state *state,
> > struct intel_crtc_state *new_crtc_state);
> > +void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c20pll_state *pll_state);
> > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state); -
> int
> > intel_c10_phy_check_hdmi_link_rate(int clock);
> > -
> > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > +clock); void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder
> > *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + u32 level);
> > #endif /* __INTEL_CX0_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index f445f2613adb..44f07011245b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3853,10 +3853,13 @@ static void mtl_ddi_get_config(struct
> > intel_encoder *encoder,
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port);
> >
> > - drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > + if (intel_is_c10phy(i915, phy)) {
> > + intel_c10pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c10);
> > + intel_c10pll_dump_hw_state(i915, &crtc_state-
> > >cx0pll_state.c10);
> > + } else {
> > + intel_c20pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c20);
> > + }
> >
> > - intel_c10pll_readout_hw_state(encoder, &crtc_state-
> > >cx0pll_state.c10);
> > - intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> > &crtc_state->cx0pll_state.c10);
> >
> > intel_ddi_get_config(encoder, crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c9927e12b95e..4eadf45c0a43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -997,6 +997,7 @@ struct intel_c10pll_state { };
> >
> > struct intel_c20pll_state {
> > + u32 link_bit_rate;
> > u32 clock; /* in kHz */
> > u16 tx[3];
> > u16 cmn[4];
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 8141d5184856..65a258507d62 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -58,7 +58,7 @@
> > #include "intel_panel.h"
> > #include "intel_snps_phy.h"
> >
> > -static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > *intel_hdmi)
> > +inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > +*intel_hdmi)
> > {
> > return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
> > }
> > @@ -1865,8 +1865,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > * FIXME: We will hopefully get an algorithmic way of programming
> > * the MPLLB for HDMI in the future.
> > */
> > - if (IS_METEORLAKE(dev_priv))
> > - return intel_c10_phy_check_hdmi_link_rate(clock);
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> > else if (IS_DG2(dev_priv))
> > return intel_snps_phy_check_hdmi_link_rate(clock);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > index 774dda2376ed..492bd3921385 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> > @@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct
> > intel_crtc_state *crtc_state,
> > int src_max_slices, int src_max_slice_width,
> > int hdmi_max_slices, int hdmi_throughput); int
> > intel_hdmi_dsc_get_slice_height(int vactive);
> > +struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi
> > +*intel_hdmi);
> >
> > #endif /* __INTEL_HDMI_H__ */
> > --
> > 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
2023-04-20 12:40 ` [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout Mika Kahola
2023-04-24 20:56 ` Radhakrishna Sripada
2023-04-27 3:31 ` Murthy, Arun R
@ 2023-04-28 9:14 ` Andi Shyti
2 siblings, 0 replies; 47+ messages in thread
From: Andi Shyti @ 2023-04-28 9:14 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
[...]
> +static int intel_c20_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> + return MODE_OK;
> + }
because you are going to resend it... you could remove these
braces here... there are a few cases below, as well.
Andi
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
2023-04-20 12:40 ` [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming Mika Kahola
2023-04-20 12:40 ` [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-24 21:18 ` Radhakrishna Sripada
` (2 more replies)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation Mika Kahola
` (13 subsequent siblings)
16 siblings, 3 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 61428c5145e5..144474540ef4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
}
}
+void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+ const struct intel_c20pll_state *hw_state)
+{
+ int i;
+
+ drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
+ drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+ hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
+ drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+ hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
+
+ if (intel_c20_use_mplla(hw_state->clock)) {
+ for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
+ drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
+ drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+ }
+}
+
static u8 intel_c20_get_dp_rate(u32 clock)
{
switch (clock) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 9760c6292c81..c643aae27bac 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state);
+void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+ const struct intel_c20pll_state *hw_state);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 44f07011245b..d414dd8c26bf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
} else {
intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
+ intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
}
crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
2023-04-20 12:40 ` [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state Mika Kahola
@ 2023-04-24 21:18 ` Radhakrishna Sripada
2023-04-27 3:37 ` Murthy, Arun R
2023-04-28 9:15 ` Andi Shyti
2 siblings, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-24 21:18 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:40PM +0300, Mika Kahola wrote:
> As we already do with C10 chip, let's dump the pll
> hw state for C20 as well.
>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 61428c5145e5..144474540ef4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> }
> }
>
> +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> + const struct intel_c20pll_state *hw_state)
> +{
> + int i;
> +
> + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
> + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
> + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
> +
> + if (intel_c20_use_mplla(hw_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
> + } else {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
> + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
> + }
> +}
> +
> static u8 intel_c20_get_dp_rate(u32 clock)
> {
> switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9760c6292c81..c643aae27bac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state);
> void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state);
> +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> + const struct intel_c20pll_state *hw_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 44f07011245b..d414dd8c26bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
> intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> } else {
> intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
> + intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
> }
>
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
2023-04-20 12:40 ` [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state Mika Kahola
2023-04-24 21:18 ` Radhakrishna Sripada
@ 2023-04-27 3:37 ` Murthy, Arun R
2023-04-28 9:15 ` Andi Shyti
2 siblings, 0 replies; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 3:37 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
>
> As we already do with C10 chip, let's dump the pll hw state for C20 as well.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 61428c5145e5..144474540ef4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> }
> }
>
> +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> + const struct intel_c20pll_state *hw_state) {
> + int i;
> +
> + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
> + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] =
> 0x%.4x\n",
> + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x,
> cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
> + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2],
> +hw_state->cmn[3]);
> +
> + if (intel_c20_use_mplla(hw_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n",
> i, hw_state->mplla[i]);
> + } else {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
> + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n",
> i, hw_state->mpllb[i]);
> + }
> +}
> +
> static u8 intel_c20_get_dp_rate(u32 clock) {
> switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9760c6292c81..c643aae27bac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state
> *state,
> struct intel_crtc_state *new_crtc_state); void
> intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state);
> +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> + const struct intel_c20pll_state *hw_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 44f07011245b..d414dd8c26bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder
> *encoder,
> intel_c10pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c10);
> } else {
> intel_c20pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c20);
> + intel_c20pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c20);
> }
>
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> &crtc_state->cx0pll_state.c10);
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
2023-04-20 12:40 ` [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state Mika Kahola
2023-04-24 21:18 ` Radhakrishna Sripada
2023-04-27 3:37 ` Murthy, Arun R
@ 2023-04-28 9:15 ` Andi Shyti
2 siblings, 0 replies; 47+ messages in thread
From: Andi Shyti @ 2023-04-28 9:15 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
> +
> + if (intel_c20_use_mplla(hw_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
> + } else {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
> + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
> + }
if you're going to resend it, brackets are nnot needed here.
Andi
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (2 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-25 19:08 ` Radhakrishna Sripada
2023-04-27 3:50 ` Murthy, Arun R
2023-04-20 12:40 ` [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
` (12 subsequent siblings)
16 siblings, 2 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Calculate port clock with C20 phy.
BSpec: 64568
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +
5 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 144474540ef4..f7720acaf58c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2274,6 +2274,51 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
return tmpclk;
}
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state)
+{
+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+ unsigned int multiplier, refclk = 38400;
+ unsigned int tx_clk_div;
+ unsigned int ref_clk_mpllb_div;
+ unsigned int fb_clk_div4_en;
+ unsigned int ref, vco;
+ unsigned int tx_rate_mult;
+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+ tx_rate_mult = 1;
+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+ frac_quot = pll_state->mpllb[8];
+ frac_rem = pll_state->mpllb[9];
+ frac_den = pll_state->mpllb[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
+ fb_clk_div4_en = 0;
+ } else {
+ tx_rate_mult = 2;
+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+ frac_quot = pll_state->mplla[8];
+ frac_rem = pll_state->mplla[9];
+ frac_den = pll_state->mplla[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
+ }
+
+ if (frac_en)
+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+ else
+ frac = 0;
+
+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
+
+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c643aae27bac..83bd3500091b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -34,6 +34,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state);
void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_c20pll_state *hw_state);
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 6fcb1680fb54..a5e5bee24533 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -195,17 +195,21 @@
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
#define C20_MPLLA_FRACEN REG_BIT(14)
+#define C20_FB_CLK_DIV4_EN REG_BIT(13)
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
#define C20_MPLLB_FRACEN REG_BIT(13)
+#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
+#define C20_PHY_USE_MPLLB REG_BIT(7)
#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d414dd8c26bf..8e6d6afca400 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3856,13 +3856,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
if (intel_is_c10phy(i915, phy)) {
intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
+ crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
} else {
intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
}
- crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
-
intel_ddi_get_config(encoder, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a9fbef0fa817..ca0f362a40e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1014,6 +1014,8 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
/* TODO: Do the readback via intel_compute_shared_dplls() */
if (intel_is_c10phy(i915, phy))
crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
+ else
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation
2023-04-20 12:40 ` [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation Mika Kahola
@ 2023-04-25 19:08 ` Radhakrishna Sripada
2023-04-27 3:50 ` Murthy, Arun R
1 sibling, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-25 19:08 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:41PM +0300, Mika Kahola wrote:
> Calculate port clock with C20 phy.
>
> BSpec: 64568
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 2 +
> 5 files changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 144474540ef4..f7720acaf58c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2274,6 +2274,51 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> return tmpclk;
> }
>
> +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c20pll_state *pll_state)
> +{
> + unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> + unsigned int multiplier, refclk = 38400;
> + unsigned int tx_clk_div;
> + unsigned int ref_clk_mpllb_div;
> + unsigned int fb_clk_div4_en;
> + unsigned int ref, vco;
> + unsigned int tx_rate_mult;
> + unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
> +
> + if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
This method of judging mplla vs mpllb seems more appropriate than the one used
during intel_c20pll_readout_hw_state in patch 02/13.
Update 2/13 mplla vs mpllb selection based on this logic.
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> + tx_rate_mult = 1;
> + frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
> + frac_quot = pll_state->mpllb[8];
> + frac_rem = pll_state->mpllb[9];
> + frac_den = pll_state->mpllb[7];
> + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
> + tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
> + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
> + fb_clk_div4_en = 0;
> + } else {
> + tx_rate_mult = 2;
> + frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
> + frac_quot = pll_state->mplla[8];
> + frac_rem = pll_state->mplla[9];
> + frac_den = pll_state->mplla[7];
> + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
> + tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
> + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
> + fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
> + }
> +
> + if (frac_en)
> + frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
> + else
> + frac = 0;
> +
> + ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
> + vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
> +
> + return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
> +}
> +
> static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> bool lane_reversal)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c643aae27bac..83bd3500091b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -34,6 +34,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state);
> void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> const struct intel_c20pll_state *hw_state);
> +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c20pll_state *pll_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 6fcb1680fb54..a5e5bee24533 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -195,17 +195,21 @@
> #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> #define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
> #define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
> +#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
> #define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
> #define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
> #define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
> #define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
> #define C20_MPLLA_FRACEN REG_BIT(14)
> +#define C20_FB_CLK_DIV4_EN REG_BIT(13)
> #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
> #define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
> #define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
> #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
> #define C20_MPLLB_FRACEN REG_BIT(13)
> +#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
> #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> +#define C20_PHY_USE_MPLLB REG_BIT(7)
>
> #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d414dd8c26bf..8e6d6afca400 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3856,13 +3856,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
> if (intel_is_c10phy(i915, phy)) {
> intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
> intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> + crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> } else {
> intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
> intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
> + crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
> }
>
> - crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> -
> intel_ddi_get_config(encoder, crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a9fbef0fa817..ca0f362a40e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1014,6 +1014,8 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> /* TODO: Do the readback via intel_compute_shared_dplls() */
> if (intel_is_c10phy(i915, phy))
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> + else
> + crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
>
> crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation
2023-04-20 12:40 ` [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation Mika Kahola
2023-04-25 19:08 ` Radhakrishna Sripada
@ 2023-04-27 3:50 ` Murthy, Arun R
1 sibling, 0 replies; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 3:50 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation
>
> Calculate port clock with C20 phy.
>
> BSpec: 64568
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
-------------------
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 2 +
> 5 files changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 144474540ef4..f7720acaf58c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2274,6 +2274,51 @@ int intel_c10pll_calc_port_clock(struct
> intel_encoder *encoder,
> return tmpclk;
> }
>
> +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c20pll_state *pll_state) {
> + unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> + unsigned int multiplier, refclk = 38400;
> + unsigned int tx_clk_div;
> + unsigned int ref_clk_mpllb_div;
> + unsigned int fb_clk_div4_en;
> + unsigned int ref, vco;
> + unsigned int tx_rate_mult;
> + unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE,
> +pll_state->tx[0]);
> +
> + if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
> + tx_rate_mult = 1;
> + frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state-
> >mpllb[6]);
> + frac_quot = pll_state->mpllb[8];
> + frac_rem = pll_state->mpllb[9];
> + frac_den = pll_state->mpllb[7];
> + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mpllb[0]);
> + tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK,
> pll_state->mpllb[0]);
> + ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
> + fb_clk_div4_en = 0;
> + } else {
> + tx_rate_mult = 2;
> + frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state-
> >mplla[6]);
> + frac_quot = pll_state->mplla[8];
> + frac_rem = pll_state->mplla[9];
> + frac_den = pll_state->mplla[7];
> + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mplla[0]);
> + tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK,
> pll_state->mplla[1]);
> + ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
> + fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN,
> pll_state->mplla[0]);
> + }
> +
> + if (frac_en)
> + frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem,
> frac_den);
> + else
> + frac = 0;
> +
> + ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
> ref_clk_mpllb_div);
> + vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17
> - 2))
> ++ frac) >> 17, 10);
> +
> + return vco << tx_rate_mult >> tx_clk_div >> tx_rate; }
> +
> static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> bool lane_reversal)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c643aae27bac..83bd3500091b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -34,6 +34,8 @@ void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> struct intel_c20pll_state *pll_state); void
> intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> const struct intel_c20pll_state *hw_state);
> +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c20pll_state *pll_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 6fcb1680fb54..a5e5bee24533 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -195,17 +195,21 @@
> #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> #define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
> #define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
> +#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
> #define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
> #define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
> #define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
> #define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
> #define C20_MPLLA_FRACEN REG_BIT(14)
> +#define C20_FB_CLK_DIV4_EN REG_BIT(13)
> #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
> #define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
> #define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
> #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
> #define C20_MPLLB_FRACEN REG_BIT(13)
> +#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
> #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> +#define C20_PHY_USE_MPLLB REG_BIT(7)
>
> #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D +
> (idx))
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d414dd8c26bf..8e6d6afca400 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3856,13 +3856,13 @@ static void mtl_ddi_get_config(struct
> intel_encoder *encoder,
> if (intel_is_c10phy(i915, phy)) {
> intel_c10pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c10);
> intel_c10pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c10);
> + crtc_state->port_clock =
> intel_c10pll_calc_port_clock(encoder,
> +&crtc_state->cx0pll_state.c10);
> } else {
> intel_c20pll_readout_hw_state(encoder, &crtc_state-
> >cx0pll_state.c20);
> intel_c20pll_dump_hw_state(i915, &crtc_state-
> >cx0pll_state.c20);
> + crtc_state->port_clock =
> intel_c20pll_calc_port_clock(encoder,
> +&crtc_state->cx0pll_state.c20);
> }
>
> - crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> &crtc_state->cx0pll_state.c10);
> -
> intel_ddi_get_config(encoder, crtc_state); }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a9fbef0fa817..ca0f362a40e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1014,6 +1014,8 @@ static int mtl_crtc_compute_clock(struct
> intel_atomic_state *state,
> /* TODO: Do the readback via intel_compute_shared_dplls() */
> if (intel_is_c10phy(i915, phy))
> crtc_state->port_clock =
> intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> + else
> + crtc_state->port_clock =
> intel_c20pll_calc_port_clock(encoder,
> +&crtc_state->cx0pll_state.c20);
>
> crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence for C20
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (3 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-27 4:29 ` Murthy, Arun R
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
` (11 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display/intel_ddi_buf_trans.c | 53 ++++++++++++++++++-
2 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index a5e5bee24533..5305cc8aad8e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -211,6 +211,10 @@
#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
#define C20_PHY_USE_MPLLB REG_BIT(7)
+/* C20 Phy VSwing Masks */
+#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
+#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
+
#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cd4becbae098..b7d20485bde5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_cx0_phy.h"
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
* them for both DP and FDI transports, allowing those ports to
@@ -1048,12 +1049,52 @@ static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = {
{ .snps = { 62, 0, 0 } }, /* preset 9 */
};
-static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+static const struct intel_ddi_buf_trans mtl_cx0_trans = {
.entries = _mtl_c10_trans_dp14,
.num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
.hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
};
+/* DP2.0 */
+static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
+ { .snps = { 48, 0, 0 } }, /* preset 0 */
+ { .snps = { 43, 0, 5 } }, /* preset 1 */
+ { .snps = { 40, 0, 8 } }, /* preset 2 */
+ { .snps = { 37, 0, 11 } }, /* preset 3 */
+ { .snps = { 33, 0, 15 } }, /* preset 4 */
+ { .snps = { 46, 2, 0 } }, /* preset 5 */
+ { .snps = { 42, 2, 4 } }, /* preset 6 */
+ { .snps = { 38, 2, 8 } }, /* preset 7 */
+ { .snps = { 35, 2, 11 } }, /* preset 8 */
+ { .snps = { 33, 2, 13 } }, /* preset 9 */
+ { .snps = { 44, 4, 0 } }, /* preset 10 */
+ { .snps = { 40, 4, 4 } }, /* preset 11 */
+ { .snps = { 37, 4, 7 } }, /* preset 12 */
+ { .snps = { 33, 4, 11 } }, /* preset 13 */
+ { .snps = { 40, 8, 0 } }, /* preset 14 */
+ { .snps = { 28, 2, 2 } }, /* preset 15 */
+};
+
+/* HDMI2.0 */
+static const union intel_ddi_buf_trans_entry _mtl_c20_trans_hdmi[] = {
+ { .snps = { 48, 0, 0 } }, /* preset 0 */
+ { .snps = { 38, 4, 6 } }, /* preset 1 */
+ { .snps = { 36, 4, 8 } }, /* preset 2 */
+ { .snps = { 34, 4, 10 } }, /* preset 3 */
+ { .snps = { 32, 4, 12 } }, /* preset 4 */
+};
+
+static const struct intel_ddi_buf_trans mtl_c20_trans_hdmi = {
+ .entries = _mtl_c20_trans_hdmi,
+ .num_entries = ARRAY_SIZE(_mtl_c20_trans_hdmi),
+ .hdmi_default_entry = 0,
+};
+
+static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
+ .entries = _mtl_c20_trans_uhbr,
+ .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1630,7 +1671,15 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000)
+ return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))
+ return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
+ else
+ return intel_get_buf_trans(&mtl_cx0_trans, n_entries);
}
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence for C20
2023-04-20 12:40 ` [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
@ 2023-04-27 4:29 ` Murthy, Arun R
0 siblings, 0 replies; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 4:29 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence
> for C20
>
> DP1.4 and DP20 voltage swing sequence for C20 phy.
>
> Bspec: 65449, 67636, 67610
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
-------------------
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
> .../drm/i915/display/intel_ddi_buf_trans.c | 53 ++++++++++++++++++-
> 2 files changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index a5e5bee24533..5305cc8aad8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -211,6 +211,10 @@
> #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
> #define C20_PHY_USE_MPLLB REG_BIT(7)
>
> +/* C20 Phy VSwing Masks */
> +#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
> +#define C20_PHY_VSWING_PREEMPH(val)
> REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
> +
> #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D +
> (idx))
>
> #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index cd4becbae098..b7d20485bde5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -9,6 +9,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_cx0_phy.h"
>
> /* HDMI/DVI modes ignore everything but the last 2 items. So we share
> * them for both DP and FDI transports, allowing those ports to @@ -
> 1048,12 +1049,52 @@ static const union intel_ddi_buf_trans_entry
> _mtl_c10_trans_dp14[] = {
> { .snps = { 62, 0, 0 } }, /* preset 9 */
> };
>
> -static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
> +static const struct intel_ddi_buf_trans mtl_cx0_trans = {
> .entries = _mtl_c10_trans_dp14,
> .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
> .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1, };
>
> +/* DP2.0 */
> +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
> + { .snps = { 48, 0, 0 } }, /* preset 0 */
> + { .snps = { 43, 0, 5 } }, /* preset 1 */
> + { .snps = { 40, 0, 8 } }, /* preset 2 */
> + { .snps = { 37, 0, 11 } }, /* preset 3 */
> + { .snps = { 33, 0, 15 } }, /* preset 4 */
> + { .snps = { 46, 2, 0 } }, /* preset 5 */
> + { .snps = { 42, 2, 4 } }, /* preset 6 */
> + { .snps = { 38, 2, 8 } }, /* preset 7 */
> + { .snps = { 35, 2, 11 } }, /* preset 8 */
> + { .snps = { 33, 2, 13 } }, /* preset 9 */
> + { .snps = { 44, 4, 0 } }, /* preset 10 */
> + { .snps = { 40, 4, 4 } }, /* preset 11 */
> + { .snps = { 37, 4, 7 } }, /* preset 12 */
> + { .snps = { 33, 4, 11 } }, /* preset 13 */
> + { .snps = { 40, 8, 0 } }, /* preset 14 */
> + { .snps = { 28, 2, 2 } }, /* preset 15 */
> +};
> +
> +/* HDMI2.0 */
> +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_hdmi[] = {
> + { .snps = { 48, 0, 0 } }, /* preset 0 */
> + { .snps = { 38, 4, 6 } }, /* preset 1 */
> + { .snps = { 36, 4, 8 } }, /* preset 2 */
> + { .snps = { 34, 4, 10 } }, /* preset 3 */
> + { .snps = { 32, 4, 12 } }, /* preset 4 */
> +};
> +
> +static const struct intel_ddi_buf_trans mtl_c20_trans_hdmi = {
> + .entries = _mtl_c20_trans_hdmi,
> + .num_entries = ARRAY_SIZE(_mtl_c20_trans_hdmi),
> + .hdmi_default_entry = 0,
> +};
> +
> +static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
> + .entries = _mtl_c20_trans_uhbr,
> + .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), };
> +
> bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) {
> return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
> @@ -1630,7 +1671,15 @@ mtl_get_cx0_buf_trans(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state,
> int *n_entries)
> {
> - return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock
> >= 1000000)
> + return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_is_c10phy(i915, phy)))
> + return intel_get_buf_trans(&mtl_c20_trans_hdmi,
> n_entries);
> + else
> + return intel_get_buf_trans(&mtl_cx0_trans, n_entries);
> }
>
> void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (4 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 05/13] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-24 18:09 ` Radhakrishna Sripada
` (3 more replies)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
` (10 subsequent siblings)
16 siblings, 4 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f7720acaf58c..4231ba98f075 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
/* TODO: HDMI FRL */
- /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
- val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ /* DP2.0 10G and 20G rates enable MPLLA*/
+ if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+ val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
+ else
+ val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
@ 2023-04-24 18:09 ` Radhakrishna Sripada
2023-04-27 4:31 ` Murthy, Arun R
` (2 subsequent siblings)
3 siblings, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-24 18:09 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:43PM +0300, Mika Kahola wrote:
> Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
- Radhakrishna(RK) Sripada
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f7720acaf58c..4231ba98f075 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> - val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> + /* DP2.0 10G and 20G rates enable MPLLA*/
> + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
> + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
> + else
> + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
2023-04-24 18:09 ` Radhakrishna Sripada
@ 2023-04-27 4:31 ` Murthy, Arun R
2023-04-27 9:14 ` Manna, Animesh
2023-05-03 8:25 ` Jani Nikula
3 siblings, 0 replies; 47+ messages in thread
From: Murthy, Arun R @ 2023-04-27 4:31 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates
> use MPLLA
>
> Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f7720acaf58c..4231ba98f075 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
> val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> - val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
> + /* DP2.0 10G and 20G rates enable MPLLA*/
> + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> 2000000)
> + val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLA : 0;
> + else
> + val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
2023-04-24 18:09 ` Radhakrishna Sripada
2023-04-27 4:31 ` Murthy, Arun R
@ 2023-04-27 9:14 ` Manna, Animesh
2023-05-03 8:25 ` Jani Nikula
3 siblings, 0 replies; 47+ messages in thread
From: Manna, Animesh @ 2023-04-27 9:14 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates
> use MPLLA
>
> Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Need to fix a typo here. It will be 10G and 20G.
Regards,
Animesh
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f7720acaf58c..4231ba98f075 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
> val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> - val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
> + /* DP2.0 10G and 20G rates enable MPLLA*/
> + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> 2000000)
> + val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLA : 0;
> + else
> + val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> --
> 2.34.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
` (2 preceding siblings ...)
2023-04-27 9:14 ` Manna, Animesh
@ 2023-05-03 8:25 ` Jani Nikula
3 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-05-03 8:25 UTC (permalink / raw)
To: Mika Kahola, intel-gfx
On Thu, 20 Apr 2023, Mika Kahola <mika.kahola@intel.com> wrote:
> Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f7720acaf58c..4231ba98f075 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> /* TODO: HDMI FRL */
> - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> - val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> + /* DP2.0 10G and 20G rates enable MPLLA*/
> + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
Please use intel_dp_is_uhbr().
> + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
> + else
> + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (5 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-25 19:32 ` Radhakrishna Sripada
2023-04-28 9:20 ` Andi Shyti
2023-04-20 12:40 ` [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
` (9 subsequent siblings)
16 siblings, 2 replies; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 138 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4231ba98f075..9722d3f1b926 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2600,8 +2600,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
return val;
}
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2676,7 +2676,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-void intel_cx0pll_disable(struct intel_encoder *encoder)
+static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+{
+ switch (clock) {
+ case 162000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+ case 270000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_270;
+ case 540000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_540;
+ case 810000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_810;
+ default:
+ MISSING_CASE(clock);
+ return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+ }
+}
+
+static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ u32 val = 0;
+
+ /*
+ * 1. Program PORT_CLOCK_CTL REGISTER to configure
+ * clock muxes, gating and SSC
+ */
+ val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
+ val |= XELPDP_FORWARD_CLOCK_UNGATE;
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
+
+ /* 2. Read back PORT_CLOCK_CTL REGISTER */
+ val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+
+ /*
+ * 3. Follow the Display Voltage Frequency Switching - Sequence
+ * Before Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
+ */
+ val |= XELPDP_TBT_CLOCK_REQUEST;
+ intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+
+ /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_ACK,
+ XELPDP_TBT_CLOCK_ACK,
+ 100, 0, NULL))
+ drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
+ encoder->base.base.id, encoder->base.name, phy_name(phy));
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 7. Program DDI_CLK_VALFREQ to match intended DDI
+ * clock frequency.
+ */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ crtc_state->port_clock);
+}
+
+void intel_mtl_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ intel_mtl_tbt_pll_enable(encoder, crtc_state);
+ else
+ intel_cx0pll_enable(encoder, crtc_state);
+}
+
+static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2728,6 +2807,56 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
intel_cx0_phy_transaction_end(encoder, wakeref);
}
+static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ /*
+ * 1. Follow the Display Voltage Frequency Switching Sequence Before
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_REQUEST, 0);
+
+ /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_ACK,
+ ~XELPDP_TBT_CLOCK_ACK,
+ 10, 0, NULL))
+ drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
+ encoder->base.base.id, encoder->base.name, phy_name(phy));
+
+ /*
+ * 4. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 5. Program PORT CLOCK CTRL register to disable and gate clocks
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_FORWARD_CLOCK_UNGATE, 0);
+
+ /* 6. Program DDI_CLK_VALFREQ to 0. */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+}
+
+void intel_mtl_pll_disable(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ intel_mtl_tbt_pll_disable(encoder);
+ else
+ intel_cx0pll_disable(encoder);
+}
+
void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 83bd3500091b..9ea6310b6d79 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -19,9 +19,9 @@ struct intel_crtc_state;
enum phy;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
-void intel_cx0pll_disable(struct intel_encoder *encoder);
+void intel_mtl_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_disable(struct intel_encoder *encoder);
void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -42,4 +42,5 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 level);
+int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8e6d6afca400..c18226edacac 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4779,8 +4779,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->pipe_mask = ~0;
if (DISPLAY_VER(dev_priv) >= 14) {
- encoder->enable_clock = intel_cx0pll_enable;
- encoder->disable_clock = intel_cx0pll_disable;
+ encoder->enable_clock = intel_mtl_pll_enable;
+ encoder->disable_clock = intel_mtl_pll_disable;
encoder->get_config = mtl_ddi_get_config;
} else if (IS_DG2(dev_priv)) {
encoder->enable_clock = intel_mpllb_enable;
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
2023-04-20 12:40 ` [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
@ 2023-04-25 19:32 ` Radhakrishna Sripada
2023-04-28 9:20 ` Andi Shyti
1 sibling, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-25 19:32 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.
>
Bspec: 64568
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> 3 files changed, 138 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 4231ba98f075..9722d3f1b926 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2600,8 +2600,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> return val;
> }
>
> -void intel_cx0pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +static void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> @@ -2676,7 +2676,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> -void intel_cx0pll_disable(struct intel_encoder *encoder)
> +static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
> +{
> + switch (clock) {
> + case 162000:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> + case 270000:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_270;
> + case 540000:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_540;
> + case 810000:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_810;
> + default:
> + MISSING_CASE(clock);
> + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> + }
> +}
> +
> +static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + u32 val = 0;
> +
> + /*
> + * 1. Program PORT_CLOCK_CTL REGISTER to configure
> + * clock muxes, gating and SSC
> + */
> + val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
> + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
> +
> + /* 2. Read back PORT_CLOCK_CTL REGISTER */
> + val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +
> + /*
> + * 3. Follow the Display Voltage Frequency Switching - Sequence
> + * Before Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
> + */
> + val |= XELPDP_TBT_CLOCK_REQUEST;
> + intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> +
> + /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> + if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
intel_de_wait_for_register can be used here.
> + XELPDP_TBT_CLOCK_ACK,
> + XELPDP_TBT_CLOCK_ACK,
> + 100, 0, NULL))
> + drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
> + encoder->base.base.id, encoder->base.name, phy_name(phy));
> +
> + /*
> + * 6. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 7. Program DDI_CLK_VALFREQ to match intended DDI
> + * clock frequency.
> + */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> + crtc_state->port_clock);
> +}
> +
> +void intel_mtl_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + intel_mtl_tbt_pll_enable(encoder, crtc_state);
> + else
> + intel_cx0pll_enable(encoder, crtc_state);
> +}
> +
> +static void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> @@ -2728,6 +2807,56 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> +static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + /*
> + * 1. Follow the Display Voltage Frequency Switching Sequence Before
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_TBT_CLOCK_REQUEST, 0);
> +
> + /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> + if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
intel_de_wait_for_register can be used here.
With that,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> + XELPDP_TBT_CLOCK_ACK,
> + ~XELPDP_TBT_CLOCK_ACK,
> + 10, 0, NULL))
> + drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
> + encoder->base.base.id, encoder->base.name, phy_name(phy));
> +
> + /*
> + * 4. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 5. Program PORT CLOCK CTRL register to disable and gate clocks
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_FORWARD_CLOCK_UNGATE, 0);
> +
> + /* 6. Program DDI_CLK_VALFREQ to 0. */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> +}
> +
> +void intel_mtl_pll_disable(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + intel_mtl_tbt_pll_disable(encoder);
> + else
> + intel_cx0pll_disable(encoder);
> +}
> +
> void intel_c10pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 83bd3500091b..9ea6310b6d79 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -19,9 +19,9 @@ struct intel_crtc_state;
> enum phy;
>
> bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
> -void intel_cx0pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state);
> -void intel_cx0pll_disable(struct intel_encoder *encoder);
> +void intel_mtl_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +void intel_mtl_pll_disable(struct intel_encoder *encoder);
> void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
> int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
> void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
> @@ -42,4 +42,5 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> u32 level);
> +int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8e6d6afca400..c18226edacac 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4779,8 +4779,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->pipe_mask = ~0;
>
> if (DISPLAY_VER(dev_priv) >= 14) {
> - encoder->enable_clock = intel_cx0pll_enable;
> - encoder->disable_clock = intel_cx0pll_disable;
> + encoder->enable_clock = intel_mtl_pll_enable;
> + encoder->disable_clock = intel_mtl_pll_disable;
> encoder->get_config = mtl_ddi_get_config;
> } else if (IS_DG2(dev_priv)) {
> encoder->enable_clock = intel_mpllb_enable;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
2023-04-20 12:40 ` [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
2023-04-25 19:32 ` Radhakrishna Sripada
@ 2023-04-28 9:20 ` Andi Shyti
1 sibling, 0 replies; 47+ messages in thread
From: Andi Shyti @ 2023-04-28 9:20 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.
if you will resend it:
/Enabling/Enable/
Andi
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (6 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-25 20:11 ` Radhakrishna Sripada
2023-04-20 12:40 ` [Intel-gfx] [PATCH 09/13] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
` (8 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9722d3f1b926..dc0555505e61 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2676,6 +2676,33 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
+int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ u32 clock;
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+
+ clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
+
+ switch (clock) {
+ case XELPDP_DDI_CLOCK_SELECT_TBT_162:
+ return 162000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_270:
+ return 270000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_540:
+ return 540000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_810:
+ return 810000;
+ default:
+ MISSING_CASE(clock);
+ return 162000;
+ }
+}
+
static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
{
switch (clock) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 9ea6310b6d79..c1b8f7980f69 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -42,5 +42,5 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 level);
-int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
+int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c18226edacac..8f0f858cde31 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3852,8 +3852,11 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- if (intel_is_c10phy(i915, phy)) {
+ if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
+ crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
+ } else if (intel_is_c10phy(i915, phy)) {
intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state
2023-04-20 12:40 ` [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
@ 2023-04-25 20:11 ` Radhakrishna Sripada
0 siblings, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-25 20:11 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:45PM +0300, Mika Kahola wrote:
> Readout hw state for Thunderbolt.
>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
> 3 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9722d3f1b926..dc0555505e61 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2676,6 +2676,33 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> +int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + u32 clock;
> + u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +
> + clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
> +
> + drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
> + drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
> + drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
> +
> + switch (clock) {
> + case XELPDP_DDI_CLOCK_SELECT_TBT_162:
> + return 162000;
> + case XELPDP_DDI_CLOCK_SELECT_TBT_270:
> + return 270000;
> + case XELPDP_DDI_CLOCK_SELECT_TBT_540:
> + return 540000;
> + case XELPDP_DDI_CLOCK_SELECT_TBT_810:
> + return 810000;
> + default:
> + MISSING_CASE(clock);
> + return 162000;
> + }
> +}
> +
> static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
> {
> switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9ea6310b6d79..c1b8f7980f69 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -42,5 +42,5 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> u32 level);
> -int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
> +int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c18226edacac..8f0f858cde31 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3852,8 +3852,11 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>
> - if (intel_is_c10phy(i915, phy)) {
> + if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> + crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> + } else if (intel_is_c10phy(i915, phy)) {
> intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
> intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
> crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 09/13] drm/i915/mtl: Define mask for DDI AUX interrupts
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (7 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-25 20:29 ` Radhakrishna Sripada
2023-04-20 12:40 ` [Intel-gfx] [PATCH 10/13] drm/i915/mtl: Power up TCSS Mika Kahola
` (7 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
From: Gustavo Sousa <gustavo.sousa@intel.com>
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b94b8ca8ec9..e5f12aa141f6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1938,7 +1938,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 13)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB;
+ else if (DISPLAY_VER(dev_priv) >= 13)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 09/13] drm/i915/mtl: Define mask for DDI AUX interrupts
2023-04-20 12:40 ` [Intel-gfx] [PATCH 09/13] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
@ 2023-04-25 20:29 ` Radhakrishna Sripada
0 siblings, 0 replies; 47+ messages in thread
From: Radhakrishna Sripada @ 2023-04-25 20:29 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:46PM +0300, Mika Kahola wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
>
> Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
> Interrupt registers. The bits for Type-C ports are defined in the PICA
> interrupt registers.
>
> BSpec: 50064
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Missing S-o-b, with that,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2b94b8ca8ec9..e5f12aa141f6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1938,7 +1938,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
> {
> u32 mask;
>
> - if (DISPLAY_VER(dev_priv) >= 13)
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return TGL_DE_PORT_AUX_DDIA |
> + TGL_DE_PORT_AUX_DDIB;
> + else if (DISPLAY_VER(dev_priv) >= 13)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB |
> TGL_DE_PORT_AUX_DDIC |
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 10/13] drm/i915/mtl: Power up TCSS
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (8 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 09/13] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-27 16:09 ` Matt Atwood
2023-04-20 12:40 ` [Intel-gfx] [PATCH 11/13] drm/i915/mtl: TypeC HPD live status query Mika Kahola
` (6 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 199 ++++++++++++++++++-
5 files changed, 216 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dc0555505e61..97d80adb921f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2884,6 +2884,25 @@ void intel_mtl_pll_disable(struct intel_encoder *encoder)
intel_cx0pll_disable(encoder);
}
+enum icl_port_dpll_id
+intel_mtl_port_pll_type(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ /*
+ * TODO: Determine the PLL type from the SW state, once MTL PLL
+ * handling is done via the standard shared DPLL framework.
+ */
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+
+ if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
+ clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
+ return ICL_PORT_DPLL_MG_PHY;
+ else
+ return ICL_PORT_DPLL_DEFAULT;
+}
+
void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c1b8f7980f69..f99809af257d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -16,12 +16,16 @@
struct drm_i915_private;
struct intel_encoder;
struct intel_crtc_state;
+enum icl_port_dpll_id;
enum phy;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
+enum icl_port_dpll_id
+intel_mtl_port_pll_type(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8f0f858cde31..55f36d9d509c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4784,6 +4784,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
if (DISPLAY_VER(dev_priv) >= 14) {
encoder->enable_clock = intel_mtl_pll_enable;
encoder->disable_clock = intel_mtl_pll_disable;
+ encoder->port_pll_type = intel_mtl_port_pll_type;
encoder->get_config = mtl_ddi_get_config;
} else if (IS_DG2(dev_priv)) {
encoder->enable_clock = intel_mpllb_enable;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1c264c17b6e4..e70bdf0e06f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1757,7 +1757,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
if (IS_DG2(dev_priv))
/* DG2's "TC1" output uses a SNPS PHY */
return false;
- else if (IS_ALDERLAKE_P(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3b60995e9dfb..951b12ac51dc 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display.h"
@@ -59,6 +60,7 @@ static enum intel_display_power_domain
tc_phy_cold_off_domain(struct intel_tc_port *);
static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc);
static bool tc_phy_is_ready(struct intel_tc_port *tc);
+static bool tc_phy_wait_for_ready(struct intel_tc_port *tc);
static enum tc_port_mode tc_phy_get_current_mode(struct intel_tc_port *tc);
static const char *tc_port_mode_name(enum tc_port_mode mode)
@@ -141,15 +143,23 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
*
* POWER_DOMAIN_TC_COLD_OFF:
* -------------------------
- * TGL/legacy, DP-alt modes:
+ * ICL/DP-alt, TBT mode:
+ * - TCSS/TBT: block TC-cold power state for using the (direct or
+ * TBT DP-IN) AUX and main lanes.
+ *
+ * TGL/all modes:
* - TCSS/IOM,FIA access for PHY ready, owned and HPD live state
- * - TCSS/PHY: block TC-cold power state for using the PHY AUX and
- * main lanes.
+ * - TCSS/PHY: block TC-cold power state for using the (direct or
+ * TBT DP-IN) AUX and main lanes.
*
- * ICL, TGL, ADLP/TBT mode:
- * - TCSS/IOM,FIA access for HPD live state
+ * ADLP/TBT mode:
* - TCSS/TBT: block TC-cold power state for using the (TBT DP-IN)
* AUX and main lanes.
+ *
+ * XELPDP+/all modes:
+ * - TCSS/IOM,FIA access for PHY ready, owned state
+ * - TCSS/PHY: block TC-cold power state for using the (direct or
+ * TBT DP-IN) AUX and main lanes.
*/
bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
{
@@ -872,6 +882,172 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
.init = adlp_tc_phy_init,
};
+/*
+ * XELPDP TC PHY handlers
+ * ----------------------
+ */
+static bool
+xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ enum port port = tc->dig_port->base.port;
+
+ assert_tc_cold_blocked(tc);
+
+ return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
+}
+
+static bool
+xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+
+ if (wait_for(xelpdp_tc_phy_tcss_power_is_enabled(tc) == enabled, 5)) {
+ drm_dbg_kms(&i915->drm,
+ "Port %s: timeout waiting for TCSS power to get %s\n",
+ enabled ? "enabled" : "disabled",
+ tc->port_name);
+ return false;
+ }
+
+ return true;
+}
+
+static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ enum port port = tc->dig_port->base.port;
+ u32 val;
+
+ assert_tc_cold_blocked(tc);
+
+ val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ if (enable)
+ val |= XELPDP_TCSS_POWER_REQUEST;
+ else
+ val &= ~XELPDP_TCSS_POWER_REQUEST;
+ intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+}
+
+static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+
+ __xelpdp_tc_phy_enable_tcss_power(tc, enable);
+
+ if ((!tc_phy_wait_for_ready(tc) ||
+ !xelpdp_tc_phy_wait_for_tcss_power(tc, enable)) &&
+ !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
+ if (enable) {
+ __xelpdp_tc_phy_enable_tcss_power(tc, false);
+ xelpdp_tc_phy_wait_for_tcss_power(tc, false);
+ }
+
+ return false;
+ }
+
+ return true;
+}
+
+static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ enum port port = tc->dig_port->base.port;
+ u32 val;
+
+ assert_tc_cold_blocked(tc);
+
+ val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ if (take)
+ val |= XELPDP_TC_PHY_OWNERSHIP;
+ else
+ val &= ~XELPDP_TC_PHY_OWNERSHIP;
+ intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+}
+
+static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ enum port port = tc->dig_port->base.port;
+
+ assert_tc_cold_blocked(tc);
+
+ return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
+}
+
+static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ intel_wakeref_t tc_cold_wref;
+ enum intel_display_power_domain domain;
+
+ tc_cold_wref = __tc_cold_block(tc, &domain);
+
+ tc->mode = tc_phy_get_current_mode(tc);
+ if (tc->mode != TC_PORT_DISCONNECTED)
+ tc->lock_wakeref = tc_cold_block(tc);
+
+ drm_WARN_ON(&i915->drm,
+ (tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) &&
+ !xelpdp_tc_phy_tcss_power_is_enabled(tc));
+
+ __tc_cold_unblock(tc, domain, tc_cold_wref);
+}
+
+static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
+{
+ tc->lock_wakeref = tc_cold_block(tc);
+
+ if (tc->mode == TC_PORT_TBT_ALT)
+ return true;
+
+ if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
+ goto out_unblock_tccold;
+
+ xelpdp_tc_phy_take_ownership(tc, true);
+
+ if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
+ goto out_release_phy;
+
+ return true;
+
+out_release_phy:
+ xelpdp_tc_phy_take_ownership(tc, false);
+ xelpdp_tc_phy_wait_for_tcss_power(tc, false);
+
+out_unblock_tccold:
+ tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
+
+ return false;
+}
+
+static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
+{
+ switch (tc->mode) {
+ case TC_PORT_LEGACY:
+ case TC_PORT_DP_ALT:
+ xelpdp_tc_phy_take_ownership(tc, false);
+ xelpdp_tc_phy_enable_tcss_power(tc, false);
+ fallthrough;
+ case TC_PORT_TBT_ALT:
+ tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
+ break;
+ default:
+ MISSING_CASE(tc->mode);
+ }
+}
+
+static const struct intel_tc_phy_ops xelpdp_tc_phy_ops = {
+ .cold_off_domain = tgl_tc_phy_cold_off_domain,
+ .hpd_live_status = adlp_tc_phy_hpd_live_status,
+ .is_ready = adlp_tc_phy_is_ready,
+ .is_owned = xelpdp_tc_phy_is_owned,
+ .get_hw_state = xelpdp_tc_phy_get_hw_state,
+ .connect = xelpdp_tc_phy_connect,
+ .disconnect = xelpdp_tc_phy_disconnect,
+ .init = adlp_tc_phy_init,
+};
+
/*
* Generic TC PHY handlers
* -----------------------
@@ -945,13 +1121,18 @@ static bool tc_phy_is_connected(struct intel_tc_port *tc,
return is_connected;
}
-static void tc_phy_wait_for_ready(struct intel_tc_port *tc)
+static bool tc_phy_wait_for_ready(struct intel_tc_port *tc)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
- if (wait_for(tc_phy_is_ready(tc), 100))
+ if (wait_for(tc_phy_is_ready(tc), 500)) {
drm_err(&i915->drm, "Port %s: timeout waiting for PHY ready\n",
tc->port_name);
+
+ return false;
+ }
+
+ return true;
}
static enum tc_port_mode
@@ -1442,7 +1623,9 @@ int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
dig_port->tc = tc;
tc->dig_port = dig_port;
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(i915) >= 14)
+ tc->phy_ops = &xelpdp_tc_phy_ops;
+ else if (DISPLAY_VER(i915) >= 13)
tc->phy_ops = &adlp_tc_phy_ops;
else if (DISPLAY_VER(i915) >= 12)
tc->phy_ops = &tgl_tc_phy_ops;
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 10/13] drm/i915/mtl: Power up TCSS
2023-04-20 12:40 ` [Intel-gfx] [PATCH 10/13] drm/i915/mtl: Power up TCSS Mika Kahola
@ 2023-04-27 16:09 ` Matt Atwood
0 siblings, 0 replies; 47+ messages in thread
From: Matt Atwood @ 2023-04-27 16:09 UTC (permalink / raw)
To: Mika Kahola, Imre.deak, intel-gfx; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:47PM +0300, Mika Kahola wrote:
> Add register writes to enable powering up Type-C subsystem i.e. TCSS.
> For MeteorLake we need to request TCSS to power up and check the TCSS
> power state after 500 us.
>
> In addition, for PICA we need to set/clear the Type-C PHY ownnership
> bit when Type-C device is connected/disconnected.
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tc.c | 199 ++++++++++++++++++-
> 5 files changed, 216 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dc0555505e61..97d80adb921f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2884,6 +2884,25 @@ void intel_mtl_pll_disable(struct intel_encoder *encoder)
> intel_cx0pll_disable(encoder);
> }
>
> +enum icl_port_dpll_id
> +intel_mtl_port_pll_type(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + /*
> + * TODO: Determine the PLL type from the SW state, once MTL PLL
> + * handling is done via the standard shared DPLL framework.
> + */
> + u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> + u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
> +
> + if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
> + clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
> + return ICL_PORT_DPLL_MG_PHY;
> + else
> + return ICL_PORT_DPLL_DEFAULT;
> +}
> +
> void intel_c10pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c1b8f7980f69..f99809af257d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -16,12 +16,16 @@
> struct drm_i915_private;
> struct intel_encoder;
> struct intel_crtc_state;
> +enum icl_port_dpll_id;
> enum phy;
>
> bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
> void intel_mtl_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_mtl_pll_disable(struct intel_encoder *encoder);
> +enum icl_port_dpll_id
> +intel_mtl_port_pll_type(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
> int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
> void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8f0f858cde31..55f36d9d509c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4784,6 +4784,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> if (DISPLAY_VER(dev_priv) >= 14) {
> encoder->enable_clock = intel_mtl_pll_enable;
> encoder->disable_clock = intel_mtl_pll_disable;
> + encoder->port_pll_type = intel_mtl_port_pll_type;
> encoder->get_config = mtl_ddi_get_config;
> } else if (IS_DG2(dev_priv)) {
> encoder->enable_clock = intel_mpllb_enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1c264c17b6e4..e70bdf0e06f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1757,7 +1757,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> if (IS_DG2(dev_priv))
> /* DG2's "TC1" output uses a SNPS PHY */
> return false;
> - else if (IS_ALDERLAKE_P(dev_priv))
> + else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
> return phy >= PHY_F && phy <= PHY_I;
> else if (IS_TIGERLAKE(dev_priv))
> return phy >= PHY_D && phy <= PHY_I;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 3b60995e9dfb..951b12ac51dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display.h"
> @@ -59,6 +60,7 @@ static enum intel_display_power_domain
> tc_phy_cold_off_domain(struct intel_tc_port *);
> static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc);
> static bool tc_phy_is_ready(struct intel_tc_port *tc);
> +static bool tc_phy_wait_for_ready(struct intel_tc_port *tc);
> static enum tc_port_mode tc_phy_get_current_mode(struct intel_tc_port *tc);
>
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> @@ -141,15 +143,23 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
> *
> * POWER_DOMAIN_TC_COLD_OFF:
> * -------------------------
> - * TGL/legacy, DP-alt modes:
> + * ICL/DP-alt, TBT mode:
> + * - TCSS/TBT: block TC-cold power state for using the (direct or
> + * TBT DP-IN) AUX and main lanes.
> + *
> + * TGL/all modes:
> * - TCSS/IOM,FIA access for PHY ready, owned and HPD live state
> - * - TCSS/PHY: block TC-cold power state for using the PHY AUX and
> - * main lanes.
> + * - TCSS/PHY: block TC-cold power state for using the (direct or
> + * TBT DP-IN) AUX and main lanes.
> *
> - * ICL, TGL, ADLP/TBT mode:
> - * - TCSS/IOM,FIA access for HPD live state
> + * ADLP/TBT mode:
> * - TCSS/TBT: block TC-cold power state for using the (TBT DP-IN)
> * AUX and main lanes.
> + *
> + * XELPDP+/all modes:
> + * - TCSS/IOM,FIA access for PHY ready, owned state
> + * - TCSS/PHY: block TC-cold power state for using the (direct or
> + * TBT DP-IN) AUX and main lanes.
> */
> bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
> {
> @@ -872,6 +882,172 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
> .init = adlp_tc_phy_init,
> };
>
> +/*
> + * XELPDP TC PHY handlers
> + * ----------------------
> + */
> +static bool
> +xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum port port = tc->dig_port->base.port;
> +
> + assert_tc_cold_blocked(tc);
> +
> + return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
> +}
> +
> +static bool
> +xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> +
> + if (wait_for(xelpdp_tc_phy_tcss_power_is_enabled(tc) == enabled, 5)) {
> + drm_dbg_kms(&i915->drm,
> + "Port %s: timeout waiting for TCSS power to get %s\n",
> + enabled ? "enabled" : "disabled",
> + tc->port_name);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum port port = tc->dig_port->base.port;
> + u32 val;
> +
> + assert_tc_cold_blocked(tc);
> +
> + val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> + if (enable)
> + val |= XELPDP_TCSS_POWER_REQUEST;
> + else
> + val &= ~XELPDP_TCSS_POWER_REQUEST;
> + intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +}
> +
> +static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> +
> + __xelpdp_tc_phy_enable_tcss_power(tc, enable);
> +
> + if ((!tc_phy_wait_for_ready(tc) ||
> + !xelpdp_tc_phy_wait_for_tcss_power(tc, enable)) &&
> + !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
> + if (enable) {
> + __xelpdp_tc_phy_enable_tcss_power(tc, false);
> + xelpdp_tc_phy_wait_for_tcss_power(tc, false);
> + }
> +
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum port port = tc->dig_port->base.port;
> + u32 val;
> +
> + assert_tc_cold_blocked(tc);
> +
> + val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> + if (take)
> + val |= XELPDP_TC_PHY_OWNERSHIP;
> + else
> + val &= ~XELPDP_TC_PHY_OWNERSHIP;
> + intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +}
> +
> +static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum port port = tc->dig_port->base.port;
> +
> + assert_tc_cold_blocked(tc);
> +
> + return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
> +}
> +
> +static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + intel_wakeref_t tc_cold_wref;
> + enum intel_display_power_domain domain;
> +
> + tc_cold_wref = __tc_cold_block(tc, &domain);
> +
> + tc->mode = tc_phy_get_current_mode(tc);
> + if (tc->mode != TC_PORT_DISCONNECTED)
> + tc->lock_wakeref = tc_cold_block(tc);
> +
> + drm_WARN_ON(&i915->drm,
> + (tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) &&
> + !xelpdp_tc_phy_tcss_power_is_enabled(tc));
> +
> + __tc_cold_unblock(tc, domain, tc_cold_wref);
> +}
> +
> +static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
> +{
> + tc->lock_wakeref = tc_cold_block(tc);
> +
> + if (tc->mode == TC_PORT_TBT_ALT)
> + return true;
> +
> + if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
> + goto out_unblock_tccold;
> +
> + xelpdp_tc_phy_take_ownership(tc, true);
> +
> + if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
> + goto out_release_phy;
> +
> + return true;
> +
> +out_release_phy:
> + xelpdp_tc_phy_take_ownership(tc, false);
> + xelpdp_tc_phy_wait_for_tcss_power(tc, false);
> +
> +out_unblock_tccold:
> + tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
> +
> + return false;
> +}
> +
> +static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
> +{
> + switch (tc->mode) {
> + case TC_PORT_LEGACY:
> + case TC_PORT_DP_ALT:
> + xelpdp_tc_phy_take_ownership(tc, false);
> + xelpdp_tc_phy_enable_tcss_power(tc, false);
> + fallthrough;
> + case TC_PORT_TBT_ALT:
> + tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
> + break;
> + default:
> + MISSING_CASE(tc->mode);
> + }
> +}
> +
> +static const struct intel_tc_phy_ops xelpdp_tc_phy_ops = {
> + .cold_off_domain = tgl_tc_phy_cold_off_domain,
> + .hpd_live_status = adlp_tc_phy_hpd_live_status,
> + .is_ready = adlp_tc_phy_is_ready,
> + .is_owned = xelpdp_tc_phy_is_owned,
> + .get_hw_state = xelpdp_tc_phy_get_hw_state,
> + .connect = xelpdp_tc_phy_connect,
> + .disconnect = xelpdp_tc_phy_disconnect,
> + .init = adlp_tc_phy_init,
> +};
> +
> /*
> * Generic TC PHY handlers
> * -----------------------
> @@ -945,13 +1121,18 @@ static bool tc_phy_is_connected(struct intel_tc_port *tc,
> return is_connected;
> }
>
> -static void tc_phy_wait_for_ready(struct intel_tc_port *tc)
> +static bool tc_phy_wait_for_ready(struct intel_tc_port *tc)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
>
> - if (wait_for(tc_phy_is_ready(tc), 100))
> + if (wait_for(tc_phy_is_ready(tc), 500)) {
> drm_err(&i915->drm, "Port %s: timeout waiting for PHY ready\n",
> tc->port_name);
> +
> + return false;
> + }
> +
> + return true;
> }
>
> static enum tc_port_mode
> @@ -1442,7 +1623,9 @@ int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
> dig_port->tc = tc;
> tc->dig_port = dig_port;
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(i915) >= 14)
> + tc->phy_ops = &xelpdp_tc_phy_ops;
> + else if (DISPLAY_VER(i915) >= 13)
> tc->phy_ops = &adlp_tc_phy_ops;
> else if (DISPLAY_VER(i915) >= 12)
> tc->phy_ops = &tgl_tc_phy_ops;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 11/13] drm/i915/mtl: TypeC HPD live status query
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (9 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 10/13] drm/i915/mtl: Power up TCSS Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-27 16:13 ` Matt Atwood
2023-04-20 12:40 ` [Intel-gfx] [PATCH 12/13] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
` (5 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
From: Imre Deak <imre.deak@intel.com>
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 30 ++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 951b12ac51dc..b192265a3d78 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -886,6 +886,34 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
* XELPDP TC PHY handlers
* ----------------------
*/
+static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc)
+{
+ struct drm_i915_private *i915 = tc_to_i915(tc);
+ struct intel_digital_port *dig_port = tc->dig_port;
+ enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
+ u32 pica_isr_bits = i915->display.hotplug.hpd[hpd_pin];
+ u32 pch_isr_bit = i915->display.hotplug.pch_hpd[hpd_pin];
+ intel_wakeref_t wakeref;
+ u32 pica_isr;
+ u32 pch_isr;
+ u32 mask = 0;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
+ pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR);
+ pch_isr = intel_de_read(i915, SDEISR);
+ }
+
+ if (pica_isr & (pica_isr_bits & XELPDP_DP_ALT_HOTPLUG_MASK))
+ mask |= BIT(TC_PORT_DP_ALT);
+ if (pica_isr & (pica_isr_bits & XELPDP_TBT_HOTPLUG_MASK))
+ mask |= BIT(TC_PORT_TBT_ALT);
+
+ if (tc->legacy_port && (pch_isr & pch_isr_bit))
+ mask |= BIT(TC_PORT_LEGACY);
+
+ return mask;
+}
+
static bool
xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
{
@@ -1039,7 +1067,7 @@ static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
static const struct intel_tc_phy_ops xelpdp_tc_phy_ops = {
.cold_off_domain = tgl_tc_phy_cold_off_domain,
- .hpd_live_status = adlp_tc_phy_hpd_live_status,
+ .hpd_live_status = xelpdp_tc_phy_hpd_live_status,
.is_ready = adlp_tc_phy_is_ready,
.is_owned = xelpdp_tc_phy_is_owned,
.get_hw_state = xelpdp_tc_phy_get_hw_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 11/13] drm/i915/mtl: TypeC HPD live status query
2023-04-20 12:40 ` [Intel-gfx] [PATCH 11/13] drm/i915/mtl: TypeC HPD live status query Mika Kahola
@ 2023-04-27 16:13 ` Matt Atwood
0 siblings, 0 replies; 47+ messages in thread
From: Matt Atwood @ 2023-04-27 16:13 UTC (permalink / raw)
To: Mika Kahola, intel-gfx; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:48PM +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> The HPD live status for MTL has to be read from different set of
> registers. MTL deserves a new function for this purpose
> and cannot reuse the existing HPD live status detection
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 30 ++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 951b12ac51dc..b192265a3d78 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -886,6 +886,34 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
> * XELPDP TC PHY handlers
> * ----------------------
> */
> +static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc)
> +{
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + struct intel_digital_port *dig_port = tc->dig_port;
> + enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
> + u32 pica_isr_bits = i915->display.hotplug.hpd[hpd_pin];
> + u32 pch_isr_bit = i915->display.hotplug.pch_hpd[hpd_pin];
> + intel_wakeref_t wakeref;
> + u32 pica_isr;
> + u32 pch_isr;
> + u32 mask = 0;
> +
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
> + pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR);
> + pch_isr = intel_de_read(i915, SDEISR);
> + }
> +
> + if (pica_isr & (pica_isr_bits & XELPDP_DP_ALT_HOTPLUG_MASK))
> + mask |= BIT(TC_PORT_DP_ALT);
> + if (pica_isr & (pica_isr_bits & XELPDP_TBT_HOTPLUG_MASK))
> + mask |= BIT(TC_PORT_TBT_ALT);
> +
> + if (tc->legacy_port && (pch_isr & pch_isr_bit))
> + mask |= BIT(TC_PORT_LEGACY);
> +
> + return mask;
> +}
> +
> static bool
> xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
> {
> @@ -1039,7 +1067,7 @@ static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
>
> static const struct intel_tc_phy_ops xelpdp_tc_phy_ops = {
> .cold_off_domain = tgl_tc_phy_cold_off_domain,
> - .hpd_live_status = adlp_tc_phy_hpd_live_status,
> + .hpd_live_status = xelpdp_tc_phy_hpd_live_status,
> .is_ready = adlp_tc_phy_is_ready,
> .is_owned = xelpdp_tc_phy_is_owned,
> .get_hw_state = xelpdp_tc_phy_get_hw_state,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 12/13] drm/i915/mtl: Pin assignment for TypeC
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (10 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 11/13] drm/i915/mtl: TypeC HPD live status query Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-27 16:17 ` Matt Atwood
2023-04-20 12:40 ` [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports Mika Kahola
` (4 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index b192265a3d78..4fca711a58bc 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -16,6 +16,10 @@
#include "intel_mg_phy_regs.h"
#include "intel_tc.h"
+#define DP_PIN_ASSIGNMENT_C 0x3
+#define DP_PIN_ASSIGNMENT_D 0x4
+#define DP_PIN_ASSIGNMENT_E 0x5
+
enum tc_port_mode {
TC_PORT_DISCONNECTED,
TC_PORT_TBT_ALT,
@@ -281,6 +285,27 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
}
+static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ intel_wakeref_t wakeref;
+ u32 pin_mask;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
+
+ switch (pin_mask) {
+ default:
+ MISSING_CASE(pin_mask);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -294,6 +319,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
assert_tc_cold_blocked(tc);
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_tc_port_get_pin_assignment_mask(dig_port);
+
lane_mask = 0;
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 12/13] drm/i915/mtl: Pin assignment for TypeC
2023-04-20 12:40 ` [Intel-gfx] [PATCH 12/13] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
@ 2023-04-27 16:17 ` Matt Atwood
0 siblings, 0 replies; 47+ messages in thread
From: Matt Atwood @ 2023-04-27 16:17 UTC (permalink / raw)
To: Mika Kahola, intel-gfx; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:40:49PM +0300, Mika Kahola wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index b192265a3d78..4fca711a58bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -16,6 +16,10 @@
> #include "intel_mg_phy_regs.h"
> #include "intel_tc.h"
>
> +#define DP_PIN_ASSIGNMENT_C 0x3
> +#define DP_PIN_ASSIGNMENT_D 0x4
> +#define DP_PIN_ASSIGNMENT_E 0x5
> +
> enum tc_port_mode {
> TC_PORT_DISCONNECTED,
> TC_PORT_TBT_ALT,
> @@ -281,6 +285,27 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> }
>
> +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + intel_wakeref_t wakeref;
> + u32 pin_mask;
> +
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
> +
> + switch (pin_mask) {
> + default:
> + MISSING_CASE(pin_mask);
> + fallthrough;
> + case DP_PIN_ASSIGNMENT_D:
> + return 2;
> + case DP_PIN_ASSIGNMENT_C:
> + case DP_PIN_ASSIGNMENT_E:
> + return 4;
> + }
> +}
> +
> int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -294,6 +319,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>
> assert_tc_cold_blocked(tc);
>
> + if (DISPLAY_VER(i915) >= 14)
> + return mtl_tc_port_get_pin_assignment_mask(dig_port);
> +
> lane_mask = 0;
> with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> lane_mask = intel_tc_port_get_lane_mask(dig_port);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (11 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 12/13] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
@ 2023-04-20 12:40 ` Mika Kahola
2023-04-27 15:49 ` Clint Taylor
2023-04-20 15:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add support for C20 phy Patchwork
` (3 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Mika Kahola @ 2023-04-20 12:40 UTC (permalink / raw)
To: intel-gfx
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e70bdf0e06f3..dc777c3b1b1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7587,9 +7587,12 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_METEORLAKE(dev_priv)) {
- /* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
} else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports
2023-04-20 12:40 ` [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports Mika Kahola
@ 2023-04-27 15:49 ` Clint Taylor
0 siblings, 0 replies; 47+ messages in thread
From: Clint Taylor @ 2023-04-27 15:49 UTC (permalink / raw)
To: intel-gfx
On 4/20/23 05:40, Mika Kahola wrote:
> Finally, we can enable TC ports for Meteorlake.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e70bdf0e06f3..dc777c3b1b1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7587,9 +7587,12 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> return;
>
> if (IS_METEORLAKE(dev_priv)) {
> - /* TODO: initialize TC ports as well */
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_TC1);
> + intel_ddi_init(dev_priv, PORT_TC2);
> + intel_ddi_init(dev_priv, PORT_TC3);
> + intel_ddi_init(dev_priv, PORT_TC4);
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
-Clint
> } else if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add support for C20 phy
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (12 preceding siblings ...)
2023-04-20 12:40 ` [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports Mika Kahola
@ 2023-04-20 15:36 ` Patchwork
2023-04-20 15:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-04-20 15:36 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim checkpatch failed
46e88ddde94d drm/i915/mtl: C20 PLL programming
-:155: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#155: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1539:
+ cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
-:164: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#164: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1548:
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
-:165: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#165: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1549:
+ msleep(4);
-:172: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#172: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1556:
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
-:174: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1558:
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
-:180: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#180: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1564:
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
-:182: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#182: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1566:
+ intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
-:218: CHECK:BRACES: Unbalanced braces around else statement
#218: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1602:
+ } else
-:226: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#226: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1610:
+ BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
-:229: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1613:
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
total: 0 errors, 9 warnings, 1 checks, 460 lines checked
d82ad92a3433 drm/i915/mtl: C20 HW readout
-:617: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#617: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1962:
+int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
-:643: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#643: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1990:
+ cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
-:658: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#658: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2005:
+ pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:661: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#661: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2008:
+ pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:665: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#665: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2012:
+ val = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_MPLLA_CNTX_CFG(6));
-:672: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#672: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2019:
+ pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:673: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#673: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2020:
+ PHY_C20_B_MPLLA_CNTX_CFG(i));
-:675: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#675: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2022:
+ pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:676: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#676: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2023:
+ PHY_C20_A_MPLLA_CNTX_CFG(i));
-:682: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#682: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2029:
+ pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:683: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#683: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2030:
+ PHY_C20_B_MPLLB_CNTX_CFG(i));
-:685: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#685: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2032:
+ pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,
-:686: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#686: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2033:
+ PHY_C20_A_MPLLB_CNTX_CFG(i));
total: 0 errors, 12 warnings, 1 checks, 726 lines checked
ce6b7fb67873 drm/i915/mtl: Dump C20 pll hw state
5a2d3ba050ea drm/i915/mtl: C20 port clock calculation
-:114: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3859:
+ crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
-:118: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3863:
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
-:135: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#135: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1018:
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
total: 0 errors, 3 warnings, 0 checks, 103 lines checked
61bee4b75b89 drm/i915/mtl: Add voltage swing sequence for C20
-:105: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1679:
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))
total: 0 errors, 1 warnings, 0 checks, 86 lines checked
9cd1246607e2 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
4f7e469f9d1f drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
5265ce50e00d drm/i915/mtl: Readout Thunderbolt HW state
5e90edc92f1b drm/i915/mtl: Define mask for DDI AUX interrupts
b9cf0eac8d47 drm/i915/mtl: Power up TCSS
8e2329e034ed drm/i915/mtl: TypeC HPD live status query
c45407f3bc4c drm/i915/mtl: Pin assignment for TypeC
1940631d8e23 drm/i915/mtl: Enable TC ports
^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add support for C20 phy
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (13 preceding siblings ...)
2023-04-20 15:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add support for C20 phy Patchwork
@ 2023-04-20 15:36 ` Patchwork
2023-04-20 15:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-20 21:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-04-20 15:36 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch
^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add support for C20 phy
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (14 preceding siblings ...)
2023-04-20 15:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-04-20 15:53 ` Patchwork
2023-04-20 21:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-04-20 15:53 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8375 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116755v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/index.html
Participating hosts (37 -> 36)
------------------------------
Additional (1): fi-kbl-soraka
Missing (2): bat-kbl-2 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116755v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [ABORT][1] ([i915#8369]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- {bat-mtlp-8}: [DMESG-FAIL][3] ([i915#8370]) -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-mtlp-8/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-mtlp-8/igt@i915_selftest@live@gt_pm.html
Known issues
------------
Here are the changes found in Patchwork_116755v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][5] -> [ABORT][6] ([i915#8225])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#6687] / [i915#7978])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#5334] / [i915#7872])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_mocs:
- bat-rpls-1: [PASS][12] -> [DMESG-FAIL][13] ([i915#7059])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][14] ([i915#1886])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: NOTRUN -> [ABORT][15] ([i915#7913])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-FAIL][16] ([i915#6367] / [i915#7996])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271]) +16 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-adlp-6: NOTRUN -> [SKIP][18] ([i915#7828])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-adlp-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][19] -> [FAIL][20] ([i915#7932])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@mman:
- bat-rpls-1: [TIMEOUT][21] ([i915#6794]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-rpls-1/igt@i915_selftest@live@mman.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-adlp-6: [INCOMPLETE][23] ([i915#7443]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-adlp-6/igt@i915_suspend@basic-s3-without-i915.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/bat-adlp-6/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8225]: https://gitlab.freedesktop.org/drm/intel/issues/8225
[i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369
[i915#8370]: https://gitlab.freedesktop.org/drm/intel/issues/8370
Build changes
-------------
* Linux: CI_DRM_13034 -> Patchwork_116755v1
CI-20190529: 20190529
CI_DRM_13034: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7263: a6bd8f415c4ec41b5a014c7db47e46c81ffd0074 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116755v1: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e3c137f819e4 drm/i915/mtl: Enable TC ports
2d9b163c7db0 drm/i915/mtl: Pin assignment for TypeC
8e8b5702b7e6 drm/i915/mtl: TypeC HPD live status query
a717529d75f7 drm/i915/mtl: Power up TCSS
56380268e4b0 drm/i915/mtl: Define mask for DDI AUX interrupts
e333e09d19da drm/i915/mtl: Readout Thunderbolt HW state
237cb96989c1 drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
b36c2eb41f35 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
3fadea602c5f drm/i915/mtl: Add voltage swing sequence for C20
7a65fa8626f7 drm/i915/mtl: C20 port clock calculation
5c7af5d2fa23 drm/i915/mtl: Dump C20 pll hw state
8f894bb900b0 drm/i915/mtl: C20 HW readout
cd4d5a1c9b50 drm/i915/mtl: C20 PLL programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/index.html
[-- Attachment #2: Type: text/html, Size: 9596 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Add support for C20 phy
2023-04-20 12:40 [Intel-gfx] [PATCH 00/13] drm/i915/mtl: Add support for C20 phy Mika Kahola
` (15 preceding siblings ...)
2023-04-20 15:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-04-20 21:38 ` Patchwork
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-04-20 21:38 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13920 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116755v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116755v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116755v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116755v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- shard-apl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl2/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-apl1/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- {shard-dg1}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-dg1-16/igt@kms_flip@2x-flip-vs-fences-interruptible.html
Known issues
------------
Here are the changes found in Patchwork_116755v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@smoketest:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#5099])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl2/igt@gem_ctx_persistence@smoketest.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-apl1/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-apl: [PASS][8] -> [TIMEOUT][9] ([i915#3778])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl1/igt@gem_exec_endless@dispatch@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-apl2/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][10] -> [ABORT][11] ([i915#5566])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-glk9/igt@gen9_exec_parse@allowed-single.html
* igt@kms_color@ctm-0-25@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-snb4/igt@kms_color@ctm-0-25@pipe-b-vga-1.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#72])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@perf@oa-exponents@0-rcs0:
- shard-glk: [PASS][15] -> [ABORT][16] ([i915#5213])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-glk6/igt@perf@oa-exponents@0-rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-glk1/igt@perf@oa-exponents@0-rcs0.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-rkl}: [ABORT][17] ([i915#8211]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-3/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][19] ([i915#6268]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_endless@dispatch@rcs0:
- {shard-tglu}: [TIMEOUT][21] ([i915#3778]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-tglu-8/igt@gem_exec_endless@dispatch@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-tglu-5/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}: [FAIL][23] ([i915#2842]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][25] ([i915#2842]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][27] ([i915#1937]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-dg1-18/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-dg1-14/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][29] ([i915#1397]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-dg1}: [SKIP][31] ([i915#1397]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][33] ([i915#8011]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-3/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [FAIL][35] ([i915#79]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-apl3/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][37] ([i915#4349]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-2/igt@perf_pmu@idle@rcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/shard-rkl-3/igt@perf_pmu@idle@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* Linux: CI_DRM_13034 -> Patchwork_116755v1
CI-20190529: 20190529
CI_DRM_13034: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7263: a6bd8f415c4ec41b5a014c7db47e46c81ffd0074 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116755v1: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v1/index.html
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