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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
Date: Tue, 5 Sep 2023 08:25:17 +0300	[thread overview]
Message-ID: <ZPa7vdxwCnD1shU8@intel.com> (raw)
In-Reply-To: <ZPW6tkb73MXs7NuP@ideak-desk.fi.intel.com>

On Mon, Sep 04, 2023 at 02:08:38PM +0300, Imre Deak wrote:
> On Mon, Sep 04, 2023 at 06:48:25AM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> > > In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> > > range, while in DSC mode it can be set in 1/16 bpp steps to any value
> > > up to the maximum pipe bpp. Update the limits accordingly in both modes
> > > to prepare for a follow-up patch which may need to reduce the max link
> > > bpp value and starts to check the link bpp limits in DSC mode as well.
> > > 
> > > While at it add more detail to the link limit debug print and print it
> > > also for DSC mode.
> > > 
> > > v2:
> > > - Add to_bpp_frac_dec() instead of open coding it. (Jani)
> > > 
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_types.h    |  5 ++
> > >  drivers/gpu/drm/i915/display/intel_dp.c       | 89 +++++++++++++++----
> > >  drivers/gpu/drm/i915/display/intel_dp.h       |  6 ++
> > >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 23 +++--
> > >  4 files changed, 101 insertions(+), 22 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5875eff5012ce..a0a404967b5d2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
> > >  	return bpp_x16 >> 4;
> > >  }
> > >  
> > > +static inline int to_bpp_frac_dec(int bpp_x16)
> > > +{
> > > +	return (bpp_x16 & 0xf) * 625;
> > > +}
> > 
> > This gives me the impression that this would be somehow
> > generally useful, but I presume we only use it for the printk?
> > So maybe should just have some printk FMT+ARG macros for
> > this stuff?
> 
> Yes, only used by printks. Make sense to define the FMT+ARG helpers at
> one place, can add these here.
> 
> > 
> > > +
> > >  static inline int to_bpp_x16(int bpp)
> > >  {
> > >  	return bpp << 4;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index c580472c06b85..9ce861a7fd418 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2189,16 +2189,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > >  	return 0;
> > >  }
> > >  
> > > -static void
> > > +/**
> > > + * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
> > > + * @intel_dp: intel DP
> > > + * @crtc_state: crtc state
> > > + * @dsc: DSC compression mode
> > > + * @limits: link configuration limits
> > > + *
> > > + * Calculates the output link min, max bpp values in @limits based on the
> > > + * pipe bpp range, @crtc_state and @dsc mode.
> > > + *
> > > + * Returns %true in case of success.
> > > + */
> > > +bool
> > > +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> > > +					const struct intel_crtc_state *crtc_state,
> > > +					bool dsc,
> > > +					struct link_config_limits *limits)
> > > +{
> > > +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > > +	const struct drm_display_mode *adjusted_mode =
> > > +		&crtc_state->hw.adjusted_mode;
> > > +	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > > +	int max_link_bpp_x16;
> > > +
> > > +	max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > > +
> > > +	if (!dsc) {
> > > +		max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> > > +
> > > +		if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
> > > +			return false;
> > 
> > Quite a few to_bpp_x16()'s in there. Seems like it would a bit simpler
> > to just do that once at the end.
> 
> At the moment yes, but in a later patch max_link_bpp_x16 starts out as
> crtc_state->max_link_bpp_x16 limited value (with a non-zero fractional
> part).
> 
> > 
> > > +
> > > +		limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> > > +	} else {
> > > +		limits->link.min_bpp_x16 = 0;
> > 
> > Why is that zero? Don't we now have some helpers to fill
> > this stuff correctly?
> 
> At the moment it's calculated only later in
> intel_edp_dsc_compute_pipe_bpp() /  intel_dp_dsc_compute_pipe_bpp().
> 
> It should be inited already here, but I wanted to do that only as a
> follow-up, since there's been other DSC changes from Ankit still under
> review. Is that ok, adding a TODO: here?

Sure.

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-09-05  5:25 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-24  8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-24  8:04 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-09-04  3:19   ` Ville Syrjälä
2023-09-04 10:25     ` Imre Deak
2023-08-24  8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
2023-09-14  9:33   ` Luca Coelho
2023-09-14  9:55     ` Imre Deak
2023-09-14 10:51       ` Luca Coelho
2023-09-14 11:08         ` Imre Deak
2023-09-14 12:08           ` Luca Coelho
2023-08-24  8:04 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
2023-09-04  3:24   ` Ville Syrjälä
2023-08-24  8:04 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
2023-09-04  3:48   ` Ville Syrjälä
2023-09-04 11:08     ` Imre Deak
2023-09-05  5:25       ` Ville Syrjälä [this message]
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/dp: Limit the output link bpp in " Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes Imre Deak
2023-09-08 19:25   ` Ville Syrjälä
2023-09-08 20:08     ` Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
2023-09-08 19:31   ` Ville Syrjälä
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
2023-09-11 18:59   ` Ville Syrjälä
2023-09-11 20:42     ` Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode() Imre Deak
2023-08-30 21:27   ` Lyude Paul
2023-09-04  2:53   ` Ville Syrjälä
2023-09-04 10:22     ` Imre Deak
2023-09-06 10:45       ` Ville Syrjälä
2023-09-06 11:14         ` Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 10/22] drm/dp_mst: Add a way to calculate PBN values with FEC overhead Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 11/22] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 12/22] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 13/22] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
2023-08-24  9:31   ` Lisovskiy, Stanislav
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-08-24  9:44   ` Lisovskiy, Stanislav
2023-08-24 10:37     ` Imre Deak
2023-09-11 12:29   ` Lisovskiy, Stanislav
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-08-24  8:05 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
2023-09-25  7:46   ` Lisovskiy, Stanislav
2023-08-24  9:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev2) Patchwork
2023-08-24  9:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-24 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-24 17:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-04  7:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev3) Patchwork

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