[PATCH v3 0/6] drm/i915: add display irq hooks

[PATCH v3 0/6] drm/i915: add display irq hooks

[Jani Nikula]

v3 of [1].


[1] https://lore.kernel.org/r/cover.1777933454.git.jani.nikula@intel.com


Jani Nikula (6):
  drm/i915/irq: deduplicate dg1_de_irq_postinstall() and
    gen11_de_irq_postinstall()
  drm/i915/irq: constify pipe stats parameters
  drm/i915/irq: add display irq funcs, start with
    intel_display_irq_reset()
  drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
  drm/i915/irq: add intel_display_irq_ack() to irq funcs
  drm/i915/irq: add intel_display_irq_handler() to irq funcs

 .../gpu/drm/i915/display/intel_display_core.h |   3 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 238 +++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  |  37 +--
 drivers/gpu/drm/i915/i915_irq.c               | 182 +++++---------
 drivers/gpu/drm/xe/display/xe_display.c       |   6 +-
 5 files changed, 277 insertions(+), 189 deletions(-)

-- 
2.47.3

[PATCH v3 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()

[Jani Nikula]

dg1_de_irq_postinstall() and gen11_de_irq_postinstall() are exactly the
same. Remove dg1_de_irq_postinstall() and call
gen11_de_irq_postinstall() instead.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 9 ---------
 drivers/gpu/drm/i915/display/intel_display_irq.h | 1 -
 drivers/gpu/drm/i915/i915_irq.c                  | 2 +-
 3 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b5bfdebc66ca..bf4b5e7b6011 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2449,15 +2449,6 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 }
 
-void dg1_de_irq_postinstall(struct intel_display *display)
-{
-	if (!HAS_DISPLAY(display))
-		return;
-
-	gen8_de_irq_postinstall(display);
-	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
-}
-
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b25d180254d7..e2b1674fae06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -71,7 +71,6 @@ void vlv_display_irq_postinstall(struct intel_display *display);
 void ilk_de_irq_postinstall(struct intel_display *display);
 void gen8_de_irq_postinstall(struct intel_display *display);
 void gen11_de_irq_postinstall(struct intel_display *display);
-void dg1_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d4d8dd0a4174..ef9eadf38a53 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	dg1_de_irq_postinstall(display);
+	gen11_de_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
-- 
2.47.3

Re: [PATCH v3 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:06PM +0300, Jani Nikula wrote:
> dg1_de_irq_postinstall() and gen11_de_irq_postinstall() are exactly the
> same. Remove dg1_de_irq_postinstall() and call
> gen11_de_irq_postinstall() instead.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 9 ---------
>  drivers/gpu/drm/i915/display/intel_display_irq.h | 1 -
>  drivers/gpu/drm/i915/i915_irq.c                  | 2 +-
>  3 files changed, 1 insertion(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index b5bfdebc66ca..bf4b5e7b6011 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -2449,15 +2449,6 @@ void gen11_de_irq_postinstall(struct intel_display *display)
>  	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>  }
>  
> -void dg1_de_irq_postinstall(struct intel_display *display)
> -{
> -	if (!HAS_DISPLAY(display))
> -		return;
> -
> -	gen8_de_irq_postinstall(display);
> -	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> -}
> -
>  struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index b25d180254d7..e2b1674fae06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -71,7 +71,6 @@ void vlv_display_irq_postinstall(struct intel_display *display);
>  void ilk_de_irq_postinstall(struct intel_display *display);
>  void gen8_de_irq_postinstall(struct intel_display *display);
>  void gen11_de_irq_postinstall(struct intel_display *display);
> -void dg1_de_irq_postinstall(struct intel_display *display);
>  
>  u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
>  void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d4d8dd0a4174..ef9eadf38a53 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
>  
> -	dg1_de_irq_postinstall(display);
> +	gen11_de_irq_postinstall(display);
>  
>  	dg1_master_intr_enable(intel_uncore_regs(uncore));
>  	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

[PATCH v3 2/6] drm/i915/irq: constify pipe stats parameters

[Jani Nikula]

The pipe stat irq handling doesn't need to modify the pipe stats
arrays. Make them const.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_irq.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index bf4b5e7b6011..d30b063714b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
 }
 
 void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 }
 
 void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 }
 
 void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     u32 pipe_stats[I915_MAX_PIPES])
+				     const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index e2b1674fae06..d25b9ea4272b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st
 
 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-- 
2.47.3

Re: [PATCH v3 2/6] drm/i915/irq: constify pipe stats parameters

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:07PM +0300, Jani Nikula wrote:
> The pipe stat irq handling doesn't need to modify the pipe stats
> arrays. Make them const.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++---
>  drivers/gpu/drm/i915/display/intel_display_irq.h | 6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index bf4b5e7b6011..d30b063714b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
>  }
>  
>  void i915_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> +			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display,
>  }
>  
>  void i965_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> +			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display,
>  }
>  
>  void valleyview_pipestat_irq_handler(struct intel_display *display,
> -				     u32 pipe_stats[I915_MAX_PIPES])
> +				     const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	enum pipe pipe;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index e2b1674fae06..d25b9ea4272b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st
>  
>  void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
>  
> -void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
> -void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
> -void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
> +void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> +void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> +void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
>  
>  void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
>  void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

[PATCH v3 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()

[Jani Nikula]

Introduce display irq hooks with struct intel_display_irq_funcs, and add
the ->reset hook as the first thing. Call the reset hooks from i915 and
xe core via intel_display_irq_reset().

Relocate the gen8 and gen11 HAS_DISPLAY() check to
intel_display_irq_reset(), as the funcs pointer won't be initialized for
no display.

Note: We're increasingly moving to the territory of not touching display
at all if there's no display or it has been fused off. Which is good,
but care must be taken to not have hardware setup required also for no
display cases in display code. Also note that the line is fuzzy for
older platforms, but there we also don't have fusing.

v2:
- make the structs static const (Sashiko)
- relocate HAS_DISPLAY() (Sashiko)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 61 +++++++++++++++----
 .../gpu/drm/i915/display/intel_display_irq.h  |  6 +-
 drivers/gpu/drm/i915/i915_irq.c               | 16 ++---
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 5 files changed, 63 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 76745ce6a716..3dc5ac75a98b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -475,6 +475,9 @@ struct intel_display {
 	} ips;
 
 	struct {
+		/* internal display irq functions */
+		const struct intel_display_irq_funcs *funcs;
+
 		/* protects the irq masks */
 		spinlock_t lock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d30b063714b0..62a849673454 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1947,7 +1947,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
 	display->irq.vlv_imr_mask = ~0u;
 }
 
-void vlv_display_irq_reset(struct intel_display *display)
+static void vlv_display_irq_reset(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -1955,7 +1955,7 @@ void vlv_display_irq_reset(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void i9xx_display_irq_reset(struct intel_display *display)
+static void i9xx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_HOTPLUG(display)) {
 		i915_hotplug_interrupt_update(display, 0xffffffff, 0);
@@ -2076,7 +2076,7 @@ static void ibx_display_irq_reset(struct intel_display *display)
 		intel_de_write(display, SERR_INT, 0xffffffff);
 }
 
-void ilk_display_irq_reset(struct intel_display *display)
+static void ilk_display_irq_reset(struct intel_display *display)
 {
 	irq_reset(display, DE_IRQ_REGS);
 	display->irq.ilk_de_imr_mask = ~0u;
@@ -2092,13 +2092,10 @@ void ilk_display_irq_reset(struct intel_display *display)
 	ibx_display_irq_reset(display);
 }
 
-void gen8_display_irq_reset(struct intel_display *display)
+static void gen8_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 
-	if (!HAS_DISPLAY(display))
-		return;
-
 	intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
 	intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
 
@@ -2114,15 +2111,12 @@ void gen8_display_irq_reset(struct intel_display *display)
 		ibx_display_irq_reset(display);
 }
 
-void gen11_display_irq_reset(struct intel_display *display)
+static void gen11_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
 
-	if (!HAS_DISPLAY(display))
-		return;
-
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
 
 	if (DISPLAY_VER(display) >= 12) {
@@ -2453,6 +2447,38 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
 
+static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
+	.reset = gen11_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
+	.reset = gen8_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
+	.reset = vlv_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
+	.reset = ilk_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i965_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i915_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+void intel_display_irq_reset(struct intel_display *display)
+{
+	if (!HAS_DISPLAY(display))
+		return;
+
+	display->irq.funcs->reset(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
@@ -2463,6 +2489,19 @@ void intel_display_irq_init(struct intel_display *display)
 
 	INIT_WORK(&display->irq.vblank_notify_work,
 		  intel_display_vblank_notify_work);
+
+	if (DISPLAY_VER(display) >= 11)
+		display->irq.funcs = &gen11_display_irq_funcs;
+	else if (display->platform.cherryview || display->platform.valleyview)
+		display->irq.funcs = &vlv_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 8)
+		display->irq.funcs = &gen8_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 5)
+		display->irq.funcs = &ilk_display_irq_funcs;
+	else if (DISPLAY_VER(display) == 4)
+		display->irq.funcs = &i965_display_irq_funcs;
+	else
+		display->irq.funcs = &i915_display_irq_funcs;
 }
 
 struct intel_display_irq_snapshot {
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index d25b9ea4272b..21b2145656cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,11 +58,7 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
-void i9xx_display_irq_reset(struct intel_display *display);
-void ilk_display_irq_reset(struct intel_display *display);
-void vlv_display_irq_reset(struct intel_display *display);
-void gen8_display_irq_reset(struct intel_display *display);
-void gen11_display_irq_reset(struct intel_display *display);
+void intel_display_irq_reset(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 void i915_display_irq_postinstall(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ef9eadf38a53..c4f56a869910 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -640,7 +640,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	/* The master interrupt enable is in DEIER, reset display irq first */
-	ilk_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen5_gt_irq_reset(to_gt(dev_priv));
 }
 
@@ -653,7 +653,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_reset(to_gt(dev_priv));
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
@@ -664,7 +664,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 	gen8_master_intr_disable(intel_uncore_regs(uncore));
 
 	gen8_gt_irq_reset(to_gt(dev_priv));
-	gen8_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 }
 
@@ -677,7 +677,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
 	gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
 
 	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -695,7 +695,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 	for_each_gt(gt, dev_priv, i)
 		gen11_gt_irq_reset(gt);
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -715,7 +715,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -864,7 +864,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -951,7 +951,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index aa73023b7398..ba3225878c61 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -236,7 +236,7 @@ void xe_display_irq_reset(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 void xe_display_irq_postinstall(struct xe_device *xe)
-- 
2.47.3

Re: [PATCH v3 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:08PM +0300, Jani Nikula wrote:
> Introduce display irq hooks with struct intel_display_irq_funcs, and add
> the ->reset hook as the first thing. Call the reset hooks from i915 and
> xe core via intel_display_irq_reset().
> 
> Relocate the gen8 and gen11 HAS_DISPLAY() check to
> intel_display_irq_reset(), as the funcs pointer won't be initialized for
> no display.
> 
> Note: We're increasingly moving to the territory of not touching display
> at all if there's no display or it has been fused off. Which is good,
> but care must be taken to not have hardware setup required also for no
> display cases in display code. Also note that the line is fuzzy for
> older platforms, but there we also don't have fusing.
> 
> v2:
> - make the structs static const (Sashiko)
> - relocate HAS_DISPLAY() (Sashiko)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  3 +
>  .../gpu/drm/i915/display/intel_display_irq.c  | 61 +++++++++++++++----
>  .../gpu/drm/i915/display/intel_display_irq.h  |  6 +-
>  drivers/gpu/drm/i915/i915_irq.c               | 16 ++---
>  drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
>  5 files changed, 63 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 76745ce6a716..3dc5ac75a98b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -475,6 +475,9 @@ struct intel_display {
>  	} ips;
>  
>  	struct {
> +		/* internal display irq functions */
> +		const struct intel_display_irq_funcs *funcs;
> +
>  		/* protects the irq masks */
>  		spinlock_t lock;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index d30b063714b0..62a849673454 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1947,7 +1947,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
>  	display->irq.vlv_imr_mask = ~0u;
>  }
>  
> -void vlv_display_irq_reset(struct intel_display *display)
> +static void vlv_display_irq_reset(struct intel_display *display)
>  {
>  	spin_lock_irq(&display->irq.lock);
>  	if (display->irq.vlv_display_irqs_enabled)
> @@ -1955,7 +1955,7 @@ void vlv_display_irq_reset(struct intel_display *display)
>  	spin_unlock_irq(&display->irq.lock);
>  }
>  
> -void i9xx_display_irq_reset(struct intel_display *display)
> +static void i9xx_display_irq_reset(struct intel_display *display)
>  {
>  	if (HAS_HOTPLUG(display)) {
>  		i915_hotplug_interrupt_update(display, 0xffffffff, 0);
> @@ -2076,7 +2076,7 @@ static void ibx_display_irq_reset(struct intel_display *display)
>  		intel_de_write(display, SERR_INT, 0xffffffff);
>  }
>  
> -void ilk_display_irq_reset(struct intel_display *display)
> +static void ilk_display_irq_reset(struct intel_display *display)
>  {
>  	irq_reset(display, DE_IRQ_REGS);
>  	display->irq.ilk_de_imr_mask = ~0u;
> @@ -2092,13 +2092,10 @@ void ilk_display_irq_reset(struct intel_display *display)
>  	ibx_display_irq_reset(display);
>  }
>  
> -void gen8_display_irq_reset(struct intel_display *display)
> +static void gen8_display_irq_reset(struct intel_display *display)
>  {
>  	enum pipe pipe;
>  
> -	if (!HAS_DISPLAY(display))
> -		return;
> -
>  	intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
>  	intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
>  
> @@ -2114,15 +2111,12 @@ void gen8_display_irq_reset(struct intel_display *display)
>  		ibx_display_irq_reset(display);
>  }
>  
> -void gen11_display_irq_reset(struct intel_display *display)
> +static void gen11_display_irq_reset(struct intel_display *display)
>  {
>  	enum pipe pipe;
>  	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>  		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
>  
> -	if (!HAS_DISPLAY(display))
> -		return;
> -
>  	intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
>  
>  	if (DISPLAY_VER(display) >= 12) {
> @@ -2453,6 +2447,38 @@ struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
>  };
>  
> +static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
> +	.reset = gen11_display_irq_reset,
> +};
> +
> +static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
> +	.reset = gen8_display_irq_reset,
> +};
> +
> +static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
> +	.reset = vlv_display_irq_reset,
> +};
> +
> +static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
> +	.reset = ilk_display_irq_reset,
> +};
> +
> +static const struct intel_display_irq_funcs i965_display_irq_funcs = {
> +	.reset = i9xx_display_irq_reset,
> +};
> +
> +static const struct intel_display_irq_funcs i915_display_irq_funcs = {
> +	.reset = i9xx_display_irq_reset,
> +};
> +
> +void intel_display_irq_reset(struct intel_display *display)
> +{
> +	if (!HAS_DISPLAY(display))
> +		return;
> +
> +	display->irq.funcs->reset(display);
> +}
> +
>  void intel_display_irq_init(struct intel_display *display)
>  {
>  	spin_lock_init(&display->irq.lock);
> @@ -2463,6 +2489,19 @@ void intel_display_irq_init(struct intel_display *display)
>  
>  	INIT_WORK(&display->irq.vblank_notify_work,
>  		  intel_display_vblank_notify_work);
> +
> +	if (DISPLAY_VER(display) >= 11)
> +		display->irq.funcs = &gen11_display_irq_funcs;
> +	else if (display->platform.cherryview || display->platform.valleyview)
> +		display->irq.funcs = &vlv_display_irq_funcs;
> +	else if (DISPLAY_VER(display) >= 8)
> +		display->irq.funcs = &gen8_display_irq_funcs;
> +	else if (DISPLAY_VER(display) >= 5)
> +		display->irq.funcs = &ilk_display_irq_funcs;
> +	else if (DISPLAY_VER(display) == 4)
> +		display->irq.funcs = &i965_display_irq_funcs;
> +	else
> +		display->irq.funcs = &i915_display_irq_funcs;
>  }
>  
>  struct intel_display_irq_snapshot {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index d25b9ea4272b..21b2145656cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -58,11 +58,7 @@ void gen11_display_irq_handler(struct intel_display *display);
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>  
> -void i9xx_display_irq_reset(struct intel_display *display);
> -void ilk_display_irq_reset(struct intel_display *display);
> -void vlv_display_irq_reset(struct intel_display *display);
> -void gen8_display_irq_reset(struct intel_display *display);
> -void gen11_display_irq_reset(struct intel_display *display);
> +void intel_display_irq_reset(struct intel_display *display);
>  
>  u32 i9xx_display_irq_enable_mask(struct intel_display *display);
>  void i915_display_irq_postinstall(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ef9eadf38a53..c4f56a869910 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -640,7 +640,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
>  	struct intel_display *display = dev_priv->display;
>  
>  	/* The master interrupt enable is in DEIER, reset display irq first */
> -	ilk_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  	gen5_gt_irq_reset(to_gt(dev_priv));
>  }
>  
> @@ -653,7 +653,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
>  
>  	gen5_gt_irq_reset(to_gt(dev_priv));
>  
> -	vlv_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  }
>  
>  static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> @@ -664,7 +664,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>  	gen8_master_intr_disable(intel_uncore_regs(uncore));
>  
>  	gen8_gt_irq_reset(to_gt(dev_priv));
> -	gen8_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
>  }
>  
> @@ -677,7 +677,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
>  	gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
>  
>  	gen11_gt_irq_reset(gt);
> -	gen11_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  
>  	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
>  	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
> @@ -695,7 +695,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
>  	for_each_gt(gt, dev_priv, i)
>  		gen11_gt_irq_reset(gt);
>  
> -	gen11_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  
>  	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
>  	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
> @@ -715,7 +715,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
>  
>  	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
>  
> -	vlv_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  }
>  
>  static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -864,7 +864,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
>  	struct intel_display *display = dev_priv->display;
>  	struct intel_uncore *uncore = &dev_priv->uncore;
>  
> -	i9xx_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  
>  	gen2_error_reset(uncore, GEN2_ERROR_REGS);
>  	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
> @@ -951,7 +951,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
>  	struct intel_display *display = dev_priv->display;
>  	struct intel_uncore *uncore = &dev_priv->uncore;
>  
> -	i9xx_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  
>  	gen2_error_reset(uncore, GEN2_ERROR_REGS);
>  	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index aa73023b7398..ba3225878c61 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -236,7 +236,7 @@ void xe_display_irq_reset(struct xe_device *xe)
>  	if (!xe->info.probe_display)
>  		return;
>  
> -	gen11_display_irq_reset(display);
> +	intel_display_irq_reset(display);
>  }
>  
>  void xe_display_irq_postinstall(struct xe_device *xe)
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

[PATCH v3 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs

[Jani Nikula]

Call the platform specific display irq postinstall hooks via
intel_display_irq_postinstall().

Relocate the gen11 HAS_DISPLAY() check to
intel_display_irq_postinstall(), as the funcs pointer won't be
initialized for no display.

v2:
- relocate HAS_DISPLAY() (Sashiko)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 30 +++++++++++++------
 .../gpu/drm/i915/display/intel_display_irq.h  |  7 +----
 drivers/gpu/drm/i915/i915_irq.c               | 16 +++++-----
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 31 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62a849673454..1c3c8095765d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
 	return enable_mask;
 }
 
-void i915_display_irq_postinstall(struct intel_display *display)
+static void i915_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
-void i965_display_irq_postinstall(struct intel_display *display)
+static void i965_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
 	irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
 }
 
-void vlv_display_irq_postinstall(struct intel_display *display)
+static void vlv_display_irq_postinstall(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -2262,7 +2262,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void ilk_de_irq_postinstall(struct intel_display *display)
+static void ilk_de_irq_postinstall(struct intel_display *display)
 {
 	u32 display_mask, extra_mask;
 
@@ -2306,7 +2306,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
 static void mtp_irq_postinstall(struct intel_display *display);
 static void icp_irq_postinstall(struct intel_display *display);
 
-void gen8_de_irq_postinstall(struct intel_display *display)
+static void gen8_de_irq_postinstall(struct intel_display *display)
 {
 	u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
 		GEN8_PIPE_CDCLK_CRC_DONE;
@@ -2433,11 +2433,8 @@ static void icp_irq_postinstall(struct intel_display *display)
 	irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
 }
 
-void gen11_de_irq_postinstall(struct intel_display *display)
+static void gen11_de_irq_postinstall(struct intel_display *display)
 {
-	if (!HAS_DISPLAY(display))
-		return;
-
 	gen8_de_irq_postinstall(display);
 
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -2445,30 +2442,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
+	void (*postinstall)(struct intel_display *display);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
+	.postinstall = gen11_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
+	.postinstall = gen8_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
+	.postinstall = vlv_display_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
+	.postinstall = ilk_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i965_display_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i915_display_irq_postinstall,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2479,6 +2483,14 @@ void intel_display_irq_reset(struct intel_display *display)
 	display->irq.funcs->reset(display);
 }
 
+void intel_display_irq_postinstall(struct intel_display *display)
+{
+	if (!HAS_DISPLAY(display))
+		return;
+
+	display->irq.funcs->postinstall(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 21b2145656cd..fd9873ce9755 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 void intel_display_irq_reset(struct intel_display *display);
+void intel_display_irq_postinstall(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
-void i915_display_irq_postinstall(struct intel_display *display);
-void i965_display_irq_postinstall(struct intel_display *display);
-void vlv_display_irq_postinstall(struct intel_display *display);
-void ilk_de_irq_postinstall(struct intel_display *display);
-void gen8_de_irq_postinstall(struct intel_display *display);
-void gen11_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c4f56a869910..c21b289b8007 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	ilk_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
@@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
-	gen8_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
 }
@@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
 
 	gen11_gt_irq_postinstall(gt);
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
@@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
@@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i915_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i965_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i965_irq_handler(int irq, void *arg)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index ba3225878c61..62e5d38938eb 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -246,7 +246,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static bool suspend_to_idle(void)
-- 
2.47.3

Re: [PATCH v3 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:09PM +0300, Jani Nikula wrote:
> Call the platform specific display irq postinstall hooks via
> intel_display_irq_postinstall().
> 
> Relocate the gen11 HAS_DISPLAY() check to
> intel_display_irq_postinstall(), as the funcs pointer won't be
> initialized for no display.
> 
> v2:
> - relocate HAS_DISPLAY() (Sashiko)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  | 30 +++++++++++++------
>  .../gpu/drm/i915/display/intel_display_irq.h  |  7 +----
>  drivers/gpu/drm/i915/i915_irq.c               | 16 +++++-----
>  drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
>  4 files changed, 31 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 62a849673454..1c3c8095765d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
>  	return enable_mask;
>  }
>  
> -void i915_display_irq_postinstall(struct intel_display *display)
> +static void i915_display_irq_postinstall(struct intel_display *display)
>  {
>  	/*
>  	 * Interrupt setup is already guaranteed to be single-threaded, this is
> @@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
>  	i915_enable_asle_pipestat(display);
>  }
>  
> -void i965_display_irq_postinstall(struct intel_display *display)
> +static void i965_display_irq_postinstall(struct intel_display *display)
>  {
>  	/*
>  	 * Interrupt setup is already guaranteed to be single-threaded, this is
> @@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
>  	irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
>  }
>  
> -void vlv_display_irq_postinstall(struct intel_display *display)
> +static void vlv_display_irq_postinstall(struct intel_display *display)
>  {
>  	spin_lock_irq(&display->irq.lock);
>  	if (display->irq.vlv_display_irqs_enabled)
> @@ -2262,7 +2262,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
>  	spin_unlock_irq(&display->irq.lock);
>  }
>  
> -void ilk_de_irq_postinstall(struct intel_display *display)
> +static void ilk_de_irq_postinstall(struct intel_display *display)
>  {
>  	u32 display_mask, extra_mask;
>  
> @@ -2306,7 +2306,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
>  static void mtp_irq_postinstall(struct intel_display *display);
>  static void icp_irq_postinstall(struct intel_display *display);
>  
> -void gen8_de_irq_postinstall(struct intel_display *display)
> +static void gen8_de_irq_postinstall(struct intel_display *display)
>  {
>  	u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
>  		GEN8_PIPE_CDCLK_CRC_DONE;
> @@ -2433,11 +2433,8 @@ static void icp_irq_postinstall(struct intel_display *display)
>  	irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
>  }
>  
> -void gen11_de_irq_postinstall(struct intel_display *display)
> +static void gen11_de_irq_postinstall(struct intel_display *display)
>  {
> -	if (!HAS_DISPLAY(display))
> -		return;
> -
>  	gen8_de_irq_postinstall(display);
>  
>  	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> @@ -2445,30 +2442,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
>  
>  struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
> +	void (*postinstall)(struct intel_display *display);
>  };
>  
>  static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
>  	.reset = gen11_display_irq_reset,
> +	.postinstall = gen11_de_irq_postinstall,
>  };
>  
>  static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
>  	.reset = gen8_display_irq_reset,
> +	.postinstall = gen8_de_irq_postinstall,
>  };
>  
>  static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
>  	.reset = vlv_display_irq_reset,
> +	.postinstall = vlv_display_irq_postinstall,
>  };
>  
>  static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
>  	.reset = ilk_display_irq_reset,
> +	.postinstall = ilk_de_irq_postinstall,
>  };
>  
>  static const struct intel_display_irq_funcs i965_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
> +	.postinstall = i965_display_irq_postinstall,
>  };
>  
>  static const struct intel_display_irq_funcs i915_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
> +	.postinstall = i915_display_irq_postinstall,
>  };
>  
>  void intel_display_irq_reset(struct intel_display *display)
> @@ -2479,6 +2483,14 @@ void intel_display_irq_reset(struct intel_display *display)
>  	display->irq.funcs->reset(display);
>  }
>  
> +void intel_display_irq_postinstall(struct intel_display *display)
> +{
> +	if (!HAS_DISPLAY(display))
> +		return;
> +
> +	display->irq.funcs->postinstall(display);
> +}
> +
>  void intel_display_irq_init(struct intel_display *display)
>  {
>  	spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 21b2145656cd..fd9873ce9755 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>  
>  void intel_display_irq_reset(struct intel_display *display);
> +void intel_display_irq_postinstall(struct intel_display *display);
>  
>  u32 i9xx_display_irq_enable_mask(struct intel_display *display);
> -void i915_display_irq_postinstall(struct intel_display *display);
> -void i965_display_irq_postinstall(struct intel_display *display);
> -void vlv_display_irq_postinstall(struct intel_display *display);
> -void ilk_de_irq_postinstall(struct intel_display *display);
> -void gen8_de_irq_postinstall(struct intel_display *display);
> -void gen11_de_irq_postinstall(struct intel_display *display);
>  
>  u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
>  void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c4f56a869910..c21b289b8007 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen5_gt_irq_postinstall(to_gt(dev_priv));
>  
> -	ilk_de_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  }
>  
>  static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen5_gt_irq_postinstall(to_gt(dev_priv));
>  
> -	vlv_display_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  
>  	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
>  	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
> @@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  	struct intel_display *display = dev_priv->display;
>  
>  	gen8_gt_irq_postinstall(to_gt(dev_priv));
> -	gen8_de_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  
>  	gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
>  }
> @@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>  	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>  
>  	gen11_gt_irq_postinstall(gt);
> -	gen11_de_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  
>  	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
>  
> @@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
>  
> -	gen11_de_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  
>  	dg1_master_intr_enable(intel_uncore_regs(uncore));
>  	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> @@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen8_gt_irq_postinstall(to_gt(dev_priv));
>  
> -	vlv_display_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  
>  	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
> @@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
>  
> -	i915_display_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  }
>  
>  static irqreturn_t i915_irq_handler(int irq, void *arg)
> @@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
>  
> -	i965_display_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  }
>  
>  static irqreturn_t i965_irq_handler(int irq, void *arg)
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index ba3225878c61..62e5d38938eb 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -246,7 +246,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
>  	if (!xe->info.probe_display)
>  		return;
>  
> -	gen11_de_irq_postinstall(display);
> +	intel_display_irq_postinstall(display);
>  }
>  
>  static bool suspend_to_idle(void)
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

[PATCH v3 5/6] drm/i915/irq: add intel_display_irq_ack() to irq funcs

[Jani Nikula]

Some platforms have a separate step for acking display irqs. Call the
platform specific display irq ack hooks, if any, via
intel_display_irq_ack().

Introduce struct intel_display_irq_state to group together all the data
the ack hooks need. In the follow-up, this state will be passed on to a
shared handler function.

Check for HAS_DISPLAY() in intel_display_irq_ack() for completeness even
though fusing is not possible on the platforms in question.

v2:
- Include LPE audio in the ack part
- Check for HAS_DISPLAY()

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  58 ++++++-
 .../gpu/drm/i915/display/intel_display_irq.h  |  12 +-
 drivers/gpu/drm/i915/i915_irq.c               | 144 ++++++------------
 3 files changed, 113 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 1c3c8095765d..4b2a61e97ed1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -23,6 +23,7 @@
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hotplug_irq.h"
+#include "intel_lpe_audio.h"
 #include "intel_parent.h"
 #include "intel_pipe_crc_regs.h"
 #include "intel_plane.h"
@@ -529,8 +530,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
 	}
 }
 
-void i9xx_pipestat_irq_ack(struct intel_display *display,
-			   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_ack(struct intel_display *display,
+				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1898,8 +1899,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
 	}
 }
 
-void vlv_display_error_irq_ack(struct intel_display *display,
-			       u32 *eir, u32 *dpinvgtt)
+static void vlv_display_error_irq_ack(struct intel_display *display,
+				      u32 *eir, u32 *dpinvgtt)
 {
 	u32 emr;
 
@@ -2010,6 +2011,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
+static void i9xx_display_irq_ack(struct intel_display *display,
+				 struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2065,6 +2076,32 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
+static u32 vlv_lpe_irq_mask(struct intel_display *display)
+{
+	if (display->platform.cherryview)
+		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT |
+			I915_LPE_PIPE_C_INTERRUPT;
+	else
+		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
+}
+
+static void vlv_display_irq_ack(struct intel_display *display,
+				struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+
+	/* The handler acks the irq, so need to call the handler here */
+	if (state->iir & vlv_lpe_irq_mask(display))
+		intel_lpe_audio_irq_handler(display);
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
@@ -2443,6 +2480,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
+	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
@@ -2458,6 +2496,7 @@ static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
+	.ack = vlv_display_irq_ack,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
@@ -2468,11 +2507,13 @@ static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2491,6 +2532,15 @@ void intel_display_irq_postinstall(struct intel_display *display)
 	display->irq.funcs->postinstall(display);
 }
 
+void intel_display_irq_ack(struct intel_display *display,
+			   struct intel_display_irq_state *state)
+{
+	if (!HAS_DISPLAY(display) || !display->irq.funcs->ack)
+		return;
+
+	display->irq.funcs->ack(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index fd9873ce9755..3773a31e48f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,8 +58,17 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
+struct intel_display_irq_state {
+	u32 iir;
+	u32 eir;
+	u32 hotplug_status;
+	u32 dpinvgtt;
+	u32 pipe_stats[I915_MAX_PIPES];
+};
+
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
+void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
@@ -67,13 +76,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-
 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
-void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
 
 void intel_display_irq_init(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c21b289b8007..b28e89fdb6fd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -39,7 +39,6 @@
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
 #include "display/intel_hotplug_irq.h"
-#include "display/intel_lpe_audio.h"
 
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_gt.h"
@@ -236,17 +235,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 iir, gt_iir, pm_iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 gt_iir, pm_iir;
 		u32 ier = 0;
 
 		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
 		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+		if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -272,26 +269,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -301,13 +286,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -330,16 +315,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 master_ctl, iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 master_ctl;
 		u32 ier = 0;
 
 		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (master_ctl == 0 && iir == 0)
+		if (master_ctl == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -362,38 +345,25 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT |
-			   I915_LPE_PIPE_C_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -904,39 +874,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
+		intel_display_irq_ack(display, &state);
 
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
-			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
+		if (state.iir & I915_USER_INTERRUPT)
+			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i915_pipestat_irq_handler(display, iir, pipe_stats);
+		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1013,44 +976,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		intel_display_irq_ack(display, &state);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
+		if (state.iir & I915_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
-					    iir);
+					    state.iir);
 
-		if (iir & I915_BSD_USER_INTERRUPT)
+		if (state.iir & I915_BSD_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
-					    iir >> 25);
+					    state.iir >> 25);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i965_pipestat_irq_handler(display, iir, pipe_stats);
+		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
-- 
2.47.3

Re: [PATCH v3 5/6] drm/i915/irq: add intel_display_irq_ack() to irq funcs

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:10PM +0300, Jani Nikula wrote:
> Some platforms have a separate step for acking display irqs. Call the
> platform specific display irq ack hooks, if any, via
> intel_display_irq_ack().
> 
> Introduce struct intel_display_irq_state to group together all the data
> the ack hooks need. In the follow-up, this state will be passed on to a
> shared handler function.

This also might be a bit cleaner done in two steps:
1. extract the gmch ack() funcs
2. add the vfunc

> 
> Check for HAS_DISPLAY() in intel_display_irq_ack() for completeness even
> though fusing is not possible on the platforms in question.
> 
> v2:
> - Include LPE audio in the ack part
> - Check for HAS_DISPLAY()
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  |  58 ++++++-
>  .../gpu/drm/i915/display/intel_display_irq.h  |  12 +-
>  drivers/gpu/drm/i915/i915_irq.c               | 144 ++++++------------
>  3 files changed, 113 insertions(+), 101 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 1c3c8095765d..4b2a61e97ed1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -23,6 +23,7 @@
>  #include "intel_fifo_underrun.h"
>  #include "intel_gmbus.h"
>  #include "intel_hotplug_irq.h"
> +#include "intel_lpe_audio.h"
>  #include "intel_parent.h"
>  #include "intel_pipe_crc_regs.h"
>  #include "intel_plane.h"
> @@ -529,8 +530,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
>  	}
>  }
>  
> -void i9xx_pipestat_irq_ack(struct intel_display *display,
> -			   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> +static void i9xx_pipestat_irq_ack(struct intel_display *display,
> +				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	enum pipe pipe;
>  
> @@ -1898,8 +1899,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
>  	}
>  }
>  
> -void vlv_display_error_irq_ack(struct intel_display *display,
> -			       u32 *eir, u32 *dpinvgtt)
> +static void vlv_display_error_irq_ack(struct intel_display *display,
> +				      u32 *eir, u32 *dpinvgtt)
>  {
>  	u32 emr;
>  
> @@ -2010,6 +2011,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
>  	i915_enable_asle_pipestat(display);
>  }
>  
> +static void i9xx_display_irq_ack(struct intel_display *display,
> +				 struct intel_display_irq_state *state)
> +{
> +	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
> +		state->hotplug_status = i9xx_hpd_irq_ack(display);
> +
> +	/* Call regardless, as some status bits might not be signalled in IIR */
> +	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
> +}
> +
>  static u32 vlv_error_mask(void)
>  {
>  	/* TODO enable other errors too? */
> @@ -2065,6 +2076,32 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
>  	spin_unlock_irq(&display->irq.lock);
>  }
>  
> +static u32 vlv_lpe_irq_mask(struct intel_display *display)
> +{
> +	if (display->platform.cherryview)
> +		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT |
> +			I915_LPE_PIPE_C_INTERRUPT;
> +	else
> +		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
> +}
> +
> +static void vlv_display_irq_ack(struct intel_display *display,
> +				struct intel_display_irq_state *state)
> +{
> +	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
> +		state->hotplug_status = i9xx_hpd_irq_ack(display);
> +
> +	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
> +		vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
> +
> +	/* Call regardless, as some status bits might not be signalled in IIR */
> +	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
> +
> +	/* The handler acks the irq, so need to call the handler here */
> +	if (state->iir & vlv_lpe_irq_mask(display))
> +		intel_lpe_audio_irq_handler(display);
> +}
> +
>  static void ibx_display_irq_reset(struct intel_display *display)
>  {
>  	if (HAS_PCH_NOP(display))
> @@ -2443,6 +2480,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
>  struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
>  	void (*postinstall)(struct intel_display *display);
> +	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
>  };
>  
>  static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
> @@ -2458,6 +2496,7 @@ static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
>  static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
>  	.reset = vlv_display_irq_reset,
>  	.postinstall = vlv_display_irq_postinstall,
> +	.ack = vlv_display_irq_ack,
>  };
>  
>  static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
> @@ -2468,11 +2507,13 @@ static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
>  static const struct intel_display_irq_funcs i965_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i965_display_irq_postinstall,
> +	.ack = i9xx_display_irq_ack,
>  };
>  
>  static const struct intel_display_irq_funcs i915_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i915_display_irq_postinstall,
> +	.ack = i9xx_display_irq_ack,
>  };
>  
>  void intel_display_irq_reset(struct intel_display *display)
> @@ -2491,6 +2532,15 @@ void intel_display_irq_postinstall(struct intel_display *display)
>  	display->irq.funcs->postinstall(display);
>  }
>  
> +void intel_display_irq_ack(struct intel_display *display,
> +			   struct intel_display_irq_state *state)
> +{
> +	if (!HAS_DISPLAY(display) || !display->irq.funcs->ack)
> +		return;
> +
> +	display->irq.funcs->ack(display, state);
> +}
> +
>  void intel_display_irq_init(struct intel_display *display)
>  {
>  	spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index fd9873ce9755..3773a31e48f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -58,8 +58,17 @@ void gen11_display_irq_handler(struct intel_display *display);
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>  
> +struct intel_display_irq_state {
> +	u32 iir;
> +	u32 eir;
> +	u32 hotplug_status;
> +	u32 dpinvgtt;
> +	u32 pipe_stats[I915_MAX_PIPES];
> +};
> +
>  void intel_display_irq_reset(struct intel_display *display);
>  void intel_display_irq_postinstall(struct intel_display *display);
> +void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
>  
>  u32 i9xx_display_irq_enable_mask(struct intel_display *display);
>  
> @@ -67,13 +76,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
>  void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  
> -void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
> -
>  void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
>  void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
>  void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
>  
> -void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
>  void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
>  
>  void intel_display_irq_init(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c21b289b8007..b28e89fdb6fd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -39,7 +39,6 @@
>  #include "display/intel_display_irq.h"
>  #include "display/intel_hotplug.h"
>  #include "display/intel_hotplug_irq.h"
> -#include "display/intel_lpe_audio.h"
>  
>  #include "gt/intel_breadcrumbs.h"
>  #include "gt/intel_gt.h"
> @@ -236,17 +235,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	do {
> -		u32 iir, gt_iir, pm_iir;
> -		u32 eir = 0, dpinvgtt = 0;
> -		u32 pipe_stats[I915_MAX_PIPES] = {};
> -		u32 hotplug_status = 0;
> +		struct intel_display_irq_state state = {};
> +		u32 gt_iir, pm_iir;
>  		u32 ier = 0;
>  
>  		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
>  		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
> -		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
> +		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
>  
> -		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
> +		if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
>  			break;
>  
>  		ret = IRQ_HANDLED;
> @@ -272,26 +269,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		if (pm_iir)
>  			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
>  
> -		if (iir & I915_DISPLAY_PORT_INTERRUPT)
> -			hotplug_status = i9xx_hpd_irq_ack(display);
> -
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> -
> -		/* Call regardless, as some status bits might not be
> -		 * signalled in IIR */
> -		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> -			   I915_LPE_PIPE_B_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);
> +		intel_display_irq_ack(display, &state);
>  
>  		/*
>  		 * VLV_IIR is single buffered, and reflects the level
>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
>  		 */
> -		if (iir)
> -			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
> +		if (state.iir)
> +			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
>  
>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>  		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> @@ -301,13 +286,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		if (pm_iir)
>  			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>  
> -		if (hotplug_status)
> -			i9xx_hpd_irq_handler(display, hotplug_status);
> +		if (state.hotplug_status)
> +			i9xx_hpd_irq_handler(display, state.hotplug_status);
>  
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, eir, dpinvgtt);
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> +			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
>  
> -		valleyview_pipestat_irq_handler(display, pipe_stats);
> +		valleyview_pipestat_irq_handler(display, state.pipe_stats);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -330,16 +315,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	do {
> -		u32 master_ctl, iir;
> -		u32 eir = 0, dpinvgtt = 0;
> -		u32 pipe_stats[I915_MAX_PIPES] = {};
> -		u32 hotplug_status = 0;
> +		struct intel_display_irq_state state = {};
> +		u32 master_ctl;
>  		u32 ier = 0;
>  
>  		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> -		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
> +		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
>  
> -		if (master_ctl == 0 && iir == 0)
> +		if (master_ctl == 0 && state.iir == 0)
>  			break;
>  
>  		ret = IRQ_HANDLED;
> @@ -362,38 +345,25 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  
>  		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
>  
> -		if (iir & I915_DISPLAY_PORT_INTERRUPT)
> -			hotplug_status = i9xx_hpd_irq_ack(display);
> -
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> -
> -		/* Call regardless, as some status bits might not be
> -		 * signalled in IIR */
> -		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> -			   I915_LPE_PIPE_B_INTERRUPT |
> -			   I915_LPE_PIPE_C_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);
> +		intel_display_irq_ack(display, &state);
>  
>  		/*
>  		 * VLV_IIR is single buffered, and reflects the level
>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
>  		 */
> -		if (iir)
> -			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
> +		if (state.iir)
> +			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
>  
>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>  		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  
> -		if (hotplug_status)
> -			i9xx_hpd_irq_handler(display, hotplug_status);
> +		if (state.hotplug_status)
> +			i9xx_hpd_irq_handler(display, state.hotplug_status);
>  
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, eir, dpinvgtt);
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> +			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
>  
> -		valleyview_pipestat_irq_handler(display, pipe_stats);
> +		valleyview_pipestat_irq_handler(display, state.pipe_stats);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -904,39 +874,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	do {
> -		u32 pipe_stats[I915_MAX_PIPES] = {};
> +		struct intel_display_irq_state state = {};
>  		u32 eir = 0, eir_stuck = 0;
> -		u32 hotplug_status = 0;
> -		u32 iir;
>  
> -		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> -		if (iir == 0)
> +		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> +		if (state.iir == 0)
>  			break;
>  
>  		ret = IRQ_HANDLED;
>  
> -		if (iir & I915_DISPLAY_PORT_INTERRUPT)
> -			hotplug_status = i9xx_hpd_irq_ack(display);
> +		intel_display_irq_ack(display, &state);
>  
> -		/* Call regardless, as some status bits might not be
> -		 * signalled in IIR */
> -		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>  
> -		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
> +		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
>  
> -		if (iir & I915_USER_INTERRUPT)
> -			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
> +		if (state.iir & I915_USER_INTERRUPT)
> +			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
>  
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (hotplug_status)
> -			i9xx_hpd_irq_handler(display, hotplug_status);
> +		if (state.hotplug_status)
> +			i9xx_hpd_irq_handler(display, state.hotplug_status);
>  
> -		i915_pipestat_irq_handler(display, iir, pipe_stats);
> +		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -1013,44 +976,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	do {
> -		u32 pipe_stats[I915_MAX_PIPES] = {};
> +		struct intel_display_irq_state state = {};
>  		u32 eir = 0, eir_stuck = 0;
> -		u32 hotplug_status = 0;
> -		u32 iir;
>  
> -		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> -		if (iir == 0)
> +		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> +		if (state.iir == 0)
>  			break;
>  
>  		ret = IRQ_HANDLED;
>  
> -		if (iir & I915_DISPLAY_PORT_INTERRUPT)
> -			hotplug_status = i9xx_hpd_irq_ack(display);
> -
> -		/* Call regardless, as some status bits might not be
> -		 * signalled in IIR */
> -		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> +		intel_display_irq_ack(display, &state);
>  
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>  
> -		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
> +		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
>  
> -		if (iir & I915_USER_INTERRUPT)
> +		if (state.iir & I915_USER_INTERRUPT)
>  			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
> -					    iir);
> +					    state.iir);
>  
> -		if (iir & I915_BSD_USER_INTERRUPT)
> +		if (state.iir & I915_BSD_USER_INTERRUPT)
>  			intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
> -					    iir >> 25);
> +					    state.iir >> 25);
>  
> -		if (iir & I915_MASTER_ERROR_INTERRUPT)
> +		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (hotplug_status)
> -			i9xx_hpd_irq_handler(display, hotplug_status);
> +		if (state.hotplug_status)
> +			i9xx_hpd_irq_handler(display, state.hotplug_status);
>  
> -		i965_pipestat_irq_handler(display, iir, pipe_stats);
> +		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, IRQ_HANDLED);
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

[PATCH v3 6/6] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Jani Nikula]

Call the platform specific display irq handler hooks via
intel_display_irq_handler(). Add master_ctl to struct
intel_display_irq_state, and pass the state pointer to the handler where
necessary.

v2: Rebase, handle LPE audio in ack (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 86 ++++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  | 11 +--
 drivers/gpu/drm/i915/i915_irq.c               | 38 +++-----
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 89 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 4b2a61e97ed1..e8c1e0f88054 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
 	spin_unlock(&display->irq.lock);
 }
 
-void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i915_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -621,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 		intel_opregion_asle_intr(display);
 }
 
-void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i965_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -648,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 		intel_gmbus_irq_handler(display);
 }
 
-void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     const u32 pipe_stats[I915_MAX_PIPES])
+static void valleyview_pipestat_irq_handler(struct intel_display *display,
+					    const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1021,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
 		intel_de_write_fw(display, SDEIER, sde_ier);
 }
 
-bool ilk_display_irq_handler(struct intel_display *display)
+static bool ilk_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
 {
 	u32 de_iir;
 	bool handled = false;
@@ -1405,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
 		intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
 }
 
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
+static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 {
 	u32 iir;
 	enum pipe pipe;
@@ -1566,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 	}
 }
 
+static bool gen8_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	gen8_de_irq_handler(display, state->master_ctl);
+
+	return true;
+}
+
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
 {
 	u32 iir;
@@ -1590,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
 		intel_opregion_asle_intr(display);
 }
 
-void gen11_display_irq_handler(struct intel_display *display)
+static bool gen11_display_irq_handler(struct intel_display *display,
+				      const struct intel_display_irq_state *state)
 {
 	u32 disp_ctl;
 
@@ -1606,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
 	intel_display_rpm_assert_unblock(display);
+
+	return true;
 }
 
 static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
@@ -1921,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
 	intel_de_write(display, VLV_EMR, emr);
 }
 
-void vlv_display_error_irq_handler(struct intel_display *display,
-				   u32 eir, u32 dpinvgtt)
+static void vlv_display_error_irq_handler(struct intel_display *display,
+					  u32 eir, u32 dpinvgtt)
 {
 	drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
 
@@ -2021,6 +2033,28 @@ static void i9xx_display_irq_ack(struct intel_display *display,
 	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
 }
 
+static bool i965_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
+static bool i915_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2102,6 +2136,20 @@ static void vlv_display_irq_ack(struct intel_display *display,
 		intel_lpe_audio_irq_handler(display);
 }
 
+static bool vlv_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
+
+	valleyview_pipestat_irq_handler(display, state->pipe_stats);
+
+	return true;
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
@@ -2481,39 +2529,46 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
 	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
+	bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
 	.postinstall = gen11_de_irq_postinstall,
+	.handler = gen11_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
 	.postinstall = gen8_de_irq_postinstall,
+	.handler = gen8_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
 	.ack = vlv_display_irq_ack,
+	.handler = vlv_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
 	.postinstall = ilk_de_irq_postinstall,
+	.handler = ilk_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i965_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i915_display_irq_handler,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2541,6 +2596,15 @@ void intel_display_irq_ack(struct intel_display *display,
 	display->irq.funcs->ack(display, state);
 }
 
+bool intel_display_irq_handler(struct intel_display *display,
+			       const struct intel_display_irq_state *state)
+{
+	if (!HAS_DISPLAY(display) || !display->irq.funcs->handler)
+		return true;
+
+	return display->irq.funcs->handler(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 3773a31e48f2..a1227cee885a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
 
 void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
 void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
-bool ilk_display_irq_handler(struct intel_display *display);
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
-void gen11_display_irq_handler(struct intel_display *display);
 
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 struct intel_display_irq_state {
+	u32 master_ctl;
 	u32 iir;
 	u32 eir;
 	u32 hotplug_status;
@@ -69,6 +67,7 @@ struct intel_display_irq_state {
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
 void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
@@ -76,12 +75,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
-
-void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-
 void intel_display_irq_init(struct intel_display *display);
 
 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b28e89fdb6fd..30ce462e92ab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -38,7 +38,6 @@
 
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
-#include "display/intel_hotplug_irq.h"
 
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_gt.h"
@@ -286,13 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -357,13 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -410,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
 		ret = IRQ_HANDLED;
 	}
 
-	if (ilk_display_irq_handler(display))
+	if (intel_display_irq_handler(display, NULL))
 		ret = IRQ_HANDLED;
 
 	if (GRAPHICS_VER(i915) >= 6) {
@@ -472,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & ~GEN8_GT_IRQS) {
+		const struct intel_display_irq_state state = {
+			.master_ctl = master_ctl,
+		};
 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
-		gen8_de_irq_handler(display, master_ctl);
+		intel_display_irq_handler(display, &state);
 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 	}
 
@@ -525,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -592,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 	gen11_gt_irq_handler(gt, master_ctl);
 
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -896,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1003,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 62e5d38938eb..796164e9bc20 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -215,7 +215,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
 		return;
 
 	if (master_ctl & DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 }
 
 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
-- 
2.47.3

Re: [PATCH v3 6/6] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Ville Syrjälä]

On Wed, May 13, 2026 at 01:10:11PM +0300, Jani Nikula wrote:
> Call the platform specific display irq handler hooks via
> intel_display_irq_handler(). Add master_ctl to struct
> intel_display_irq_state, and pass the state pointer to the handler where
> necessary.

Would probably be cleaner to extract the gmch *_display_irq_handler()
in a separate patch before adding the vfunc.

> 
> v2: Rebase, handle LPE audio in ack (Ville)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  | 86 ++++++++++++++++---
>  .../gpu/drm/i915/display/intel_display_irq.h  | 11 +--
>  drivers/gpu/drm/i915/i915_irq.c               | 38 +++-----
>  drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
>  4 files changed, 89 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 4b2a61e97ed1..e8c1e0f88054 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -597,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
>  	spin_unlock(&display->irq.lock);
>  }
>  
> -void i915_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
> +static void i915_pipestat_irq_handler(struct intel_display *display,
> +				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -621,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
>  		intel_opregion_asle_intr(display);
>  }
>  
> -void i965_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
> +static void i965_pipestat_irq_handler(struct intel_display *display,
> +				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -648,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
>  		intel_gmbus_irq_handler(display);
>  }
>  
> -void valleyview_pipestat_irq_handler(struct intel_display *display,
> -				     const u32 pipe_stats[I915_MAX_PIPES])
> +static void valleyview_pipestat_irq_handler(struct intel_display *display,
> +					    const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	enum pipe pipe;
>  
> @@ -1021,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
>  		intel_de_write_fw(display, SDEIER, sde_ier);
>  }
>  
> -bool ilk_display_irq_handler(struct intel_display *display)
> +static bool ilk_display_irq_handler(struct intel_display *display,
> +				    const struct intel_display_irq_state *state)
>  {
>  	u32 de_iir;
>  	bool handled = false;
> @@ -1405,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
>  		intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
>  }
>  
> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
> +static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>  {
>  	u32 iir;
>  	enum pipe pipe;
> @@ -1566,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>  	}
>  }
>  
> +static bool gen8_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	gen8_de_irq_handler(display, state->master_ctl);
> +
> +	return true;
> +}
> +
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
>  {
>  	u32 iir;
> @@ -1590,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
>  		intel_opregion_asle_intr(display);
>  }
>  
> -void gen11_display_irq_handler(struct intel_display *display)
> +static bool gen11_display_irq_handler(struct intel_display *display,
> +				      const struct intel_display_irq_state *state)
>  {
>  	u32 disp_ctl;
>  
> @@ -1606,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
>  	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>  
>  	intel_display_rpm_assert_unblock(display);
> +
> +	return true;
>  }
>  
>  static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
> @@ -1921,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
>  	intel_de_write(display, VLV_EMR, emr);
>  }
>  
> -void vlv_display_error_irq_handler(struct intel_display *display,
> -				   u32 eir, u32 dpinvgtt)
> +static void vlv_display_error_irq_handler(struct intel_display *display,
> +					  u32 eir, u32 dpinvgtt)
>  {
>  	drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
>  
> @@ -2021,6 +2033,28 @@ static void i9xx_display_irq_ack(struct intel_display *display,
>  	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
>  }
>  
> +static bool i965_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
> +
> +	return true;
> +}
> +
> +static bool i915_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
> +
> +	return true;
> +}
> +
>  static u32 vlv_error_mask(void)
>  {
>  	/* TODO enable other errors too? */
> @@ -2102,6 +2136,20 @@ static void vlv_display_irq_ack(struct intel_display *display,
>  		intel_lpe_audio_irq_handler(display);
>  }
>  
> +static bool vlv_display_irq_handler(struct intel_display *display,
> +				    const struct intel_display_irq_state *state)
> +{
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
> +		vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
> +
> +	valleyview_pipestat_irq_handler(display, state->pipe_stats);
> +
> +	return true;
> +}
> +
>  static void ibx_display_irq_reset(struct intel_display *display)
>  {
>  	if (HAS_PCH_NOP(display))
> @@ -2481,39 +2529,46 @@ struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
>  	void (*postinstall)(struct intel_display *display);
>  	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
> +	bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
>  };
>  
>  static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
>  	.reset = gen11_display_irq_reset,
>  	.postinstall = gen11_de_irq_postinstall,
> +	.handler = gen11_display_irq_handler,
>  };
>  
>  static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
>  	.reset = gen8_display_irq_reset,
>  	.postinstall = gen8_de_irq_postinstall,
> +	.handler = gen8_display_irq_handler,
>  };
>  
>  static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
>  	.reset = vlv_display_irq_reset,
>  	.postinstall = vlv_display_irq_postinstall,
>  	.ack = vlv_display_irq_ack,
> +	.handler = vlv_display_irq_handler,
>  };
>  
>  static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
>  	.reset = ilk_display_irq_reset,
>  	.postinstall = ilk_de_irq_postinstall,
> +	.handler = ilk_display_irq_handler,
>  };
>  
>  static const struct intel_display_irq_funcs i965_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i965_display_irq_postinstall,
>  	.ack = i9xx_display_irq_ack,
> +	.handler = i965_display_irq_handler,
>  };
>  
>  static const struct intel_display_irq_funcs i915_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i915_display_irq_postinstall,
>  	.ack = i9xx_display_irq_ack,
> +	.handler = i915_display_irq_handler,
>  };
>  
>  void intel_display_irq_reset(struct intel_display *display)
> @@ -2541,6 +2596,15 @@ void intel_display_irq_ack(struct intel_display *display,
>  	display->irq.funcs->ack(display, state);
>  }
>  
> +bool intel_display_irq_handler(struct intel_display *display,
> +			       const struct intel_display_irq_state *state)
> +{
> +	if (!HAS_DISPLAY(display) || !display->irq.funcs->handler)
> +		return true;
> +
> +	return display->irq.funcs->handler(display, state);
> +}
> +
>  void intel_display_irq_init(struct intel_display *display)
>  {
>  	spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 3773a31e48f2..a1227cee885a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
>  
>  void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
>  void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
> -bool ilk_display_irq_handler(struct intel_display *display);
> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
> -void gen11_display_irq_handler(struct intel_display *display);
>  
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>  
>  struct intel_display_irq_state {
> +	u32 master_ctl;
>  	u32 iir;
>  	u32 eir;
>  	u32 hotplug_status;
> @@ -69,6 +67,7 @@ struct intel_display_irq_state {
>  void intel_display_irq_reset(struct intel_display *display);
>  void intel_display_irq_postinstall(struct intel_display *display);
>  void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
> +bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
>  
>  u32 i9xx_display_irq_enable_mask(struct intel_display *display);
>  
> @@ -76,12 +75,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
>  void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  
> -void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> -void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> -void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
> -
> -void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
> -
>  void intel_display_irq_init(struct intel_display *display);
>  
>  void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b28e89fdb6fd..30ce462e92ab 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -38,7 +38,6 @@
>  
>  #include "display/intel_display_irq.h"
>  #include "display/intel_hotplug.h"
> -#include "display/intel_hotplug_irq.h"
>  
>  #include "gt/intel_breadcrumbs.h"
>  #include "gt/intel_gt.h"
> @@ -286,13 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		if (pm_iir)
>  			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
> -
> -		valleyview_pipestat_irq_handler(display, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -357,13 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>  		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
> -
> -		valleyview_pipestat_irq_handler(display, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -410,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
>  		ret = IRQ_HANDLED;
>  	}
>  
> -	if (ilk_display_irq_handler(display))
> +	if (intel_display_irq_handler(display, NULL))
>  		ret = IRQ_HANDLED;
>  
>  	if (GRAPHICS_VER(i915) >= 6) {
> @@ -472,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  
>  	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
>  	if (master_ctl & ~GEN8_GT_IRQS) {
> +		const struct intel_display_irq_state state = {
> +			.master_ctl = master_ctl,
> +		};
>  		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> -		gen8_de_irq_handler(display, master_ctl);
> +		intel_display_irq_handler(display, &state);
>  		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  	}
>  
> @@ -525,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
>  
>  	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
>  	if (master_ctl & GEN11_DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  
>  	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>  
> @@ -592,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>  	gen11_gt_irq_handler(gt, master_ctl);
>  
>  	if (master_ctl & GEN11_DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  
>  	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>  
> @@ -896,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -1003,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, IRQ_HANDLED);
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index 62e5d38938eb..796164e9bc20 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -215,7 +215,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
>  		return;
>  
>  	if (master_ctl & DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  }
>  
>  void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4241 bytes --]

== Series Details ==

Series: drm/i915: add display irq hooks (rev2)
URL   : https://patchwork.freedesktop.org/series/165935/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18481 -> Patchwork_165935v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_165935v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_165935v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_165935v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/fi-bsw-n3050/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/fi-bsw-n3050/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_165935v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-8:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [PASS][5] -> [DMESG-FAIL][6] ([i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][13] ([i915#12061]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#14204])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * Linux: CI_DRM_18481 -> Patchwork_165935v2

  CI-20190529: 20190529
  CI_DRM_18481: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_165935v2: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

[-- Attachment #2: Type: text/html, Size: 5415 bytes --]

✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4241 bytes --]

== Series Details ==

Series: drm/i915: add display irq hooks (rev2)
URL   : https://patchwork.freedesktop.org/series/165935/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18481 -> Patchwork_165935v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_165935v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_165935v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_165935v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/fi-bsw-n3050/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/fi-bsw-n3050/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_165935v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-8:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [PASS][5] -> [DMESG-FAIL][6] ([i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][13] ([i915#12061]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#14204])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * Linux: CI_DRM_18481 -> Patchwork_165935v2

  CI-20190529: 20190529
  CI_DRM_18481: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_165935v2: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

[-- Attachment #2: Type: text/html, Size: 5415 bytes --]

✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4241 bytes --]

== Series Details ==

Series: drm/i915: add display irq hooks (rev2)
URL   : https://patchwork.freedesktop.org/series/165935/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18481 -> Patchwork_165935v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_165935v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_165935v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_165935v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/fi-bsw-n3050/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/fi-bsw-n3050/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_165935v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-8:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [PASS][5] -> [DMESG-FAIL][6] ([i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][13] ([i915#12061]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#14204])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * Linux: CI_DRM_18481 -> Patchwork_165935v2

  CI-20190529: 20190529
  CI_DRM_18481: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_165935v2: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

[-- Attachment #2: Type: text/html, Size: 5415 bytes --]

✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4241 bytes --]

== Series Details ==

Series: drm/i915: add display irq hooks (rev2)
URL   : https://patchwork.freedesktop.org/series/165935/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18481 -> Patchwork_165935v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_165935v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_165935v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_165935v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/fi-bsw-n3050/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/fi-bsw-n3050/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_165935v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-8:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [PASS][5] -> [DMESG-FAIL][6] ([i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][13] ([i915#12061]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#14204])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18481/bat-atsm-1/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * Linux: CI_DRM_18481 -> Patchwork_165935v2

  CI-20190529: 20190529
  CI_DRM_18481: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_165935v2: 896e027423be1efc1b1a690bc56bafe6cf49c213 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v2/index.html

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