* [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs
@ 2021-11-11 0:45 Michael Cheng
2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE Michael Cheng
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Michael Cheng @ 2021-11-11 0:45 UTC (permalink / raw)
To: intel-gfx
Cc: michael.cheng, wayne.boyer, jani.nikula, lucas.demarchi,
siva.mullati
This series is to introduce new macros generic to i915 for checking 0 and 1 bits,
instead on relying on whats defined by the mmu, since it could be different
or non-exisitent between different platforms.
v2: Corrected sender's email.
v3: Corrected spelling error.
v4: Clean up a few other macros that are checking 0 and 1 bits.
Thanks to Lucas De Marchi for suggesting these cleanups.
Michael Cheng (3):
drm/i915: Introduce new macros for i915 PTE
drm/i915: Clean up GEN6 page valid macros
drm/i915: Clean up BYT_PTE_WRITEABLE
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++++++-------
drivers/gpu/drm/i915/gt/intel_gtt.h | 6 +++---
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------
5 files changed, 20 insertions(+), 20 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng @ 2021-11-11 0:45 ` Michael Cheng 2021-11-13 1:28 ` Matt Roper 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 2/3] drm/i915: Clean up GEN6 page valid macros Michael Cheng ` (3 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Michael Cheng @ 2021-11-11 0:45 UTC (permalink / raw) To: intel-gfx Cc: michael.cheng, wayne.boyer, jani.nikula, lucas.demarchi, siva.mullati Certain functions within i915 uses macros that are defined for specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT (Some architectures don't even have these macros defined, like ARM64). Instead of re-using bits defined for the CPU, we should use bits defined for i915. This patch introduces two new macros, I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the same throughout the generations. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ 4 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 9966e9dc5218..f89b50ffc286 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -18,7 +18,7 @@ static u64 gen8_pde_encode(const dma_addr_t addr, const enum i915_cache_level level) { - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW; if (level != I915_CACHE_NONE) pde |= PPAT_CACHED_PDE; @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW; if (unlikely(flags & PTE_READ_ONLY)) - pte &= ~_PAGE_RW; + pte &= ~I915_PAGE_RW; if (flags & PTE_LM) pte |= GEN12_PPGTT_PTE_LM; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 1fb4a03d7ac3..3f8e1ee0fbfa 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen8_pte_t pte = addr | _PAGE_PRESENT; + gen8_pte_t pte = addr | I915_PAGE_PRESENT; if (flags & PTE_LM) pte |= GEN12_GGTT_PTE_LM; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index dfeaef680aac..fba9c0c18f4a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -39,6 +39,9 @@ #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ +#define I915_PAGE_PRESENT BIT_ULL(0) +#define I915_PAGE_RW BIT_ULL(1) + #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 53d0cb327539..8f6a055854f7 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) return (e->val64 != 0); else - return (e->val64 & _PAGE_PRESENT); + return (e->val64 & I915_PAGE_PRESENT); } static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) { - e->val64 &= ~_PAGE_PRESENT; + e->val64 &= ~I915_PAGE_PRESENT; } static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) { - e->val64 |= _PAGE_PRESENT; + e->val64 |= I915_PAGE_PRESENT; } static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, /* The entry parameters like present/writeable/cache type * set to the same as i915's scratch page tree. */ - se.val64 |= _PAGE_PRESENT | _PAGE_RW; + se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW; if (type == GTT_TYPE_PPGTT_PDE_PT) se.val64 |= PPAT_CACHED; @@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; for (idx = 0; idx < num_low; idx++) { pte = mm->ggtt_mm.host_ggtt_aperture[idx]; - if (pte & _PAGE_PRESENT) + if (pte & I915_PAGE_PRESENT) write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); } @@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; for (idx = 0; idx < num_hi; idx++) { pte = mm->ggtt_mm.host_ggtt_hidden[idx]; - if (pte & _PAGE_PRESENT) + if (pte & I915_PAGE_PRESENT) write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); } } -- 2.25.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE Michael Cheng @ 2021-11-13 1:28 ` Matt Roper 2021-11-13 1:31 ` Matt Roper 0 siblings, 1 reply; 13+ messages in thread From: Matt Roper @ 2021-11-13 1:28 UTC (permalink / raw) To: Michael Cheng Cc: wayne.boyer, jani.nikula, intel-gfx, lucas.demarchi, siva.mullati On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote: > Certain functions within i915 uses macros that are defined for > specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT > (Some architectures don't even have these macros defined, like ARM64). > > Instead of re-using bits defined for the CPU, we should use bits > defined for i915. This patch introduces two new macros, > I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to > replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. On older platforms we already had our own definition of GEN6_PTE_VALID (the spec uses "present" and "valid" interchangeably) which we were using to encode our ggtt ptes up through HSW; it might be better to go back to using that rather than adding a new define. It looks like BYT is when the writable bit showed up, and we did add a new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we switched over to using the CPU page table flags instead and never used it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE as well. > > Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the > same throughout the generations. This last sentence seems a bit confusing --- it's true that bit 0 has always been a present/valid flag, but bit 1 wasn't a writable bit until BYT; there just wasn't a writable bit at all (e.g., bspec page 229). It might be worth tossing a few bspec references on the commit message here, just for future reference. E.g., Bspec: 253, 45039 Matt > > Signed-off-by: Michael Cheng <michael.cheng@intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ > drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ > 4 files changed, 13 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 9966e9dc5218..f89b50ffc286 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -18,7 +18,7 @@ > static u64 gen8_pde_encode(const dma_addr_t addr, > const enum i915_cache_level level) > { > - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; > + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > if (level != I915_CACHE_NONE) > pde |= PPAT_CACHED_PDE; > @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, > enum i915_cache_level level, > u32 flags) > { > - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; > + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > if (unlikely(flags & PTE_READ_ONLY)) > - pte &= ~_PAGE_RW; > + pte &= ~I915_PAGE_RW; > > if (flags & PTE_LM) > pte |= GEN12_PPGTT_PTE_LM; > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index 1fb4a03d7ac3..3f8e1ee0fbfa 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, > enum i915_cache_level level, > u32 flags) > { > - gen8_pte_t pte = addr | _PAGE_PRESENT; > + gen8_pte_t pte = addr | I915_PAGE_PRESENT; > > if (flags & PTE_LM) > pte |= GEN12_GGTT_PTE_LM; > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index dfeaef680aac..fba9c0c18f4a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -39,6 +39,9 @@ > > #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ > > +#define I915_PAGE_PRESENT BIT_ULL(0) > +#define I915_PAGE_RW BIT_ULL(1) > + > #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) > #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) > #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c > index 53d0cb327539..8f6a055854f7 100644 > --- a/drivers/gpu/drm/i915/gvt/gtt.c > +++ b/drivers/gpu/drm/i915/gvt/gtt.c > @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) > || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) > return (e->val64 != 0); > else > - return (e->val64 & _PAGE_PRESENT); > + return (e->val64 & I915_PAGE_PRESENT); > } > > static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) > { > - e->val64 &= ~_PAGE_PRESENT; > + e->val64 &= ~I915_PAGE_PRESENT; > } > > static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) > { > - e->val64 |= _PAGE_PRESENT; > + e->val64 |= I915_PAGE_PRESENT; > } > > static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) > @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, > /* The entry parameters like present/writeable/cache type > * set to the same as i915's scratch page tree. > */ > - se.val64 |= _PAGE_PRESENT | _PAGE_RW; > + se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW; > if (type == GTT_TYPE_PPGTT_PDE_PT) > se.val64 |= PPAT_CACHED; > > @@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; > for (idx = 0; idx < num_low; idx++) { > pte = mm->ggtt_mm.host_ggtt_aperture[idx]; > - if (pte & _PAGE_PRESENT) > + if (pte & I915_PAGE_PRESENT) > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > } > > @@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; > for (idx = 0; idx < num_hi; idx++) { > pte = mm->ggtt_mm.host_ggtt_hidden[idx]; > - if (pte & _PAGE_PRESENT) > + if (pte & I915_PAGE_PRESENT) > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > } > } > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 1:28 ` Matt Roper @ 2021-11-13 1:31 ` Matt Roper 2021-11-13 1:42 ` Michael Cheng 2021-11-13 16:20 ` Lucas De Marchi 0 siblings, 2 replies; 13+ messages in thread From: Matt Roper @ 2021-11-13 1:31 UTC (permalink / raw) To: Michael Cheng Cc: wayne.boyer, jani.nikula, intel-gfx, lucas.demarchi, siva.mullati On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote: > On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote: > > Certain functions within i915 uses macros that are defined for > > specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT > > (Some architectures don't even have these macros defined, like ARM64). > > > > Instead of re-using bits defined for the CPU, we should use bits > > defined for i915. This patch introduces two new macros, > > I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to > > replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. > > On older platforms we already had our own definition of GEN6_PTE_VALID > (the spec uses "present" and "valid" interchangeably) which we were > using to encode our ggtt ptes up through HSW; it might be better to go > back to using that rather than adding a new define. > > It looks like BYT is when the writable bit showed up, and we did add a > new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we > switched over to using the CPU page table flags instead and never used > it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE > as well. Okay, I should have looked at the rest of the series before reviewing the first patch; it looks like your next two patches replace GEN6_PTE_VALID and BYT_PTE_WRITEABLE with the new definitions here. I still think it might be preferable to reuse the existing macros (which also help clarify the platforms that those bits first showed up in the PTE on) rather than replacing them with new macros, but I don't feel super strongly about it if other reviewers feel differently. Matt > > > > > Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the > > same throughout the generations. > > This last sentence seems a bit confusing --- it's true that bit 0 has > always been a present/valid flag, but bit 1 wasn't a writable bit until > BYT; there just wasn't a writable bit at all (e.g., bspec page 229). > > It might be worth tossing a few bspec references on the commit message > here, just for future reference. E.g., > > Bspec: 253, 45039 > > > Matt > > > > > Signed-off-by: Michael Cheng <michael.cheng@intel.com> > > --- > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- > > drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ > > drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ > > 4 files changed, 13 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > index 9966e9dc5218..f89b50ffc286 100644 > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > @@ -18,7 +18,7 @@ > > static u64 gen8_pde_encode(const dma_addr_t addr, > > const enum i915_cache_level level) > > { > > - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; > > + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > > > if (level != I915_CACHE_NONE) > > pde |= PPAT_CACHED_PDE; > > @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, > > enum i915_cache_level level, > > u32 flags) > > { > > - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; > > + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > > > if (unlikely(flags & PTE_READ_ONLY)) > > - pte &= ~_PAGE_RW; > > + pte &= ~I915_PAGE_RW; > > > > if (flags & PTE_LM) > > pte |= GEN12_PPGTT_PTE_LM; > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > index 1fb4a03d7ac3..3f8e1ee0fbfa 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, > > enum i915_cache_level level, > > u32 flags) > > { > > - gen8_pte_t pte = addr | _PAGE_PRESENT; > > + gen8_pte_t pte = addr | I915_PAGE_PRESENT; > > > > if (flags & PTE_LM) > > pte |= GEN12_GGTT_PTE_LM; > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > > index dfeaef680aac..fba9c0c18f4a 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > > @@ -39,6 +39,9 @@ > > > > #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ > > > > +#define I915_PAGE_PRESENT BIT_ULL(0) > > +#define I915_PAGE_RW BIT_ULL(1) > > + > > #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) > > #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) > > #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c > > index 53d0cb327539..8f6a055854f7 100644 > > --- a/drivers/gpu/drm/i915/gvt/gtt.c > > +++ b/drivers/gpu/drm/i915/gvt/gtt.c > > @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) > > || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) > > return (e->val64 != 0); > > else > > - return (e->val64 & _PAGE_PRESENT); > > + return (e->val64 & I915_PAGE_PRESENT); > > } > > > > static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) > > { > > - e->val64 &= ~_PAGE_PRESENT; > > + e->val64 &= ~I915_PAGE_PRESENT; > > } > > > > static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) > > { > > - e->val64 |= _PAGE_PRESENT; > > + e->val64 |= I915_PAGE_PRESENT; > > } > > > > static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) > > @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, > > /* The entry parameters like present/writeable/cache type > > * set to the same as i915's scratch page tree. > > */ > > - se.val64 |= _PAGE_PRESENT | _PAGE_RW; > > + se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW; > > if (type == GTT_TYPE_PPGTT_PDE_PT) > > se.val64 |= PPAT_CACHED; > > > > @@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > > offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; > > for (idx = 0; idx < num_low; idx++) { > > pte = mm->ggtt_mm.host_ggtt_aperture[idx]; > > - if (pte & _PAGE_PRESENT) > > + if (pte & I915_PAGE_PRESENT) > > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > > } > > > > @@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > > offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; > > for (idx = 0; idx < num_hi; idx++) { > > pte = mm->ggtt_mm.host_ggtt_hidden[idx]; > > - if (pte & _PAGE_PRESENT) > > + if (pte & I915_PAGE_PRESENT) > > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > > } > > } > > -- > > 2.25.1 > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 1:31 ` Matt Roper @ 2021-11-13 1:42 ` Michael Cheng 2021-11-13 1:47 ` Matt Roper 2021-11-13 16:20 ` Lucas De Marchi 1 sibling, 1 reply; 13+ messages in thread From: Michael Cheng @ 2021-11-13 1:42 UTC (permalink / raw) To: Matt Roper Cc: wayne.boyer, jani.nikula, intel-gfx, lucas.demarchi, siva.mullati Thanks for the feed back! I feel like using something name GEN6 or BYT for a platform that's not GEN6 or BYT could be a bit confusing, that's why we decided to go with something more generic. I do agree I need to cite the bspec more. Ill wait for more feedback before I send a new revision out. On 2021-11-12 5:31 p.m., Matt Roper wrote: > On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote: >> On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote: >>> Certain functions within i915 uses macros that are defined for >>> specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT >>> (Some architectures don't even have these macros defined, like ARM64). >>> >>> Instead of re-using bits defined for the CPU, we should use bits >>> defined for i915. This patch introduces two new macros, >>> I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to >>> replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. >> On older platforms we already had our own definition of GEN6_PTE_VALID >> (the spec uses "present" and "valid" interchangeably) which we were >> using to encode our ggtt ptes up through HSW; it might be better to go >> back to using that rather than adding a new define. >> >> It looks like BYT is when the writable bit showed up, and we did add a >> new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we >> switched over to using the CPU page table flags instead and never used >> it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE >> as well. > Okay, I should have looked at the rest of the series before reviewing > the first patch; it looks like your next two patches replace > GEN6_PTE_VALID and BYT_PTE_WRITEABLE with the new definitions here. I > still think it might be preferable to reuse the existing macros (which > also help clarify the platforms that those bits first showed up in the > PTE on) rather than replacing them with new macros, but I don't feel > super strongly about it if other reviewers feel differently. > > > Matt > >>> Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the >>> same throughout the generations. >> This last sentence seems a bit confusing --- it's true that bit 0 has >> always been a present/valid flag, but bit 1 wasn't a writable bit until >> BYT; there just wasn't a writable bit at all (e.g., bspec page 229). >> >> It might be worth tossing a few bspec references on the commit message >> here, just for future reference. E.g., >> >> Bspec: 253, 45039 >> >> >> Matt >> >>> Signed-off-by: Michael Cheng <michael.cheng@intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- >>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- >>> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ >>> drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ >>> 4 files changed, 13 insertions(+), 10 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >>> index 9966e9dc5218..f89b50ffc286 100644 >>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >>> @@ -18,7 +18,7 @@ >>> static u64 gen8_pde_encode(const dma_addr_t addr, >>> const enum i915_cache_level level) >>> { >>> - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; >>> + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW; >>> >>> if (level != I915_CACHE_NONE) >>> pde |= PPAT_CACHED_PDE; >>> @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, >>> enum i915_cache_level level, >>> u32 flags) >>> { >>> - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; >>> + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW; >>> >>> if (unlikely(flags & PTE_READ_ONLY)) >>> - pte &= ~_PAGE_RW; >>> + pte &= ~I915_PAGE_RW; >>> >>> if (flags & PTE_LM) >>> pte |= GEN12_PPGTT_PTE_LM; >>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c >>> index 1fb4a03d7ac3..3f8e1ee0fbfa 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c >>> @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, >>> enum i915_cache_level level, >>> u32 flags) >>> { >>> - gen8_pte_t pte = addr | _PAGE_PRESENT; >>> + gen8_pte_t pte = addr | I915_PAGE_PRESENT; >>> >>> if (flags & PTE_LM) >>> pte |= GEN12_GGTT_PTE_LM; >>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h >>> index dfeaef680aac..fba9c0c18f4a 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h >>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h >>> @@ -39,6 +39,9 @@ >>> >>> #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ >>> >>> +#define I915_PAGE_PRESENT BIT_ULL(0) >>> +#define I915_PAGE_RW BIT_ULL(1) >>> + >>> #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) >>> #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) >>> #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) >>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c >>> index 53d0cb327539..8f6a055854f7 100644 >>> --- a/drivers/gpu/drm/i915/gvt/gtt.c >>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c >>> @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) >>> || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) >>> return (e->val64 != 0); >>> else >>> - return (e->val64 & _PAGE_PRESENT); >>> + return (e->val64 & I915_PAGE_PRESENT); >>> } >>> >>> static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) >>> { >>> - e->val64 &= ~_PAGE_PRESENT; >>> + e->val64 &= ~I915_PAGE_PRESENT; >>> } >>> >>> static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) >>> { >>> - e->val64 |= _PAGE_PRESENT; >>> + e->val64 |= I915_PAGE_PRESENT; >>> } >>> >>> static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) >>> @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, >>> /* The entry parameters like present/writeable/cache type >>> * set to the same as i915's scratch page tree. >>> */ >>> - se.val64 |= _PAGE_PRESENT | _PAGE_RW; >>> + se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW; >>> if (type == GTT_TYPE_PPGTT_PDE_PT) >>> se.val64 |= PPAT_CACHED; >>> >>> @@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) >>> offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; >>> for (idx = 0; idx < num_low; idx++) { >>> pte = mm->ggtt_mm.host_ggtt_aperture[idx]; >>> - if (pte & _PAGE_PRESENT) >>> + if (pte & I915_PAGE_PRESENT) >>> write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); >>> } >>> >>> @@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) >>> offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; >>> for (idx = 0; idx < num_hi; idx++) { >>> pte = mm->ggtt_mm.host_ggtt_hidden[idx]; >>> - if (pte & _PAGE_PRESENT) >>> + if (pte & I915_PAGE_PRESENT) >>> write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); >>> } >>> } >>> -- >>> 2.25.1 >>> >> -- >> Matt Roper >> Graphics Software Engineer >> VTT-OSGC Platform Enablement >> Intel Corporation >> (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 1:42 ` Michael Cheng @ 2021-11-13 1:47 ` Matt Roper 2021-11-13 16:22 ` Lucas De Marchi 0 siblings, 1 reply; 13+ messages in thread From: Matt Roper @ 2021-11-13 1:47 UTC (permalink / raw) To: Michael Cheng Cc: wayne.boyer, jani.nikula, intel-gfx, lucas.demarchi, siva.mullati On Fri, Nov 12, 2021 at 05:42:28PM -0800, Michael Cheng wrote: > Thanks for the feed back! I feel like using something name GEN6 or BYT for a > platform that's not GEN6 or BYT could be a bit confusing, that's why we > decided to go with something more generic. I do agree I need to cite the > bspec more. Ill wait for more feedback before I send a new revision out. In general that's the pattern that i915 tries to use --- we name functions, macros, etc. after the first platform or generation that they apply to and then continue to use them on all subsequent platforms until the hardware changes again and we need a new version. E.g., we're still calling "gen8_ppgtt_create" to create our PPGTTs on the latest platforms, even though we're well past gen8 at this point. Matt > > On 2021-11-12 5:31 p.m., Matt Roper wrote: > > On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote: > > > On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote: > > > > Certain functions within i915 uses macros that are defined for > > > > specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT > > > > (Some architectures don't even have these macros defined, like ARM64). > > > > > > > > Instead of re-using bits defined for the CPU, we should use bits > > > > defined for i915. This patch introduces two new macros, > > > > I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to > > > > replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. > > > On older platforms we already had our own definition of GEN6_PTE_VALID > > > (the spec uses "present" and "valid" interchangeably) which we were > > > using to encode our ggtt ptes up through HSW; it might be better to go > > > back to using that rather than adding a new define. > > > > > > It looks like BYT is when the writable bit showed up, and we did add a > > > new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we > > > switched over to using the CPU page table flags instead and never used > > > it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE > > > as well. > > Okay, I should have looked at the rest of the series before reviewing > > the first patch; it looks like your next two patches replace > > GEN6_PTE_VALID and BYT_PTE_WRITEABLE with the new definitions here. I > > still think it might be preferable to reuse the existing macros (which > > also help clarify the platforms that those bits first showed up in the > > PTE on) rather than replacing them with new macros, but I don't feel > > super strongly about it if other reviewers feel differently. > > > > > > Matt > > > > > > Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the > > > > same throughout the generations. > > > This last sentence seems a bit confusing --- it's true that bit 0 has > > > always been a present/valid flag, but bit 1 wasn't a writable bit until > > > BYT; there just wasn't a writable bit at all (e.g., bspec page 229). > > > > > > It might be worth tossing a few bspec references on the commit message > > > here, just for future reference. E.g., > > > > > > Bspec: 253, 45039 > > > > > > > > > Matt > > > > > > > Signed-off-by: Michael Cheng <michael.cheng@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- > > > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- > > > > drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ > > > > drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ > > > > 4 files changed, 13 insertions(+), 10 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > > > index 9966e9dc5218..f89b50ffc286 100644 > > > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > > > > @@ -18,7 +18,7 @@ > > > > static u64 gen8_pde_encode(const dma_addr_t addr, > > > > const enum i915_cache_level level) > > > > { > > > > - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; > > > > + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > > > if (level != I915_CACHE_NONE) > > > > pde |= PPAT_CACHED_PDE; > > > > @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, > > > > enum i915_cache_level level, > > > > u32 flags) > > > > { > > > > - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; > > > > + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW; > > > > if (unlikely(flags & PTE_READ_ONLY)) > > > > - pte &= ~_PAGE_RW; > > > > + pte &= ~I915_PAGE_RW; > > > > if (flags & PTE_LM) > > > > pte |= GEN12_PPGTT_PTE_LM; > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > > > index 1fb4a03d7ac3..3f8e1ee0fbfa 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > > > @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, > > > > enum i915_cache_level level, > > > > u32 flags) > > > > { > > > > - gen8_pte_t pte = addr | _PAGE_PRESENT; > > > > + gen8_pte_t pte = addr | I915_PAGE_PRESENT; > > > > if (flags & PTE_LM) > > > > pte |= GEN12_GGTT_PTE_LM; > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > > > > index dfeaef680aac..fba9c0c18f4a 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > > > > @@ -39,6 +39,9 @@ > > > > #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ > > > > +#define I915_PAGE_PRESENT BIT_ULL(0) > > > > +#define I915_PAGE_RW BIT_ULL(1) > > > > + > > > > #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) > > > > #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) > > > > #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) > > > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c > > > > index 53d0cb327539..8f6a055854f7 100644 > > > > --- a/drivers/gpu/drm/i915/gvt/gtt.c > > > > +++ b/drivers/gpu/drm/i915/gvt/gtt.c > > > > @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) > > > > || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) > > > > return (e->val64 != 0); > > > > else > > > > - return (e->val64 & _PAGE_PRESENT); > > > > + return (e->val64 & I915_PAGE_PRESENT); > > > > } > > > > static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) > > > > { > > > > - e->val64 &= ~_PAGE_PRESENT; > > > > + e->val64 &= ~I915_PAGE_PRESENT; > > > > } > > > > static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) > > > > { > > > > - e->val64 |= _PAGE_PRESENT; > > > > + e->val64 |= I915_PAGE_PRESENT; > > > > } > > > > static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) > > > > @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, > > > > /* The entry parameters like present/writeable/cache type > > > > * set to the same as i915's scratch page tree. > > > > */ > > > > - se.val64 |= _PAGE_PRESENT | _PAGE_RW; > > > > + se.val64 |= I915_PAGE_PRESENT | I915_PAGE_RW; > > > > if (type == GTT_TYPE_PPGTT_PDE_PT) > > > > se.val64 |= PPAT_CACHED; > > > > @@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > > > > offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; > > > > for (idx = 0; idx < num_low; idx++) { > > > > pte = mm->ggtt_mm.host_ggtt_aperture[idx]; > > > > - if (pte & _PAGE_PRESENT) > > > > + if (pte & I915_PAGE_PRESENT) > > > > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > > > > } > > > > @@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) > > > > offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; > > > > for (idx = 0; idx < num_hi; idx++) { > > > > pte = mm->ggtt_mm.host_ggtt_hidden[idx]; > > > > - if (pte & _PAGE_PRESENT) > > > > + if (pte & I915_PAGE_PRESENT) > > > > write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); > > > > } > > > > } > > > > -- > > > > 2.25.1 > > > > > > > -- > > > Matt Roper > > > Graphics Software Engineer > > > VTT-OSGC Platform Enablement > > > Intel Corporation > > > (916) 356-2795 -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 1:47 ` Matt Roper @ 2021-11-13 16:22 ` Lucas De Marchi 2021-11-17 22:29 ` Lucas De Marchi 0 siblings, 1 reply; 13+ messages in thread From: Lucas De Marchi @ 2021-11-13 16:22 UTC (permalink / raw) To: Matt Roper Cc: Michael Cheng, wayne.boyer, jani.nikula, intel-gfx, siva.mullati On Fri, Nov 12, 2021 at 05:47:27PM -0800, Matt Roper wrote: >On Fri, Nov 12, 2021 at 05:42:28PM -0800, Michael Cheng wrote: >> Thanks for the feed back! I feel like using something name GEN6 or BYT for a >> platform that's not GEN6 or BYT could be a bit confusing, that's why we >> decided to go with something more generic. I do agree I need to cite the >> bspec more. Ill wait for more feedback before I send a new revision out. > >In general that's the pattern that i915 tries to use --- we name >functions, macros, etc. after the first platform or generation that they >apply to and then continue to use them on all subsequent platforms until >the hardware changes again and we need a new version. E.g., we're still >calling "gen8_ppgtt_create" to create our PPGTTs on the latest >platforms, even though we're well past gen8 at this point. I'd be totally ok with it if it was gen8 or gen6, but here the define is BYT. But if it's only me who find strange using the BYT_ define, I'm fine with it. Lucas De Marchi ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 16:22 ` Lucas De Marchi @ 2021-11-17 22:29 ` Lucas De Marchi 0 siblings, 0 replies; 13+ messages in thread From: Lucas De Marchi @ 2021-11-17 22:29 UTC (permalink / raw) To: Matt Roper Cc: jani.nikula, siva.mullati, intel-gfx, Michael Cheng, wayne.boyer On Sat, Nov 13, 2021 at 08:22:20AM -0800, Lucas De Marchi wrote: >On Fri, Nov 12, 2021 at 05:47:27PM -0800, Matt Roper wrote: >>On Fri, Nov 12, 2021 at 05:42:28PM -0800, Michael Cheng wrote: >>>Thanks for the feed back! I feel like using something name GEN6 or BYT for a >>>platform that's not GEN6 or BYT could be a bit confusing, that's why we >>>decided to go with something more generic. I do agree I need to cite the >>>bspec more. Ill wait for more feedback before I send a new revision out. >> >>In general that's the pattern that i915 tries to use --- we name >>functions, macros, etc. after the first platform or generation that they >>apply to and then continue to use them on all subsequent platforms until >>the hardware changes again and we need a new version. E.g., we're still >>calling "gen8_ppgtt_create" to create our PPGTTs on the latest >>platforms, even though we're well past gen8 at this point. > > >I'd be totally ok with it if it was gen8 or gen6, but here the define is >BYT. But if it's only me who find strange using the BYT_ define, I'm >fine with it. let's ignore that and go with the GEN6 + BYT defines. Please also Cc dri-devel since this touches gt/ code. thanks Lucas De Marchi ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE 2021-11-13 1:31 ` Matt Roper 2021-11-13 1:42 ` Michael Cheng @ 2021-11-13 16:20 ` Lucas De Marchi 1 sibling, 0 replies; 13+ messages in thread From: Lucas De Marchi @ 2021-11-13 16:20 UTC (permalink / raw) To: Matt Roper Cc: Michael Cheng, wayne.boyer, jani.nikula, intel-gfx, siva.mullati On Fri, Nov 12, 2021 at 05:31:46PM -0800, Matt Roper wrote: >On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote: >> On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote: >> > Certain functions within i915 uses macros that are defined for >> > specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT >> > (Some architectures don't even have these macros defined, like ARM64). >> > >> > Instead of re-using bits defined for the CPU, we should use bits >> > defined for i915. This patch introduces two new macros, >> > I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to >> > replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. >> >> On older platforms we already had our own definition of GEN6_PTE_VALID >> (the spec uses "present" and "valid" interchangeably) which we were >> using to encode our ggtt ptes up through HSW; it might be better to go >> back to using that rather than adding a new define. >> >> It looks like BYT is when the writable bit showed up, and we did add a >> new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we >> switched over to using the CPU page table flags instead and never used >> it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE >> as well. > >Okay, I should have looked at the rest of the series before reviewing >the first patch; it looks like your next two patches replace >GEN6_PTE_VALID and BYT_PTE_WRITEABLE with the new definitions here. I >still think it might be preferable to reuse the existing macros (which >also help clarify the platforms that those bits first showed up in the >PTE on) rather than replacing them with new macros, but I don't feel >super strongly about it if other reviewers feel differently. I think it deserves a I915_ particularly because of the RW definition. To me it's always suspicious when code spanning for several platforms use a definition for BYT or CHV, because those are usually the one that deviates from the norm, not the ones that dictate new behavior going forward. Lucas De Marchi ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v4 2/3] drm/i915: Clean up GEN6 page valid macros 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE Michael Cheng @ 2021-11-11 0:45 ` Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Clean up BYT_PTE_WRITEABLE Michael Cheng ` (2 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Michael Cheng @ 2021-11-11 0:45 UTC (permalink / raw) To: intel-gfx Cc: michael.cheng, wayne.boyer, jani.nikula, lucas.demarchi, siva.mullati GEN6_PTE_VALID and GEN6_PDE_VALID both checks the 0 bit to see weather the mapping of the corresponding graphics memory page is valid. Instead of having two different macros doing the same thing, this patch replaces the macros with I915_PAGE_PRESENT. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +++++----- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 -- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index ae693bf88ef0..aeefe70a0e83 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -19,7 +19,7 @@ static void gen6_write_pde(const struct gen6_ppgtt *ppgtt, dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]); /* Caller needs to make sure the write completes if necessary */ - iowrite32(GEN6_PDE_ADDR_ENCODE(addr) | GEN6_PDE_VALID, + iowrite32(GEN6_PDE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT, ppgtt->pd_addr + pde); } diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 3f8e1ee0fbfa..995a1c47cd35 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -979,7 +979,7 @@ static u64 snb_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID; + gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; switch (level) { case I915_CACHE_L3_LLC: @@ -1000,7 +1000,7 @@ static u64 ivb_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID; + gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; switch (level) { case I915_CACHE_L3_LLC: @@ -1023,7 +1023,7 @@ static u64 byt_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID; + gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; if (!(flags & PTE_READ_ONLY)) pte |= BYT_PTE_WRITEABLE; @@ -1038,7 +1038,7 @@ static u64 hsw_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID; + gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; if (level != I915_CACHE_NONE) pte |= HSW_WB_LLC_AGE3; @@ -1050,7 +1050,7 @@ static u64 iris_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID; + gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; switch (level) { case I915_CACHE_NONE: diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index fba9c0c18f4a..884bc250260c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -74,13 +74,11 @@ typedef u64 gen8_pte_t; #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) #define GEN6_PTE_CACHE_LLC (2 << 1) #define GEN6_PTE_UNCACHED (1 << 1) -#define GEN6_PTE_VALID REG_BIT(0) #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) #define GEN6_PD_ALIGN (PAGE_SIZE * 16) #define GEN6_PDE_SHIFT 22 -#define GEN6_PDE_VALID REG_BIT(0) #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) #define GEN7_PTE_CACHE_L3_LLC (3 << 1) -- 2.25.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v4 3/3] drm/i915: Clean up BYT_PTE_WRITEABLE 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 2/3] drm/i915: Clean up GEN6 page valid macros Michael Cheng @ 2021-11-11 0:45 ` Michael Cheng 2021-11-11 1:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev4) Patchwork 2021-11-11 3:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Michael Cheng @ 2021-11-11 0:45 UTC (permalink / raw) To: intel-gfx Cc: michael.cheng, wayne.boyer, jani.nikula, lucas.demarchi, siva.mullati Removes BYT_PTE_WRITEABLE and replace it with I915_PAGE_RW. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 995a1c47cd35..ac4ad82fdcdd 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -1026,7 +1026,7 @@ static u64 byt_pte_encode(dma_addr_t addr, gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; if (!(flags & PTE_READ_ONLY)) - pte |= BYT_PTE_WRITEABLE; + pte |= I915_PAGE_RW; if (level != I915_CACHE_NONE) pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 884bc250260c..0eb77e2fb45f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -84,7 +84,6 @@ typedef u64 gen8_pte_t; #define GEN7_PTE_CACHE_L3_LLC (3 << 1) #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) -#define BYT_PTE_WRITEABLE REG_BIT(1) #define GEN12_PPGTT_PTE_LM BIT_ULL(11) -- 2.25.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev4) 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng ` (2 preceding siblings ...) 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Clean up BYT_PTE_WRITEABLE Michael Cheng @ 2021-11-11 1:30 ` Patchwork 2021-11-11 3:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-11-11 1:30 UTC (permalink / raw) To: Michael Cheng; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4848 bytes --] == Series Details == Series: Introduce new i915 macros for checking PTEs (rev4) URL : https://patchwork.freedesktop.org/series/96679/ State : success == Summary == CI Bug Log - changes from CI_DRM_10864 -> Patchwork_21557 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/index.html Participating hosts (38 -> 35) ------------------------------ Additional (2): fi-kbl-soraka fi-pnv-d510 Missing (5): bat-dg1-6 fi-tgl-u2 bat-dg1-5 fi-bsw-cyan bat-adlp-4 Known issues ------------ Here are the changes found in Patchwork_21557 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@i915_selftest@live@execlists: - fi-bsw-nick: [PASS][5] -> [INCOMPLETE][6] ([i915#2940]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/fi-bsw-nick/igt@i915_selftest@live@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-bsw-nick/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510: NOTRUN -> [SKIP][10] ([fdo#109271]) +53 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-pnv-d510/igt@prime_vgem@basic-userptr.html #### Possible fixes #### * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [DMESG-WARN][11] ([i915#295]) -> [PASS][12] +12 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#4290]: https://gitlab.freedesktop.org/drm/intel/issues/4290 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes ------------- * Linux: CI_DRM_10864 -> Patchwork_21557 CI-20190529: 20190529 CI_DRM_10864: c3b05d080332576b2bc1d05201eae563401eb3ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6277: 7201d343fced07a1951feea119480d55bce787e4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21557: 590e6b6a1ecad6560703f401f5d267f4943c25b0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 590e6b6a1eca drm/i915: Clean up BYT_PTE_WRITEABLE 476ccbe1547c drm/i915: Clean up GEN6 page valid macros c6a7accc2eca drm/i915: Introduce new macros for i915 PTE == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/index.html [-- Attachment #2: Type: text/html, Size: 5884 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce new i915 macros for checking PTEs (rev4) 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng ` (3 preceding siblings ...) 2021-11-11 1:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev4) Patchwork @ 2021-11-11 3:20 ` Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-11-11 3:20 UTC (permalink / raw) To: Michael Cheng; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30273 bytes --] == Series Details == Series: Introduce new i915 macros for checking PTEs (rev4) URL : https://patchwork.freedesktop.org/series/96679/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10864_full -> Patchwork_21557_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21557_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21557_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21557_full: ### IGT changes ### #### Possible regressions #### * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-tglb8/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb8/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html * igt@perf@i915-ref-count: - shard-iclb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@perf@i915-ref-count.html - shard-tglb: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-tglb1/igt@perf@i915-ref-count.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb6/igt@perf@i915-ref-count.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_color@pipe-a-legacy-gamma-reset: - {shard-rkl}: [SKIP][6] ([i915#1849] / [i915#4070]) -> ([SKIP][7], [PASS][8]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_color@pipe-a-legacy-gamma-reset.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_color@pipe-a-legacy-gamma-reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_color@pipe-a-legacy-gamma-reset.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement: - {shard-rkl}: [SKIP][9] ([fdo#112022] / [i915#4070]) -> ([SKIP][10], [PASS][11]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html * igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen: - {shard-rkl}: NOTRUN -> ([SKIP][12], [SKIP][13]) ([fdo#112022] / [i915#4070]) +10 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen: - {shard-rkl}: ([SKIP][14], [SKIP][15]) ([fdo#112022] / [i915#4070]) -> [SKIP][16] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding: - {shard-rkl}: [PASS][17] -> ([SKIP][18], [PASS][19]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement: - {shard-rkl}: ([SKIP][20], [SKIP][21]) ([fdo#112022] / [i915#4070]) -> ([SKIP][22], [SKIP][23]) ([i915#3359] / [i915#4070]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement.html * igt@kms_cursor_crc@pipe-b-cursor-dpms: - {shard-rkl}: [SKIP][24] ([fdo#112022] / [i915#4070]) -> [SKIP][25] +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-dpms.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-dpms.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen: - {shard-rkl}: [SKIP][26] ([fdo#112022] / [i915#4070]) -> ([SKIP][27], [SKIP][28]) ([i915#4070]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding: - {shard-rkl}: [SKIP][29] -> ([SKIP][30], [SKIP][31]) ([fdo#112022] / [i915#4070]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-2/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html * igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge: - {shard-rkl}: NOTRUN -> ([SKIP][32], [SKIP][33]) ([i915#1849] / [i915#4070]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled: - {shard-rkl}: [SKIP][34] ([fdo#111314]) -> ([PASS][35], [SKIP][36]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled: - {shard-rkl}: NOTRUN -> ([SKIP][37], [SKIP][38]) ([fdo#111314]) +4 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - {shard-rkl}: NOTRUN -> ([SKIP][39], [SKIP][40]) ([i915#1849]) +11 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - {shard-rkl}: [SKIP][41] ([i915#1849]) -> [SKIP][42] +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - {shard-rkl}: [PASS][43] -> [SKIP][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt: - {shard-rkl}: ([SKIP][45], [SKIP][46]) ([fdo#111825]) -> [SKIP][47] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render: - {shard-rkl}: ([SKIP][48], [SKIP][49]) ([i915#1849]) -> [SKIP][50] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt: - {shard-rkl}: [SKIP][51] ([fdo#111825] / [i915#1825]) -> [SKIP][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move: - {shard-rkl}: ([SKIP][53], [SKIP][54]) ([i915#1849]) -> ([SKIP][55], [SKIP][56]) ([fdo#111825] / [i915#1825]) +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc: - {shard-rkl}: [SKIP][57] ([i915#1849]) -> ([SKIP][58], [SKIP][59]) ([fdo#111825] / [i915#1825]) +6 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt: - {shard-rkl}: NOTRUN -> [SKIP][60] +18 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - {shard-rkl}: [SKIP][61] -> ([SKIP][62], [SKIP][63]) ([i915#1849]) +3 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu: - {shard-rkl}: [SKIP][64] ([i915#1849]) -> ([PASS][65], [SKIP][66]) +3 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite: - {shard-rkl}: ([SKIP][67], [SKIP][68]) ([i915#1849]) -> ([SKIP][69], [PASS][70]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - {shard-rkl}: NOTRUN -> ([SKIP][71], [SKIP][72]) ([i915#4070]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - {shard-rkl}: [SKIP][73] ([i915#1849] / [i915#4070]) -> [SKIP][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant: - {shard-rkl}: ([SKIP][75], [SKIP][76]) ([i915#1849] / [i915#4070]) -> [SKIP][77] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-4/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html * igt@kms_plane_lowres@pipe-b-tiling-y: - {shard-rkl}: [SKIP][78] ([i915#1849]) -> ([SKIP][79], [SKIP][80]) ([i915#3536]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-rkl-1/igt@kms_plane_lowres@pipe-b-tiling-y.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-6/igt@kms_plane_lowres@pipe-b-tiling-y.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@kms_plane_lowres@pipe-b-tiling-y.html * igt@perf@i915-ref-count: - {shard-rkl}: NOTRUN -> ([PASS][81], [FAIL][82]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-4/igt@perf@i915-ref-count.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-rkl-1/igt@perf@i915-ref-count.html Known issues ------------ Here are the changes found in Patchwork_21557_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@psr2: - shard-iclb: [PASS][83] -> [SKIP][84] ([i915#658]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-iclb2/igt@feature_discovery@psr2.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb4/igt@feature_discovery@psr2.html * igt@gem_eio@in-flight-contexts-1us: - shard-tglb: NOTRUN -> [TIMEOUT][85] ([i915#3063]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][86] -> [INCOMPLETE][87] ([i915#2369]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-skl8/igt@gem_exec_capture@pi@rcs0.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl7/igt@gem_exec_capture@pi@rcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +355 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl3/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-kbl: NOTRUN -> [FAIL][89] ([i915#2842]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl7/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][90] -> [FAIL][91] ([i915#2842]) +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][92] ([i915#2842]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][93] -> [FAIL][94] ([i915#2842]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][95] -> [FAIL][96] ([i915#2842]) +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-kbl: [PASS][97] -> [SKIP][98] ([fdo#109271]) +1 similar issue [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-kbl4/igt@gem_exec_fair@basic-sync@rcs0.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl6/igt@gem_exec_fair@basic-sync@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][99] -> [FAIL][100] ([i915#2849]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][101] ([fdo#112283]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb5/igt@gem_exec_params@secure-non-master.html * igt@gem_exec_schedule@submit-early-slice@vcs0: - shard-skl: [PASS][102] -> [INCOMPLETE][103] ([i915#3797]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-skl9/igt@gem_exec_schedule@submit-early-slice@vcs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl3/igt@gem_exec_schedule@submit-early-slice@vcs0.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][104] -> [DMESG-WARN][105] ([i915#180]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-apl3/igt@gem_exec_suspend@basic-s3.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl8/igt@gem_exec_suspend@basic-s3.html * igt@gem_exec_whisper@basic-normal-all: - shard-glk: [PASS][106] -> [DMESG-WARN][107] ([i915#118]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-glk3/igt@gem_exec_whisper@basic-normal-all.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-glk7/igt@gem_exec_whisper@basic-normal-all.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][108] -> [SKIP][109] ([i915#2190]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-tglb3/igt@gem_huc_copy@huc-copy.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb6/igt@gem_huc_copy@huc-copy.html - shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2190]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl6/igt@gem_huc_copy@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][111] ([i915#2658]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl7/igt@gem_pread@exhaustion.html * igt@gem_pxp@regular-baseline-src-copy-readible: - shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271]) +73 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl4/igt@gem_pxp@regular-baseline-src-copy-readible.html * igt@gem_pxp@reject-modify-context-protection-on: - shard-iclb: NOTRUN -> [SKIP][113] ([i915#4270]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@gem_pxp@reject-modify-context-protection-on.html * igt@gem_render_copy@y-tiled-to-vebox-x-tiled: - shard-iclb: NOTRUN -> [SKIP][114] ([i915#768]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html * igt@gem_userptr_blits@dmabuf-sync: - shard-skl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#3323]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][116] ([i915#3002]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl2/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@unsync-overlap: - shard-tglb: NOTRUN -> [SKIP][117] ([i915#3297]) +1 similar issue [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb1/igt@gem_userptr_blits@unsync-overlap.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][118] ([i915#3318]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl2/igt@gem_userptr_blits@vma-merge.html * igt@gen9_exec_parse@basic-rejected-ctx-param: - shard-iclb: NOTRUN -> [SKIP][119] ([i915#2856]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@gen9_exec_parse@basic-rejected-ctx-param.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][120] ([i915#2856]) +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb1/igt@gen9_exec_parse@bb-large.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-tglb: NOTRUN -> [SKIP][121] ([fdo#109506] / [i915#2411]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_query@query-topology-known-pci-ids: - shard-tglb: NOTRUN -> [SKIP][122] ([fdo#109303]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@i915_query@query-topology-known-pci-ids.html * igt@i915_suspend@forcewake: - shard-kbl: NOTRUN -> [DMESG-WARN][123] ([i915#180]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl7/igt@i915_suspend@forcewake.html - shard-skl: [PASS][124] -> [INCOMPLETE][125] ([i915#636]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10864/shard-skl10/igt@i915_suspend@forcewake.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl8/igt@i915_suspend@forcewake.html * igt@kms_async_flips@crc: - shard-skl: NOTRUN -> [FAIL][126] ([i915#4272]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl1/igt@kms_async_flips@crc.html * igt@kms_atomic@plane-primary-overlay-mutable-zpos: - shard-tglb: NOTRUN -> [SKIP][127] ([i915#404]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][128] ([i915#3743]) +3 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@y-tiled-64bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][129] ([fdo#111614]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb1/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-8bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][130] ([fdo#110725] / [fdo#111614]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#3777]) +2 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-skl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#3777]) +3 similar issues [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-tglb: NOTRUN -> [SKIP][133] ([fdo#111615]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: - shard-apl: NOTRUN -> [SKIP][134] ([fdo#109271]) +176 similar issues [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][135] ([fdo#110723]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_joiner@2x-modeset: - shard-iclb: NOTRUN -> [SKIP][136] ([i915#2705]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb6/igt@kms_big_joiner@2x-modeset.html * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#3886]) +3 similar issues [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-apl2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#3886]) +1 similar issue [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-kbl4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#3886]) +18 similar issues [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-skl9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][140] ([fdo#109278] / [i915#3886]) +1 similar issue [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-iclb5/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][141] ([i915#3689]) +6 similar issues [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-hpd-for-each-pipe: - shard-tglb: NOTRUN -> [SKIP][142] ([fdo#109284] / [fdo#111827]) +3 similar issues [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/shard-tglb3/igt@kms_chamelium@dp-hpd-for-each-pipe.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21557/index.html [-- Attachment #2: Type: text/html, Size: 33017 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-11-17 22:29 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-11-11 0:45 [Intel-gfx] [PATCH v4 0/3] Introduce new i915 macros for checking PTEs Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE Michael Cheng 2021-11-13 1:28 ` Matt Roper 2021-11-13 1:31 ` Matt Roper 2021-11-13 1:42 ` Michael Cheng 2021-11-13 1:47 ` Matt Roper 2021-11-13 16:22 ` Lucas De Marchi 2021-11-17 22:29 ` Lucas De Marchi 2021-11-13 16:20 ` Lucas De Marchi 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 2/3] drm/i915: Clean up GEN6 page valid macros Michael Cheng 2021-11-11 0:45 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Clean up BYT_PTE_WRITEABLE Michael Cheng 2021-11-11 1:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce new i915 macros for checking PTEs (rev4) Patchwork 2021-11-11 3:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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