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* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-10 14:37 Nemesa Garg
  2024-09-10 16:36 ` Pottumuttu, Sai Teja
                   ` (8 more replies)
  0 siblings, 9 replies; 32+ messages in thread
From: Nemesa Garg @ 2024-09-10 14:37 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..4afe808f128c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,13 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format != DRM_FORMAT_NV12)
+			hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-30 11:21 Nemesa Garg
  2024-10-16  7:24 ` Nemesa Garg
  0 siblings, 1 reply; 32+ messages in thread
From: Nemesa Garg @ 2024-09-30 11:21 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for even xsize for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

v5: Replace IS_LUNARLAKE with display version.
    Resolve nitpicks[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..e3401a4f7992 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+		/*
+		 *  Wa_16023981245 for display version 20.
+		 *  Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12 &&
+		    src_x % 2 != 0 && src_w % 2 == 0)
+			return -EINVAL;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-25 12:25 Nemesa Garg
  2024-09-25 13:09 ` Jani Nikula
  2024-09-25 13:57 ` Pottumuttu, Sai Teja
  0 siblings, 2 replies; 32+ messages in thread
From: Nemesa Garg @ 2024-09-25 12:25 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..dfe795b8e917 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,16 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format == DRM_FORMAT_NV12
+		    && src_w % 2 == 0)
+			return -EINVAL;
+
+		hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-06  7:01 Nemesa Garg
  2024-09-06  8:51 ` Jani Nikula
  0 siblings, 1 reply; 32+ messages in thread
From: Nemesa Garg @ 2024-09-06  7:01 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    | 16 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display_wa.h  |  2 ++
 drivers/gpu/drm/xe/display/xe_display_wa.c       |  5 +++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..9b17321f3477 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -47,11 +47,13 @@
 #include "intel_display_rps.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_fb.h"
 #include "intel_fb_pin.h"
 #include "skl_scaler.h"
 #include "skl_watermark.h"
 
+
 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
 				    struct intel_plane *plane)
 {
@@ -1029,8 +1031,18 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
-		vsub = 1;
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (intel_display_needs_wa_16023981245(i915) &&
+		    fb->format->format == DRM_FORMAT_NV12) {
+			vsub = 1;
+		} else {
+			hsub = 1;
+			vsub = 1;
+		}
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index be644ab6ae00..9be35a751503 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -14,8 +14,10 @@ void intel_display_wa_apply(struct drm_i915_private *i915);
 
 #ifdef I915
 static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; }
+static inline bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915) { return false; }
 #else
 bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915);
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915);
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c
index 68e3d1959ad6..fde4e09589a3 100644
--- a/drivers/gpu/drm/xe/display/xe_display_wa.c
+++ b/drivers/gpu/drm/xe/display/xe_display_wa.c
@@ -14,3 +14,8 @@ bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915)
 {
 	return XE_WA(xe_root_mmio_gt(i915), 16023588340);
 }
+
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915)
+{
+	return XE_WA(xe_root_mmio_gt(i915), 22019338487_display);
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-07-24 13:06 Nemesa Garg
  2024-07-24 17:01 ` Kandpal, Suraj
  0 siblings, 1 reply; 32+ messages in thread
From: Nemesa Garg @ 2024-07-24 13:06 UTC (permalink / raw)
  To: intel-xe; +Cc: juha-pekka.heikkila, uma.shankar, Nemesa Garg

Underrun/corruption issue is seen for NV12 format
for odd panning on LNL due to hardware bug.
Disable the format.

HSD: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..f927e6a0b28b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Disable odd pan for NV12 format.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12)
+			return 0;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 32+ messages in thread
end of thread, other threads:[~2024-10-18 17:36 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-10 14:37 [PATCH] drm/i915/display: Workaround for odd panning for planar yuv Nemesa Garg
2024-09-10 16:36 ` Pottumuttu, Sai Teja
2024-09-25  7:49   ` Garg, Nemesa
2024-09-10 17:02 ` ✓ CI.Patch_applied: success for drm/i915/display: Workaround for odd panning for planar yuv (rev3) Patchwork
2024-09-10 17:03 ` ✓ CI.checkpatch: " Patchwork
2024-09-10 17:04 ` ✓ CI.KUnit: " Patchwork
2024-09-10 17:16 ` ✓ CI.Build: " Patchwork
2024-09-10 17:18 ` ✓ CI.Hooks: " Patchwork
2024-09-10 17:19 ` ✗ CI.checksparse: warning " Patchwork
2024-09-10 18:02 ` ✗ CI.BAT: failure " Patchwork
2024-09-10 21:08 ` ✗ CI.FULL: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-09-30 11:21 [PATCH] drm/i915/display: Workaround for odd panning for planar yuv Nemesa Garg
2024-10-16  7:24 ` Nemesa Garg
2024-10-17  8:05   ` Kandpal, Suraj
2024-10-17 16:53     ` Pottumuttu, Sai Teja
2024-10-18  5:04       ` Garg, Nemesa
2024-10-18  5:05         ` Garg, Nemesa
2024-10-18  5:44         ` Chauhan, Shekhar
2024-10-18 17:36           ` Matt Roper
2024-09-25 12:25 Nemesa Garg
2024-09-25 13:09 ` Jani Nikula
2024-09-25 13:57 ` Pottumuttu, Sai Teja
2024-09-06  7:01 Nemesa Garg
2024-09-06  8:51 ` Jani Nikula
2024-09-06  9:07   ` Jani Nikula
2024-09-06 13:51   ` Lucas De Marchi
2024-09-06 14:18     ` Jani Nikula
2024-09-06 15:33       ` Rodrigo Vivi
2024-07-24 13:06 Nemesa Garg
2024-07-24 17:01 ` Kandpal, Suraj
2024-07-25  2:59   ` Kandpal, Suraj
2024-08-12  5:18     ` Garg, Nemesa

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