* [CI 01/17] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 02/17] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
` (20 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Xe3p_LPD (display version 35) is similar to Xe2_LPD with respect to the
features described by struct intel_display_device_info, so reuse its
device descriptor.
v2:
- Add reference to Bspec 74201. (Shekhar)
Bspec: 74201, 74304
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-1-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 328447a5e5e8..1170afaa8680 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1507,6 +1507,7 @@ static const struct {
{ 20, 0, &xe2_lpd_display },
{ 30, 0, &xe2_lpd_display },
{ 30, 2, &wcl_display },
+ { 35, 0, &xe2_lpd_display },
};
static const struct intel_display_device_info *
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 02/17] drm/i915/xe3p_lpd: Drop north display reset option programming
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-11-05 14:06 ` [CI 01/17] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 03/17] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
` (19 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Matt Roper <matthew.d.roper@intel.com>
The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option
programming is no longer necessary during display init.
Bspec: 68846, 69137
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-2-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fbfa823b6dce..74fcd9cfe911 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1438,6 +1438,9 @@ static void intel_pch_reset_handshake(struct intel_display *display,
i915_reg_t reg;
u32 reset_bits;
+ if (DISPLAY_VER(display) >= 35)
+ return;
+
if (display->platform.ivybridge) {
reg = GEN7_MSG_CTL;
reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 03/17] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-11-05 14:06 ` [CI 01/17] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-11-05 14:06 ` [CI 02/17] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 04/17] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
` (18 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Looking at the current if-ladder in intel_bw_init_hw(), we see that
Xe2_HPD contains two entries, differing only for ECC memories. Let's
improve readability by using braces and allowing adding extra conditions
for each case.
v2:
- Tweaked commit message, since we are not going to add the ECC case
for Xe3p_LPD anymore.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-3-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 29 +++++++++++++------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f97ccc1a96a7..bf37d7a9732e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,29 +805,30 @@ void intel_bw_init_hw(struct intel_display *display)
if (!HAS_DISPLAY(display))
return;
- if (DISPLAY_VERx100(display) >= 3002)
+ if (DISPLAY_VERx100(display) >= 3002) {
tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
- else if (DISPLAY_VER(display) >= 30)
+ } else if (DISPLAY_VER(display) >= 30) {
tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
- else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
- dram_info->type == INTEL_DRAM_GDDR_ECC)
- xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
- else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
- xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
- else if (DISPLAY_VER(display) >= 14)
+ } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+ if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+ xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
+ else
+ xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+ } else if (DISPLAY_VER(display) >= 14) {
tgl_get_bw_info(display, dram_info, &mtl_sa_info);
- else if (display->platform.dg2)
+ } else if (display->platform.dg2) {
dg2_get_bw_info(display);
- else if (display->platform.alderlake_p)
+ } else if (display->platform.alderlake_p) {
tgl_get_bw_info(display, dram_info, &adlp_sa_info);
- else if (display->platform.alderlake_s)
+ } else if (display->platform.alderlake_s) {
tgl_get_bw_info(display, dram_info, &adls_sa_info);
- else if (display->platform.rocketlake)
+ } else if (display->platform.rocketlake) {
tgl_get_bw_info(display, dram_info, &rkl_sa_info);
- else if (DISPLAY_VER(display) == 12)
+ } else if (DISPLAY_VER(display) == 12) {
tgl_get_bw_info(display, dram_info, &tgl_sa_info);
- else if (DISPLAY_VER(display) == 11)
+ } else if (DISPLAY_VER(display) == 11) {
icl_get_bw_info(display, dram_info, &icl_sa_info);
+ }
}
static unsigned int intel_bw_num_active_planes(struct intel_display *display,
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 04/17] drm/i915/xe3p_lpd: Update bandwidth parameters
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (2 preceding siblings ...)
2025-11-05 14:06 ` [CI 03/17] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 05/17] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
` (17 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Matt Atwood <matthew.s.atwood@intel.com>
Bandwidth parameters for Xe3p_LPD are the same as for Xe3_LPD. Re-use
them.
Since handling for Xe3_LPD version 30.02 is more like a special case,
let's use a "== 3002" check for it inside the ">= 30" branch instead of
adding a new branch for version 35. That allows us to re-use the ">=
30" branch for Xe3p_LPD.
v2:
- Do not have a special case for ecc_impacting_de_bw, since there are
no specific instructions in Bspec for this scenario. (Matt Roper)
v3:
- Re-use the ">= 30" branch in the if-ladder. (Matt Roper)
Bspec: 68859
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-4-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bf37d7a9732e..919b25a5fbac 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,10 +805,11 @@ void intel_bw_init_hw(struct intel_display *display)
if (!HAS_DISPLAY(display))
return;
- if (DISPLAY_VERx100(display) >= 3002) {
- tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
- } else if (DISPLAY_VER(display) >= 30) {
- tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+ if (DISPLAY_VER(display) >= 30) {
+ if (DISPLAY_VERx100(display) == 3002)
+ tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
+ else
+ tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
if (dram_info->type == INTEL_DRAM_GDDR_ECC)
xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 05/17] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (3 preceding siblings ...)
2025-11-05 14:06 ` [CI 04/17] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 06/17] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
` (16 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
On Xe3p_LPD, the dbuf blocks fields of different registers are now
documented as 13-bit fields. The dbuf isn't really large enough to need
the 13th bit, but let's go ahead and update the definition now just in
case some new display IP in future ends up needing the larger size. The
extra bit is an unused bit in previous display versions, so we can
safely just extend the existing definition.
Bspec: 69847, 69880, 72053
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-5-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
.../gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7c944d3ca855..6f815b231340 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -324,7 +324,7 @@
#define PLANE_WM_IGNORE_LINES REG_BIT(30)
#define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29)
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
-#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(12, 0)
#define _PLANE_WM_SAGV_1_A 0x70258
#define _PLANE_WM_SAGV_1_B 0x71258
@@ -375,10 +375,10 @@
_PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
_PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(28, 16)
#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START_MASK REG_GENMASK(12, 0)
#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_MIN_BUF_CFG_1_A 0x70274
@@ -389,9 +389,9 @@
_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
#define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31)
-#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(27, 16)
+#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(28, 16)
#define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
-#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(11, 0)
+#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(12, 0)
#define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
/* tgl+ */
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 06/17] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (4 preceding siblings ...)
2025-11-05 14:06 ` [CI 05/17] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 07/17] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
` (15 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Starting from Xe3p_LPD, linear surfaces also support horizontal flip.
Bspec: 68904
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-6-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ba1bf0bd4c55..bc55fafe9ce3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1748,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
}
if (rotation & DRM_MODE_REFLECT_X &&
- fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+ DISPLAY_VER(display) < 35) {
drm_dbg_kms(display->drm,
"[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n",
plane->base.base.id, plane->base.name);
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 07/17] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (5 preceding siblings ...)
2025-11-05 14:06 ` [CI 06/17] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 08/17] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
` (14 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
With Xe3p_LPD, the SKL_BOTTOM_COLOR_GAMMA_ENABLE and
SKL_BOTTOM_COLOR_CSC_ENABLE bits are being removed. Thus, we need not
set gamma_enable nor csc_enable in crtc_state.
Note that GAMMA_MODE.POST_CSC_GAMMA_ENABLE and CSC_MODE.ICL_CSC_ENABLE
are the documented alternatives for the bottom color bits being removed.
But as these suggested bits are being checked in state checker as part
of gamma_mode, csc_mode fields and as gamma_enable/csc_enable are not
being used anywhere else functionally post ICL, we need not set these
fields in crtc_state.
Bspec: 69734
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-7-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 1e97020e7304..a217a67ceb43 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1090,18 +1090,19 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- u32 tmp;
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
- tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
+ if (DISPLAY_VER(display) < 35) {
+ u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
- if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
- crtc_state->gamma_enable = true;
+ if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+ crtc_state->gamma_enable = true;
- if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
- crtc_state->csc_enable = true;
+ if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+ crtc_state->csc_enable = true;
+ }
}
static void skl_color_commit_arm(struct intel_dsb *dsb,
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 08/17] drm/i915/xe3p_lpd: Add CDCLK table
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (6 preceding siblings ...)
2025-11-05 14:06 ` [CI 07/17] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 09/17] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
` (13 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Add CDCLK table for Xe3p_LPD.
Just as with Xe3_LPD, we don't need to send voltage index info in the
PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.
With the new CDCLK table, we also need to update the maximum CDCLK value
returned by intel_update_max_cdclk().
Bspec: 68861, 68863
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-8-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 44 +++++++++++++++++++++-
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bdb42fcc4cb2..4d03cfefc72c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1535,6 +1535,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
+ { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
+ { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
+ {}
+};
+
static const int cdclk_squash_len = 16;
static int cdclk_squash_divider(u16 waveform)
@@ -3561,7 +3596,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
*/
void intel_update_max_cdclk(struct intel_display *display)
{
- if (DISPLAY_VERx100(display) >= 3002) {
+ if (DISPLAY_VER(display) >= 35) {
+ display->cdclk.max_cdclk_freq = 787200;
+ } else if (DISPLAY_VERx100(display) >= 3002) {
display->cdclk.max_cdclk_freq = 480000;
} else if (DISPLAY_VER(display) >= 30) {
display->cdclk.max_cdclk_freq = 691200;
@@ -3912,7 +3949,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct intel_display *display)
{
- if (DISPLAY_VER(display) >= 30) {
+ if (DISPLAY_VER(display) >= 35) {
+ display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+ display->cdclk.table = xe3p_lpd_cdclk_table;
+ } else if (DISPLAY_VER(display) >= 30) {
display->funcs.cdclk = &xe3lpd_cdclk_funcs;
display->cdclk.table = xe3lpd_cdclk_table;
} else if (DISPLAY_VER(display) >= 20) {
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 09/17] drm/i915/xe3p_lpd: Load DMC firmware
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (7 preceding siblings ...)
2025-11-05 14:06 ` [CI 08/17] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:06 ` [CI 10/17] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
` (12 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Load the DMC firmware for Xe3p_LPD.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-9-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 0bddb20a7c86..1b3a9b5608c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -127,6 +127,9 @@ static bool dmc_firmware_param_disabled(struct intel_display *display)
#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd)
+MODULE_FIRMWARE(XE3P_LPD_DMC_PATH);
+
#define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002)
MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH);
@@ -186,7 +189,11 @@ static const char *dmc_firmware_default(struct intel_display *display, u32 *size
{
const char *fw_path = NULL;
u32 max_fw_size = 0;
- if (DISPLAY_VERx100(display) == 3002) {
+
+ if (DISPLAY_VERx100(display) == 3500) {
+ fw_path = XE3P_LPD_DMC_PATH;
+ max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
+ } else if (DISPLAY_VERx100(display) == 3002) {
fw_path = XE3LPD_3002_DMC_PATH;
max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VERx100(display) == 3000) {
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 10/17] drm/i915/xe3p_lpd: Drop support for interlace mode
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (8 preceding siblings ...)
2025-11-05 14:06 ` [CI 09/17] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
@ 2025-11-05 14:06 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 11/17] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
` (11 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:06 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Interlace mode is officially removed from HW from Xe3p_LPD. The
register TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so
make sure we do not set/get these anymore.
Bspec: 69961, 70000
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-10-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 42ec78798666..25986bd8fbdd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2658,7 +2658,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
}
- if (DISPLAY_VER(display) >= 4)
+ if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
intel_de_write(display,
TRANS_VSYNCSHIFT(display, cpu_transcoder),
vsyncshift);
@@ -2799,7 +2799,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (DISPLAY_VER(display) == 2)
+ if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
return false;
if (DISPLAY_VER(display) >= 9 ||
@@ -3190,10 +3190,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
if (display->platform.haswell && crtc_state->dither)
val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= TRANSCONF_INTERLACE_IF_ID_ILK;
- else
- val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+ if (DISPLAY_VER(display) < 35) {
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ val |= TRANSCONF_INTERLACE_IF_ID_ILK;
+ else
+ val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+ }
if (display->platform.haswell &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 11/17] drm/i915/xe3p_lpd: Extend Wa_16025573575
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (9 preceding siblings ...)
2025-11-05 14:06 ` [CI 10/17] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 12/17] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
` (10 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Wa_16025573575 also applies to Xe3p_LPD, so let's include it in the IP
version checks.
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-11-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_wa.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index c528aaa679ca..e38e5e87877c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -49,7 +49,8 @@ void intel_display_wa_apply(struct intel_display *display)
*/
static bool intel_display_needs_wa_16025573575(struct intel_display *display)
{
- return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
+ return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
+ DISPLAY_VERx100(display) == 3500;
}
/*
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 12/17] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (10 preceding siblings ...)
2025-11-05 14:07 ` [CI 11/17] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 13/17] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
` (9 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
Disable support for odd panning and size in y direction when running on
display version 35 and using semiplanar formats.
Bspec: 68903
Signed-off-by: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-12-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 505c776c0585..5105e3278bc4 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -1051,6 +1051,9 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
DISPLAY_VERx100(display) == 3002) &&
src_x % 2 != 0)
hsub = 2;
+
+ if (DISPLAY_VER(display) == 35)
+ vsub = 2;
} else {
hsub = fb->format->hsub;
vsub = fb->format->vsub;
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 13/17] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (11 preceding siblings ...)
2025-11-05 14:07 ` [CI 12/17] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 14/17] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
` (8 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC
context data for pipes C and D, which are lost when their power wells
are disabled. As such, let's extend the condition for Xe3_LPD in
need_pipedmc_load_mmio() to also catch Xe3p_LPD.
Bspec: 68851
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-13-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1b3a9b5608c0..ca70cc4932df 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -718,11 +718,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
{
/*
- * PTL:
+ * Xe3_LPD/Xe3p_LPD:
* - pipe A/B DMC doesn't need save/restore
* - pipe C/D DMC is in PG0, needs manual save/restore
*/
- if (DISPLAY_VER(display) == 30)
+ if (IS_DISPLAY_VER(display, 30, 35))
return pipe >= PIPE_C;
/*
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 14/17] drm/i915/wm: don't use method1 in Xe3p_LPD onwards
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (12 preceding siblings ...)
2025-11-05 14:07 ` [CI 13/17] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 15/17] drm/i915/dram: Add field ecc_impacting_de_bw Gustavo Sousa
` (7 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Luca Coelho <luciano.coelho@intel.com>
Starting from display version 35, we don't need to use method1 to
calculate the watermark values anymore, so skip it.
Bspec: 68985
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-14-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 6d050408618c..c888b0896d89 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1812,6 +1812,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
if (wp->y_tiled) {
selected_result = max_fixed16(method2, wp->y_tile_minimum);
+ } else if (DISPLAY_VER(display) >= 35) {
+ selected_result = method2;
} else {
if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
wp->dbuf_block_size < 1) &&
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 15/17] drm/i915/dram: Add field ecc_impacting_de_bw
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (13 preceding siblings ...)
2025-11-05 14:07 ` [CI 14/17] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 16/17] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency Gustavo Sousa
` (6 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
that indicates whether the memory has enabled ECC that limits display
bandwidth. Add the field ecc_impacting_de_bw to struct dram_info to
contain that information and set it appropriately when probing for
memory info.
Currently there are no instructions in Bspec on how to handle that case,
so let's throw a warning if we ever find such a scenario.
v2:
- s/ecc_impacting_de/ecc_impacting_de_bw/ to be more specific. (Matt
Atwood)
- Add warning if ecc_impacting_de_bw is true, since we currently do
not have instructions on how to handle it. (Matt Roper)
v3:
- Check on ecc_impacting_de_bw for the warning only for Xe3p_LPD and
beyond.
- Change warning macro from drm_WARN_ON_ONCE() to drm_WARN_ON().
Bspec: 69131
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-15-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
4 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 919b25a5fbac..1f6461be50ef 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,6 +805,15 @@ void intel_bw_init_hw(struct intel_display *display)
if (!HAS_DISPLAY(display))
return;
+ /*
+ * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
+ * enabled that would impact display bandwidth. However, so far there
+ * are no instructions in Bspec on how to handle that case. Let's
+ * complain if we ever find such a scenario.
+ */
+ if (DISPLAY_VER(display) >= 35)
+ drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
+
if (DISPLAY_VER(display) >= 30) {
if (DISPLAY_VERx100(display) == 3002)
tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 354ef75ef6a5..5bf3b4ab2baa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1233,6 +1233,7 @@
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
+#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 2e16346a6cc0..3e588762709a 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -686,6 +686,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
{
+ struct intel_display *display = i915->display;
u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
@@ -724,6 +725,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
/* PSF GV points not supported in D14+ */
+ if (DISPLAY_VER(display) >= 35)
+ dram_info->ecc_impacting_de_bw = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
index 03a973f1c941..8475ee379daa 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -30,6 +30,7 @@ struct dram_info {
u8 num_channels;
u8 num_qgv_points;
u8 num_psf_gv_points;
+ bool ecc_impacting_de_bw; /* Only valid from Xe3p_LPD onward. */
bool symmetric_memory;
bool has_16gb_dimms;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 16/17] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (14 preceding siblings ...)
2025-11-05 14:07 ` [CI 15/17] drm/i915/dram: Add field ecc_impacting_de_bw Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:07 ` [CI 17/17] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
` (5 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
When reading memory latencies for watermark calculations, previous
display releases instructed to apply an adjustment of adding a certain
value (e.g. 6us) to all levels when the level 0's memory latency read
from hardware was zero.
For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
add that value to the other levels. Add the necessary code in
sanitize_wm_latency() so that WaWmMemoryReadLatency is always applied
for Xe3p_LPD and beyond.
v2:
- Rebased after addition of prep patch "drm/i915/wm: Reorder
adjust_wm_latency() for Xe3_LPD" (dropped in v3).
v3:
- Back to the simpler approach of doing the 'wm[0] = 0' step without
modifying the rest of the code, and that inside
sanitize_wm_latency(). (Matt Roper, Ville)
Bspec: 68986, 69126
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-20-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index c888b0896d89..95941e878bf1 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3184,6 +3184,13 @@ static void sanitize_wm_latency(struct intel_display *display)
u16 *wm = display->wm.skl_latency;
int level, num_levels = display->wm.num_levels;
+ /*
+ * Xe3p and beyond should ignore level 0's reported latency and
+ * always apply WaWmMemoryReadLatency logic.
+ */
+ if (DISPLAY_VER(display) >= 35)
+ wm[0] = 0;
+
/*
* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
* need to be disabled. We make sure to sanitize the values out
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [CI 17/17] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (15 preceding siblings ...)
2025-11-05 14:07 ` [CI 16/17] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency Gustavo Sousa
@ 2025-11-05 14:07 ` Gustavo Sousa
2025-11-05 14:58 ` ✗ CI.checkpatch: warning for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Patchwork
` (4 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Gustavo Sousa @ 2025-11-05 14:07 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: gustavo.sousa
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to
accommodate for higher MDCLK:CDCLK ratios. Update the code to use the
new fields.
The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range
[15:13] to [16:13]. Since bit 16 is not reserved in previous display
IPs and already used for something else, we can't simply extend the mask
definition to include it, but rather define an Xe3p-specific mask and
select the correct one to use based on the IP version.
Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range
[18:16] to [20:16]. For the same reasons stated above, it needs a
Xe3p-specific mask definition.
v2:
- Keep definitions in the same line (i.e. without line continuation
breaks) for better readability. (Jani)
v3:
- Keep mask fields sorted by the upper limit. (Matt)
- Extend commit message to indicate why we need Xe3p-specific
definitions of the masks instead of just extending the existing
ones. (Matt)
Bspec: 68868, 68872
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-18-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 16 ++++--
.../gpu/drm/i915/display/skl_watermark_regs.h | 52 ++++++++++---------
2 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 95941e878bf1..36a266f882d1 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3486,7 +3486,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
if (!HAS_MBUS_JOINING(display))
return;
- if (DISPLAY_VER(display) >= 20)
+ if (DISPLAY_VER(display) >= 35)
+ intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
+ XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
+ else if (DISPLAY_VER(display) >= 20)
intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
@@ -3497,9 +3500,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
ratio, str_yes_no(joined_mbus));
for_each_dbuf_slice(display, slice)
- intel_de_rmw(display, DBUF_CTL_S(slice),
- DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
- DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+ if (DISPLAY_VER(display) >= 35)
+ intel_de_rmw(display, DBUF_CTL_S(slice),
+ XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+ else
+ intel_de_rmw(display, DBUF_CTL_S(slice),
+ DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
}
static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index c5572fc0e847..abf56ac31105 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -32,16 +32,18 @@
#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
-#define MBUS_CTL _MMIO(0x4438C)
-#define MBUS_JOIN REG_BIT(31)
-#define MBUS_HASHING_MODE_MASK REG_BIT(30)
-#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
-#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
-#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
-#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
-#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
-#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
-#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define MBUS_CTL _MMIO(0x4438C)
+#define MBUS_JOIN REG_BIT(31)
+#define MBUS_HASHING_MODE_MASK REG_BIT(30)
+#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
+#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
+#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
+#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
+#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
+#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13)
+#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
+#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
/*
* The below are numbered starting from "S1" on gen11/gen12, but starting
@@ -51,20 +53,22 @@
* way things will be named by the hardware team going forward, plus it's more
* consistent with how most of the rest of our registers are named.
*/
-#define _DBUF_CTL_S0 0x45008
-#define _DBUF_CTL_S1 0x44FE8
-#define _DBUF_CTL_S2 0x44300
-#define _DBUF_CTL_S3 0x44304
-#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
- _DBUF_CTL_S0, \
- _DBUF_CTL_S1, \
- _DBUF_CTL_S2, \
- _DBUF_CTL_S3))
-#define DBUF_POWER_REQUEST REG_BIT(31)
-#define DBUF_POWER_STATE REG_BIT(30)
-#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
-#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
-#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
+#define _DBUF_CTL_S0 0x45008
+#define _DBUF_CTL_S1 0x44FE8
+#define _DBUF_CTL_S2 0x44300
+#define _DBUF_CTL_S3 0x44304
+#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
+ _DBUF_CTL_S0, \
+ _DBUF_CTL_S1, \
+ _DBUF_CTL_S2, \
+ _DBUF_CTL_S3))
+#define DBUF_POWER_REQUEST REG_BIT(31)
+#define DBUF_POWER_STATE REG_BIT(30)
+#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
+#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20, 16)
+#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
+#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
--
2.51.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* ✗ CI.checkpatch: warning for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (16 preceding siblings ...)
2025-11-05 14:07 ` [CI 17/17] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
@ 2025-11-05 14:58 ` Patchwork
2025-11-05 15:00 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-11-05 14:58 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
URL : https://patchwork.freedesktop.org/series/157072/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f867e605613af1770f90c4b0afd4a8f06424d1f0
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 832a780cdb7a1a5a4b73f1baac753412c39b5b64
Author: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Date: Wed Nov 5 11:07:06 2025 -0300
drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to
accommodate for higher MDCLK:CDCLK ratios. Update the code to use the
new fields.
The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range
[15:13] to [16:13]. Since bit 16 is not reserved in previous display
IPs and already used for something else, we can't simply extend the mask
definition to include it, but rather define an Xe3p-specific mask and
select the correct one to use based on the IP version.
Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range
[18:16] to [20:16]. For the same reasons stated above, it needs a
Xe3p-specific mask definition.
v2:
- Keep definitions in the same line (i.e. without line continuation
breaks) for better readability. (Jani)
v3:
- Keep mask fields sorted by the upper limit. (Matt)
- Extend commit message to indicate why we need Xe3p-specific
definitions of the masks instead of just extending the existing
ones. (Matt)
Bspec: 68868, 68872
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-18-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+ /mt/dim checkpatch 16a75a91c651f103f022b6b3c6ca29b13205cc9b drm-intel
2e5aa252d648 drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
586f36a2ab65 drm/i915/xe3p_lpd: Drop north display reset option programming
3d737a8e0d21 drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
2b159990c666 drm/i915/xe3p_lpd: Update bandwidth parameters
48bd95a23ee3 drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
9dec679dadf5 drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
0a51107a4e28 drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
d4bd90fe975a drm/i915/xe3p_lpd: Add CDCLK table
19c0a45773f5 drm/i915/xe3p_lpd: Load DMC firmware
6bcbb106642d drm/i915/xe3p_lpd: Drop support for interlace mode
4146e459d402 drm/i915/xe3p_lpd: Extend Wa_16025573575
bf967752b1bf drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format
43cfb71b0ac0 drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
def8122d808e drm/i915/wm: don't use method1 in Xe3p_LPD onwards
91afcf28fa99 drm/i915/dram: Add field ecc_impacting_de_bw
5f7f990b091b drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency
832a780cdb7a drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
-:95: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:41:
+#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
-:98: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:44:
+#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
-:100: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#100: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:46:
+#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
-:134: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:68:
+#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
-:136: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#136: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:70:
+#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
total: 0 errors, 5 warnings, 0 checks, 92 lines checked
^ permalink raw reply [flat|nested] 24+ messages in thread* ✓ CI.KUnit: success for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (17 preceding siblings ...)
2025-11-05 14:58 ` ✗ CI.checkpatch: warning for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Patchwork
@ 2025-11-05 15:00 ` Patchwork
2025-11-05 15:15 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-11-05 15:00 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
URL : https://patchwork.freedesktop.org/series/157072/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:58:58] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:59:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:59:32] Starting KUnit Kernel (1/1)...
[14:59:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:59:33] ================== guc_buf (11 subtests) ===================
[14:59:33] [PASSED] test_smallest
[14:59:33] [PASSED] test_largest
[14:59:33] [PASSED] test_granular
[14:59:33] [PASSED] test_unique
[14:59:33] [PASSED] test_overlap
[14:59:33] [PASSED] test_reusable
[14:59:33] [PASSED] test_too_big
[14:59:33] [PASSED] test_flush
[14:59:33] [PASSED] test_lookup
[14:59:33] [PASSED] test_data
[14:59:33] [PASSED] test_class
[14:59:33] ===================== [PASSED] guc_buf =====================
[14:59:33] =================== guc_dbm (7 subtests) ===================
[14:59:33] [PASSED] test_empty
[14:59:33] [PASSED] test_default
[14:59:33] ======================== test_size ========================
[14:59:33] [PASSED] 4
[14:59:33] [PASSED] 8
[14:59:33] [PASSED] 32
[14:59:33] [PASSED] 256
[14:59:33] ==================== [PASSED] test_size ====================
[14:59:33] ======================= test_reuse ========================
[14:59:33] [PASSED] 4
[14:59:33] [PASSED] 8
[14:59:33] [PASSED] 32
[14:59:33] [PASSED] 256
[14:59:33] =================== [PASSED] test_reuse ====================
[14:59:33] =================== test_range_overlap ====================
[14:59:33] [PASSED] 4
[14:59:33] [PASSED] 8
[14:59:33] [PASSED] 32
[14:59:33] [PASSED] 256
[14:59:33] =============== [PASSED] test_range_overlap ================
[14:59:33] =================== test_range_compact ====================
[14:59:33] [PASSED] 4
[14:59:33] [PASSED] 8
[14:59:33] [PASSED] 32
[14:59:33] [PASSED] 256
[14:59:33] =============== [PASSED] test_range_compact ================
[14:59:33] ==================== test_range_spare =====================
[14:59:33] [PASSED] 4
[14:59:33] [PASSED] 8
[14:59:33] [PASSED] 32
[14:59:33] [PASSED] 256
[14:59:33] ================ [PASSED] test_range_spare =================
[14:59:33] ===================== [PASSED] guc_dbm =====================
[14:59:33] =================== guc_idm (6 subtests) ===================
[14:59:33] [PASSED] bad_init
[14:59:33] [PASSED] no_init
[14:59:33] [PASSED] init_fini
[14:59:33] [PASSED] check_used
[14:59:33] [PASSED] check_quota
[14:59:33] [PASSED] check_all
[14:59:33] ===================== [PASSED] guc_idm =====================
[14:59:33] ================== no_relay (3 subtests) ===================
[14:59:33] [PASSED] xe_drops_guc2pf_if_not_ready
[14:59:33] [PASSED] xe_drops_guc2vf_if_not_ready
[14:59:33] [PASSED] xe_rejects_send_if_not_ready
[14:59:33] ==================== [PASSED] no_relay =====================
[14:59:33] ================== pf_relay (14 subtests) ==================
[14:59:33] [PASSED] pf_rejects_guc2pf_too_short
[14:59:33] [PASSED] pf_rejects_guc2pf_too_long
[14:59:33] [PASSED] pf_rejects_guc2pf_no_payload
[14:59:33] [PASSED] pf_fails_no_payload
[14:59:33] [PASSED] pf_fails_bad_origin
[14:59:33] [PASSED] pf_fails_bad_type
[14:59:33] [PASSED] pf_txn_reports_error
[14:59:33] [PASSED] pf_txn_sends_pf2guc
[14:59:33] [PASSED] pf_sends_pf2guc
[14:59:33] [SKIPPED] pf_loopback_nop
[14:59:33] [SKIPPED] pf_loopback_echo
[14:59:33] [SKIPPED] pf_loopback_fail
[14:59:33] [SKIPPED] pf_loopback_busy
[14:59:33] [SKIPPED] pf_loopback_retry
[14:59:33] ==================== [PASSED] pf_relay =====================
[14:59:33] ================== vf_relay (3 subtests) ===================
[14:59:33] [PASSED] vf_rejects_guc2vf_too_short
[14:59:33] [PASSED] vf_rejects_guc2vf_too_long
[14:59:33] [PASSED] vf_rejects_guc2vf_no_payload
[14:59:33] ==================== [PASSED] vf_relay =====================
[14:59:33] ===================== lmtt (1 subtest) =====================
[14:59:33] ======================== test_ops =========================
[14:59:33] [PASSED] 2-level
[14:59:33] [PASSED] multi-level
[14:59:33] ==================== [PASSED] test_ops =====================
[14:59:33] ====================== [PASSED] lmtt =======================
[14:59:33] ================= pf_service (11 subtests) =================
[14:59:33] [PASSED] pf_negotiate_any
[14:59:33] [PASSED] pf_negotiate_base_match
[14:59:33] [PASSED] pf_negotiate_base_newer
[14:59:33] [PASSED] pf_negotiate_base_next
[14:59:33] [SKIPPED] pf_negotiate_base_older
[14:59:33] [PASSED] pf_negotiate_base_prev
[14:59:33] [PASSED] pf_negotiate_latest_match
[14:59:33] [PASSED] pf_negotiate_latest_newer
[14:59:33] [PASSED] pf_negotiate_latest_next
[14:59:33] [SKIPPED] pf_negotiate_latest_older
[14:59:33] [SKIPPED] pf_negotiate_latest_prev
[14:59:33] =================== [PASSED] pf_service ====================
[14:59:33] ================= xe_guc_g2g (2 subtests) ==================
[14:59:33] ============== xe_live_guc_g2g_kunit_default ==============
[14:59:33] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:59:33] ============== xe_live_guc_g2g_kunit_allmem ===============
[14:59:33] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:59:33] =================== [SKIPPED] xe_guc_g2g ===================
[14:59:33] =================== xe_mocs (2 subtests) ===================
[14:59:33] ================ xe_live_mocs_kernel_kunit ================
[14:59:33] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:59:33] ================ xe_live_mocs_reset_kunit =================
[14:59:33] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:59:33] ==================== [SKIPPED] xe_mocs =====================
[14:59:33] ================= xe_migrate (2 subtests) ==================
[14:59:33] ================= xe_migrate_sanity_kunit =================
[14:59:33] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:59:33] ================== xe_validate_ccs_kunit ==================
[14:59:33] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:59:33] =================== [SKIPPED] xe_migrate ===================
[14:59:33] ================== xe_dma_buf (1 subtest) ==================
[14:59:33] ==================== xe_dma_buf_kunit =====================
[14:59:33] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:59:33] =================== [SKIPPED] xe_dma_buf ===================
[14:59:33] ================= xe_bo_shrink (1 subtest) =================
[14:59:33] =================== xe_bo_shrink_kunit ====================
[14:59:33] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:59:33] ================== [SKIPPED] xe_bo_shrink ==================
[14:59:33] ==================== xe_bo (2 subtests) ====================
[14:59:33] ================== xe_ccs_migrate_kunit ===================
[14:59:33] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:59:33] ==================== xe_bo_evict_kunit ====================
[14:59:33] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:59:33] ===================== [SKIPPED] xe_bo ======================
[14:59:33] ==================== args (11 subtests) ====================
[14:59:33] [PASSED] count_args_test
[14:59:33] [PASSED] call_args_example
[14:59:33] [PASSED] call_args_test
[14:59:33] [PASSED] drop_first_arg_example
[14:59:33] [PASSED] drop_first_arg_test
[14:59:33] [PASSED] first_arg_example
[14:59:33] [PASSED] first_arg_test
[14:59:33] [PASSED] last_arg_example
[14:59:33] [PASSED] last_arg_test
[14:59:33] [PASSED] pick_arg_example
[14:59:33] [PASSED] sep_comma_example
[14:59:33] ====================== [PASSED] args =======================
[14:59:33] =================== xe_pci (3 subtests) ====================
[14:59:33] ==================== check_graphics_ip ====================
[14:59:33] [PASSED] 12.00 Xe_LP
[14:59:33] [PASSED] 12.10 Xe_LP+
[14:59:33] [PASSED] 12.55 Xe_HPG
[14:59:33] [PASSED] 12.60 Xe_HPC
[14:59:33] [PASSED] 12.70 Xe_LPG
[14:59:33] [PASSED] 12.71 Xe_LPG
[14:59:33] [PASSED] 12.74 Xe_LPG+
[14:59:33] [PASSED] 20.01 Xe2_HPG
[14:59:33] [PASSED] 20.02 Xe2_HPG
[14:59:33] [PASSED] 20.04 Xe2_LPG
[14:59:33] [PASSED] 30.00 Xe3_LPG
[14:59:33] [PASSED] 30.01 Xe3_LPG
[14:59:33] [PASSED] 30.03 Xe3_LPG
[14:59:33] [PASSED] 30.04 Xe3_LPG
[14:59:33] [PASSED] 30.05 Xe3_LPG
[14:59:33] [PASSED] 35.11 Xe3p_XPC
[14:59:33] ================ [PASSED] check_graphics_ip ================
[14:59:33] ===================== check_media_ip ======================
[14:59:33] [PASSED] 12.00 Xe_M
[14:59:33] [PASSED] 12.55 Xe_HPM
[14:59:33] [PASSED] 13.00 Xe_LPM+
[14:59:33] [PASSED] 13.01 Xe2_HPM
[14:59:33] [PASSED] 20.00 Xe2_LPM
[14:59:33] [PASSED] 30.00 Xe3_LPM
[14:59:33] [PASSED] 30.02 Xe3_LPM
[14:59:33] [PASSED] 35.00 Xe3p_LPM
[14:59:33] [PASSED] 35.03 Xe3p_HPM
[14:59:33] ================= [PASSED] check_media_ip ==================
[14:59:33] =================== check_platform_desc ===================
[14:59:33] [PASSED] 0x9A60 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A68 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A70 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A40 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A49 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A59 (TIGERLAKE)
[14:59:33] [PASSED] 0x9A78 (TIGERLAKE)
[14:59:33] [PASSED] 0x9AC0 (TIGERLAKE)
[14:59:33] [PASSED] 0x9AC9 (TIGERLAKE)
[14:59:33] [PASSED] 0x9AD9 (TIGERLAKE)
[14:59:33] [PASSED] 0x9AF8 (TIGERLAKE)
[14:59:33] [PASSED] 0x4C80 (ROCKETLAKE)
[14:59:33] [PASSED] 0x4C8A (ROCKETLAKE)
[14:59:33] [PASSED] 0x4C8B (ROCKETLAKE)
[14:59:33] [PASSED] 0x4C8C (ROCKETLAKE)
[14:59:33] [PASSED] 0x4C90 (ROCKETLAKE)
[14:59:33] [PASSED] 0x4C9A (ROCKETLAKE)
[14:59:33] [PASSED] 0x4680 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4682 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4688 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x468A (ALDERLAKE_S)
[14:59:33] [PASSED] 0x468B (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4690 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4692 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4693 (ALDERLAKE_S)
[14:59:33] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46AA (ALDERLAKE_P)
[14:59:33] [PASSED] 0x462A (ALDERLAKE_P)
[14:59:33] [PASSED] 0x4626 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x4628 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:59:33] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:59:33] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:59:33] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:59:33] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:59:33] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:59:33] [PASSED] 0xA721 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA720 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:59:33] [PASSED] 0xA780 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA781 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA782 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA783 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA788 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA789 (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA78A (ALDERLAKE_S)
[14:59:33] [PASSED] 0xA78B (ALDERLAKE_S)
[14:59:33] [PASSED] 0x4905 (DG1)
[14:59:33] [PASSED] 0x4906 (DG1)
[14:59:33] [PASSED] 0x4907 (DG1)
[14:59:33] [PASSED] 0x4908 (DG1)
[14:59:33] [PASSED] 0x4909 (DG1)
[14:59:33] [PASSED] 0x56C0 (DG2)
[14:59:33] [PASSED] 0x56C2 (DG2)
[14:59:33] [PASSED] 0x56C1 (DG2)
[14:59:33] [PASSED] 0x7D51 (METEORLAKE)
[14:59:33] [PASSED] 0x7DD1 (METEORLAKE)
[14:59:33] [PASSED] 0x7D41 (METEORLAKE)
[14:59:33] [PASSED] 0x7D67 (METEORLAKE)
[14:59:33] [PASSED] 0xB640 (METEORLAKE)
[14:59:33] [PASSED] 0x56A0 (DG2)
[14:59:33] [PASSED] 0x56A1 (DG2)
[14:59:33] [PASSED] 0x56A2 (DG2)
[14:59:33] [PASSED] 0x56BE (DG2)
[14:59:33] [PASSED] 0x56BF (DG2)
[14:59:33] [PASSED] 0x5690 (DG2)
[14:59:33] [PASSED] 0x5691 (DG2)
[14:59:33] [PASSED] 0x5692 (DG2)
[14:59:33] [PASSED] 0x56A5 (DG2)
[14:59:33] [PASSED] 0x56A6 (DG2)
[14:59:33] [PASSED] 0x56B0 (DG2)
[14:59:33] [PASSED] 0x56B1 (DG2)
[14:59:33] [PASSED] 0x56BA (DG2)
[14:59:33] [PASSED] 0x56BB (DG2)
[14:59:33] [PASSED] 0x56BC (DG2)
[14:59:33] [PASSED] 0x56BD (DG2)
[14:59:33] [PASSED] 0x5693 (DG2)
[14:59:33] [PASSED] 0x5694 (DG2)
[14:59:33] [PASSED] 0x5695 (DG2)
[14:59:33] [PASSED] 0x56A3 (DG2)
[14:59:33] [PASSED] 0x56A4 (DG2)
[14:59:33] [PASSED] 0x56B2 (DG2)
[14:59:33] [PASSED] 0x56B3 (DG2)
[14:59:33] [PASSED] 0x5696 (DG2)
[14:59:33] [PASSED] 0x5697 (DG2)
[14:59:33] [PASSED] 0xB69 (PVC)
[14:59:33] [PASSED] 0xB6E (PVC)
[14:59:33] [PASSED] 0xBD4 (PVC)
[14:59:33] [PASSED] 0xBD5 (PVC)
[14:59:33] [PASSED] 0xBD6 (PVC)
[14:59:33] [PASSED] 0xBD7 (PVC)
[14:59:33] [PASSED] 0xBD8 (PVC)
[14:59:33] [PASSED] 0xBD9 (PVC)
[14:59:33] [PASSED] 0xBDA (PVC)
[14:59:33] [PASSED] 0xBDB (PVC)
[14:59:33] [PASSED] 0xBE0 (PVC)
[14:59:33] [PASSED] 0xBE1 (PVC)
[14:59:33] [PASSED] 0xBE5 (PVC)
[14:59:33] [PASSED] 0x7D40 (METEORLAKE)
[14:59:33] [PASSED] 0x7D45 (METEORLAKE)
[14:59:33] [PASSED] 0x7D55 (METEORLAKE)
[14:59:33] [PASSED] 0x7D60 (METEORLAKE)
[14:59:33] [PASSED] 0x7DD5 (METEORLAKE)
[14:59:33] [PASSED] 0x6420 (LUNARLAKE)
[14:59:33] [PASSED] 0x64A0 (LUNARLAKE)
[14:59:33] [PASSED] 0x64B0 (LUNARLAKE)
[14:59:33] [PASSED] 0xE202 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE209 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE20B (BATTLEMAGE)
[14:59:33] [PASSED] 0xE20C (BATTLEMAGE)
[14:59:33] [PASSED] 0xE20D (BATTLEMAGE)
[14:59:33] [PASSED] 0xE210 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE211 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE212 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE216 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE220 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE221 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE222 (BATTLEMAGE)
[14:59:33] [PASSED] 0xE223 (BATTLEMAGE)
[14:59:33] [PASSED] 0xB080 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB081 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB082 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB083 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB084 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB085 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB086 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB087 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB08F (PANTHERLAKE)
[14:59:33] [PASSED] 0xB090 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:59:33] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:59:33] [PASSED] 0xD740 (NOVALAKE_S)
[14:59:33] [PASSED] 0xD741 (NOVALAKE_S)
[14:59:33] [PASSED] 0xD742 (NOVALAKE_S)
[14:59:33] [PASSED] 0xD743 (NOVALAKE_S)
[14:59:33] [PASSED] 0xD744 (NOVALAKE_S)
[14:59:33] [PASSED] 0xD745 (NOVALAKE_S)
[14:59:33] [PASSED] 0x674C (CRESCENTISLAND)
[14:59:33] [PASSED] 0xFD80 (PANTHERLAKE)
[14:59:33] [PASSED] 0xFD81 (PANTHERLAKE)
[14:59:33] =============== [PASSED] check_platform_desc ===============
[14:59:33] ===================== [PASSED] xe_pci ======================
[14:59:33] =================== xe_rtp (2 subtests) ====================
[14:59:33] =============== xe_rtp_process_to_sr_tests ================
[14:59:33] [PASSED] coalesce-same-reg
[14:59:33] [PASSED] no-match-no-add
[14:59:33] [PASSED] match-or
[14:59:33] [PASSED] match-or-xfail
[14:59:33] [PASSED] no-match-no-add-multiple-rules
[14:59:33] [PASSED] two-regs-two-entries
[14:59:33] [PASSED] clr-one-set-other
[14:59:33] [PASSED] set-field
[14:59:33] [PASSED] conflict-duplicate
[14:59:33] [PASSED] conflict-not-disjoint
[14:59:33] [PASSED] conflict-reg-type
[14:59:33] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:59:33] ================== xe_rtp_process_tests ===================
[14:59:33] [PASSED] active1
[14:59:33] [PASSED] active2
[14:59:33] [PASSED] active-inactive
[14:59:33] [PASSED] inactive-active
[14:59:33] [PASSED] inactive-1st_or_active-inactive
[14:59:33] [PASSED] inactive-2nd_or_active-inactive
[14:59:33] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[14:59:33] [PASSED] inactive-no_or_active-inactive
[14:59:33] ============== [PASSED] xe_rtp_process_tests ===============
[14:59:33] ===================== [PASSED] xe_rtp ======================
[14:59:33] ==================== xe_wa (1 subtest) =====================
[14:59:33] ======================== xe_wa_gt =========================
[14:59:33] [PASSED] TIGERLAKE B0
[14:59:33] [PASSED] DG1 A0
[14:59:33] [PASSED] DG1 B0
[14:59:33] [PASSED] ALDERLAKE_S A0
[14:59:33] [PASSED] ALDERLAKE_S B0
[14:59:33] [PASSED] ALDERLAKE_S C0
[14:59:33] [PASSED] ALDERLAKE_S D0
[14:59:33] [PASSED] ALDERLAKE_P A0
[14:59:33] [PASSED] ALDERLAKE_P B0
[14:59:33] [PASSED] ALDERLAKE_P C0
[14:59:33] [PASSED] ALDERLAKE_S RPLS D0
[14:59:33] [PASSED] ALDERLAKE_P RPLU E0
[14:59:33] [PASSED] DG2 G10 C0
[14:59:33] [PASSED] DG2 G11 B1
[14:59:33] [PASSED] DG2 G12 A1
[14:59:33] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:59:33] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:59:33] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:59:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:59:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:59:33] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:59:33] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:59:33] ==================== [PASSED] xe_wa_gt =====================
[14:59:33] ====================== [PASSED] xe_wa ======================
[14:59:33] ============================================================
[14:59:33] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[14:59:33] Elapsed time: 34.730s total, 4.149s configuring, 30.214s building, 0.332s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:59:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:59:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:59:59] Starting KUnit Kernel (1/1)...
[14:59:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:59:59] ============ drm_test_pick_cmdline (2 subtests) ============
[14:59:59] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:59:59] =============== drm_test_pick_cmdline_named ===============
[14:59:59] [PASSED] NTSC
[14:59:59] [PASSED] NTSC-J
[14:59:59] [PASSED] PAL
[14:59:59] [PASSED] PAL-M
[14:59:59] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:59:59] ============== [PASSED] drm_test_pick_cmdline ==============
[14:59:59] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:59:59] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:59:59] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:59:59] =========== drm_validate_clone_mode (2 subtests) ===========
[14:59:59] ============== drm_test_check_in_clone_mode ===============
[14:59:59] [PASSED] in_clone_mode
[14:59:59] [PASSED] not_in_clone_mode
[14:59:59] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:59:59] =============== drm_test_check_valid_clones ===============
[14:59:59] [PASSED] not_in_clone_mode
[14:59:59] [PASSED] valid_clone
[14:59:59] [PASSED] invalid_clone
[14:59:59] =========== [PASSED] drm_test_check_valid_clones ===========
[14:59:59] ============= [PASSED] drm_validate_clone_mode =============
[14:59:59] ============= drm_validate_modeset (1 subtest) =============
[14:59:59] [PASSED] drm_test_check_connector_changed_modeset
[14:59:59] ============== [PASSED] drm_validate_modeset ===============
[14:59:59] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:59:59] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:59:59] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:59:59] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:59:59] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:59:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:59:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:59:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:59:59] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:59:59] ============== drm_bridge_alloc (2 subtests) ===============
[14:59:59] [PASSED] drm_test_drm_bridge_alloc_basic
[14:59:59] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:59:59] ================ [PASSED] drm_bridge_alloc =================
[14:59:59] ================== drm_buddy (8 subtests) ==================
[14:59:59] [PASSED] drm_test_buddy_alloc_limit
[14:59:59] [PASSED] drm_test_buddy_alloc_optimistic
[14:59:59] [PASSED] drm_test_buddy_alloc_pessimistic
[14:59:59] [PASSED] drm_test_buddy_alloc_pathological
[14:59:59] [PASSED] drm_test_buddy_alloc_contiguous
[14:59:59] [PASSED] drm_test_buddy_alloc_clear
[15:00:00] [PASSED] drm_test_buddy_alloc_range_bias
[15:00:00] [PASSED] drm_test_buddy_fragmentation_performance
[15:00:00] ==================== [PASSED] drm_buddy ====================
[15:00:00] ============= drm_cmdline_parser (40 subtests) =============
[15:00:00] [PASSED] drm_test_cmdline_force_d_only
[15:00:00] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:00:00] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:00:00] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:00:00] [PASSED] drm_test_cmdline_force_e_only
[15:00:00] [PASSED] drm_test_cmdline_res
[15:00:00] [PASSED] drm_test_cmdline_res_vesa
[15:00:00] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:00:00] [PASSED] drm_test_cmdline_res_rblank
[15:00:00] [PASSED] drm_test_cmdline_res_bpp
[15:00:00] [PASSED] drm_test_cmdline_res_refresh
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:00:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:00:00] [PASSED] drm_test_cmdline_res_margins_force_on
[15:00:00] [PASSED] drm_test_cmdline_res_vesa_margins
[15:00:00] [PASSED] drm_test_cmdline_name
[15:00:00] [PASSED] drm_test_cmdline_name_bpp
[15:00:00] [PASSED] drm_test_cmdline_name_option
[15:00:00] [PASSED] drm_test_cmdline_name_bpp_option
[15:00:00] [PASSED] drm_test_cmdline_rotate_0
[15:00:00] [PASSED] drm_test_cmdline_rotate_90
[15:00:00] [PASSED] drm_test_cmdline_rotate_180
[15:00:00] [PASSED] drm_test_cmdline_rotate_270
[15:00:00] [PASSED] drm_test_cmdline_hmirror
[15:00:00] [PASSED] drm_test_cmdline_vmirror
[15:00:00] [PASSED] drm_test_cmdline_margin_options
[15:00:00] [PASSED] drm_test_cmdline_multiple_options
[15:00:00] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:00:00] [PASSED] drm_test_cmdline_extra_and_option
[15:00:00] [PASSED] drm_test_cmdline_freestanding_options
[15:00:00] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:00:00] [PASSED] drm_test_cmdline_panel_orientation
[15:00:00] ================ drm_test_cmdline_invalid =================
[15:00:00] [PASSED] margin_only
[15:00:00] [PASSED] interlace_only
[15:00:00] [PASSED] res_missing_x
[15:00:00] [PASSED] res_missing_y
[15:00:00] [PASSED] res_bad_y
[15:00:00] [PASSED] res_missing_y_bpp
[15:00:00] [PASSED] res_bad_bpp
[15:00:00] [PASSED] res_bad_refresh
[15:00:00] [PASSED] res_bpp_refresh_force_on_off
[15:00:00] [PASSED] res_invalid_mode
[15:00:00] [PASSED] res_bpp_wrong_place_mode
[15:00:00] [PASSED] name_bpp_refresh
[15:00:00] [PASSED] name_refresh
[15:00:00] [PASSED] name_refresh_wrong_mode
[15:00:00] [PASSED] name_refresh_invalid_mode
[15:00:00] [PASSED] rotate_multiple
[15:00:00] [PASSED] rotate_invalid_val
[15:00:00] [PASSED] rotate_truncated
[15:00:00] [PASSED] invalid_option
[15:00:00] [PASSED] invalid_tv_option
[15:00:00] [PASSED] truncated_tv_option
[15:00:00] ============ [PASSED] drm_test_cmdline_invalid =============
[15:00:00] =============== drm_test_cmdline_tv_options ===============
[15:00:00] [PASSED] NTSC
[15:00:00] [PASSED] NTSC_443
[15:00:00] [PASSED] NTSC_J
[15:00:00] [PASSED] PAL
[15:00:00] [PASSED] PAL_M
[15:00:00] [PASSED] PAL_N
[15:00:00] [PASSED] SECAM
[15:00:00] [PASSED] MONO_525
[15:00:00] [PASSED] MONO_625
[15:00:00] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:00:00] =============== [PASSED] drm_cmdline_parser ================
[15:00:00] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:00:00] [PASSED] drm_test_connector_hdmi_init_valid
[15:00:00] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:00:00] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:00:00] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:00:00] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:00:00] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:00:00] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:00:00] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:00:00] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:00:00] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:00:00] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:00:00] [PASSED] supported_formats=0x3 yuv420_allowed=1
[15:00:00] [PASSED] supported_formats=0x3 yuv420_allowed=0
[15:00:00] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:00:00] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:00:00] [PASSED] drm_test_connector_hdmi_init_null_product
[15:00:00] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:00:00] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:00:00] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:00:00] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:00:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:00:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:00:00] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:00:00] ========= drm_test_connector_hdmi_init_type_valid =========
[15:00:00] [PASSED] HDMI-A
[15:00:00] [PASSED] HDMI-B
[15:00:00] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:00:00] ======== drm_test_connector_hdmi_init_type_invalid ========
[15:00:00] [PASSED] Unknown
[15:00:00] [PASSED] VGA
[15:00:00] [PASSED] DVI-I
[15:00:00] [PASSED] DVI-D
[15:00:00] [PASSED] DVI-A
[15:00:00] [PASSED] Composite
[15:00:00] [PASSED] SVIDEO
[15:00:00] [PASSED] LVDS
[15:00:00] [PASSED] Component
[15:00:00] [PASSED] DIN
[15:00:00] [PASSED] DP
[15:00:00] [PASSED] TV
[15:00:00] [PASSED] eDP
[15:00:00] [PASSED] Virtual
[15:00:00] [PASSED] DSI
[15:00:00] [PASSED] DPI
[15:00:00] [PASSED] Writeback
[15:00:00] [PASSED] SPI
[15:00:00] [PASSED] USB
[15:00:00] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:00:00] ============ [PASSED] drmm_connector_hdmi_init =============
[15:00:00] ============= drmm_connector_init (3 subtests) =============
[15:00:00] [PASSED] drm_test_drmm_connector_init
[15:00:00] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:00:00] ========= drm_test_drmm_connector_init_type_valid =========
[15:00:00] [PASSED] Unknown
[15:00:00] [PASSED] VGA
[15:00:00] [PASSED] DVI-I
[15:00:00] [PASSED] DVI-D
[15:00:00] [PASSED] DVI-A
[15:00:00] [PASSED] Composite
[15:00:00] [PASSED] SVIDEO
[15:00:00] [PASSED] LVDS
[15:00:00] [PASSED] Component
[15:00:00] [PASSED] DIN
[15:00:00] [PASSED] DP
[15:00:00] [PASSED] HDMI-A
[15:00:00] [PASSED] HDMI-B
[15:00:00] [PASSED] TV
[15:00:00] [PASSED] eDP
[15:00:00] [PASSED] Virtual
[15:00:00] [PASSED] DSI
[15:00:00] [PASSED] DPI
[15:00:00] [PASSED] Writeback
[15:00:00] [PASSED] SPI
[15:00:00] [PASSED] USB
[15:00:00] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:00:00] =============== [PASSED] drmm_connector_init ===============
[15:00:00] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_init
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:00:00] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[15:00:00] [PASSED] Unknown
[15:00:00] [PASSED] VGA
[15:00:00] [PASSED] DVI-I
[15:00:00] [PASSED] DVI-D
[15:00:00] [PASSED] DVI-A
[15:00:00] [PASSED] Composite
[15:00:00] [PASSED] SVIDEO
[15:00:00] [PASSED] LVDS
[15:00:00] [PASSED] Component
[15:00:00] [PASSED] DIN
[15:00:00] [PASSED] DP
[15:00:00] [PASSED] HDMI-A
[15:00:00] [PASSED] HDMI-B
[15:00:00] [PASSED] TV
[15:00:00] [PASSED] eDP
[15:00:00] [PASSED] Virtual
[15:00:00] [PASSED] DSI
[15:00:00] [PASSED] DPI
[15:00:00] [PASSED] Writeback
[15:00:00] [PASSED] SPI
[15:00:00] [PASSED] USB
[15:00:00] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:00:00] ======== drm_test_drm_connector_dynamic_init_name =========
[15:00:00] [PASSED] Unknown
[15:00:00] [PASSED] VGA
[15:00:00] [PASSED] DVI-I
[15:00:00] [PASSED] DVI-D
[15:00:00] [PASSED] DVI-A
[15:00:00] [PASSED] Composite
[15:00:00] [PASSED] SVIDEO
[15:00:00] [PASSED] LVDS
[15:00:00] [PASSED] Component
[15:00:00] [PASSED] DIN
[15:00:00] [PASSED] DP
[15:00:00] [PASSED] HDMI-A
[15:00:00] [PASSED] HDMI-B
[15:00:00] [PASSED] TV
[15:00:00] [PASSED] eDP
[15:00:00] [PASSED] Virtual
[15:00:00] [PASSED] DSI
[15:00:00] [PASSED] DPI
[15:00:00] [PASSED] Writeback
[15:00:00] [PASSED] SPI
[15:00:00] [PASSED] USB
[15:00:00] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:00:00] =========== [PASSED] drm_connector_dynamic_init ============
[15:00:00] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:00:00] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:00:00] ======= drm_connector_dynamic_register (7 subtests) ========
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:00:00] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:00:00] ========= [PASSED] drm_connector_dynamic_register ==========
[15:00:00] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:00:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:00:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:00:00] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:00:00] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:00:00] ========== drm_test_get_tv_mode_from_name_valid ===========
[15:00:00] [PASSED] NTSC
[15:00:00] [PASSED] NTSC-443
[15:00:00] [PASSED] NTSC-J
[15:00:00] [PASSED] PAL
[15:00:00] [PASSED] PAL-M
[15:00:00] [PASSED] PAL-N
[15:00:00] [PASSED] SECAM
[15:00:00] [PASSED] Mono
[15:00:00] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:00:00] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:00:00] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:00:00] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:00:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:00:00] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[15:00:00] [PASSED] VIC 96
[15:00:00] [PASSED] VIC 97
[15:00:00] [PASSED] VIC 101
[15:00:00] [PASSED] VIC 102
[15:00:00] [PASSED] VIC 106
[15:00:00] [PASSED] VIC 107
[15:00:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:00:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:00:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:00:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:00:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:00:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:00:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:00:00] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:00:00] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[15:00:00] [PASSED] Automatic
[15:00:00] [PASSED] Full
[15:00:00] [PASSED] Limited 16:235
[15:00:00] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:00:00] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:00:00] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:00:00] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:00:00] === drm_test_drm_hdmi_connector_get_output_format_name ====
[15:00:00] [PASSED] RGB
[15:00:00] [PASSED] YUV 4:2:0
[15:00:00] [PASSED] YUV 4:2:2
[15:00:00] [PASSED] YUV 4:4:4
[15:00:00] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:00:00] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:00:00] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:00:00] ============= drm_damage_helper (21 subtests) ==============
[15:00:00] [PASSED] drm_test_damage_iter_no_damage
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:00:00] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:00:00] [PASSED] drm_test_damage_iter_simple_damage
[15:00:00] [PASSED] drm_test_damage_iter_single_damage
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:00:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:00:00] [PASSED] drm_test_damage_iter_damage
[15:00:00] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:00:00] [PASSED] drm_test_damage_iter_damage_one_outside
[15:00:00] [PASSED] drm_test_damage_iter_damage_src_moved
[15:00:00] [PASSED] drm_test_damage_iter_damage_not_visible
[15:00:00] ================ [PASSED] drm_damage_helper ================
[15:00:00] ============== drm_dp_mst_helper (3 subtests) ==============
[15:00:00] ============== drm_test_dp_mst_calc_pbn_mode ==============
[15:00:00] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:00:00] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:00:00] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:00:00] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:00:00] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:00:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:00:00] ============== drm_test_dp_mst_calc_pbn_div ===============
[15:00:00] [PASSED] Link rate 2000000 lane count 4
[15:00:00] [PASSED] Link rate 2000000 lane count 2
[15:00:00] [PASSED] Link rate 2000000 lane count 1
[15:00:00] [PASSED] Link rate 1350000 lane count 4
[15:00:00] [PASSED] Link rate 1350000 lane count 2
[15:00:00] [PASSED] Link rate 1350000 lane count 1
[15:00:00] [PASSED] Link rate 1000000 lane count 4
[15:00:00] [PASSED] Link rate 1000000 lane count 2
[15:00:00] [PASSED] Link rate 1000000 lane count 1
[15:00:00] [PASSED] Link rate 810000 lane count 4
[15:00:00] [PASSED] Link rate 810000 lane count 2
[15:00:00] [PASSED] Link rate 810000 lane count 1
[15:00:00] [PASSED] Link rate 540000 lane count 4
[15:00:00] [PASSED] Link rate 540000 lane count 2
[15:00:00] [PASSED] Link rate 540000 lane count 1
[15:00:00] [PASSED] Link rate 270000 lane count 4
[15:00:00] [PASSED] Link rate 270000 lane count 2
[15:00:00] [PASSED] Link rate 270000 lane count 1
[15:00:00] [PASSED] Link rate 162000 lane count 4
[15:00:00] [PASSED] Link rate 162000 lane count 2
[15:00:00] [PASSED] Link rate 162000 lane count 1
[15:00:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:00:00] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[15:00:00] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:00:00] [PASSED] DP_POWER_UP_PHY with port number
[15:00:00] [PASSED] DP_POWER_DOWN_PHY with port number
[15:00:00] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:00:00] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:00:00] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:00:00] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:00:00] [PASSED] DP_QUERY_PAYLOAD with port number
[15:00:00] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:00:00] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:00:00] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:00:00] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:00:00] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:00:00] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:00:00] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:00:00] [PASSED] DP_REMOTE_I2C_READ with port number
[15:00:00] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:00:00] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:00:00] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:00:00] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:00:00] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:00:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:00:00] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:00:00] ================ [PASSED] drm_dp_mst_helper ================
[15:00:00] ================== drm_exec (7 subtests) ===================
[15:00:00] [PASSED] sanitycheck
[15:00:00] [PASSED] test_lock
[15:00:00] [PASSED] test_lock_unlock
[15:00:00] [PASSED] test_duplicates
[15:00:00] [PASSED] test_prepare
[15:00:00] [PASSED] test_prepare_array
[15:00:00] [PASSED] test_multiple_loops
[15:00:00] ==================== [PASSED] drm_exec =====================
[15:00:00] =========== drm_format_helper_test (17 subtests) ===========
[15:00:00] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:00:00] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:00:00] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:00:00] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:00:00] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:00:00] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:00:00] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:00:00] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:00:00] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:00:00] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:00:00] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:00:00] ============== drm_test_fb_xrgb8888_to_mono ===============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:00:00] ==================== drm_test_fb_swab =====================
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ================ [PASSED] drm_test_fb_swab =================
[15:00:00] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:00:00] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[15:00:00] [PASSED] single_pixel_source_buffer
[15:00:00] [PASSED] single_pixel_clip_rectangle
[15:00:00] [PASSED] well_known_colors
[15:00:00] [PASSED] destination_pitch
[15:00:00] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:00:00] ================= drm_test_fb_clip_offset =================
[15:00:00] [PASSED] pass through
[15:00:00] [PASSED] horizontal offset
[15:00:00] [PASSED] vertical offset
[15:00:00] [PASSED] horizontal and vertical offset
[15:00:00] [PASSED] horizontal offset (custom pitch)
[15:00:00] [PASSED] vertical offset (custom pitch)
[15:00:00] [PASSED] horizontal and vertical offset (custom pitch)
[15:00:00] ============= [PASSED] drm_test_fb_clip_offset =============
[15:00:00] =================== drm_test_fb_memcpy ====================
[15:00:00] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:00:00] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:00:00] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:00:00] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:00:00] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:00:00] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:00:00] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:00:00] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:00:00] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:00:00] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:00:00] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:00:00] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:00:00] =============== [PASSED] drm_test_fb_memcpy ================
[15:00:00] ============= [PASSED] drm_format_helper_test ==============
[15:00:00] ================= drm_format (18 subtests) =================
[15:00:00] [PASSED] drm_test_format_block_width_invalid
[15:00:00] [PASSED] drm_test_format_block_width_one_plane
[15:00:00] [PASSED] drm_test_format_block_width_two_plane
[15:00:00] [PASSED] drm_test_format_block_width_three_plane
[15:00:00] [PASSED] drm_test_format_block_width_tiled
[15:00:00] [PASSED] drm_test_format_block_height_invalid
[15:00:00] [PASSED] drm_test_format_block_height_one_plane
[15:00:00] [PASSED] drm_test_format_block_height_two_plane
[15:00:00] [PASSED] drm_test_format_block_height_three_plane
[15:00:00] [PASSED] drm_test_format_block_height_tiled
[15:00:00] [PASSED] drm_test_format_min_pitch_invalid
[15:00:00] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:00:00] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:00:00] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:00:00] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:00:00] [PASSED] drm_test_format_min_pitch_two_plane
[15:00:00] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:00:00] [PASSED] drm_test_format_min_pitch_tiled
[15:00:00] =================== [PASSED] drm_format ====================
[15:00:00] ============== drm_framebuffer (10 subtests) ===============
[15:00:00] ========== drm_test_framebuffer_check_src_coords ==========
[15:00:00] [PASSED] Success: source fits into fb
[15:00:00] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:00:00] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:00:00] [PASSED] Fail: overflowing fb with source width
[15:00:00] [PASSED] Fail: overflowing fb with source height
[15:00:00] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:00:00] [PASSED] drm_test_framebuffer_cleanup
[15:00:00] =============== drm_test_framebuffer_create ===============
[15:00:00] [PASSED] ABGR8888 normal sizes
[15:00:00] [PASSED] ABGR8888 max sizes
[15:00:00] [PASSED] ABGR8888 pitch greater than min required
[15:00:00] [PASSED] ABGR8888 pitch less than min required
[15:00:00] [PASSED] ABGR8888 Invalid width
[15:00:00] [PASSED] ABGR8888 Invalid buffer handle
[15:00:00] [PASSED] No pixel format
[15:00:00] [PASSED] ABGR8888 Width 0
[15:00:00] [PASSED] ABGR8888 Height 0
[15:00:00] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:00:00] [PASSED] ABGR8888 Large buffer offset
[15:00:00] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:00:00] [PASSED] ABGR8888 Invalid flag
[15:00:00] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:00:00] [PASSED] ABGR8888 Valid buffer modifier
[15:00:00] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:00:00] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] NV12 Normal sizes
[15:00:00] [PASSED] NV12 Max sizes
[15:00:00] [PASSED] NV12 Invalid pitch
[15:00:00] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:00:00] [PASSED] NV12 different modifier per-plane
[15:00:00] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:00:00] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] NV12 Modifier for inexistent plane
[15:00:00] [PASSED] NV12 Handle for inexistent plane
[15:00:00] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:00:00] [PASSED] YVU420 Normal sizes
[15:00:00] [PASSED] YVU420 Max sizes
[15:00:00] [PASSED] YVU420 Invalid pitch
[15:00:00] [PASSED] YVU420 Different pitches
[15:00:00] [PASSED] YVU420 Different buffer offsets/pitches
[15:00:00] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:00:00] [PASSED] YVU420 Valid modifier
[15:00:00] [PASSED] YVU420 Different modifiers per plane
[15:00:00] [PASSED] YVU420 Modifier for inexistent plane
[15:00:00] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:00:00] [PASSED] X0L2 Normal sizes
[15:00:00] [PASSED] X0L2 Max sizes
[15:00:00] [PASSED] X0L2 Invalid pitch
[15:00:00] [PASSED] X0L2 Pitch greater than minimum required
[15:00:00] [PASSED] X0L2 Handle for inexistent plane
[15:00:00] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:00:00] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:00:00] [PASSED] X0L2 Valid modifier
[15:00:00] [PASSED] X0L2 Modifier for inexistent plane
[15:00:00] =========== [PASSED] drm_test_framebuffer_create ===========
[15:00:00] [PASSED] drm_test_framebuffer_free
[15:00:00] [PASSED] drm_test_framebuffer_init
[15:00:00] [PASSED] drm_test_framebuffer_init_bad_format
[15:00:00] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:00:00] [PASSED] drm_test_framebuffer_lookup
[15:00:00] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:00:00] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:00:00] ================= [PASSED] drm_framebuffer =================
[15:00:00] ================ drm_gem_shmem (8 subtests) ================
[15:00:00] [PASSED] drm_gem_shmem_test_obj_create
[15:00:00] [PASSED] drm_gem_shmem_test_obj_create_private
[15:00:00] [PASSED] drm_gem_shmem_test_pin_pages
[15:00:00] [PASSED] drm_gem_shmem_test_vmap
[15:00:00] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:00:00] [PASSED] drm_gem_shmem_test_get_sg_table
[15:00:00] [PASSED] drm_gem_shmem_test_madvise
[15:00:00] [PASSED] drm_gem_shmem_test_purge
[15:00:00] ================== [PASSED] drm_gem_shmem ==================
[15:00:00] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:00:00] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[15:00:00] [PASSED] Automatic
[15:00:00] [PASSED] Full
[15:00:00] [PASSED] Limited 16:235
[15:00:00] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:00:00] [PASSED] drm_test_check_disable_connector
[15:00:00] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:00:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:00:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:00:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:00:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:00:00] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:00:00] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:00:00] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:00:00] [PASSED] drm_test_check_output_bpc_dvi
[15:00:00] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:00:00] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:00:00] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:00:00] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:00:00] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:00:00] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:00:00] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:00:00] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:00:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:00:00] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:00:00] [PASSED] drm_test_check_broadcast_rgb_value
[15:00:00] [PASSED] drm_test_check_bpc_8_value
[15:00:00] [PASSED] drm_test_check_bpc_10_value
[15:00:00] [PASSED] drm_test_check_bpc_12_value
[15:00:00] [PASSED] drm_test_check_format_value
[15:00:00] [PASSED] drm_test_check_tmds_char_value
[15:00:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:00:00] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:00:00] [PASSED] drm_test_check_mode_valid
[15:00:00] [PASSED] drm_test_check_mode_valid_reject
[15:00:00] [PASSED] drm_test_check_mode_valid_reject_rate
[15:00:00] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:00:00] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:00:00] ================= drm_managed (2 subtests) =================
[15:00:00] [PASSED] drm_test_managed_release_action
[15:00:00] [PASSED] drm_test_managed_run_action
[15:00:00] =================== [PASSED] drm_managed ===================
[15:00:00] =================== drm_mm (6 subtests) ====================
[15:00:00] [PASSED] drm_test_mm_init
[15:00:00] [PASSED] drm_test_mm_debug
[15:00:00] [PASSED] drm_test_mm_align32
[15:00:00] [PASSED] drm_test_mm_align64
[15:00:00] [PASSED] drm_test_mm_lowest
[15:00:00] [PASSED] drm_test_mm_highest
[15:00:00] ===================== [PASSED] drm_mm ======================
[15:00:00] ============= drm_modes_analog_tv (5 subtests) =============
[15:00:00] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:00:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:00:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:00:00] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:00:00] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:00:00] =============== [PASSED] drm_modes_analog_tv ===============
[15:00:00] ============== drm_plane_helper (2 subtests) ===============
[15:00:00] =============== drm_test_check_plane_state ================
[15:00:00] [PASSED] clipping_simple
[15:00:00] [PASSED] clipping_rotate_reflect
[15:00:00] [PASSED] positioning_simple
[15:00:00] [PASSED] upscaling
[15:00:00] [PASSED] downscaling
[15:00:00] [PASSED] rounding1
[15:00:00] [PASSED] rounding2
[15:00:00] [PASSED] rounding3
[15:00:00] [PASSED] rounding4
[15:00:00] =========== [PASSED] drm_test_check_plane_state ============
[15:00:00] =========== drm_test_check_invalid_plane_state ============
[15:00:00] [PASSED] positioning_invalid
[15:00:00] [PASSED] upscaling_invalid
[15:00:00] [PASSED] downscaling_invalid
[15:00:00] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:00:00] ================ [PASSED] drm_plane_helper =================
[15:00:00] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:00:00] ====== drm_test_connector_helper_tv_get_modes_check =======
[15:00:00] [PASSED] None
[15:00:00] [PASSED] PAL
[15:00:00] [PASSED] NTSC
[15:00:00] [PASSED] Both, NTSC Default
[15:00:00] [PASSED] Both, PAL Default
[15:00:00] [PASSED] Both, NTSC Default, with PAL on command-line
[15:00:00] [PASSED] Both, PAL Default, with NTSC on command-line
[15:00:00] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:00:00] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:00:00] ================== drm_rect (9 subtests) ===================
[15:00:00] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:00:00] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:00:00] [PASSED] drm_test_rect_clip_scaled_clipped
[15:00:00] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:00:00] ================= drm_test_rect_intersect =================
[15:00:00] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:00:00] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:00:00] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:00:00] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:00:00] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:00:00] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:00:00] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:00:00] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:00:00] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:00:00] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:00:00] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:00:00] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:00:00] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:00:00] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:00:00] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:00:00] ============= [PASSED] drm_test_rect_intersect =============
[15:00:00] ================ drm_test_rect_calc_hscale ================
[15:00:00] [PASSED] normal use
[15:00:00] [PASSED] out of max range
[15:00:00] [PASSED] out of min range
[15:00:00] [PASSED] zero dst
[15:00:00] [PASSED] negative src
[15:00:00] [PASSED] negative dst
[15:00:00] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:00:00] ================ drm_test_rect_calc_vscale ================
[15:00:00] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[15:00:00] [PASSED] out of max range
[15:00:00] [PASSED] out of min range
[15:00:00] [PASSED] zero dst
[15:00:00] [PASSED] negative src
[15:00:00] [PASSED] negative dst
[15:00:00] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:00:00] ================== drm_test_rect_rotate ===================
[15:00:00] [PASSED] reflect-x
[15:00:00] [PASSED] reflect-y
[15:00:00] [PASSED] rotate-0
[15:00:00] [PASSED] rotate-90
[15:00:00] [PASSED] rotate-180
[15:00:00] [PASSED] rotate-270
[15:00:00] ============== [PASSED] drm_test_rect_rotate ===============
[15:00:00] ================ drm_test_rect_rotate_inv =================
[15:00:00] [PASSED] reflect-x
[15:00:00] [PASSED] reflect-y
[15:00:00] [PASSED] rotate-0
[15:00:00] [PASSED] rotate-90
[15:00:00] [PASSED] rotate-180
[15:00:00] [PASSED] rotate-270
[15:00:00] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:00:00] ==================== [PASSED] drm_rect =====================
[15:00:00] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:00:00] ============ drm_test_sysfb_build_fourcc_list =============
[15:00:00] [PASSED] no native formats
[15:00:00] [PASSED] XRGB8888 as native format
[15:00:00] [PASSED] remove duplicates
[15:00:00] [PASSED] convert alpha formats
[15:00:00] [PASSED] random formats
[15:00:00] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:00:00] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:00:00] ============================================================
[15:00:00] Testing complete. Ran 622 tests: passed: 622
[15:00:00] Elapsed time: 26.873s total, 1.735s configuring, 24.719s building, 0.393s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:00:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:00:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:00:11] Starting KUnit Kernel (1/1)...
[15:00:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:00:11] ================= ttm_device (5 subtests) ==================
[15:00:11] [PASSED] ttm_device_init_basic
[15:00:11] [PASSED] ttm_device_init_multiple
[15:00:11] [PASSED] ttm_device_fini_basic
[15:00:11] [PASSED] ttm_device_init_no_vma_man
[15:00:11] ================== ttm_device_init_pools ==================
[15:00:11] [PASSED] No DMA allocations, no DMA32 required
[15:00:11] [PASSED] DMA allocations, DMA32 required
[15:00:11] [PASSED] No DMA allocations, DMA32 required
[15:00:11] [PASSED] DMA allocations, no DMA32 required
[15:00:11] ============== [PASSED] ttm_device_init_pools ==============
[15:00:11] =================== [PASSED] ttm_device ====================
[15:00:11] ================== ttm_pool (8 subtests) ===================
[15:00:11] ================== ttm_pool_alloc_basic ===================
[15:00:11] [PASSED] One page
[15:00:11] [PASSED] More than one page
[15:00:11] [PASSED] Above the allocation limit
[15:00:11] [PASSED] One page, with coherent DMA mappings enabled
[15:00:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:00:11] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:00:11] ============== ttm_pool_alloc_basic_dma_addr ==============
[15:00:11] [PASSED] One page
[15:00:11] [PASSED] More than one page
[15:00:11] [PASSED] Above the allocation limit
[15:00:11] [PASSED] One page, with coherent DMA mappings enabled
[15:00:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:00:11] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:00:11] [PASSED] ttm_pool_alloc_order_caching_match
[15:00:11] [PASSED] ttm_pool_alloc_caching_mismatch
[15:00:11] [PASSED] ttm_pool_alloc_order_mismatch
[15:00:11] [PASSED] ttm_pool_free_dma_alloc
[15:00:11] [PASSED] ttm_pool_free_no_dma_alloc
[15:00:11] [PASSED] ttm_pool_fini_basic
[15:00:11] ==================== [PASSED] ttm_pool =====================
[15:00:11] ================ ttm_resource (8 subtests) =================
[15:00:11] ================= ttm_resource_init_basic =================
[15:00:11] [PASSED] Init resource in TTM_PL_SYSTEM
[15:00:11] [PASSED] Init resource in TTM_PL_VRAM
[15:00:11] [PASSED] Init resource in a private placement
[15:00:11] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:00:11] ============= [PASSED] ttm_resource_init_basic =============
[15:00:11] [PASSED] ttm_resource_init_pinned
[15:00:11] [PASSED] ttm_resource_fini_basic
[15:00:11] [PASSED] ttm_resource_manager_init_basic
[15:00:11] [PASSED] ttm_resource_manager_usage_basic
[15:00:11] [PASSED] ttm_resource_manager_set_used_basic
[15:00:11] [PASSED] ttm_sys_man_alloc_basic
[15:00:11] [PASSED] ttm_sys_man_free_basic
[15:00:11] ================== [PASSED] ttm_resource ===================
[15:00:11] =================== ttm_tt (15 subtests) ===================
[15:00:11] ==================== ttm_tt_init_basic ====================
[15:00:11] [PASSED] Page-aligned size
[15:00:11] [PASSED] Extra pages requested
[15:00:11] ================ [PASSED] ttm_tt_init_basic ================
[15:00:11] [PASSED] ttm_tt_init_misaligned
[15:00:11] [PASSED] ttm_tt_fini_basic
[15:00:11] [PASSED] ttm_tt_fini_sg
[15:00:11] [PASSED] ttm_tt_fini_shmem
[15:00:11] [PASSED] ttm_tt_create_basic
[15:00:11] [PASSED] ttm_tt_create_invalid_bo_type
[15:00:11] [PASSED] ttm_tt_create_ttm_exists
[15:00:11] [PASSED] ttm_tt_create_failed
[15:00:11] [PASSED] ttm_tt_destroy_basic
[15:00:11] [PASSED] ttm_tt_populate_null_ttm
[15:00:11] [PASSED] ttm_tt_populate_populated_ttm
[15:00:11] [PASSED] ttm_tt_unpopulate_basic
[15:00:11] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:00:11] [PASSED] ttm_tt_swapin_basic
[15:00:11] ===================== [PASSED] ttm_tt ======================
[15:00:11] =================== ttm_bo (14 subtests) ===================
[15:00:11] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[15:00:11] [PASSED] Cannot be interrupted and sleeps
[15:00:11] [PASSED] Cannot be interrupted, locks straight away
[15:00:11] [PASSED] Can be interrupted, sleeps
[15:00:11] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:00:11] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:00:11] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:00:11] [PASSED] ttm_bo_reserve_double_resv
[15:00:11] [PASSED] ttm_bo_reserve_interrupted
[15:00:11] [PASSED] ttm_bo_reserve_deadlock
[15:00:11] [PASSED] ttm_bo_unreserve_basic
[15:00:11] [PASSED] ttm_bo_unreserve_pinned
[15:00:11] [PASSED] ttm_bo_unreserve_bulk
[15:00:11] [PASSED] ttm_bo_fini_basic
[15:00:11] [PASSED] ttm_bo_fini_shared_resv
[15:00:11] [PASSED] ttm_bo_pin_basic
[15:00:11] [PASSED] ttm_bo_pin_unpin_resource
[15:00:11] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:00:11] ===================== [PASSED] ttm_bo ======================
[15:00:11] ============== ttm_bo_validate (21 subtests) ===============
[15:00:11] ============== ttm_bo_init_reserved_sys_man ===============
[15:00:11] [PASSED] Buffer object for userspace
[15:00:11] [PASSED] Kernel buffer object
[15:00:11] [PASSED] Shared buffer object
[15:00:11] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:00:11] ============== ttm_bo_init_reserved_mock_man ==============
[15:00:11] [PASSED] Buffer object for userspace
[15:00:11] [PASSED] Kernel buffer object
[15:00:11] [PASSED] Shared buffer object
[15:00:11] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:00:11] [PASSED] ttm_bo_init_reserved_resv
[15:00:11] ================== ttm_bo_validate_basic ==================
[15:00:11] [PASSED] Buffer object for userspace
[15:00:11] [PASSED] Kernel buffer object
[15:00:11] [PASSED] Shared buffer object
[15:00:11] ============== [PASSED] ttm_bo_validate_basic ==============
[15:00:11] [PASSED] ttm_bo_validate_invalid_placement
[15:00:11] ============= ttm_bo_validate_same_placement ==============
[15:00:11] [PASSED] System manager
[15:00:11] [PASSED] VRAM manager
[15:00:11] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:00:11] [PASSED] ttm_bo_validate_failed_alloc
[15:00:11] [PASSED] ttm_bo_validate_pinned
[15:00:11] [PASSED] ttm_bo_validate_busy_placement
[15:00:11] ================ ttm_bo_validate_multihop =================
[15:00:11] [PASSED] Buffer object for userspace
[15:00:11] [PASSED] Kernel buffer object
[15:00:11] [PASSED] Shared buffer object
[15:00:11] ============ [PASSED] ttm_bo_validate_multihop =============
[15:00:11] ========== ttm_bo_validate_no_placement_signaled ==========
[15:00:11] [PASSED] Buffer object in system domain, no page vector
[15:00:11] [PASSED] Buffer object in system domain with an existing page vector
[15:00:11] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:00:11] ======== ttm_bo_validate_no_placement_not_signaled ========
[15:00:11] [PASSED] Buffer object for userspace
[15:00:11] [PASSED] Kernel buffer object
[15:00:11] [PASSED] Shared buffer object
[15:00:11] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:00:11] [PASSED] ttm_bo_validate_move_fence_signaled
[15:00:11] ========= ttm_bo_validate_move_fence_not_signaled =========
[15:00:11] [PASSED] Waits for GPU
[15:00:11] [PASSED] Tries to lock straight away
[15:00:11] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:00:11] [PASSED] ttm_bo_validate_happy_evict
[15:00:11] [PASSED] ttm_bo_validate_all_pinned_evict
[15:00:11] [PASSED] ttm_bo_validate_allowed_only_evict
[15:00:11] [PASSED] ttm_bo_validate_deleted_evict
[15:00:11] [PASSED] ttm_bo_validate_busy_domain_evict
[15:00:11] [PASSED] ttm_bo_validate_evict_gutting
[15:00:11] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[15:00:11] ================= [PASSED] ttm_bo_validate =================
[15:00:11] ============================================================
[15:00:11] Testing complete. Ran 101 tests: passed: 101
[15:00:11] Elapsed time: 11.272s total, 1.705s configuring, 9.351s building, 0.189s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* ✗ CI.checksparse: warning for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (18 preceding siblings ...)
2025-11-05 15:00 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-05 15:15 ` Patchwork
2025-11-05 15:45 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-05 22:42 ` ✗ Xe.CI.Full: failure " Patchwork
21 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-11-05 15:15 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
URL : https://patchwork.freedesktop.org/series/157072/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 16a75a91c651f103f022b6b3c6ca29b13205cc9b
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1605:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_gpu_error.c:692:3: warning: symbol 'guc_hw_reg_state' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* ✓ Xe.CI.BAT: success for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (19 preceding siblings ...)
2025-11-05 15:15 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-11-05 15:45 ` Patchwork
2025-11-05 22:42 ` ✗ Xe.CI.Full: failure " Patchwork
21 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-11-05 15:45 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2234 bytes --]
== Series Details ==
Series: Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
URL : https://patchwork.freedesktop.org/series/157072/
State : success
== Summary ==
CI Bug Log - changes from xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc_BAT -> xe-pw-157072v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-157072v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-plain-flip@b-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
#### Possible fixes ####
* igt@kms_flip@basic-plain-flip@c-edp1:
- bat-adlp-7: [DMESG-WARN][3] ([Intel XE#4543]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [FAIL][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/bat-dg2-oem2/igt@xe_waitfence@engine.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/bat-dg2-oem2/igt@xe_waitfence@engine.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc -> xe-pw-157072v1
IGT_8607: 8607
xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc: 8043455e28fb7b8089e55e4390547a4c3d7bd4dc
xe-pw-157072v1: 157072v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/index.html
[-- Attachment #2: Type: text/html, Size: 2938 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* ✗ Xe.CI.Full: failure for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
` (20 preceding siblings ...)
2025-11-05 15:45 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-11-05 22:42 ` Patchwork
2025-11-06 21:13 ` Gustavo Sousa
21 siblings, 1 reply; 24+ messages in thread
From: Patchwork @ 2025-11-05 22:42 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 56141 bytes --]
== Series Details ==
Series: Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD
URL : https://patchwork.freedesktop.org/series/157072/
State : failure
== Summary ==
CI Bug Log - changes from xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc_FULL -> xe-pw-157072v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157072v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157072v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157072v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@cursor-random-256x256@pipe-d-hdmi-a-6:
- shard-dg2-set2: [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-432/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-hdmi-a-6.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-436/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-hdmi-a-6.html
Known issues
------------
Here are the changes found in xe-pw-157072v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#2233])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][4] ([Intel XE#1407])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][5] ([Intel XE#316])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#610])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][7] ([Intel XE#1124])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-bmg: [PASS][10] -> [SKIP][11] ([Intel XE#2314] / [Intel XE#2894])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-3-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#367])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-3-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][13] ([Intel XE#367])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-adlp: NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][15] ([Intel XE#787]) +2 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2887]) +5 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#2887]) +2 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [PASS][18] -> [INCOMPLETE][19] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522] / [Intel XE#4842])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: [PASS][20] -> [INCOMPLETE][21] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#4842])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-adlp: NOTRUN -> [SKIP][22] ([Intel XE#373]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2252]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#373]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_content_protection@content-type-change:
- shard-adlp: NOTRUN -> [SKIP][25] ([Intel XE#455]) +5 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@legacy:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2341])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][27] ([Intel XE#1178]) +1 other test fail
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-1/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#308])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2320])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2321])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-64x21:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#1424])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_cursor_crc@cursor-sliding-64x21.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-bmg: [PASS][32] -> [SKIP][33] ([Intel XE#2291]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#309])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2291])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#309]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [PASS][37] -> [SKIP][38] ([Intel XE#4302])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#4422])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-bmg: [PASS][40] -> [SKIP][41] ([Intel XE#2316]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2316]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#1421])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
- shard-adlp: [PASS][44] -> [DMESG-WARN][45] ([Intel XE#4543]) +5 other tests dmesg-warn
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-3/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-2/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][46] -> [FAIL][47] ([Intel XE#301])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [PASS][48] -> [FAIL][49] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][50] ([Intel XE#2049] / [Intel XE#2597])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-432/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2293]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2311]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#651])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2312]) +14 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#656]) +7 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@drrs-modesetfrombusy:
- shard-adlp: NOTRUN -> [SKIP][57] ([Intel XE#651])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#6313]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-adlp: [PASS][59] -> [DMESG-WARN][60] ([Intel XE#2953] / [Intel XE#4173]) +4 other tests dmesg-warn
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#5390])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#651]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#653]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-adlp: NOTRUN -> [SKIP][64] ([Intel XE#653])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#2313]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#656]) +1 other test skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#3374] / [Intel XE#3544])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#4298])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_plane_multiple@tiling-x@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [FAIL][69] ([Intel XE#4658]) +3 other tests fail
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_plane_multiple@tiling-x@pipe-b-edp-1.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-lnl: NOTRUN -> [SKIP][70] ([Intel XE#3309])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-lnl: NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#2893])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-psr2-suspend@edp-1:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#4609])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@kms_psr@fbc-psr2-suspend@edp-1.html
* igt@kms_psr@pr-primary-page-flip:
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#1406]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@kms_psr@pr-primary-page-flip.html
* igt@kms_psr@psr-basic:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_psr@psr-basic.html
* igt@kms_psr@psr2-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_psr@psr2-dpms.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][77] ([Intel XE#3414] / [Intel XE#3904])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#2330])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [PASS][79] -> [SKIP][80] ([Intel XE#1435])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@xe_compute_preempt@compute-threadgroup-preempt:
- shard-adlp: NOTRUN -> [SKIP][81] ([Intel XE#6360])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@xe_compute_preempt@compute-threadgroup-preempt.html
* igt@xe_eudebug@discovery-race-vmbind:
- shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#4837])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_eudebug@discovery-race-vmbind.html
* igt@xe_eudebug@read-metadata:
- shard-lnl: NOTRUN -> [SKIP][83] ([Intel XE#4837]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@xe_eudebug@read-metadata.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#4837]) +4 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
- shard-adlp: NOTRUN -> [SKIP][85] ([Intel XE#4837] / [Intel XE#5565]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
* igt@xe_evict@evict-beng-large-external-cm:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#688]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@xe_evict@evict-beng-large-external-cm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2322]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html
* igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
- shard-lnl: NOTRUN -> [SKIP][88] ([Intel XE#1392]) +3 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
* igt@xe_exec_fault_mode@once-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][89] ([Intel XE#288]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_exec_fault_mode@once-rebind-imm.html
* igt@xe_exec_reset@cm-close-fd:
- shard-adlp: [PASS][90] -> [DMESG-WARN][91] ([Intel XE#3868])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-2/igt@xe_exec_reset@cm-close-fd.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-3/igt@xe_exec_reset@cm-close-fd.html
* igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#5007])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#4915]) +19 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset.html
* igt@xe_exec_system_allocator@many-large-execqueues-mmap-race:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#4915]) +19 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@xe_exec_system_allocator@many-large-execqueues-mmap-race.html
* igt@xe_exec_system_allocator@many-mmap-free-huge:
- shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#4943]) +2 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@xe_exec_system_allocator@many-mmap-free-huge.html
* igt@xe_exec_system_allocator@many-stride-malloc-prefetch:
- shard-bmg: [PASS][96] -> [WARN][97] ([Intel XE#5786])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-4/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-5/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#4943]) +9 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-prefetch:
- shard-bmg: [PASS][99] -> [ABORT][100] ([Intel XE#3970])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-prefetch.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-prefetch.html
* igt@xe_module_load@load:
- shard-dg2-set2: ([PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125]) -> ([PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [SKIP][149], [PASS][150], [PASS][151]) ([Intel XE#378])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-436/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-436/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-436/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-432/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-432/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-466/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-464/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-466/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-434/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-466/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-435/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-435/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-464/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-464/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-435/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-435/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-466/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-432/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-436/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-436/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-436/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-432/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-435/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-434/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-434/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-434/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-435/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-464/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-464/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-435/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-432/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-432/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-464/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-435/igt@xe_module_load@load.html
* igt@xe_oa@non-zero-reason:
- shard-adlp: NOTRUN -> [SKIP][152] ([Intel XE#3573])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@xe_oa@non-zero-reason.html
* igt@xe_oa@rc6-disable:
- shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#3573])
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_oa@rc6-disable.html
* igt@xe_pm@d3hot-i2c:
- shard-dg2-set2: NOTRUN -> [SKIP][154] ([Intel XE#5742])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s3-mocs:
- shard-lnl: NOTRUN -> [SKIP][155] ([Intel XE#584])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@xe_pm@s3-mocs.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0:
- shard-lnl: [PASS][156] -> [FAIL][157] ([Intel XE#6251])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
* igt@xe_pxp@pxp-stale-queue-post-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][158] ([Intel XE#4733])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@xe_pxp@pxp-stale-queue-post-suspend.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-bmg: NOTRUN -> [SKIP][159] ([Intel XE#944]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
* igt@xe_sriov_flr@flr-vfs-parallel:
- shard-lnl: NOTRUN -> [SKIP][160] ([Intel XE#4273])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-5/igt@xe_sriov_flr@flr-vfs-parallel.html
* igt@xe_vm@out-of-memory:
- shard-adlp: NOTRUN -> [SKIP][161] ([Intel XE#5745])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@xe_vm@out-of-memory.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
- shard-adlp: [DMESG-WARN][162] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][163] +3 other tests pass
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-8/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [SKIP][164] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [INCOMPLETE][166] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522] / [Intel XE#4842]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
- shard-dg2-set2: [INCOMPLETE][168] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#4842]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-bmg: [SKIP][170] ([Intel XE#2291]) -> [PASS][171] +2 other tests pass
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_fbcon_fbt@fbc:
- shard-dg2-set2: [FAIL][172] ([Intel XE#4164]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-466/igt@kms_fbcon_fbt@fbc.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-436/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [SKIP][174] ([Intel XE#2316]) -> [PASS][175] +5 other tests pass
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-8/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: [INCOMPLETE][176] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][177] +2 other tests pass
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-adlp: [ABORT][178] ([Intel XE#2953]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][180] ([Intel XE#455]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@kms_hdr@invalid-hdr.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-bmg: [SKIP][182] ([Intel XE#1503]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [SKIP][184] ([Intel XE#3012]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm:
- shard-lnl: [INCOMPLETE][186] ([Intel XE#2594]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-lnl-1/igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-7/igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
- shard-lnl: [FAIL][188] ([Intel XE#6251]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
#### Warnings ####
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][190] ([Intel XE#2341]) -> [FAIL][191] ([Intel XE#1178]) +1 other test fail
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][192] ([Intel XE#2312]) -> [SKIP][193] ([Intel XE#2311]) +10 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][194] ([Intel XE#2312]) -> [SKIP][195] ([Intel XE#5390]) +5 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][196] ([Intel XE#5390]) -> [SKIP][197] ([Intel XE#2312]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][198] ([Intel XE#2311]) -> [SKIP][199] ([Intel XE#2312]) +5 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: [SKIP][200] ([Intel XE#2313]) -> [SKIP][201] ([Intel XE#2312]) +5 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][202] ([Intel XE#2312]) -> [SKIP][203] ([Intel XE#2313]) +11 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: [SKIP][204] ([Intel XE#5021]) -> [SKIP][205] ([Intel XE#4596])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][206] ([Intel XE#2426]) -> [FAIL][207] ([Intel XE#1729])
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: [FAIL][208] ([Intel XE#1729]) -> [SKIP][209] ([Intel XE#362])
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][210] ([Intel XE#362]) -> [SKIP][211] ([Intel XE#1500])
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-adlp: [DMESG-FAIL][212] ([Intel XE#3868] / [Intel XE#5213] / [Intel XE#5545]) -> [DMESG-FAIL][213] ([Intel XE#3868] / [Intel XE#5213]) +1 other test dmesg-fail
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc/shard-adlp-3/igt@xe_sriov_scheduling@equal-throughput.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/shard-adlp-1/igt@xe_sriov_scheduling@equal-throughput.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
[Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
[Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4658
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
[Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc -> xe-pw-157072v1
IGT_8607: 8607
xe-4048-8043455e28fb7b8089e55e4390547a4c3d7bd4dc: 8043455e28fb7b8089e55e4390547a4c3d7bd4dc
xe-pw-157072v1: 157072v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157072v1/index.html
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