From: Matt Atwood <matthew.s.atwood@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Suraj Kandpal <suraj.kandpal@intel.com>,
Matt Atwood <matthew.s.atwood@intel.com>
Subject: [PATCH 09/12] drm/i915/xe3lpd: Increase max_h max_v for PSR
Date: Fri, 18 Oct 2024 13:49:38 -0700 [thread overview]
Message-ID: <20241018204941.73473-10-matthew.s.atwood@intel.com> (raw)
In-Reply-To: <20241018204941.73473-1-matthew.s.atwood@intel.com>
From: Suraj Kandpal <suraj.kandpal@intel.com>
Spec states that PSR max active is same as max pipe active values.
Now that each pipe supports 6k resolution increasing max_h and
max_v for PSR too.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3b20325b3f6a..16dbc8caef5f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1451,7 +1451,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (DISPLAY_VER(display) >= 12) {
+ if (DISPLAY_VER(display) >= 30) {
+ psr_max_h = 6144;
+ psr_max_v = 4096;
+ max_bpp = 30;
+ } else if (DISPLAY_VER(display) >= 12) {
psr_max_h = 5120;
psr_max_v = 3200;
max_bpp = 30;
--
2.45.0
next prev parent reply other threads:[~2024-10-18 20:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 20:49 [PATCH 00/12] drm/i915/xe3lpd: ptl display patches Matt Atwood
2024-10-18 20:49 ` [PATCH 01/12] drm/i915/display/ptl: Fill VRR crtc_state timings before other transcoder timings Matt Atwood
2024-10-18 23:43 ` Matt Roper
2024-10-22 4:37 ` Golani, Mitulkumar Ajitkumar
2024-10-18 20:49 ` [PATCH 02/12] drm/i915/ptl: Define IS_PANTHERLAKE macro Matt Atwood
2024-10-18 23:45 ` Matt Roper
2024-10-18 20:49 ` [PATCH 03/12] drm/i915/cx0: Extend C10 check to PTL Matt Atwood
2024-10-21 11:58 ` Gustavo Sousa
2024-10-21 12:02 ` Jani Nikula
2024-10-18 20:49 ` [PATCH 04/12] drm/i915/ptl: Move async flip bit to PLANE_SURF register Matt Atwood
2024-10-18 23:49 ` Matt Roper
2024-10-18 20:49 ` [PATCH 05/12] drm/i915/xe3: Underrun recovery does not exist post Xe2 Matt Atwood
2024-10-18 23:53 ` Matt Roper
2024-10-18 20:49 ` [PATCH 06/12] drm/i915/display/xe3: disable x-tiled framebuffers Matt Atwood
2024-10-21 12:25 ` Gustavo Sousa
2024-10-18 20:49 ` [PATCH 07/12] drm/i915/xe3lpd: Skip disabling VRR during modeset disable Matt Atwood
2024-10-18 20:49 ` [PATCH 08/12] drm/i915/xe3lpd: Increase resolution for plane to support 6k Matt Atwood
2024-10-19 7:07 ` Kandpal, Suraj
2024-10-18 20:49 ` Matt Atwood [this message]
2024-10-18 20:49 ` [PATCH 10/12] drm/i915/xe3lpd: Increase bigjoiner limitations Matt Atwood
2024-10-18 20:49 ` [PATCH 11/12] drm/i915/xe3lpd: Prune modes for YUV420 Matt Atwood
2024-10-18 20:49 ` [PATCH 12/12] drm/i915/xe3lpd: Power request asserting/deasserting Matt Atwood
2024-10-21 12:08 ` Jani Nikula
2024-10-21 12:30 ` Gustavo Sousa
2024-10-21 13:03 ` Kahola, Mika
2024-10-23 20:39 ` Gustavo Sousa
2024-10-28 9:11 ` Kahola, Mika
2024-10-18 22:08 ` ✓ CI.Patch_applied: success for drm/i915/xe3lpd: ptl display patches Patchwork
2024-10-18 22:09 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-18 22:10 ` ✓ CI.KUnit: success " Patchwork
2024-10-18 22:21 ` ✓ CI.Build: " Patchwork
2024-10-18 22:24 ` ✓ CI.Hooks: " Patchwork
2024-10-18 22:25 ` ✗ CI.checksparse: warning " Patchwork
2024-10-18 22:44 ` ✗ CI.BAT: failure " Patchwork
2024-10-19 15:34 ` ✗ CI.FULL: " Patchwork
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