Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Matt Roper <matthew.d.roper@intel.com>
To: Matt Atwood <matthew.s.atwood@intel.com>
Cc: <intel-gfx@lists.freedesktop.org>,
	<intel-xe@lists.freedesktop.org>,
	Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
	Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: Re: [PATCH 01/12] drm/i915/display/ptl: Fill VRR crtc_state timings before other transcoder timings
Date: Fri, 18 Oct 2024 16:43:59 -0700	[thread overview]
Message-ID: <20241018234359.GF4891@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20241018204941.73473-2-matthew.s.atwood@intel.com>

On Fri, Oct 18, 2024 at 01:49:30PM -0700, Matt Atwood wrote:
> From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> 
> In progress to make VRR timing generator as the default timing generator,
> rest other timings will be derived based on vrr.vmin and vrr.vmax. Call

I'm having trouble following what this first sentence is trying to say;
I think it might be missing some words?  Can you reword it to be more
clear?

We may want to elaborate more on what "VRR timing generator as the
default timing generator" means and how/why that's happening.


Matt

> intel_vrr_get_config before intel_get_transcoder_timings to accomodate
> values getting pre-filled.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ef1436146325..01466611eebe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4134,13 +4134,13 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>  	intel_joiner_get_config(pipe_config);
>  	intel_dsc_get_config(pipe_config);
>  
> +	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
> +		intel_vrr_get_config(pipe_config);
> +
>  	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
>  	    DISPLAY_VER(dev_priv) >= 11)
>  		intel_get_transcoder_timings(crtc, pipe_config);
>  
> -	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
> -		intel_vrr_get_config(pipe_config);
> -
>  	intel_get_pipe_src_size(crtc, pipe_config);
>  
>  	if (IS_HASWELL(dev_priv)) {
> -- 
> 2.45.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

  reply	other threads:[~2024-10-18 23:44 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-18 20:49 [PATCH 00/12] drm/i915/xe3lpd: ptl display patches Matt Atwood
2024-10-18 20:49 ` [PATCH 01/12] drm/i915/display/ptl: Fill VRR crtc_state timings before other transcoder timings Matt Atwood
2024-10-18 23:43   ` Matt Roper [this message]
2024-10-22  4:37     ` Golani, Mitulkumar Ajitkumar
2024-10-18 20:49 ` [PATCH 02/12] drm/i915/ptl: Define IS_PANTHERLAKE macro Matt Atwood
2024-10-18 23:45   ` Matt Roper
2024-10-18 20:49 ` [PATCH 03/12] drm/i915/cx0: Extend C10 check to PTL Matt Atwood
2024-10-21 11:58   ` Gustavo Sousa
2024-10-21 12:02     ` Jani Nikula
2024-10-18 20:49 ` [PATCH 04/12] drm/i915/ptl: Move async flip bit to PLANE_SURF register Matt Atwood
2024-10-18 23:49   ` Matt Roper
2024-10-18 20:49 ` [PATCH 05/12] drm/i915/xe3: Underrun recovery does not exist post Xe2 Matt Atwood
2024-10-18 23:53   ` Matt Roper
2024-10-18 20:49 ` [PATCH 06/12] drm/i915/display/xe3: disable x-tiled framebuffers Matt Atwood
2024-10-21 12:25   ` Gustavo Sousa
2024-10-18 20:49 ` [PATCH 07/12] drm/i915/xe3lpd: Skip disabling VRR during modeset disable Matt Atwood
2024-10-18 20:49 ` [PATCH 08/12] drm/i915/xe3lpd: Increase resolution for plane to support 6k Matt Atwood
2024-10-19  7:07   ` Kandpal, Suraj
2024-10-18 20:49 ` [PATCH 09/12] drm/i915/xe3lpd: Increase max_h max_v for PSR Matt Atwood
2024-10-18 20:49 ` [PATCH 10/12] drm/i915/xe3lpd: Increase bigjoiner limitations Matt Atwood
2024-10-18 20:49 ` [PATCH 11/12] drm/i915/xe3lpd: Prune modes for YUV420 Matt Atwood
2024-10-18 20:49 ` [PATCH 12/12] drm/i915/xe3lpd: Power request asserting/deasserting Matt Atwood
2024-10-21 12:08   ` Jani Nikula
2024-10-21 12:30   ` Gustavo Sousa
2024-10-21 13:03     ` Kahola, Mika
2024-10-23 20:39   ` Gustavo Sousa
2024-10-28  9:11     ` Kahola, Mika
2024-10-18 22:08 ` ✓ CI.Patch_applied: success for drm/i915/xe3lpd: ptl display patches Patchwork
2024-10-18 22:09 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-18 22:10 ` ✓ CI.KUnit: success " Patchwork
2024-10-18 22:21 ` ✓ CI.Build: " Patchwork
2024-10-18 22:24 ` ✓ CI.Hooks: " Patchwork
2024-10-18 22:25 ` ✗ CI.checksparse: warning " Patchwork
2024-10-18 22:44 ` ✗ CI.BAT: failure " Patchwork
2024-10-19 15:34 ` ✗ CI.FULL: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20241018234359.GF4891@mdroper-desk1.amr.corp.intel.com \
    --to=matthew.d.roper@intel.com \
    --cc=ankit.k.nautiyal@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=matthew.s.atwood@intel.com \
    --cc=mitulkumar.ajitkumar.golani@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox