From: Matt Atwood <matthew.s.atwood@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>,
Matt Atwood <matthew.s.atwood@intel.com>
Subject: [PATCH 03/12] drm/i915/cx0: Extend C10 check to PTL
Date: Fri, 18 Oct 2024 13:49:32 -0700 [thread overview]
Message-ID: <20241018204941.73473-4-matthew.s.atwood@intel.com> (raw)
In-Reply-To: <20241018204941.73473-1-matthew.s.atwood@intel.com>
From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
When deciding the type of the phy, Add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 +++++++--
| 1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 13a99f494680..73a151c81706 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -34,6 +34,9 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
+ if (IS_PANTHERLAKE(i915) && phy == PHY_A)
+ return true;
+
if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
return true;
@@ -221,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
* down and let the message bus to end up
* in a known state
*/
- intel_cx0_bus_reset(encoder, lane);
+ if (DISPLAY_VER(i915) < 30)
+ intel_cx0_bus_reset(encoder, lane);
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
}
@@ -310,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
* down and let the message bus to end up
* in a known state
*/
- intel_cx0_bus_reset(encoder, lane);
+ if (DISPLAY_VER(i915) < 30)
+ intel_cx0_bus_reset(encoder, lane);
return 0;
}
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index b7041b578e5e..bd8c3de57dcd 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -67,6 +67,7 @@ static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE)
+#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE)
#define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
#define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
--
2.45.0
next prev parent reply other threads:[~2024-10-18 20:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 20:49 [PATCH 00/12] drm/i915/xe3lpd: ptl display patches Matt Atwood
2024-10-18 20:49 ` [PATCH 01/12] drm/i915/display/ptl: Fill VRR crtc_state timings before other transcoder timings Matt Atwood
2024-10-18 23:43 ` Matt Roper
2024-10-22 4:37 ` Golani, Mitulkumar Ajitkumar
2024-10-18 20:49 ` [PATCH 02/12] drm/i915/ptl: Define IS_PANTHERLAKE macro Matt Atwood
2024-10-18 23:45 ` Matt Roper
2024-10-18 20:49 ` Matt Atwood [this message]
2024-10-21 11:58 ` [PATCH 03/12] drm/i915/cx0: Extend C10 check to PTL Gustavo Sousa
2024-10-21 12:02 ` Jani Nikula
2024-10-18 20:49 ` [PATCH 04/12] drm/i915/ptl: Move async flip bit to PLANE_SURF register Matt Atwood
2024-10-18 23:49 ` Matt Roper
2024-10-18 20:49 ` [PATCH 05/12] drm/i915/xe3: Underrun recovery does not exist post Xe2 Matt Atwood
2024-10-18 23:53 ` Matt Roper
2024-10-18 20:49 ` [PATCH 06/12] drm/i915/display/xe3: disable x-tiled framebuffers Matt Atwood
2024-10-21 12:25 ` Gustavo Sousa
2024-10-18 20:49 ` [PATCH 07/12] drm/i915/xe3lpd: Skip disabling VRR during modeset disable Matt Atwood
2024-10-18 20:49 ` [PATCH 08/12] drm/i915/xe3lpd: Increase resolution for plane to support 6k Matt Atwood
2024-10-19 7:07 ` Kandpal, Suraj
2024-10-18 20:49 ` [PATCH 09/12] drm/i915/xe3lpd: Increase max_h max_v for PSR Matt Atwood
2024-10-18 20:49 ` [PATCH 10/12] drm/i915/xe3lpd: Increase bigjoiner limitations Matt Atwood
2024-10-18 20:49 ` [PATCH 11/12] drm/i915/xe3lpd: Prune modes for YUV420 Matt Atwood
2024-10-18 20:49 ` [PATCH 12/12] drm/i915/xe3lpd: Power request asserting/deasserting Matt Atwood
2024-10-21 12:08 ` Jani Nikula
2024-10-21 12:30 ` Gustavo Sousa
2024-10-21 13:03 ` Kahola, Mika
2024-10-23 20:39 ` Gustavo Sousa
2024-10-28 9:11 ` Kahola, Mika
2024-10-18 22:08 ` ✓ CI.Patch_applied: success for drm/i915/xe3lpd: ptl display patches Patchwork
2024-10-18 22:09 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-18 22:10 ` ✓ CI.KUnit: success " Patchwork
2024-10-18 22:21 ` ✓ CI.Build: " Patchwork
2024-10-18 22:24 ` ✓ CI.Hooks: " Patchwork
2024-10-18 22:25 ` ✗ CI.checksparse: warning " Patchwork
2024-10-18 22:44 ` ✗ CI.BAT: failure " Patchwork
2024-10-19 15:34 ` ✗ CI.FULL: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241018204941.73473-4-matthew.s.atwood@intel.com \
--to=matthew.s.atwood@intel.com \
--cc=dnyaneshwar.bhadane@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox