* [PATCH v3 0/3] dGPU memory optimizations
@ 2026-02-18 4:33 Matthew Brost
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
` (11 more replies)
0 siblings, 12 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-18 4:33 UTC (permalink / raw)
To: intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
Profiling has shown that reading from VRAM on BMG is very slow and
introduces significant latency in GuC CT operations. To address this,
CPU-side read buffers (G2H) are moved to system memory, and unnecessary
CPU reads of VRAM in H2G paths are removed. This results in roughly a
50× improvement in page-fault G2H read latency and a 10× improvement in
H2G send latency (observed in ftrace) These optimizations have produced
noticeable improvements in page-fault UMD benchmarks.
Also move the seqno LRC to system memory. The performance impact of this
has not been measured, but based on GuC behavior, the HW fence signaling
path should see a noticeable speedup.
Matt
v2:
- Fix devcoredump explosion (Testing)
v3:
- Drop fixes tags
- Address Michal's comments
- Fix H2G tracepoint to avoid unconditional VRAM read
- Move LRC seqno to system memory
Matthew Brost (3):
drm/xe: Split H2G and G2H into separate buffer objects
drm/xe: Avoid unconditional VRAM reads in H2G path
drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
drivers/gpu/drm/xe/xe_guc_ct.c | 92 ++++++++++++++++++----------
drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
drivers/gpu/drm/xe/xe_lrc.c | 57 ++++++++++-------
drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++
4 files changed, 105 insertions(+), 54 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
@ 2026-02-18 4:33 ` Matthew Brost
2026-02-18 23:12 ` Summers, Stuart
2026-02-24 15:58 ` Thomas Hellström
2026-02-18 4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
` (10 subsequent siblings)
11 siblings, 2 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-18 4:33 UTC (permalink / raw)
To: intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
H2G and G2H buffers have different access patterns (H2G is CPU-write,
GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
benefit from different memory placements: H2G in VRAM and G2H in system
memory. Split the CT buffer into two separate buffers—one for H2G and
one for G2H—and select the optimal placement for each.
This provides a significant performance improvement on the G2H read
path, reducing a single read from ~20 µs to under 1 µs on BMG.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
v3:
- Move BO to ctbs h2g or g2h structure (Michal)
---
drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++---------
drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
2 files changed, 47 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 8a45573f8812..ea07a27757d5 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
#define CTB_DESC_SIZE ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
#define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
+#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
#define CTB_H2G_BUFFER_SIZE (SZ_4K)
#define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE / sizeof(u32))
#define CTB_G2H_BUFFER_SIZE (SZ_128K)
@@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
}
-static size_t guc_ct_size(void)
+static size_t guc_h2g_size(void)
{
- return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
- CTB_G2H_BUFFER_SIZE;
+ return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
+}
+
+static size_t guc_g2h_size(void)
+{
+ return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
}
static void guc_ct_fini(struct drm_device *drm, void *arg)
@@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
struct xe_gt *gt = ct_to_gt(ct);
int err;
- xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
+ xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
+ xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
err = drmm_mutex_init(&xe->drm, &ct->lock);
if (err)
@@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
struct xe_tile *tile = gt_to_tile(gt);
struct xe_bo *bo;
- bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
+ bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ ct->ctbs.h2g.bo = bo;
+
+ bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
XE_BO_FLAG_SYSTEM |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_GGTT_INVALIDATE |
@@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
if (IS_ERR(bo))
return PTR_ERR(bo);
- ct->bo = bo;
+ ct->ctbs.g2h.bo = bo;
return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
}
@@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
xe_assert(xe, !xe_guc_ct_enabled(ct));
if (IS_DGFX(xe)) {
- ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
+ ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->ctbs.h2g.bo);
if (ret)
return ret;
}
@@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
- g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
- CTB_H2G_BUFFER_SIZE);
+ g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
}
static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
@@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
u32 desc_addr, ctb_addr, size;
int err;
- desc_addr = xe_bo_ggtt_addr(ct->bo);
- ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
+ desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
+ ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) + CTB_H2G_BUFFER_OFFSET;
size = ct->ctbs.h2g.info.size * sizeof(u32);
err = xe_guc_self_cfg64(guc,
@@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
u32 desc_addr, ctb_addr, size;
int err;
- desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
- ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
- CTB_H2G_BUFFER_SIZE;
+ desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) + CTB_DESC_SIZE;
+ ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) + CTB_G2H_BUFFER_OFFSET;
size = ct->ctbs.g2h.info.size * sizeof(u32);
err = xe_guc_self_cfg64(guc,
@@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
if (needs_register) {
- xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
- guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
- guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
+ xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
+ xe_bo_size(ct->ctbs.h2g.bo));
+ xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
+ xe_bo_size(ct->ctbs.g2h.bo));
+ guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->ctbs.h2g.bo->vmap);
+ guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->ctbs.g2h.bo->vmap);
err = guc_ct_ctb_h2g_register(ct);
if (err)
@@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
ct->ctbs.h2g.info.broken = false;
ct->ctbs.g2h.info.broken = false;
/* Skip everything in H2G buffer */
- xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
+ xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
CTB_H2G_BUFFER_SIZE);
}
@@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
if (!snapshot)
return NULL;
- if (ct->bo && want_ctb) {
- snapshot->ctb_size = xe_bo_size(ct->bo);
+ if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
+ snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo) +
+ xe_bo_size(ct->ctbs.g2h.bo);
snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
}
@@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
}
- if (ct->bo && snapshot->ctb)
- xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
+ if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb) {
+ xe_map_memcpy_from(xe, snapshot->ctb, &ct->ctbs.h2g.bo->vmap, 0,
+ xe_bo_size(ct->ctbs.h2g.bo));
+ xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->ctbs.h2g.bo),
+ &ct->ctbs.g2h.bo->vmap, 0,
+ xe_bo_size(ct->ctbs.g2h.bo));
+ }
return snapshot;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
index 09d7ff1ef42a..46ad1402347d 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
@@ -39,6 +39,8 @@ struct guc_ctb_info {
* struct guc_ctb - GuC command transport buffer (CTB)
*/
struct guc_ctb {
+ /** @bo: Xe BO for CTB */
+ struct xe_bo *bo;
/** @desc: dma buffer map for CTB descriptor */
struct iosys_map desc;
/** @cmds: dma buffer map for CTB commands */
@@ -126,8 +128,6 @@ struct xe_fast_req_fence {
* for the H2G and G2H requests sent and received through the buffers.
*/
struct xe_guc_ct {
- /** @bo: Xe BO for CT */
- struct xe_bo *bo;
/** @lock: protects everything in CT layer */
struct mutex lock;
/** @fast_lock: protects G2H channel and credits */
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
@ 2026-02-18 4:33 ` Matthew Brost
2026-02-18 23:20 ` Summers, Stuart
2026-02-26 12:47 ` Thomas Hellström
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
` (9 subsequent siblings)
11 siblings, 2 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-18 4:33 UTC (permalink / raw)
To: intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
desc_read() issues an VRAM read which serializes the CPU and drains
posted writes on dGPU platforms. The H2G tracepoint evaluated its
arguments unconditionally, so even with tracing disabled the submission
path paid the full VRAM readf latency. Guard the tracepoint with
trace_xe_guc_ctb_h2g_enabled().
Adso move the descriptor status verification under CONFIG_DRM_XE_DEBUG.
This removes another unnecessary VRAM read in non-debug builfds.
This results in ~10× faster H2G submission and significantly reduces
lock contention across the driver.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ct.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index ea07a27757d5..37842c93e0ee 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
u32 full_len;
struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
tail * sizeof(u32));
- u32 desc_status;
full_len = len + GUC_CTB_HDR_LEN;
lockdep_assert_held(&ct->lock);
xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
- desc_status = desc_read(xe, h2g, status);
- if (desc_status) {
- xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
- goto corrupted;
- }
-
if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
u32 desc_tail = desc_read(xe, h2g, tail);
u32 desc_head = desc_read(xe, h2g, head);
+ u32 desc_status;
+
+ desc_status = desc_read(xe, h2g, status);
+ if (desc_status) {
+ xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
+ goto corrupted;
+ }
if (tail != desc_tail) {
desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
@@ -1023,8 +1023,15 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
/* Update descriptor */
desc_write(xe, h2g, tail, h2g->info.tail);
- trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1), full_len,
- desc_read(xe, h2g, head), h2g->info.tail);
+ /*
+ * desc_read() performs an VRAM read which serializes the CPU and drains
+ * posted writes on dGPU platforms. Tracepoints evaluate arguments even
+ * when disabled, so guard the event to avoid adding µs-scale latency to
+ * the fast H2G submission path when tracing is not active.
+ */
+ if (trace_xe_guc_ctb_h2g_enabled())
+ trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1), full_len,
+ desc_read(xe, h2g, head), h2g->info.tail);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-18 4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
@ 2026-02-18 4:33 ` Matthew Brost
2026-02-24 2:40 ` Matthew Brost
` (2 more replies)
2026-02-18 4:40 ` ✓ CI.KUnit: success for dGPU memory optimizations Patchwork
` (8 subsequent siblings)
11 siblings, 3 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-18 4:33 UTC (permalink / raw)
To: intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
The LRC seqno is read by the CPU in the fence signaling path. On dGPU
that read can turn into a PCIe transaction when the seqno lives in the
main LRC BO, making the hot-path poll/peek much more expensive.
Allocate a small dedicated seqno BO in system memory and map the seqno
and start_seqno fields from there instead. The GPU still updates the
values, but CPU reads stay in cached system memory and avoid PCIe read
latency.
Update the LRC map/address helpers to accept a BO expression and use the
new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
teardown.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++------------
drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
2 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 38f648b98868..d72146313424 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
#define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
#define __xe_lrc_regs_offset xe_lrc_regs_offset
-#define LRC_SEQNO_PPHWSP_OFFSET 512
-#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
-#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
+#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
#define LRC_PARALLEL_PPHWSP_OFFSET 2048
+#define LRC_SEQNO_OFFSET 0
+#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
+
u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
{
return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
@@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
{
- /* The seqno is stored in the driver-defined portion of PPHWSP */
- return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
+ return LRC_SEQNO_OFFSET;
}
static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
{
- /* The start seqno is stored in the driver-defined portion of PPHWSP */
- return xe_lrc_pphwsp_offset(lrc) + LRC_START_SEQNO_PPHWSP_OFFSET;
+ return LRC_START_SEQNO_OFFSET;
}
static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
@@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct xe_lrc *lrc)
return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
}
-#define DECL_MAP_ADDR_HELPERS(elem) \
+#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
{ \
- struct iosys_map map = lrc->bo->vmap; \
+ struct xe_bo *bo = (bo_expr); \
+ struct iosys_map map = bo->vmap; \
\
xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
@@ -816,20 +816,22 @@ static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
} \
static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct xe_lrc *lrc) \
{ \
- return xe_bo_ggtt_addr(lrc->bo) + __xe_lrc_##elem##_offset(lrc); \
+ struct xe_bo *bo = (bo_expr); \
+\
+ return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc); \
} \
-DECL_MAP_ADDR_HELPERS(ring)
-DECL_MAP_ADDR_HELPERS(pphwsp)
-DECL_MAP_ADDR_HELPERS(seqno)
-DECL_MAP_ADDR_HELPERS(regs)
-DECL_MAP_ADDR_HELPERS(start_seqno)
-DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
-DECL_MAP_ADDR_HELPERS(ctx_timestamp)
-DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
-DECL_MAP_ADDR_HELPERS(parallel)
-DECL_MAP_ADDR_HELPERS(indirect_ring)
-DECL_MAP_ADDR_HELPERS(engine_id)
+DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
+DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
+DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
+DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
+DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
+DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
+DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
+DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
+DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
+DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
+DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
#undef DECL_MAP_ADDR_HELPERS
@@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
{
xe_hw_fence_ctx_finish(&lrc->fence_ctx);
xe_bo_unpin_map_no_vm(lrc->bo);
+ xe_bo_unpin_map_no_vm(lrc->seqno_bo);
}
/*
@@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
struct xe_tile *tile = gt_to_tile(gt);
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_bo *seqno_bo;
struct iosys_map map;
u32 arb_enable;
u32 bo_flags;
@@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
if (IS_ERR(lrc->bo))
return PTR_ERR(lrc->bo);
+ seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_SYSTEM, false);
+ if (IS_ERR(seqno_bo)) {
+ err = PTR_ERR(lrc->bo);
+ goto err_lrc_finish;
+ }
+ lrc->seqno_bo = seqno_bo;
+
xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
hwe->fence_irq, hwe->name);
diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
index a4373d280c39..5a718f759ed6 100644
--- a/drivers/gpu/drm/xe/xe_lrc_types.h
+++ b/drivers/gpu/drm/xe/xe_lrc_types.h
@@ -22,6 +22,12 @@ struct xe_lrc {
*/
struct xe_bo *bo;
+ /**
+ * @seqno_bo: Buffer object (memory) for seqno numbers. Always in system
+ * memory as this a CPU read, GPU write path object.
+ */
+ struct xe_bo *seqno_bo;
+
/** @size: size of the lrc and optional indirect ring state */
u32 size;
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* ✓ CI.KUnit: success for dGPU memory optimizations
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (2 preceding siblings ...)
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
@ 2026-02-18 4:40 ` Patchwork
2026-02-18 5:23 ` ✗ Xe.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 4:40 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: dGPU memory optimizations
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:38:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:38:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:39:30] Starting KUnit Kernel (1/1)...
[04:39:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:39:30] ================== guc_buf (11 subtests) ===================
[04:39:30] [PASSED] test_smallest
[04:39:30] [PASSED] test_largest
[04:39:30] [PASSED] test_granular
[04:39:30] [PASSED] test_unique
[04:39:30] [PASSED] test_overlap
[04:39:30] [PASSED] test_reusable
[04:39:30] [PASSED] test_too_big
[04:39:30] [PASSED] test_flush
[04:39:30] [PASSED] test_lookup
[04:39:30] [PASSED] test_data
[04:39:30] [PASSED] test_class
[04:39:30] ===================== [PASSED] guc_buf =====================
[04:39:30] =================== guc_dbm (7 subtests) ===================
[04:39:30] [PASSED] test_empty
[04:39:30] [PASSED] test_default
[04:39:30] ======================== test_size ========================
[04:39:30] [PASSED] 4
[04:39:30] [PASSED] 8
[04:39:30] [PASSED] 32
[04:39:30] [PASSED] 256
[04:39:30] ==================== [PASSED] test_size ====================
[04:39:30] ======================= test_reuse ========================
[04:39:30] [PASSED] 4
[04:39:30] [PASSED] 8
[04:39:30] [PASSED] 32
[04:39:30] [PASSED] 256
[04:39:30] =================== [PASSED] test_reuse ====================
[04:39:30] =================== test_range_overlap ====================
[04:39:30] [PASSED] 4
[04:39:30] [PASSED] 8
[04:39:30] [PASSED] 32
[04:39:30] [PASSED] 256
[04:39:30] =============== [PASSED] test_range_overlap ================
[04:39:30] =================== test_range_compact ====================
[04:39:30] [PASSED] 4
[04:39:30] [PASSED] 8
[04:39:30] [PASSED] 32
[04:39:30] [PASSED] 256
[04:39:30] =============== [PASSED] test_range_compact ================
[04:39:30] ==================== test_range_spare =====================
[04:39:30] [PASSED] 4
[04:39:30] [PASSED] 8
[04:39:30] [PASSED] 32
[04:39:30] [PASSED] 256
[04:39:30] ================ [PASSED] test_range_spare =================
[04:39:30] ===================== [PASSED] guc_dbm =====================
[04:39:30] =================== guc_idm (6 subtests) ===================
[04:39:30] [PASSED] bad_init
[04:39:30] [PASSED] no_init
[04:39:30] [PASSED] init_fini
[04:39:30] [PASSED] check_used
[04:39:30] [PASSED] check_quota
[04:39:30] [PASSED] check_all
[04:39:30] ===================== [PASSED] guc_idm =====================
[04:39:30] ================== no_relay (3 subtests) ===================
[04:39:30] [PASSED] xe_drops_guc2pf_if_not_ready
[04:39:30] [PASSED] xe_drops_guc2vf_if_not_ready
[04:39:30] [PASSED] xe_rejects_send_if_not_ready
[04:39:30] ==================== [PASSED] no_relay =====================
[04:39:30] ================== pf_relay (14 subtests) ==================
[04:39:30] [PASSED] pf_rejects_guc2pf_too_short
[04:39:30] [PASSED] pf_rejects_guc2pf_too_long
[04:39:30] [PASSED] pf_rejects_guc2pf_no_payload
[04:39:30] [PASSED] pf_fails_no_payload
[04:39:30] [PASSED] pf_fails_bad_origin
[04:39:30] [PASSED] pf_fails_bad_type
[04:39:30] [PASSED] pf_txn_reports_error
[04:39:30] [PASSED] pf_txn_sends_pf2guc
[04:39:30] [PASSED] pf_sends_pf2guc
[04:39:30] [SKIPPED] pf_loopback_nop
[04:39:30] [SKIPPED] pf_loopback_echo
[04:39:30] [SKIPPED] pf_loopback_fail
[04:39:30] [SKIPPED] pf_loopback_busy
[04:39:30] [SKIPPED] pf_loopback_retry
[04:39:30] ==================== [PASSED] pf_relay =====================
[04:39:30] ================== vf_relay (3 subtests) ===================
[04:39:30] [PASSED] vf_rejects_guc2vf_too_short
[04:39:30] [PASSED] vf_rejects_guc2vf_too_long
[04:39:30] [PASSED] vf_rejects_guc2vf_no_payload
[04:39:30] ==================== [PASSED] vf_relay =====================
[04:39:30] ================ pf_gt_config (6 subtests) =================
[04:39:30] [PASSED] fair_contexts_1vf
[04:39:30] [PASSED] fair_doorbells_1vf
[04:39:30] [PASSED] fair_ggtt_1vf
[04:39:30] ====================== fair_contexts ======================
[04:39:30] [PASSED] 1 VF
[04:39:30] [PASSED] 2 VFs
[04:39:30] [PASSED] 3 VFs
[04:39:30] [PASSED] 4 VFs
[04:39:30] [PASSED] 5 VFs
[04:39:30] [PASSED] 6 VFs
[04:39:30] [PASSED] 7 VFs
[04:39:30] [PASSED] 8 VFs
[04:39:30] [PASSED] 9 VFs
[04:39:30] [PASSED] 10 VFs
[04:39:30] [PASSED] 11 VFs
[04:39:30] [PASSED] 12 VFs
[04:39:30] [PASSED] 13 VFs
[04:39:30] [PASSED] 14 VFs
[04:39:30] [PASSED] 15 VFs
[04:39:30] [PASSED] 16 VFs
[04:39:30] [PASSED] 17 VFs
[04:39:30] [PASSED] 18 VFs
[04:39:30] [PASSED] 19 VFs
[04:39:30] [PASSED] 20 VFs
[04:39:30] [PASSED] 21 VFs
[04:39:30] [PASSED] 22 VFs
[04:39:30] [PASSED] 23 VFs
[04:39:30] [PASSED] 24 VFs
[04:39:30] [PASSED] 25 VFs
[04:39:30] [PASSED] 26 VFs
[04:39:30] [PASSED] 27 VFs
[04:39:30] [PASSED] 28 VFs
[04:39:30] [PASSED] 29 VFs
[04:39:30] [PASSED] 30 VFs
[04:39:30] [PASSED] 31 VFs
[04:39:30] [PASSED] 32 VFs
[04:39:30] [PASSED] 33 VFs
[04:39:30] [PASSED] 34 VFs
[04:39:30] [PASSED] 35 VFs
[04:39:30] [PASSED] 36 VFs
[04:39:30] [PASSED] 37 VFs
[04:39:30] [PASSED] 38 VFs
[04:39:30] [PASSED] 39 VFs
[04:39:30] [PASSED] 40 VFs
[04:39:30] [PASSED] 41 VFs
[04:39:30] [PASSED] 42 VFs
[04:39:30] [PASSED] 43 VFs
[04:39:30] [PASSED] 44 VFs
[04:39:30] [PASSED] 45 VFs
[04:39:30] [PASSED] 46 VFs
[04:39:30] [PASSED] 47 VFs
[04:39:30] [PASSED] 48 VFs
[04:39:30] [PASSED] 49 VFs
[04:39:30] [PASSED] 50 VFs
[04:39:30] [PASSED] 51 VFs
[04:39:30] [PASSED] 52 VFs
[04:39:30] [PASSED] 53 VFs
[04:39:30] [PASSED] 54 VFs
[04:39:30] [PASSED] 55 VFs
[04:39:30] [PASSED] 56 VFs
[04:39:30] [PASSED] 57 VFs
[04:39:30] [PASSED] 58 VFs
[04:39:30] [PASSED] 59 VFs
[04:39:30] [PASSED] 60 VFs
[04:39:30] [PASSED] 61 VFs
[04:39:30] [PASSED] 62 VFs
[04:39:30] [PASSED] 63 VFs
[04:39:30] ================== [PASSED] fair_contexts ==================
[04:39:30] ===================== fair_doorbells ======================
[04:39:30] [PASSED] 1 VF
[04:39:30] [PASSED] 2 VFs
[04:39:30] [PASSED] 3 VFs
[04:39:30] [PASSED] 4 VFs
[04:39:30] [PASSED] 5 VFs
[04:39:30] [PASSED] 6 VFs
[04:39:30] [PASSED] 7 VFs
[04:39:30] [PASSED] 8 VFs
[04:39:30] [PASSED] 9 VFs
[04:39:30] [PASSED] 10 VFs
[04:39:30] [PASSED] 11 VFs
[04:39:30] [PASSED] 12 VFs
[04:39:30] [PASSED] 13 VFs
[04:39:30] [PASSED] 14 VFs
[04:39:30] [PASSED] 15 VFs
[04:39:30] [PASSED] 16 VFs
[04:39:30] [PASSED] 17 VFs
[04:39:30] [PASSED] 18 VFs
[04:39:30] [PASSED] 19 VFs
[04:39:30] [PASSED] 20 VFs
[04:39:30] [PASSED] 21 VFs
[04:39:30] [PASSED] 22 VFs
[04:39:30] [PASSED] 23 VFs
[04:39:30] [PASSED] 24 VFs
[04:39:30] [PASSED] 25 VFs
[04:39:30] [PASSED] 26 VFs
[04:39:30] [PASSED] 27 VFs
[04:39:30] [PASSED] 28 VFs
[04:39:30] [PASSED] 29 VFs
[04:39:30] [PASSED] 30 VFs
[04:39:30] [PASSED] 31 VFs
[04:39:30] [PASSED] 32 VFs
[04:39:30] [PASSED] 33 VFs
[04:39:30] [PASSED] 34 VFs
[04:39:30] [PASSED] 35 VFs
[04:39:30] [PASSED] 36 VFs
[04:39:30] [PASSED] 37 VFs
[04:39:30] [PASSED] 38 VFs
[04:39:30] [PASSED] 39 VFs
[04:39:30] [PASSED] 40 VFs
[04:39:30] [PASSED] 41 VFs
[04:39:30] [PASSED] 42 VFs
[04:39:30] [PASSED] 43 VFs
[04:39:30] [PASSED] 44 VFs
[04:39:30] [PASSED] 45 VFs
[04:39:30] [PASSED] 46 VFs
[04:39:30] [PASSED] 47 VFs
[04:39:30] [PASSED] 48 VFs
[04:39:30] [PASSED] 49 VFs
[04:39:30] [PASSED] 50 VFs
[04:39:30] [PASSED] 51 VFs
[04:39:30] [PASSED] 52 VFs
[04:39:30] [PASSED] 53 VFs
[04:39:30] [PASSED] 54 VFs
[04:39:30] [PASSED] 55 VFs
[04:39:30] [PASSED] 56 VFs
[04:39:30] [PASSED] 57 VFs
[04:39:30] [PASSED] 58 VFs
[04:39:30] [PASSED] 59 VFs
[04:39:30] [PASSED] 60 VFs
[04:39:30] [PASSED] 61 VFs
[04:39:30] [PASSED] 62 VFs
[04:39:30] [PASSED] 63 VFs
[04:39:30] ================= [PASSED] fair_doorbells ==================
[04:39:30] ======================== fair_ggtt ========================
[04:39:30] [PASSED] 1 VF
[04:39:30] [PASSED] 2 VFs
[04:39:30] [PASSED] 3 VFs
[04:39:30] [PASSED] 4 VFs
[04:39:30] [PASSED] 5 VFs
[04:39:30] [PASSED] 6 VFs
[04:39:30] [PASSED] 7 VFs
[04:39:30] [PASSED] 8 VFs
[04:39:30] [PASSED] 9 VFs
[04:39:30] [PASSED] 10 VFs
[04:39:30] [PASSED] 11 VFs
[04:39:30] [PASSED] 12 VFs
[04:39:30] [PASSED] 13 VFs
[04:39:30] [PASSED] 14 VFs
[04:39:30] [PASSED] 15 VFs
[04:39:30] [PASSED] 16 VFs
[04:39:30] [PASSED] 17 VFs
[04:39:30] [PASSED] 18 VFs
[04:39:30] [PASSED] 19 VFs
[04:39:30] [PASSED] 20 VFs
[04:39:30] [PASSED] 21 VFs
[04:39:30] [PASSED] 22 VFs
[04:39:30] [PASSED] 23 VFs
[04:39:30] [PASSED] 24 VFs
[04:39:30] [PASSED] 25 VFs
[04:39:30] [PASSED] 26 VFs
[04:39:30] [PASSED] 27 VFs
[04:39:30] [PASSED] 28 VFs
[04:39:30] [PASSED] 29 VFs
[04:39:30] [PASSED] 30 VFs
[04:39:30] [PASSED] 31 VFs
[04:39:30] [PASSED] 32 VFs
[04:39:30] [PASSED] 33 VFs
[04:39:30] [PASSED] 34 VFs
[04:39:30] [PASSED] 35 VFs
[04:39:30] [PASSED] 36 VFs
[04:39:30] [PASSED] 37 VFs
[04:39:30] [PASSED] 38 VFs
[04:39:30] [PASSED] 39 VFs
[04:39:30] [PASSED] 40 VFs
[04:39:30] [PASSED] 41 VFs
[04:39:30] [PASSED] 42 VFs
[04:39:30] [PASSED] 43 VFs
[04:39:30] [PASSED] 44 VFs
[04:39:30] [PASSED] 45 VFs
[04:39:30] [PASSED] 46 VFs
[04:39:30] [PASSED] 47 VFs
[04:39:30] [PASSED] 48 VFs
[04:39:30] [PASSED] 49 VFs
[04:39:30] [PASSED] 50 VFs
[04:39:30] [PASSED] 51 VFs
[04:39:30] [PASSED] 52 VFs
[04:39:30] [PASSED] 53 VFs
[04:39:30] [PASSED] 54 VFs
[04:39:30] [PASSED] 55 VFs
[04:39:30] [PASSED] 56 VFs
[04:39:30] [PASSED] 57 VFs
[04:39:30] [PASSED] 58 VFs
[04:39:30] [PASSED] 59 VFs
[04:39:30] [PASSED] 60 VFs
[04:39:30] [PASSED] 61 VFs
[04:39:30] [PASSED] 62 VFs
[04:39:30] [PASSED] 63 VFs
[04:39:30] ==================== [PASSED] fair_ggtt ====================
[04:39:30] ================== [PASSED] pf_gt_config ===================
[04:39:30] ===================== lmtt (1 subtest) =====================
[04:39:30] ======================== test_ops =========================
[04:39:30] [PASSED] 2-level
[04:39:30] [PASSED] multi-level
[04:39:30] ==================== [PASSED] test_ops =====================
[04:39:30] ====================== [PASSED] lmtt =======================
[04:39:30] ================= pf_service (11 subtests) =================
[04:39:30] [PASSED] pf_negotiate_any
[04:39:30] [PASSED] pf_negotiate_base_match
[04:39:30] [PASSED] pf_negotiate_base_newer
[04:39:30] [PASSED] pf_negotiate_base_next
[04:39:30] [SKIPPED] pf_negotiate_base_older
[04:39:30] [PASSED] pf_negotiate_base_prev
[04:39:30] [PASSED] pf_negotiate_latest_match
[04:39:30] [PASSED] pf_negotiate_latest_newer
[04:39:30] [PASSED] pf_negotiate_latest_next
[04:39:30] [SKIPPED] pf_negotiate_latest_older
[04:39:30] [SKIPPED] pf_negotiate_latest_prev
[04:39:30] =================== [PASSED] pf_service ====================
[04:39:30] ================= xe_guc_g2g (2 subtests) ==================
[04:39:30] ============== xe_live_guc_g2g_kunit_default ==============
[04:39:30] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:39:30] ============== xe_live_guc_g2g_kunit_allmem ===============
[04:39:30] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:39:30] =================== [SKIPPED] xe_guc_g2g ===================
[04:39:30] =================== xe_mocs (2 subtests) ===================
[04:39:30] ================ xe_live_mocs_kernel_kunit ================
[04:39:30] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:39:30] ================ xe_live_mocs_reset_kunit =================
[04:39:30] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:39:30] ==================== [SKIPPED] xe_mocs =====================
[04:39:30] ================= xe_migrate (2 subtests) ==================
[04:39:30] ================= xe_migrate_sanity_kunit =================
[04:39:30] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:39:30] ================== xe_validate_ccs_kunit ==================
[04:39:30] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:39:30] =================== [SKIPPED] xe_migrate ===================
[04:39:30] ================== xe_dma_buf (1 subtest) ==================
[04:39:30] ==================== xe_dma_buf_kunit =====================
[04:39:30] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:39:30] =================== [SKIPPED] xe_dma_buf ===================
[04:39:30] ================= xe_bo_shrink (1 subtest) =================
[04:39:30] =================== xe_bo_shrink_kunit ====================
[04:39:30] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:39:30] ================== [SKIPPED] xe_bo_shrink ==================
[04:39:30] ==================== xe_bo (2 subtests) ====================
[04:39:30] ================== xe_ccs_migrate_kunit ===================
[04:39:30] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:39:30] ==================== xe_bo_evict_kunit ====================
[04:39:30] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:39:30] ===================== [SKIPPED] xe_bo ======================
[04:39:30] ==================== args (13 subtests) ====================
[04:39:30] [PASSED] count_args_test
[04:39:30] [PASSED] call_args_example
[04:39:30] [PASSED] call_args_test
[04:39:30] [PASSED] drop_first_arg_example
[04:39:30] [PASSED] drop_first_arg_test
[04:39:30] [PASSED] first_arg_example
[04:39:30] [PASSED] first_arg_test
[04:39:30] [PASSED] last_arg_example
[04:39:30] [PASSED] last_arg_test
[04:39:30] [PASSED] pick_arg_example
[04:39:30] [PASSED] if_args_example
[04:39:30] [PASSED] if_args_test
[04:39:30] [PASSED] sep_comma_example
[04:39:30] ====================== [PASSED] args =======================
[04:39:30] =================== xe_pci (3 subtests) ====================
[04:39:30] ==================== check_graphics_ip ====================
[04:39:30] [PASSED] 12.00 Xe_LP
[04:39:30] [PASSED] 12.10 Xe_LP+
[04:39:30] [PASSED] 12.55 Xe_HPG
[04:39:30] [PASSED] 12.60 Xe_HPC
[04:39:30] [PASSED] 12.70 Xe_LPG
[04:39:30] [PASSED] 12.71 Xe_LPG
[04:39:30] [PASSED] 12.74 Xe_LPG+
[04:39:30] [PASSED] 20.01 Xe2_HPG
[04:39:30] [PASSED] 20.02 Xe2_HPG
[04:39:30] [PASSED] 20.04 Xe2_LPG
[04:39:30] [PASSED] 30.00 Xe3_LPG
[04:39:30] [PASSED] 30.01 Xe3_LPG
[04:39:30] [PASSED] 30.03 Xe3_LPG
[04:39:30] [PASSED] 30.04 Xe3_LPG
[04:39:30] [PASSED] 30.05 Xe3_LPG
[04:39:30] [PASSED] 35.10 Xe3p_LPG
[04:39:30] [PASSED] 35.11 Xe3p_XPC
[04:39:30] ================ [PASSED] check_graphics_ip ================
[04:39:30] ===================== check_media_ip ======================
[04:39:30] [PASSED] 12.00 Xe_M
[04:39:30] [PASSED] 12.55 Xe_HPM
[04:39:30] [PASSED] 13.00 Xe_LPM+
[04:39:30] [PASSED] 13.01 Xe2_HPM
[04:39:30] [PASSED] 20.00 Xe2_LPM
[04:39:30] [PASSED] 30.00 Xe3_LPM
[04:39:30] [PASSED] 30.02 Xe3_LPM
[04:39:30] [PASSED] 35.00 Xe3p_LPM
[04:39:30] [PASSED] 35.03 Xe3p_HPM
[04:39:30] ================= [PASSED] check_media_ip ==================
[04:39:30] =================== check_platform_desc ===================
[04:39:30] [PASSED] 0x9A60 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A68 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A70 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A40 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A49 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A59 (TIGERLAKE)
[04:39:30] [PASSED] 0x9A78 (TIGERLAKE)
[04:39:30] [PASSED] 0x9AC0 (TIGERLAKE)
[04:39:30] [PASSED] 0x9AC9 (TIGERLAKE)
[04:39:30] [PASSED] 0x9AD9 (TIGERLAKE)
[04:39:30] [PASSED] 0x9AF8 (TIGERLAKE)
[04:39:30] [PASSED] 0x4C80 (ROCKETLAKE)
[04:39:30] [PASSED] 0x4C8A (ROCKETLAKE)
[04:39:30] [PASSED] 0x4C8B (ROCKETLAKE)
[04:39:30] [PASSED] 0x4C8C (ROCKETLAKE)
[04:39:30] [PASSED] 0x4C90 (ROCKETLAKE)
[04:39:30] [PASSED] 0x4C9A (ROCKETLAKE)
[04:39:30] [PASSED] 0x4680 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4682 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4688 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x468A (ALDERLAKE_S)
[04:39:30] [PASSED] 0x468B (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4690 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4692 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4693 (ALDERLAKE_S)
[04:39:30] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46AA (ALDERLAKE_P)
[04:39:30] [PASSED] 0x462A (ALDERLAKE_P)
[04:39:30] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[04:39:30] [PASSED] 0x4628 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:39:30] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:39:30] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:39:30] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:39:30] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:39:30] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:39:30] [PASSED] 0xA721 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA720 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:39:30] [PASSED] 0xA780 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA781 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA782 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA783 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA788 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA789 (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA78A (ALDERLAKE_S)
[04:39:30] [PASSED] 0xA78B (ALDERLAKE_S)
[04:39:30] [PASSED] 0x4905 (DG1)
[04:39:30] [PASSED] 0x4906 (DG1)
[04:39:30] [PASSED] 0x4907 (DG1)
[04:39:30] [PASSED] 0x4908 (DG1)
[04:39:30] [PASSED] 0x4909 (DG1)
[04:39:30] [PASSED] 0x56C0 (DG2)
[04:39:30] [PASSED] 0x56C2 (DG2)
[04:39:30] [PASSED] 0x56C1 (DG2)
[04:39:30] [PASSED] 0x7D51 (METEORLAKE)
[04:39:30] [PASSED] 0x7DD1 (METEORLAKE)
[04:39:30] [PASSED] 0x7D41 (METEORLAKE)
[04:39:30] [PASSED] 0x7D67 (METEORLAKE)
[04:39:30] [PASSED] 0xB640 (METEORLAKE)
[04:39:30] [PASSED] 0x56A0 (DG2)
[04:39:30] [PASSED] 0x56A1 (DG2)
[04:39:30] [PASSED] 0x56A2 (DG2)
[04:39:30] [PASSED] 0x56BE (DG2)
[04:39:30] [PASSED] 0x56BF (DG2)
[04:39:30] [PASSED] 0x5690 (DG2)
[04:39:30] [PASSED] 0x5691 (DG2)
[04:39:30] [PASSED] 0x5692 (DG2)
[04:39:30] [PASSED] 0x56A5 (DG2)
[04:39:30] [PASSED] 0x56A6 (DG2)
[04:39:30] [PASSED] 0x56B0 (DG2)
[04:39:30] [PASSED] 0x56B1 (DG2)
[04:39:30] [PASSED] 0x56BA (DG2)
[04:39:30] [PASSED] 0x56BB (DG2)
[04:39:30] [PASSED] 0x56BC (DG2)
[04:39:30] [PASSED] 0x56BD (DG2)
[04:39:30] [PASSED] 0x5693 (DG2)
[04:39:30] [PASSED] 0x5694 (DG2)
[04:39:30] [PASSED] 0x5695 (DG2)
[04:39:30] [PASSED] 0x56A3 (DG2)
[04:39:30] [PASSED] 0x56A4 (DG2)
[04:39:30] [PASSED] 0x56B2 (DG2)
[04:39:30] [PASSED] 0x56B3 (DG2)
[04:39:30] [PASSED] 0x5696 (DG2)
[04:39:30] [PASSED] 0x5697 (DG2)
[04:39:30] [PASSED] 0xB69 (PVC)
[04:39:30] [PASSED] 0xB6E (PVC)
[04:39:30] [PASSED] 0xBD4 (PVC)
[04:39:30] [PASSED] 0xBD5 (PVC)
[04:39:30] [PASSED] 0xBD6 (PVC)
[04:39:30] [PASSED] 0xBD7 (PVC)
[04:39:30] [PASSED] 0xBD8 (PVC)
[04:39:30] [PASSED] 0xBD9 (PVC)
[04:39:30] [PASSED] 0xBDA (PVC)
[04:39:30] [PASSED] 0xBDB (PVC)
[04:39:30] [PASSED] 0xBE0 (PVC)
[04:39:30] [PASSED] 0xBE1 (PVC)
[04:39:30] [PASSED] 0xBE5 (PVC)
[04:39:30] [PASSED] 0x7D40 (METEORLAKE)
[04:39:30] [PASSED] 0x7D45 (METEORLAKE)
[04:39:30] [PASSED] 0x7D55 (METEORLAKE)
[04:39:30] [PASSED] 0x7D60 (METEORLAKE)
[04:39:30] [PASSED] 0x7DD5 (METEORLAKE)
[04:39:30] [PASSED] 0x6420 (LUNARLAKE)
[04:39:30] [PASSED] 0x64A0 (LUNARLAKE)
[04:39:30] [PASSED] 0x64B0 (LUNARLAKE)
[04:39:30] [PASSED] 0xE202 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE209 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE20B (BATTLEMAGE)
[04:39:30] [PASSED] 0xE20C (BATTLEMAGE)
[04:39:30] [PASSED] 0xE20D (BATTLEMAGE)
[04:39:30] [PASSED] 0xE210 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE211 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE212 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE216 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE220 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE221 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE222 (BATTLEMAGE)
[04:39:30] [PASSED] 0xE223 (BATTLEMAGE)
[04:39:30] [PASSED] 0xB080 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB081 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB082 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB083 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB084 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB085 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB086 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB087 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB08F (PANTHERLAKE)
[04:39:30] [PASSED] 0xB090 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:39:30] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:39:30] [PASSED] 0xFD80 (PANTHERLAKE)
[04:39:30] [PASSED] 0xFD81 (PANTHERLAKE)
[04:39:30] [PASSED] 0xD740 (NOVALAKE_S)
[04:39:30] [PASSED] 0xD741 (NOVALAKE_S)
[04:39:30] [PASSED] 0xD742 (NOVALAKE_S)
[04:39:30] [PASSED] 0xD743 (NOVALAKE_S)
[04:39:30] [PASSED] 0xD744 (NOVALAKE_S)
[04:39:30] [PASSED] 0xD745 (NOVALAKE_S)
[04:39:30] [PASSED] 0x674C (CRESCENTISLAND)
[04:39:30] [PASSED] 0xD750 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD751 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD752 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD753 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD754 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD755 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD756 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD757 (NOVALAKE_P)
[04:39:30] [PASSED] 0xD75F (NOVALAKE_P)
[04:39:30] =============== [PASSED] check_platform_desc ===============
[04:39:30] ===================== [PASSED] xe_pci ======================
[04:39:30] =================== xe_rtp (2 subtests) ====================
[04:39:30] =============== xe_rtp_process_to_sr_tests ================
[04:39:30] [PASSED] coalesce-same-reg
[04:39:30] [PASSED] no-match-no-add
[04:39:30] [PASSED] match-or
[04:39:30] [PASSED] match-or-xfail
[04:39:30] [PASSED] no-match-no-add-multiple-rules
[04:39:30] [PASSED] two-regs-two-entries
[04:39:30] [PASSED] clr-one-set-other
[04:39:30] [PASSED] set-field
[04:39:30] [PASSED] conflict-duplicate
[04:39:30] [PASSED] conflict-not-disjoint
[04:39:30] [PASSED] conflict-reg-type
[04:39:30] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:39:30] ================== xe_rtp_process_tests ===================
[04:39:30] [PASSED] active1
[04:39:30] [PASSED] active2
[04:39:30] [PASSED] active-inactive
[04:39:30] [PASSED] inactive-active
[04:39:30] [PASSED] inactive-1st_or_active-inactive
[04:39:30] [PASSED] inactive-2nd_or_active-inactive
[04:39:30] [PASSED] inactive-last_or_active-inactive
[04:39:30] [PASSED] inactive-no_or_active-inactive
[04:39:30] ============== [PASSED] xe_rtp_process_tests ===============
[04:39:30] ===================== [PASSED] xe_rtp ======================
[04:39:30] ==================== xe_wa (1 subtest) =====================
[04:39:30] ======================== xe_wa_gt =========================
[04:39:30] [PASSED] TIGERLAKE B0
[04:39:30] [PASSED] DG1 A0
[04:39:30] [PASSED] DG1 B0
[04:39:30] [PASSED] ALDERLAKE_S A0
[04:39:30] [PASSED] ALDERLAKE_S B0
[04:39:30] [PASSED] ALDERLAKE_S C0
[04:39:30] [PASSED] ALDERLAKE_S D0
[04:39:30] [PASSED] ALDERLAKE_P A0
[04:39:30] [PASSED] ALDERLAKE_P B0
[04:39:30] [PASSED] ALDERLAKE_P C0
[04:39:30] [PASSED] ALDERLAKE_S RPLS D0
[04:39:30] [PASSED] ALDERLAKE_P RPLU E0
[04:39:30] [PASSED] DG2 G10 C0
[04:39:30] [PASSED] DG2 G11 B1
[04:39:30] [PASSED] DG2 G12 A1
[04:39:30] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:39:30] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:39:30] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:39:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:39:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:39:30] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:39:30] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:39:30] ==================== [PASSED] xe_wa_gt =====================
[04:39:30] ====================== [PASSED] xe_wa ======================
[04:39:30] ============================================================
[04:39:30] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[04:39:30] Elapsed time: 36.530s total, 4.201s configuring, 31.812s building, 0.466s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:39:30] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:39:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:39:58] Starting KUnit Kernel (1/1)...
[04:39:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:39:58] ============ drm_test_pick_cmdline (2 subtests) ============
[04:39:58] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:39:58] =============== drm_test_pick_cmdline_named ===============
[04:39:58] [PASSED] NTSC
[04:39:58] [PASSED] NTSC-J
[04:39:58] [PASSED] PAL
[04:39:58] [PASSED] PAL-M
[04:39:58] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:39:58] ============== [PASSED] drm_test_pick_cmdline ==============
[04:39:58] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:39:58] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:39:58] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:39:58] =========== drm_validate_clone_mode (2 subtests) ===========
[04:39:58] ============== drm_test_check_in_clone_mode ===============
[04:39:58] [PASSED] in_clone_mode
[04:39:58] [PASSED] not_in_clone_mode
[04:39:58] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:39:58] =============== drm_test_check_valid_clones ===============
[04:39:58] [PASSED] not_in_clone_mode
[04:39:58] [PASSED] valid_clone
[04:39:58] [PASSED] invalid_clone
[04:39:58] =========== [PASSED] drm_test_check_valid_clones ===========
[04:39:58] ============= [PASSED] drm_validate_clone_mode =============
[04:39:58] ============= drm_validate_modeset (1 subtest) =============
[04:39:58] [PASSED] drm_test_check_connector_changed_modeset
[04:39:58] ============== [PASSED] drm_validate_modeset ===============
[04:39:58] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:39:58] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:39:58] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:39:58] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:39:58] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:39:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:39:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:39:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:39:58] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:39:58] ============== drm_bridge_alloc (2 subtests) ===============
[04:39:58] [PASSED] drm_test_drm_bridge_alloc_basic
[04:39:58] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:39:58] ================ [PASSED] drm_bridge_alloc =================
[04:39:58] ============= drm_cmdline_parser (40 subtests) =============
[04:39:58] [PASSED] drm_test_cmdline_force_d_only
[04:39:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:39:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:39:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:39:58] [PASSED] drm_test_cmdline_force_e_only
[04:39:58] [PASSED] drm_test_cmdline_res
[04:39:58] [PASSED] drm_test_cmdline_res_vesa
[04:39:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:39:58] [PASSED] drm_test_cmdline_res_rblank
[04:39:58] [PASSED] drm_test_cmdline_res_bpp
[04:39:58] [PASSED] drm_test_cmdline_res_refresh
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:39:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:39:58] [PASSED] drm_test_cmdline_res_margins_force_on
[04:39:58] [PASSED] drm_test_cmdline_res_vesa_margins
[04:39:58] [PASSED] drm_test_cmdline_name
[04:39:58] [PASSED] drm_test_cmdline_name_bpp
[04:39:58] [PASSED] drm_test_cmdline_name_option
[04:39:58] [PASSED] drm_test_cmdline_name_bpp_option
[04:39:58] [PASSED] drm_test_cmdline_rotate_0
[04:39:58] [PASSED] drm_test_cmdline_rotate_90
[04:39:58] [PASSED] drm_test_cmdline_rotate_180
[04:39:58] [PASSED] drm_test_cmdline_rotate_270
[04:39:58] [PASSED] drm_test_cmdline_hmirror
[04:39:58] [PASSED] drm_test_cmdline_vmirror
[04:39:58] [PASSED] drm_test_cmdline_margin_options
[04:39:58] [PASSED] drm_test_cmdline_multiple_options
[04:39:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:39:58] [PASSED] drm_test_cmdline_extra_and_option
[04:39:58] [PASSED] drm_test_cmdline_freestanding_options
[04:39:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:39:58] [PASSED] drm_test_cmdline_panel_orientation
[04:39:58] ================ drm_test_cmdline_invalid =================
[04:39:58] [PASSED] margin_only
[04:39:58] [PASSED] interlace_only
[04:39:58] [PASSED] res_missing_x
[04:39:58] [PASSED] res_missing_y
[04:39:58] [PASSED] res_bad_y
[04:39:58] [PASSED] res_missing_y_bpp
[04:39:58] [PASSED] res_bad_bpp
[04:39:58] [PASSED] res_bad_refresh
[04:39:58] [PASSED] res_bpp_refresh_force_on_off
[04:39:58] [PASSED] res_invalid_mode
[04:39:58] [PASSED] res_bpp_wrong_place_mode
[04:39:58] [PASSED] name_bpp_refresh
[04:39:58] [PASSED] name_refresh
[04:39:58] [PASSED] name_refresh_wrong_mode
[04:39:58] [PASSED] name_refresh_invalid_mode
[04:39:58] [PASSED] rotate_multiple
[04:39:58] [PASSED] rotate_invalid_val
[04:39:58] [PASSED] rotate_truncated
[04:39:58] [PASSED] invalid_option
[04:39:58] [PASSED] invalid_tv_option
[04:39:58] [PASSED] truncated_tv_option
[04:39:58] ============ [PASSED] drm_test_cmdline_invalid =============
[04:39:58] =============== drm_test_cmdline_tv_options ===============
[04:39:58] [PASSED] NTSC
[04:39:58] [PASSED] NTSC_443
[04:39:58] [PASSED] NTSC_J
[04:39:58] [PASSED] PAL
[04:39:58] [PASSED] PAL_M
[04:39:58] [PASSED] PAL_N
[04:39:58] [PASSED] SECAM
[04:39:58] [PASSED] MONO_525
[04:39:58] [PASSED] MONO_625
[04:39:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:39:58] =============== [PASSED] drm_cmdline_parser ================
[04:39:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:39:58] [PASSED] drm_test_connector_hdmi_init_valid
[04:39:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:39:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:39:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:39:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:39:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:39:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:39:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:39:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:39:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:39:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:39:58] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:39:58] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:39:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:39:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:39:58] [PASSED] drm_test_connector_hdmi_init_null_product
[04:39:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:39:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:39:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:39:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:39:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:39:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:39:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:39:58] ========= drm_test_connector_hdmi_init_type_valid =========
[04:39:58] [PASSED] HDMI-A
[04:39:58] [PASSED] HDMI-B
[04:39:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:39:58] ======== drm_test_connector_hdmi_init_type_invalid ========
[04:39:58] [PASSED] Unknown
[04:39:58] [PASSED] VGA
[04:39:58] [PASSED] DVI-I
[04:39:58] [PASSED] DVI-D
[04:39:58] [PASSED] DVI-A
[04:39:58] [PASSED] Composite
[04:39:58] [PASSED] SVIDEO
[04:39:58] [PASSED] LVDS
[04:39:58] [PASSED] Component
[04:39:58] [PASSED] DIN
[04:39:58] [PASSED] DP
[04:39:58] [PASSED] TV
[04:39:58] [PASSED] eDP
[04:39:58] [PASSED] Virtual
[04:39:58] [PASSED] DSI
[04:39:58] [PASSED] DPI
[04:39:58] [PASSED] Writeback
[04:39:58] [PASSED] SPI
[04:39:58] [PASSED] USB
[04:39:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:39:58] ============ [PASSED] drmm_connector_hdmi_init =============
[04:39:58] ============= drmm_connector_init (3 subtests) =============
[04:39:58] [PASSED] drm_test_drmm_connector_init
[04:39:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:39:58] ========= drm_test_drmm_connector_init_type_valid =========
[04:39:58] [PASSED] Unknown
[04:39:58] [PASSED] VGA
[04:39:58] [PASSED] DVI-I
[04:39:58] [PASSED] DVI-D
[04:39:58] [PASSED] DVI-A
[04:39:58] [PASSED] Composite
[04:39:58] [PASSED] SVIDEO
[04:39:58] [PASSED] LVDS
[04:39:58] [PASSED] Component
[04:39:58] [PASSED] DIN
[04:39:58] [PASSED] DP
[04:39:58] [PASSED] HDMI-A
[04:39:58] [PASSED] HDMI-B
[04:39:58] [PASSED] TV
[04:39:58] [PASSED] eDP
[04:39:58] [PASSED] Virtual
[04:39:58] [PASSED] DSI
[04:39:58] [PASSED] DPI
[04:39:58] [PASSED] Writeback
[04:39:58] [PASSED] SPI
[04:39:58] [PASSED] USB
[04:39:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:39:58] =============== [PASSED] drmm_connector_init ===============
[04:39:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_init
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:39:58] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[04:39:58] [PASSED] Unknown
[04:39:58] [PASSED] VGA
[04:39:58] [PASSED] DVI-I
[04:39:58] [PASSED] DVI-D
[04:39:58] [PASSED] DVI-A
[04:39:58] [PASSED] Composite
[04:39:58] [PASSED] SVIDEO
[04:39:58] [PASSED] LVDS
[04:39:58] [PASSED] Component
[04:39:58] [PASSED] DIN
[04:39:58] [PASSED] DP
[04:39:58] [PASSED] HDMI-A
[04:39:58] [PASSED] HDMI-B
[04:39:58] [PASSED] TV
[04:39:58] [PASSED] eDP
[04:39:58] [PASSED] Virtual
[04:39:58] [PASSED] DSI
[04:39:58] [PASSED] DPI
[04:39:58] [PASSED] Writeback
[04:39:58] [PASSED] SPI
[04:39:58] [PASSED] USB
[04:39:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:39:58] ======== drm_test_drm_connector_dynamic_init_name =========
[04:39:58] [PASSED] Unknown
[04:39:58] [PASSED] VGA
[04:39:58] [PASSED] DVI-I
[04:39:58] [PASSED] DVI-D
[04:39:58] [PASSED] DVI-A
[04:39:58] [PASSED] Composite
[04:39:58] [PASSED] SVIDEO
[04:39:58] [PASSED] LVDS
[04:39:58] [PASSED] Component
[04:39:58] [PASSED] DIN
[04:39:58] [PASSED] DP
[04:39:58] [PASSED] HDMI-A
[04:39:58] [PASSED] HDMI-B
[04:39:58] [PASSED] TV
[04:39:58] [PASSED] eDP
[04:39:58] [PASSED] Virtual
[04:39:58] [PASSED] DSI
[04:39:58] [PASSED] DPI
[04:39:58] [PASSED] Writeback
[04:39:58] [PASSED] SPI
[04:39:58] [PASSED] USB
[04:39:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:39:58] =========== [PASSED] drm_connector_dynamic_init ============
[04:39:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:39:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:39:58] ======= drm_connector_dynamic_register (7 subtests) ========
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:39:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:39:58] ========= [PASSED] drm_connector_dynamic_register ==========
[04:39:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:39:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:39:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:39:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:39:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:39:58] ========== drm_test_get_tv_mode_from_name_valid ===========
[04:39:58] [PASSED] NTSC
[04:39:58] [PASSED] NTSC-443
[04:39:58] [PASSED] NTSC-J
[04:39:58] [PASSED] PAL
[04:39:58] [PASSED] PAL-M
[04:39:58] [PASSED] PAL-N
[04:39:58] [PASSED] SECAM
[04:39:58] [PASSED] Mono
[04:39:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:39:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:39:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:39:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:39:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:39:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[04:39:58] [PASSED] VIC 96
[04:39:58] [PASSED] VIC 97
[04:39:58] [PASSED] VIC 101
[04:39:58] [PASSED] VIC 102
[04:39:58] [PASSED] VIC 106
[04:39:58] [PASSED] VIC 107
[04:39:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:39:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:39:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:39:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:39:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:39:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:39:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:39:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:39:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[04:39:58] [PASSED] Automatic
[04:39:58] [PASSED] Full
[04:39:58] [PASSED] Limited 16:235
[04:39:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:39:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:39:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:39:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:39:58] === drm_test_drm_hdmi_connector_get_output_format_name ====
[04:39:58] [PASSED] RGB
[04:39:58] [PASSED] YUV 4:2:0
[04:39:58] [PASSED] YUV 4:2:2
[04:39:58] [PASSED] YUV 4:4:4
[04:39:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:39:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:39:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:39:58] ============= drm_damage_helper (21 subtests) ==============
[04:39:58] [PASSED] drm_test_damage_iter_no_damage
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:39:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:39:58] [PASSED] drm_test_damage_iter_simple_damage
[04:39:58] [PASSED] drm_test_damage_iter_single_damage
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:39:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:39:58] [PASSED] drm_test_damage_iter_damage
[04:39:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:39:58] [PASSED] drm_test_damage_iter_damage_one_outside
[04:39:58] [PASSED] drm_test_damage_iter_damage_src_moved
[04:39:58] [PASSED] drm_test_damage_iter_damage_not_visible
[04:39:58] ================ [PASSED] drm_damage_helper ================
[04:39:58] ============== drm_dp_mst_helper (3 subtests) ==============
[04:39:58] ============== drm_test_dp_mst_calc_pbn_mode ==============
[04:39:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:39:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:39:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:39:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:39:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:39:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:39:58] ============== drm_test_dp_mst_calc_pbn_div ===============
[04:39:58] [PASSED] Link rate 2000000 lane count 4
[04:39:58] [PASSED] Link rate 2000000 lane count 2
[04:39:58] [PASSED] Link rate 2000000 lane count 1
[04:39:58] [PASSED] Link rate 1350000 lane count 4
[04:39:58] [PASSED] Link rate 1350000 lane count 2
[04:39:58] [PASSED] Link rate 1350000 lane count 1
[04:39:58] [PASSED] Link rate 1000000 lane count 4
[04:39:58] [PASSED] Link rate 1000000 lane count 2
[04:39:58] [PASSED] Link rate 1000000 lane count 1
[04:39:58] [PASSED] Link rate 810000 lane count 4
[04:39:58] [PASSED] Link rate 810000 lane count 2
[04:39:58] [PASSED] Link rate 810000 lane count 1
[04:39:58] [PASSED] Link rate 540000 lane count 4
[04:39:58] [PASSED] Link rate 540000 lane count 2
[04:39:58] [PASSED] Link rate 540000 lane count 1
[04:39:58] [PASSED] Link rate 270000 lane count 4
[04:39:58] [PASSED] Link rate 270000 lane count 2
[04:39:58] [PASSED] Link rate 270000 lane count 1
[04:39:58] [PASSED] Link rate 162000 lane count 4
[04:39:58] [PASSED] Link rate 162000 lane count 2
[04:39:58] [PASSED] Link rate 162000 lane count 1
[04:39:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:39:58] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[04:39:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:39:58] [PASSED] DP_POWER_UP_PHY with port number
[04:39:58] [PASSED] DP_POWER_DOWN_PHY with port number
[04:39:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:39:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:39:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:39:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:39:58] [PASSED] DP_QUERY_PAYLOAD with port number
[04:39:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:39:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:39:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:39:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:39:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:39:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:39:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:39:58] [PASSED] DP_REMOTE_I2C_READ with port number
[04:39:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:39:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:39:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:39:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:39:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:39:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:39:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:39:58] ================ [PASSED] drm_dp_mst_helper ================
[04:39:58] ================== drm_exec (7 subtests) ===================
[04:39:58] [PASSED] sanitycheck
[04:39:58] [PASSED] test_lock
[04:39:58] [PASSED] test_lock_unlock
[04:39:58] [PASSED] test_duplicates
[04:39:58] [PASSED] test_prepare
[04:39:58] [PASSED] test_prepare_array
[04:39:58] [PASSED] test_multiple_loops
[04:39:58] ==================== [PASSED] drm_exec =====================
[04:39:58] =========== drm_format_helper_test (17 subtests) ===========
[04:39:58] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:39:58] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:39:58] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:39:58] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:39:58] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:39:58] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:39:58] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:39:58] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:39:58] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:39:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:39:58] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:39:58] ============== drm_test_fb_xrgb8888_to_mono ===============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:39:58] ==================== drm_test_fb_swab =====================
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ================ [PASSED] drm_test_fb_swab =================
[04:39:58] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:39:58] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[04:39:58] [PASSED] single_pixel_source_buffer
[04:39:58] [PASSED] single_pixel_clip_rectangle
[04:39:58] [PASSED] well_known_colors
[04:39:58] [PASSED] destination_pitch
[04:39:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:39:58] ================= drm_test_fb_clip_offset =================
[04:39:58] [PASSED] pass through
[04:39:58] [PASSED] horizontal offset
[04:39:58] [PASSED] vertical offset
[04:39:58] [PASSED] horizontal and vertical offset
[04:39:58] [PASSED] horizontal offset (custom pitch)
[04:39:58] [PASSED] vertical offset (custom pitch)
[04:39:58] [PASSED] horizontal and vertical offset (custom pitch)
[04:39:58] ============= [PASSED] drm_test_fb_clip_offset =============
[04:39:58] =================== drm_test_fb_memcpy ====================
[04:39:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:39:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:39:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:39:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:39:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:39:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:39:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:39:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:39:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:39:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:39:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:39:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:39:58] =============== [PASSED] drm_test_fb_memcpy ================
[04:39:58] ============= [PASSED] drm_format_helper_test ==============
[04:39:58] ================= drm_format (18 subtests) =================
[04:39:58] [PASSED] drm_test_format_block_width_invalid
[04:39:58] [PASSED] drm_test_format_block_width_one_plane
[04:39:58] [PASSED] drm_test_format_block_width_two_plane
[04:39:58] [PASSED] drm_test_format_block_width_three_plane
[04:39:58] [PASSED] drm_test_format_block_width_tiled
[04:39:58] [PASSED] drm_test_format_block_height_invalid
[04:39:58] [PASSED] drm_test_format_block_height_one_plane
[04:39:58] [PASSED] drm_test_format_block_height_two_plane
[04:39:58] [PASSED] drm_test_format_block_height_three_plane
[04:39:58] [PASSED] drm_test_format_block_height_tiled
[04:39:58] [PASSED] drm_test_format_min_pitch_invalid
[04:39:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:39:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:39:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:39:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:39:58] [PASSED] drm_test_format_min_pitch_two_plane
[04:39:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:39:58] [PASSED] drm_test_format_min_pitch_tiled
[04:39:58] =================== [PASSED] drm_format ====================
[04:39:58] ============== drm_framebuffer (10 subtests) ===============
[04:39:58] ========== drm_test_framebuffer_check_src_coords ==========
[04:39:58] [PASSED] Success: source fits into fb
[04:39:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:39:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:39:58] [PASSED] Fail: overflowing fb with source width
[04:39:58] [PASSED] Fail: overflowing fb with source height
[04:39:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:39:58] [PASSED] drm_test_framebuffer_cleanup
[04:39:58] =============== drm_test_framebuffer_create ===============
[04:39:58] [PASSED] ABGR8888 normal sizes
[04:39:58] [PASSED] ABGR8888 max sizes
[04:39:58] [PASSED] ABGR8888 pitch greater than min required
[04:39:58] [PASSED] ABGR8888 pitch less than min required
[04:39:58] [PASSED] ABGR8888 Invalid width
[04:39:58] [PASSED] ABGR8888 Invalid buffer handle
[04:39:58] [PASSED] No pixel format
[04:39:58] [PASSED] ABGR8888 Width 0
[04:39:58] [PASSED] ABGR8888 Height 0
[04:39:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:39:58] [PASSED] ABGR8888 Large buffer offset
[04:39:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:39:58] [PASSED] ABGR8888 Invalid flag
[04:39:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:39:58] [PASSED] ABGR8888 Valid buffer modifier
[04:39:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:39:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] NV12 Normal sizes
[04:39:58] [PASSED] NV12 Max sizes
[04:39:58] [PASSED] NV12 Invalid pitch
[04:39:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:39:58] [PASSED] NV12 different modifier per-plane
[04:39:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:39:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] NV12 Modifier for inexistent plane
[04:39:58] [PASSED] NV12 Handle for inexistent plane
[04:39:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:39:58] [PASSED] YVU420 Normal sizes
[04:39:58] [PASSED] YVU420 Max sizes
[04:39:58] [PASSED] YVU420 Invalid pitch
[04:39:58] [PASSED] YVU420 Different pitches
[04:39:58] [PASSED] YVU420 Different buffer offsets/pitches
[04:39:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:39:58] [PASSED] YVU420 Valid modifier
[04:39:58] [PASSED] YVU420 Different modifiers per plane
[04:39:58] [PASSED] YVU420 Modifier for inexistent plane
[04:39:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:39:58] [PASSED] X0L2 Normal sizes
[04:39:58] [PASSED] X0L2 Max sizes
[04:39:58] [PASSED] X0L2 Invalid pitch
[04:39:58] [PASSED] X0L2 Pitch greater than minimum required
[04:39:58] [PASSED] X0L2 Handle for inexistent plane
[04:39:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:39:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:39:58] [PASSED] X0L2 Valid modifier
[04:39:58] [PASSED] X0L2 Modifier for inexistent plane
[04:39:58] =========== [PASSED] drm_test_framebuffer_create ===========
[04:39:58] [PASSED] drm_test_framebuffer_free
[04:39:58] [PASSED] drm_test_framebuffer_init
[04:39:58] [PASSED] drm_test_framebuffer_init_bad_format
[04:39:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:39:58] [PASSED] drm_test_framebuffer_lookup
[04:39:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:39:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:39:58] ================= [PASSED] drm_framebuffer =================
[04:39:58] ================ drm_gem_shmem (8 subtests) ================
[04:39:58] [PASSED] drm_gem_shmem_test_obj_create
[04:39:58] [PASSED] drm_gem_shmem_test_obj_create_private
[04:39:58] [PASSED] drm_gem_shmem_test_pin_pages
[04:39:58] [PASSED] drm_gem_shmem_test_vmap
[04:39:58] [PASSED] drm_gem_shmem_test_get_sg_table
[04:39:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:39:58] [PASSED] drm_gem_shmem_test_madvise
[04:39:58] [PASSED] drm_gem_shmem_test_purge
[04:39:58] ================== [PASSED] drm_gem_shmem ==================
[04:39:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:39:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[04:39:58] [PASSED] Automatic
[04:39:58] [PASSED] Full
[04:39:58] [PASSED] Limited 16:235
[04:39:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:39:58] [PASSED] drm_test_check_disable_connector
[04:39:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:39:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:39:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:39:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:39:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:39:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:39:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:39:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:39:58] [PASSED] drm_test_check_output_bpc_dvi
[04:39:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:39:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:39:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:39:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:39:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:39:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:39:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:39:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:39:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:39:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:39:58] [PASSED] drm_test_check_broadcast_rgb_value
[04:39:58] [PASSED] drm_test_check_bpc_8_value
[04:39:58] [PASSED] drm_test_check_bpc_10_value
[04:39:58] [PASSED] drm_test_check_bpc_12_value
[04:39:58] [PASSED] drm_test_check_format_value
[04:39:58] [PASSED] drm_test_check_tmds_char_value
[04:39:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:39:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:39:58] [PASSED] drm_test_check_mode_valid
[04:39:58] [PASSED] drm_test_check_mode_valid_reject
[04:39:58] [PASSED] drm_test_check_mode_valid_reject_rate
[04:39:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:39:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:39:58] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[04:39:58] [PASSED] drm_test_check_infoframes
[04:39:58] [PASSED] drm_test_check_reject_avi_infoframe
[04:39:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[04:39:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[04:39:58] [PASSED] drm_test_check_reject_audio_infoframe
[04:39:58] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[04:39:58] ================= drm_managed (2 subtests) =================
[04:39:58] [PASSED] drm_test_managed_release_action
[04:39:58] [PASSED] drm_test_managed_run_action
[04:39:58] =================== [PASSED] drm_managed ===================
[04:39:58] =================== drm_mm (6 subtests) ====================
[04:39:58] [PASSED] drm_test_mm_init
[04:39:58] [PASSED] drm_test_mm_debug
[04:39:58] [PASSED] drm_test_mm_align32
[04:39:58] [PASSED] drm_test_mm_align64
[04:39:58] [PASSED] drm_test_mm_lowest
[04:39:58] [PASSED] drm_test_mm_highest
[04:39:58] ===================== [PASSED] drm_mm ======================
[04:39:58] ============= drm_modes_analog_tv (5 subtests) =============
[04:39:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:39:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:39:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:39:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:39:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:39:58] =============== [PASSED] drm_modes_analog_tv ===============
[04:39:58] ============== drm_plane_helper (2 subtests) ===============
[04:39:58] =============== drm_test_check_plane_state ================
[04:39:58] [PASSED] clipping_simple
[04:39:58] [PASSED] clipping_rotate_reflect
[04:39:58] [PASSED] positioning_simple
[04:39:58] [PASSED] upscaling
[04:39:58] [PASSED] downscaling
[04:39:58] [PASSED] rounding1
[04:39:58] [PASSED] rounding2
[04:39:58] [PASSED] rounding3
[04:39:58] [PASSED] rounding4
[04:39:58] =========== [PASSED] drm_test_check_plane_state ============
[04:39:58] =========== drm_test_check_invalid_plane_state ============
[04:39:58] [PASSED] positioning_invalid
[04:39:58] [PASSED] upscaling_invalid
[04:39:58] [PASSED] downscaling_invalid
[04:39:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:39:58] ================ [PASSED] drm_plane_helper =================
[04:39:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:39:58] ====== drm_test_connector_helper_tv_get_modes_check =======
[04:39:58] [PASSED] None
[04:39:58] [PASSED] PAL
[04:39:58] [PASSED] NTSC
[04:39:58] [PASSED] Both, NTSC Default
[04:39:58] [PASSED] Both, PAL Default
[04:39:58] [PASSED] Both, NTSC Default, with PAL on command-line
[04:39:58] [PASSED] Both, PAL Default, with NTSC on command-line
[04:39:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:39:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:39:58] ================== drm_rect (9 subtests) ===================
[04:39:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:39:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:39:58] [PASSED] drm_test_rect_clip_scaled_clipped
[04:39:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:39:58] ================= drm_test_rect_intersect =================
[04:39:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:39:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:39:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:39:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:39:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:39:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:39:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:39:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:39:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:39:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:39:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:39:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:39:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:39:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:39:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:39:58] ============= [PASSED] drm_test_rect_intersect =============
[04:39:58] ================ drm_test_rect_calc_hscale ================
[04:39:58] [PASSED] normal use
[04:39:58] [PASSED] out of max range
[04:39:58] [PASSED] out of min range
[04:39:58] [PASSED] zero dst
[04:39:58] [PASSED] negative src
[04:39:58] [PASSED] negative dst
[04:39:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:39:58] ================ drm_test_rect_calc_vscale ================
[04:39:58] [PASSED] normal use
[04:39:58] [PASSED] out of max range
[04:39:58] [PASSED] out of min range
[04:39:58] [PASSED] zero dst
[04:39:58] [PASSED] negative src
[04:39:58] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[04:39:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:39:58] ================== drm_test_rect_rotate ===================
[04:39:58] [PASSED] reflect-x
[04:39:58] [PASSED] reflect-y
[04:39:58] [PASSED] rotate-0
[04:39:58] [PASSED] rotate-90
[04:39:58] [PASSED] rotate-180
[04:39:58] [PASSED] rotate-270
[04:39:58] ============== [PASSED] drm_test_rect_rotate ===============
[04:39:58] ================ drm_test_rect_rotate_inv =================
[04:39:58] [PASSED] reflect-x
[04:39:58] [PASSED] reflect-y
[04:39:58] [PASSED] rotate-0
[04:39:58] [PASSED] rotate-90
[04:39:58] [PASSED] rotate-180
[04:39:58] [PASSED] rotate-270
[04:39:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:39:58] ==================== [PASSED] drm_rect =====================
[04:39:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:39:58] ============ drm_test_sysfb_build_fourcc_list =============
[04:39:58] [PASSED] no native formats
[04:39:58] [PASSED] XRGB8888 as native format
[04:39:58] [PASSED] remove duplicates
[04:39:58] [PASSED] convert alpha formats
[04:39:58] [PASSED] random formats
[04:39:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:39:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:39:58] ================== drm_fixp (2 subtests) ===================
[04:39:58] [PASSED] drm_test_int2fixp
[04:39:58] [PASSED] drm_test_sm2fixp
[04:39:58] ==================== [PASSED] drm_fixp =====================
[04:39:58] ============================================================
[04:39:58] Testing complete. Ran 621 tests: passed: 621
[04:39:58] Elapsed time: 27.218s total, 1.647s configuring, 25.390s building, 0.180s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:39:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:39:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:40:09] Starting KUnit Kernel (1/1)...
[04:40:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:40:09] ================= ttm_device (5 subtests) ==================
[04:40:09] [PASSED] ttm_device_init_basic
[04:40:09] [PASSED] ttm_device_init_multiple
[04:40:09] [PASSED] ttm_device_fini_basic
[04:40:09] [PASSED] ttm_device_init_no_vma_man
[04:40:09] ================== ttm_device_init_pools ==================
[04:40:09] [PASSED] No DMA allocations, no DMA32 required
[04:40:09] [PASSED] DMA allocations, DMA32 required
[04:40:09] [PASSED] No DMA allocations, DMA32 required
[04:40:09] [PASSED] DMA allocations, no DMA32 required
[04:40:09] ============== [PASSED] ttm_device_init_pools ==============
[04:40:09] =================== [PASSED] ttm_device ====================
[04:40:09] ================== ttm_pool (8 subtests) ===================
[04:40:09] ================== ttm_pool_alloc_basic ===================
[04:40:09] [PASSED] One page
[04:40:09] [PASSED] More than one page
[04:40:09] [PASSED] Above the allocation limit
[04:40:09] [PASSED] One page, with coherent DMA mappings enabled
[04:40:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:40:09] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:40:09] ============== ttm_pool_alloc_basic_dma_addr ==============
[04:40:09] [PASSED] One page
[04:40:09] [PASSED] More than one page
[04:40:09] [PASSED] Above the allocation limit
[04:40:09] [PASSED] One page, with coherent DMA mappings enabled
[04:40:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:40:09] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:40:09] [PASSED] ttm_pool_alloc_order_caching_match
[04:40:09] [PASSED] ttm_pool_alloc_caching_mismatch
[04:40:09] [PASSED] ttm_pool_alloc_order_mismatch
[04:40:09] [PASSED] ttm_pool_free_dma_alloc
[04:40:09] [PASSED] ttm_pool_free_no_dma_alloc
[04:40:09] [PASSED] ttm_pool_fini_basic
[04:40:09] ==================== [PASSED] ttm_pool =====================
[04:40:09] ================ ttm_resource (8 subtests) =================
[04:40:09] ================= ttm_resource_init_basic =================
[04:40:09] [PASSED] Init resource in TTM_PL_SYSTEM
[04:40:09] [PASSED] Init resource in TTM_PL_VRAM
[04:40:09] [PASSED] Init resource in a private placement
[04:40:09] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:40:09] ============= [PASSED] ttm_resource_init_basic =============
[04:40:09] [PASSED] ttm_resource_init_pinned
[04:40:09] [PASSED] ttm_resource_fini_basic
[04:40:09] [PASSED] ttm_resource_manager_init_basic
[04:40:09] [PASSED] ttm_resource_manager_usage_basic
[04:40:09] [PASSED] ttm_resource_manager_set_used_basic
[04:40:09] [PASSED] ttm_sys_man_alloc_basic
[04:40:09] [PASSED] ttm_sys_man_free_basic
[04:40:09] ================== [PASSED] ttm_resource ===================
[04:40:09] =================== ttm_tt (15 subtests) ===================
[04:40:09] ==================== ttm_tt_init_basic ====================
[04:40:09] [PASSED] Page-aligned size
[04:40:09] [PASSED] Extra pages requested
[04:40:09] ================ [PASSED] ttm_tt_init_basic ================
[04:40:09] [PASSED] ttm_tt_init_misaligned
[04:40:09] [PASSED] ttm_tt_fini_basic
[04:40:09] [PASSED] ttm_tt_fini_sg
[04:40:09] [PASSED] ttm_tt_fini_shmem
[04:40:09] [PASSED] ttm_tt_create_basic
[04:40:09] [PASSED] ttm_tt_create_invalid_bo_type
[04:40:09] [PASSED] ttm_tt_create_ttm_exists
[04:40:09] [PASSED] ttm_tt_create_failed
[04:40:09] [PASSED] ttm_tt_destroy_basic
[04:40:09] [PASSED] ttm_tt_populate_null_ttm
[04:40:09] [PASSED] ttm_tt_populate_populated_ttm
[04:40:09] [PASSED] ttm_tt_unpopulate_basic
[04:40:09] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:40:09] [PASSED] ttm_tt_swapin_basic
[04:40:09] ===================== [PASSED] ttm_tt ======================
[04:40:09] =================== ttm_bo (14 subtests) ===================
[04:40:09] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[04:40:09] [PASSED] Cannot be interrupted and sleeps
[04:40:09] [PASSED] Cannot be interrupted, locks straight away
[04:40:09] [PASSED] Can be interrupted, sleeps
[04:40:09] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:40:09] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:40:09] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:40:09] [PASSED] ttm_bo_reserve_double_resv
[04:40:09] [PASSED] ttm_bo_reserve_interrupted
[04:40:09] [PASSED] ttm_bo_reserve_deadlock
[04:40:09] [PASSED] ttm_bo_unreserve_basic
[04:40:09] [PASSED] ttm_bo_unreserve_pinned
[04:40:09] [PASSED] ttm_bo_unreserve_bulk
[04:40:09] [PASSED] ttm_bo_fini_basic
[04:40:09] [PASSED] ttm_bo_fini_shared_resv
[04:40:09] [PASSED] ttm_bo_pin_basic
[04:40:09] [PASSED] ttm_bo_pin_unpin_resource
[04:40:09] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:40:09] ===================== [PASSED] ttm_bo ======================
[04:40:09] ============== ttm_bo_validate (21 subtests) ===============
[04:40:09] ============== ttm_bo_init_reserved_sys_man ===============
[04:40:09] [PASSED] Buffer object for userspace
[04:40:09] [PASSED] Kernel buffer object
[04:40:09] [PASSED] Shared buffer object
[04:40:09] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:40:09] ============== ttm_bo_init_reserved_mock_man ==============
[04:40:09] [PASSED] Buffer object for userspace
[04:40:09] [PASSED] Kernel buffer object
[04:40:09] [PASSED] Shared buffer object
[04:40:09] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:40:09] [PASSED] ttm_bo_init_reserved_resv
[04:40:09] ================== ttm_bo_validate_basic ==================
[04:40:09] [PASSED] Buffer object for userspace
[04:40:09] [PASSED] Kernel buffer object
[04:40:09] [PASSED] Shared buffer object
[04:40:09] ============== [PASSED] ttm_bo_validate_basic ==============
[04:40:09] [PASSED] ttm_bo_validate_invalid_placement
[04:40:09] ============= ttm_bo_validate_same_placement ==============
[04:40:09] [PASSED] System manager
[04:40:09] [PASSED] VRAM manager
[04:40:09] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:40:09] [PASSED] ttm_bo_validate_failed_alloc
[04:40:09] [PASSED] ttm_bo_validate_pinned
[04:40:09] [PASSED] ttm_bo_validate_busy_placement
[04:40:09] ================ ttm_bo_validate_multihop =================
[04:40:09] [PASSED] Buffer object for userspace
[04:40:09] [PASSED] Kernel buffer object
[04:40:09] [PASSED] Shared buffer object
[04:40:09] ============ [PASSED] ttm_bo_validate_multihop =============
[04:40:09] ========== ttm_bo_validate_no_placement_signaled ==========
[04:40:09] [PASSED] Buffer object in system domain, no page vector
[04:40:09] [PASSED] Buffer object in system domain with an existing page vector
[04:40:09] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:40:09] ======== ttm_bo_validate_no_placement_not_signaled ========
[04:40:09] [PASSED] Buffer object for userspace
[04:40:09] [PASSED] Kernel buffer object
[04:40:09] [PASSED] Shared buffer object
[04:40:09] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:40:09] [PASSED] ttm_bo_validate_move_fence_signaled
[04:40:09] ========= ttm_bo_validate_move_fence_not_signaled =========
[04:40:09] [PASSED] Waits for GPU
[04:40:09] [PASSED] Tries to lock straight away
[04:40:09] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:40:09] [PASSED] ttm_bo_validate_happy_evict
[04:40:09] [PASSED] ttm_bo_validate_all_pinned_evict
[04:40:09] [PASSED] ttm_bo_validate_allowed_only_evict
[04:40:09] [PASSED] ttm_bo_validate_deleted_evict
[04:40:09] [PASSED] ttm_bo_validate_busy_domain_evict
[04:40:09] [PASSED] ttm_bo_validate_evict_gutting
[04:40:09] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:40:09] ================= [PASSED] ttm_bo_validate =================
[04:40:09] ============================================================
[04:40:09] Testing complete. Ran 101 tests: passed: 101
[04:40:09] Elapsed time: 11.530s total, 1.678s configuring, 9.585s building, 0.225s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✗ Xe.CI.BAT: failure for dGPU memory optimizations
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (3 preceding siblings ...)
2026-02-18 4:40 ` ✓ CI.KUnit: success for dGPU memory optimizations Patchwork
@ 2026-02-18 5:23 ` Patchwork
2026-02-18 6:15 ` ✗ Xe.CI.FULL: " Patchwork
` (6 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 5:23 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1479 bytes --]
== Series Details ==
Series: dGPU memory optimizations
URL : https://patchwork.freedesktop.org/series/161737/
State : failure
== Summary ==
CI Bug Log - changes from xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d_BAT -> xe-pw-161737v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-161737v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-161737v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (14 -> 0)
------------------------------
ERROR: It appears as if the changes made in xe-pw-161737v1_BAT prevented too many machines from booting.
Missing (14): bat-bmg-1 bat-lnl-2 bat-lnl-1 bat-ptl-1 bat-ptl-vm bat-ptl-2 bat-dg2-oem2 bat-atsm-2 bat-bmg-3 bat-wcl-1 bat-wcl-2 bat-bmg-2 bat-adlp-vm bat-adlp-7
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8757 -> IGT_8758
* Linux: xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d -> xe-pw-161737v1
IGT_8757: 8757
IGT_8758: 8758
xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d: c8daef66f8603b6216e5fa70288998d7f0357e3d
xe-pw-161737v1: 161737v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v1/index.html
[-- Attachment #2: Type: text/html, Size: 2065 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✗ Xe.CI.FULL: failure for dGPU memory optimizations
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (4 preceding siblings ...)
2026-02-18 5:23 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-02-18 6:15 ` Patchwork
2026-02-18 7:07 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev2) Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 6:15 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1354 bytes --]
== Series Details ==
Series: dGPU memory optimizations
URL : https://patchwork.freedesktop.org/series/161737/
State : failure
== Summary ==
CI Bug Log - changes from xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d_FULL -> xe-pw-161737v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-161737v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-161737v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 0)
------------------------------
ERROR: It appears as if the changes made in xe-pw-161737v1_FULL prevented too many machines from booting.
Missing (2): shard-bmg shard-lnl
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8757 -> IGT_8758
* Linux: xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d -> xe-pw-161737v1
IGT_8757: 8757
IGT_8758: 8758
xe-4571-c8daef66f8603b6216e5fa70288998d7f0357e3d: c8daef66f8603b6216e5fa70288998d7f0357e3d
xe-pw-161737v1: 161737v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v1/index.html
[-- Attachment #2: Type: text/html, Size: 1940 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ CI.KUnit: success for dGPU memory optimizations (rev2)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (5 preceding siblings ...)
2026-02-18 6:15 ` ✗ Xe.CI.FULL: " Patchwork
@ 2026-02-18 7:07 ` Patchwork
2026-02-18 7:36 ` ✓ Xe.CI.BAT: " Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 7:07 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: dGPU memory optimizations (rev2)
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:05:58] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:06:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:06:34] Starting KUnit Kernel (1/1)...
[07:06:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:06:34] ================== guc_buf (11 subtests) ===================
[07:06:34] [PASSED] test_smallest
[07:06:34] [PASSED] test_largest
[07:06:34] [PASSED] test_granular
[07:06:34] [PASSED] test_unique
[07:06:34] [PASSED] test_overlap
[07:06:34] [PASSED] test_reusable
[07:06:34] [PASSED] test_too_big
[07:06:34] [PASSED] test_flush
[07:06:34] [PASSED] test_lookup
[07:06:34] [PASSED] test_data
[07:06:34] [PASSED] test_class
[07:06:34] ===================== [PASSED] guc_buf =====================
[07:06:34] =================== guc_dbm (7 subtests) ===================
[07:06:34] [PASSED] test_empty
[07:06:34] [PASSED] test_default
[07:06:34] ======================== test_size ========================
[07:06:34] [PASSED] 4
[07:06:34] [PASSED] 8
[07:06:34] [PASSED] 32
[07:06:34] [PASSED] 256
[07:06:34] ==================== [PASSED] test_size ====================
[07:06:34] ======================= test_reuse ========================
[07:06:34] [PASSED] 4
[07:06:34] [PASSED] 8
[07:06:34] [PASSED] 32
[07:06:34] [PASSED] 256
[07:06:34] =================== [PASSED] test_reuse ====================
[07:06:34] =================== test_range_overlap ====================
[07:06:34] [PASSED] 4
[07:06:34] [PASSED] 8
[07:06:34] [PASSED] 32
[07:06:34] [PASSED] 256
[07:06:34] =============== [PASSED] test_range_overlap ================
[07:06:34] =================== test_range_compact ====================
[07:06:34] [PASSED] 4
[07:06:34] [PASSED] 8
[07:06:34] [PASSED] 32
[07:06:34] [PASSED] 256
[07:06:34] =============== [PASSED] test_range_compact ================
[07:06:34] ==================== test_range_spare =====================
[07:06:34] [PASSED] 4
[07:06:34] [PASSED] 8
[07:06:34] [PASSED] 32
[07:06:34] [PASSED] 256
[07:06:34] ================ [PASSED] test_range_spare =================
[07:06:34] ===================== [PASSED] guc_dbm =====================
[07:06:34] =================== guc_idm (6 subtests) ===================
[07:06:34] [PASSED] bad_init
[07:06:34] [PASSED] no_init
[07:06:34] [PASSED] init_fini
[07:06:34] [PASSED] check_used
[07:06:34] [PASSED] check_quota
[07:06:34] [PASSED] check_all
[07:06:34] ===================== [PASSED] guc_idm =====================
[07:06:34] ================== no_relay (3 subtests) ===================
[07:06:34] [PASSED] xe_drops_guc2pf_if_not_ready
[07:06:34] [PASSED] xe_drops_guc2vf_if_not_ready
[07:06:34] [PASSED] xe_rejects_send_if_not_ready
[07:06:34] ==================== [PASSED] no_relay =====================
[07:06:34] ================== pf_relay (14 subtests) ==================
[07:06:34] [PASSED] pf_rejects_guc2pf_too_short
[07:06:34] [PASSED] pf_rejects_guc2pf_too_long
[07:06:34] [PASSED] pf_rejects_guc2pf_no_payload
[07:06:34] [PASSED] pf_fails_no_payload
[07:06:34] [PASSED] pf_fails_bad_origin
[07:06:34] [PASSED] pf_fails_bad_type
[07:06:34] [PASSED] pf_txn_reports_error
[07:06:34] [PASSED] pf_txn_sends_pf2guc
[07:06:34] [PASSED] pf_sends_pf2guc
[07:06:34] [SKIPPED] pf_loopback_nop
[07:06:34] [SKIPPED] pf_loopback_echo
[07:06:34] [SKIPPED] pf_loopback_fail
[07:06:34] [SKIPPED] pf_loopback_busy
[07:06:34] [SKIPPED] pf_loopback_retry
[07:06:34] ==================== [PASSED] pf_relay =====================
[07:06:34] ================== vf_relay (3 subtests) ===================
[07:06:34] [PASSED] vf_rejects_guc2vf_too_short
[07:06:34] [PASSED] vf_rejects_guc2vf_too_long
[07:06:34] [PASSED] vf_rejects_guc2vf_no_payload
[07:06:34] ==================== [PASSED] vf_relay =====================
[07:06:34] ================ pf_gt_config (6 subtests) =================
[07:06:34] [PASSED] fair_contexts_1vf
[07:06:34] [PASSED] fair_doorbells_1vf
[07:06:34] [PASSED] fair_ggtt_1vf
[07:06:34] ====================== fair_contexts ======================
[07:06:34] [PASSED] 1 VF
[07:06:34] [PASSED] 2 VFs
[07:06:34] [PASSED] 3 VFs
[07:06:34] [PASSED] 4 VFs
[07:06:34] [PASSED] 5 VFs
[07:06:34] [PASSED] 6 VFs
[07:06:34] [PASSED] 7 VFs
[07:06:34] [PASSED] 8 VFs
[07:06:35] [PASSED] 9 VFs
[07:06:35] [PASSED] 10 VFs
[07:06:35] [PASSED] 11 VFs
[07:06:35] [PASSED] 12 VFs
[07:06:35] [PASSED] 13 VFs
[07:06:35] [PASSED] 14 VFs
[07:06:35] [PASSED] 15 VFs
[07:06:35] [PASSED] 16 VFs
[07:06:35] [PASSED] 17 VFs
[07:06:35] [PASSED] 18 VFs
[07:06:35] [PASSED] 19 VFs
[07:06:35] [PASSED] 20 VFs
[07:06:35] [PASSED] 21 VFs
[07:06:35] [PASSED] 22 VFs
[07:06:35] [PASSED] 23 VFs
[07:06:35] [PASSED] 24 VFs
[07:06:35] [PASSED] 25 VFs
[07:06:35] [PASSED] 26 VFs
[07:06:35] [PASSED] 27 VFs
[07:06:35] [PASSED] 28 VFs
[07:06:35] [PASSED] 29 VFs
[07:06:35] [PASSED] 30 VFs
[07:06:35] [PASSED] 31 VFs
[07:06:35] [PASSED] 32 VFs
[07:06:35] [PASSED] 33 VFs
[07:06:35] [PASSED] 34 VFs
[07:06:35] [PASSED] 35 VFs
[07:06:35] [PASSED] 36 VFs
[07:06:35] [PASSED] 37 VFs
[07:06:35] [PASSED] 38 VFs
[07:06:35] [PASSED] 39 VFs
[07:06:35] [PASSED] 40 VFs
[07:06:35] [PASSED] 41 VFs
[07:06:35] [PASSED] 42 VFs
[07:06:35] [PASSED] 43 VFs
[07:06:35] [PASSED] 44 VFs
[07:06:35] [PASSED] 45 VFs
[07:06:35] [PASSED] 46 VFs
[07:06:35] [PASSED] 47 VFs
[07:06:35] [PASSED] 48 VFs
[07:06:35] [PASSED] 49 VFs
[07:06:35] [PASSED] 50 VFs
[07:06:35] [PASSED] 51 VFs
[07:06:35] [PASSED] 52 VFs
[07:06:35] [PASSED] 53 VFs
[07:06:35] [PASSED] 54 VFs
[07:06:35] [PASSED] 55 VFs
[07:06:35] [PASSED] 56 VFs
[07:06:35] [PASSED] 57 VFs
[07:06:35] [PASSED] 58 VFs
[07:06:35] [PASSED] 59 VFs
[07:06:35] [PASSED] 60 VFs
[07:06:35] [PASSED] 61 VFs
[07:06:35] [PASSED] 62 VFs
[07:06:35] [PASSED] 63 VFs
[07:06:35] ================== [PASSED] fair_contexts ==================
[07:06:35] ===================== fair_doorbells ======================
[07:06:35] [PASSED] 1 VF
[07:06:35] [PASSED] 2 VFs
[07:06:35] [PASSED] 3 VFs
[07:06:35] [PASSED] 4 VFs
[07:06:35] [PASSED] 5 VFs
[07:06:35] [PASSED] 6 VFs
[07:06:35] [PASSED] 7 VFs
[07:06:35] [PASSED] 8 VFs
[07:06:35] [PASSED] 9 VFs
[07:06:35] [PASSED] 10 VFs
[07:06:35] [PASSED] 11 VFs
[07:06:35] [PASSED] 12 VFs
[07:06:35] [PASSED] 13 VFs
[07:06:35] [PASSED] 14 VFs
[07:06:35] [PASSED] 15 VFs
[07:06:35] [PASSED] 16 VFs
[07:06:35] [PASSED] 17 VFs
[07:06:35] [PASSED] 18 VFs
[07:06:35] [PASSED] 19 VFs
[07:06:35] [PASSED] 20 VFs
[07:06:35] [PASSED] 21 VFs
[07:06:35] [PASSED] 22 VFs
[07:06:35] [PASSED] 23 VFs
[07:06:35] [PASSED] 24 VFs
[07:06:35] [PASSED] 25 VFs
[07:06:35] [PASSED] 26 VFs
[07:06:35] [PASSED] 27 VFs
[07:06:35] [PASSED] 28 VFs
[07:06:35] [PASSED] 29 VFs
[07:06:35] [PASSED] 30 VFs
[07:06:35] [PASSED] 31 VFs
[07:06:35] [PASSED] 32 VFs
[07:06:35] [PASSED] 33 VFs
[07:06:35] [PASSED] 34 VFs
[07:06:35] [PASSED] 35 VFs
[07:06:35] [PASSED] 36 VFs
[07:06:35] [PASSED] 37 VFs
[07:06:35] [PASSED] 38 VFs
[07:06:35] [PASSED] 39 VFs
[07:06:35] [PASSED] 40 VFs
[07:06:35] [PASSED] 41 VFs
[07:06:35] [PASSED] 42 VFs
[07:06:35] [PASSED] 43 VFs
[07:06:35] [PASSED] 44 VFs
[07:06:35] [PASSED] 45 VFs
[07:06:35] [PASSED] 46 VFs
[07:06:35] [PASSED] 47 VFs
[07:06:35] [PASSED] 48 VFs
[07:06:35] [PASSED] 49 VFs
[07:06:35] [PASSED] 50 VFs
[07:06:35] [PASSED] 51 VFs
[07:06:35] [PASSED] 52 VFs
[07:06:35] [PASSED] 53 VFs
[07:06:35] [PASSED] 54 VFs
[07:06:35] [PASSED] 55 VFs
[07:06:35] [PASSED] 56 VFs
[07:06:35] [PASSED] 57 VFs
[07:06:35] [PASSED] 58 VFs
[07:06:35] [PASSED] 59 VFs
[07:06:35] [PASSED] 60 VFs
[07:06:35] [PASSED] 61 VFs
[07:06:35] [PASSED] 62 VFs
[07:06:35] [PASSED] 63 VFs
[07:06:35] ================= [PASSED] fair_doorbells ==================
[07:06:35] ======================== fair_ggtt ========================
[07:06:35] [PASSED] 1 VF
[07:06:35] [PASSED] 2 VFs
[07:06:35] [PASSED] 3 VFs
[07:06:35] [PASSED] 4 VFs
[07:06:35] [PASSED] 5 VFs
[07:06:35] [PASSED] 6 VFs
[07:06:35] [PASSED] 7 VFs
[07:06:35] [PASSED] 8 VFs
[07:06:35] [PASSED] 9 VFs
[07:06:35] [PASSED] 10 VFs
[07:06:35] [PASSED] 11 VFs
[07:06:35] [PASSED] 12 VFs
[07:06:35] [PASSED] 13 VFs
[07:06:35] [PASSED] 14 VFs
[07:06:35] [PASSED] 15 VFs
[07:06:35] [PASSED] 16 VFs
[07:06:35] [PASSED] 17 VFs
[07:06:35] [PASSED] 18 VFs
[07:06:35] [PASSED] 19 VFs
[07:06:35] [PASSED] 20 VFs
[07:06:35] [PASSED] 21 VFs
[07:06:35] [PASSED] 22 VFs
[07:06:35] [PASSED] 23 VFs
[07:06:35] [PASSED] 24 VFs
[07:06:35] [PASSED] 25 VFs
[07:06:35] [PASSED] 26 VFs
[07:06:35] [PASSED] 27 VFs
[07:06:35] [PASSED] 28 VFs
[07:06:35] [PASSED] 29 VFs
[07:06:35] [PASSED] 30 VFs
[07:06:35] [PASSED] 31 VFs
[07:06:35] [PASSED] 32 VFs
[07:06:35] [PASSED] 33 VFs
[07:06:35] [PASSED] 34 VFs
[07:06:35] [PASSED] 35 VFs
[07:06:35] [PASSED] 36 VFs
[07:06:35] [PASSED] 37 VFs
[07:06:35] [PASSED] 38 VFs
[07:06:35] [PASSED] 39 VFs
[07:06:35] [PASSED] 40 VFs
[07:06:35] [PASSED] 41 VFs
[07:06:35] [PASSED] 42 VFs
[07:06:35] [PASSED] 43 VFs
[07:06:35] [PASSED] 44 VFs
[07:06:35] [PASSED] 45 VFs
[07:06:35] [PASSED] 46 VFs
[07:06:35] [PASSED] 47 VFs
[07:06:35] [PASSED] 48 VFs
[07:06:35] [PASSED] 49 VFs
[07:06:35] [PASSED] 50 VFs
[07:06:35] [PASSED] 51 VFs
[07:06:35] [PASSED] 52 VFs
[07:06:35] [PASSED] 53 VFs
[07:06:35] [PASSED] 54 VFs
[07:06:35] [PASSED] 55 VFs
[07:06:35] [PASSED] 56 VFs
[07:06:35] [PASSED] 57 VFs
[07:06:35] [PASSED] 58 VFs
[07:06:35] [PASSED] 59 VFs
[07:06:35] [PASSED] 60 VFs
[07:06:35] [PASSED] 61 VFs
[07:06:35] [PASSED] 62 VFs
[07:06:35] [PASSED] 63 VFs
[07:06:35] ==================== [PASSED] fair_ggtt ====================
[07:06:35] ================== [PASSED] pf_gt_config ===================
[07:06:35] ===================== lmtt (1 subtest) =====================
[07:06:35] ======================== test_ops =========================
[07:06:35] [PASSED] 2-level
[07:06:35] [PASSED] multi-level
[07:06:35] ==================== [PASSED] test_ops =====================
[07:06:35] ====================== [PASSED] lmtt =======================
[07:06:35] ================= pf_service (11 subtests) =================
[07:06:35] [PASSED] pf_negotiate_any
[07:06:35] [PASSED] pf_negotiate_base_match
[07:06:35] [PASSED] pf_negotiate_base_newer
[07:06:35] [PASSED] pf_negotiate_base_next
[07:06:35] [SKIPPED] pf_negotiate_base_older
[07:06:35] [PASSED] pf_negotiate_base_prev
[07:06:35] [PASSED] pf_negotiate_latest_match
[07:06:35] [PASSED] pf_negotiate_latest_newer
[07:06:35] [PASSED] pf_negotiate_latest_next
[07:06:35] [SKIPPED] pf_negotiate_latest_older
[07:06:35] [SKIPPED] pf_negotiate_latest_prev
[07:06:35] =================== [PASSED] pf_service ====================
[07:06:35] ================= xe_guc_g2g (2 subtests) ==================
[07:06:35] ============== xe_live_guc_g2g_kunit_default ==============
[07:06:35] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:06:35] ============== xe_live_guc_g2g_kunit_allmem ===============
[07:06:35] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:06:35] =================== [SKIPPED] xe_guc_g2g ===================
[07:06:35] =================== xe_mocs (2 subtests) ===================
[07:06:35] ================ xe_live_mocs_kernel_kunit ================
[07:06:35] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:06:35] ================ xe_live_mocs_reset_kunit =================
[07:06:35] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:06:35] ==================== [SKIPPED] xe_mocs =====================
[07:06:35] ================= xe_migrate (2 subtests) ==================
[07:06:35] ================= xe_migrate_sanity_kunit =================
[07:06:35] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:06:35] ================== xe_validate_ccs_kunit ==================
[07:06:35] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:06:35] =================== [SKIPPED] xe_migrate ===================
[07:06:35] ================== xe_dma_buf (1 subtest) ==================
[07:06:35] ==================== xe_dma_buf_kunit =====================
[07:06:35] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:06:35] =================== [SKIPPED] xe_dma_buf ===================
[07:06:35] ================= xe_bo_shrink (1 subtest) =================
[07:06:35] =================== xe_bo_shrink_kunit ====================
[07:06:35] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:06:35] ================== [SKIPPED] xe_bo_shrink ==================
[07:06:35] ==================== xe_bo (2 subtests) ====================
[07:06:35] ================== xe_ccs_migrate_kunit ===================
[07:06:35] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:06:35] ==================== xe_bo_evict_kunit ====================
[07:06:35] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:06:35] ===================== [SKIPPED] xe_bo ======================
[07:06:35] ==================== args (13 subtests) ====================
[07:06:35] [PASSED] count_args_test
[07:06:35] [PASSED] call_args_example
[07:06:35] [PASSED] call_args_test
[07:06:35] [PASSED] drop_first_arg_example
[07:06:35] [PASSED] drop_first_arg_test
[07:06:35] [PASSED] first_arg_example
[07:06:35] [PASSED] first_arg_test
[07:06:35] [PASSED] last_arg_example
[07:06:35] [PASSED] last_arg_test
[07:06:35] [PASSED] pick_arg_example
[07:06:35] [PASSED] if_args_example
[07:06:35] [PASSED] if_args_test
[07:06:35] [PASSED] sep_comma_example
[07:06:35] ====================== [PASSED] args =======================
[07:06:35] =================== xe_pci (3 subtests) ====================
[07:06:35] ==================== check_graphics_ip ====================
[07:06:35] [PASSED] 12.00 Xe_LP
[07:06:35] [PASSED] 12.10 Xe_LP+
[07:06:35] [PASSED] 12.55 Xe_HPG
[07:06:35] [PASSED] 12.60 Xe_HPC
[07:06:35] [PASSED] 12.70 Xe_LPG
[07:06:35] [PASSED] 12.71 Xe_LPG
[07:06:35] [PASSED] 12.74 Xe_LPG+
[07:06:35] [PASSED] 20.01 Xe2_HPG
[07:06:35] [PASSED] 20.02 Xe2_HPG
[07:06:35] [PASSED] 20.04 Xe2_LPG
[07:06:35] [PASSED] 30.00 Xe3_LPG
[07:06:35] [PASSED] 30.01 Xe3_LPG
[07:06:35] [PASSED] 30.03 Xe3_LPG
[07:06:35] [PASSED] 30.04 Xe3_LPG
[07:06:35] [PASSED] 30.05 Xe3_LPG
[07:06:35] [PASSED] 35.10 Xe3p_LPG
[07:06:35] [PASSED] 35.11 Xe3p_XPC
[07:06:35] ================ [PASSED] check_graphics_ip ================
[07:06:35] ===================== check_media_ip ======================
[07:06:35] [PASSED] 12.00 Xe_M
[07:06:35] [PASSED] 12.55 Xe_HPM
[07:06:35] [PASSED] 13.00 Xe_LPM+
[07:06:35] [PASSED] 13.01 Xe2_HPM
[07:06:35] [PASSED] 20.00 Xe2_LPM
[07:06:35] [PASSED] 30.00 Xe3_LPM
[07:06:35] [PASSED] 30.02 Xe3_LPM
[07:06:35] [PASSED] 35.00 Xe3p_LPM
[07:06:35] [PASSED] 35.03 Xe3p_HPM
[07:06:35] ================= [PASSED] check_media_ip ==================
[07:06:35] =================== check_platform_desc ===================
[07:06:35] [PASSED] 0x9A60 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A68 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A70 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A40 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A49 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A59 (TIGERLAKE)
[07:06:35] [PASSED] 0x9A78 (TIGERLAKE)
[07:06:35] [PASSED] 0x9AC0 (TIGERLAKE)
[07:06:35] [PASSED] 0x9AC9 (TIGERLAKE)
[07:06:35] [PASSED] 0x9AD9 (TIGERLAKE)
[07:06:35] [PASSED] 0x9AF8 (TIGERLAKE)
[07:06:35] [PASSED] 0x4C80 (ROCKETLAKE)
[07:06:35] [PASSED] 0x4C8A (ROCKETLAKE)
[07:06:35] [PASSED] 0x4C8B (ROCKETLAKE)
[07:06:35] [PASSED] 0x4C8C (ROCKETLAKE)
[07:06:35] [PASSED] 0x4C90 (ROCKETLAKE)
[07:06:35] [PASSED] 0x4C9A (ROCKETLAKE)
[07:06:35] [PASSED] 0x4680 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4682 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4688 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x468A (ALDERLAKE_S)
[07:06:35] [PASSED] 0x468B (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4690 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4692 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4693 (ALDERLAKE_S)
[07:06:35] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46AA (ALDERLAKE_P)
[07:06:35] [PASSED] 0x462A (ALDERLAKE_P)
[07:06:35] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[07:06:35] [PASSED] 0x4628 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:06:35] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:06:35] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:06:35] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:06:35] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:06:35] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:06:35] [PASSED] 0xA721 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA720 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:06:35] [PASSED] 0xA780 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA781 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA782 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA783 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA788 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA789 (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA78A (ALDERLAKE_S)
[07:06:35] [PASSED] 0xA78B (ALDERLAKE_S)
[07:06:35] [PASSED] 0x4905 (DG1)
[07:06:35] [PASSED] 0x4906 (DG1)
[07:06:35] [PASSED] 0x4907 (DG1)
[07:06:35] [PASSED] 0x4908 (DG1)
[07:06:35] [PASSED] 0x4909 (DG1)
[07:06:35] [PASSED] 0x56C0 (DG2)
[07:06:35] [PASSED] 0x56C2 (DG2)
[07:06:35] [PASSED] 0x56C1 (DG2)
[07:06:35] [PASSED] 0x7D51 (METEORLAKE)
[07:06:35] [PASSED] 0x7DD1 (METEORLAKE)
[07:06:35] [PASSED] 0x7D41 (METEORLAKE)
[07:06:35] [PASSED] 0x7D67 (METEORLAKE)
[07:06:35] [PASSED] 0xB640 (METEORLAKE)
[07:06:35] [PASSED] 0x56A0 (DG2)
[07:06:35] [PASSED] 0x56A1 (DG2)
[07:06:35] [PASSED] 0x56A2 (DG2)
[07:06:35] [PASSED] 0x56BE (DG2)
[07:06:35] [PASSED] 0x56BF (DG2)
[07:06:35] [PASSED] 0x5690 (DG2)
[07:06:35] [PASSED] 0x5691 (DG2)
[07:06:35] [PASSED] 0x5692 (DG2)
[07:06:35] [PASSED] 0x56A5 (DG2)
[07:06:35] [PASSED] 0x56A6 (DG2)
[07:06:35] [PASSED] 0x56B0 (DG2)
[07:06:35] [PASSED] 0x56B1 (DG2)
[07:06:35] [PASSED] 0x56BA (DG2)
[07:06:35] [PASSED] 0x56BB (DG2)
[07:06:35] [PASSED] 0x56BC (DG2)
[07:06:35] [PASSED] 0x56BD (DG2)
[07:06:35] [PASSED] 0x5693 (DG2)
[07:06:35] [PASSED] 0x5694 (DG2)
[07:06:35] [PASSED] 0x5695 (DG2)
[07:06:35] [PASSED] 0x56A3 (DG2)
[07:06:35] [PASSED] 0x56A4 (DG2)
[07:06:35] [PASSED] 0x56B2 (DG2)
[07:06:35] [PASSED] 0x56B3 (DG2)
[07:06:35] [PASSED] 0x5696 (DG2)
[07:06:35] [PASSED] 0x5697 (DG2)
[07:06:35] [PASSED] 0xB69 (PVC)
[07:06:35] [PASSED] 0xB6E (PVC)
[07:06:35] [PASSED] 0xBD4 (PVC)
[07:06:35] [PASSED] 0xBD5 (PVC)
[07:06:35] [PASSED] 0xBD6 (PVC)
[07:06:35] [PASSED] 0xBD7 (PVC)
[07:06:35] [PASSED] 0xBD8 (PVC)
[07:06:35] [PASSED] 0xBD9 (PVC)
[07:06:35] [PASSED] 0xBDA (PVC)
[07:06:35] [PASSED] 0xBDB (PVC)
[07:06:35] [PASSED] 0xBE0 (PVC)
[07:06:35] [PASSED] 0xBE1 (PVC)
[07:06:35] [PASSED] 0xBE5 (PVC)
[07:06:35] [PASSED] 0x7D40 (METEORLAKE)
[07:06:35] [PASSED] 0x7D45 (METEORLAKE)
[07:06:35] [PASSED] 0x7D55 (METEORLAKE)
[07:06:35] [PASSED] 0x7D60 (METEORLAKE)
[07:06:35] [PASSED] 0x7DD5 (METEORLAKE)
[07:06:35] [PASSED] 0x6420 (LUNARLAKE)
[07:06:35] [PASSED] 0x64A0 (LUNARLAKE)
[07:06:35] [PASSED] 0x64B0 (LUNARLAKE)
[07:06:35] [PASSED] 0xE202 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE209 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE20B (BATTLEMAGE)
[07:06:35] [PASSED] 0xE20C (BATTLEMAGE)
[07:06:35] [PASSED] 0xE20D (BATTLEMAGE)
[07:06:35] [PASSED] 0xE210 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE211 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE212 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE216 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE220 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE221 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE222 (BATTLEMAGE)
[07:06:35] [PASSED] 0xE223 (BATTLEMAGE)
[07:06:35] [PASSED] 0xB080 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB081 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB082 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB083 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB084 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB085 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB086 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB087 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB08F (PANTHERLAKE)
[07:06:35] [PASSED] 0xB090 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:06:35] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:06:35] [PASSED] 0xFD80 (PANTHERLAKE)
[07:06:35] [PASSED] 0xFD81 (PANTHERLAKE)
[07:06:35] [PASSED] 0xD740 (NOVALAKE_S)
[07:06:35] [PASSED] 0xD741 (NOVALAKE_S)
[07:06:35] [PASSED] 0xD742 (NOVALAKE_S)
[07:06:35] [PASSED] 0xD743 (NOVALAKE_S)
[07:06:35] [PASSED] 0xD744 (NOVALAKE_S)
[07:06:35] [PASSED] 0xD745 (NOVALAKE_S)
[07:06:35] [PASSED] 0x674C (CRESCENTISLAND)
[07:06:35] [PASSED] 0xD750 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD751 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD752 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD753 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD754 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD755 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD756 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD757 (NOVALAKE_P)
[07:06:35] [PASSED] 0xD75F (NOVALAKE_P)
[07:06:35] =============== [PASSED] check_platform_desc ===============
[07:06:35] ===================== [PASSED] xe_pci ======================
[07:06:35] =================== xe_rtp (2 subtests) ====================
[07:06:35] =============== xe_rtp_process_to_sr_tests ================
[07:06:35] [PASSED] coalesce-same-reg
[07:06:35] [PASSED] no-match-no-add
[07:06:35] [PASSED] match-or
[07:06:35] [PASSED] match-or-xfail
[07:06:35] [PASSED] no-match-no-add-multiple-rules
[07:06:35] [PASSED] two-regs-two-entries
[07:06:35] [PASSED] clr-one-set-other
[07:06:35] [PASSED] set-field
[07:06:35] [PASSED] conflict-duplicate
[07:06:35] [PASSED] conflict-not-disjoint
[07:06:35] [PASSED] conflict-reg-type
[07:06:35] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:06:35] ================== xe_rtp_process_tests ===================
[07:06:35] [PASSED] active1
[07:06:35] [PASSED] active2
[07:06:35] [PASSED] active-inactive
[07:06:35] [PASSED] inactive-active
[07:06:35] [PASSED] inactive-1st_or_active-inactive
[07:06:35] [PASSED] inactive-2nd_or_active-inactive
[07:06:35] [PASSED] inactive-last_or_active-inactive
[07:06:35] [PASSED] inactive-no_or_active-inactive
[07:06:35] ============== [PASSED] xe_rtp_process_tests ===============
[07:06:35] ===================== [PASSED] xe_rtp ======================
[07:06:35] ==================== xe_wa (1 subtest) =====================
[07:06:35] ======================== xe_wa_gt =========================
[07:06:35] [PASSED] TIGERLAKE B0
[07:06:35] [PASSED] DG1 A0
[07:06:35] [PASSED] DG1 B0
[07:06:35] [PASSED] ALDERLAKE_S A0
[07:06:35] [PASSED] ALDERLAKE_S B0
[07:06:35] [PASSED] ALDERLAKE_S C0
[07:06:35] [PASSED] ALDERLAKE_S D0
[07:06:35] [PASSED] ALDERLAKE_P A0
[07:06:35] [PASSED] ALDERLAKE_P B0
[07:06:35] [PASSED] ALDERLAKE_P C0
[07:06:35] [PASSED] ALDERLAKE_S RPLS D0
[07:06:35] [PASSED] ALDERLAKE_P RPLU E0
[07:06:35] [PASSED] DG2 G10 C0
[07:06:35] [PASSED] DG2 G11 B1
[07:06:35] [PASSED] DG2 G12 A1
[07:06:35] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:06:35] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:06:35] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:06:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:06:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:06:35] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:06:35] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:06:35] ==================== [PASSED] xe_wa_gt =====================
[07:06:35] ====================== [PASSED] xe_wa ======================
[07:06:35] ============================================================
[07:06:35] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[07:06:35] Elapsed time: 36.529s total, 4.220s configuring, 31.792s building, 0.469s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:06:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:06:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:07:02] Starting KUnit Kernel (1/1)...
[07:07:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:07:02] ============ drm_test_pick_cmdline (2 subtests) ============
[07:07:02] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:07:02] =============== drm_test_pick_cmdline_named ===============
[07:07:02] [PASSED] NTSC
[07:07:02] [PASSED] NTSC-J
[07:07:02] [PASSED] PAL
[07:07:02] [PASSED] PAL-M
[07:07:02] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:07:02] ============== [PASSED] drm_test_pick_cmdline ==============
[07:07:02] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:07:02] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:07:02] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:07:02] =========== drm_validate_clone_mode (2 subtests) ===========
[07:07:02] ============== drm_test_check_in_clone_mode ===============
[07:07:02] [PASSED] in_clone_mode
[07:07:02] [PASSED] not_in_clone_mode
[07:07:02] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:07:02] =============== drm_test_check_valid_clones ===============
[07:07:02] [PASSED] not_in_clone_mode
[07:07:02] [PASSED] valid_clone
[07:07:02] [PASSED] invalid_clone
[07:07:02] =========== [PASSED] drm_test_check_valid_clones ===========
[07:07:02] ============= [PASSED] drm_validate_clone_mode =============
[07:07:02] ============= drm_validate_modeset (1 subtest) =============
[07:07:02] [PASSED] drm_test_check_connector_changed_modeset
[07:07:02] ============== [PASSED] drm_validate_modeset ===============
[07:07:02] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:07:02] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:07:02] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:07:02] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:07:02] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:07:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:07:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:07:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:07:02] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:07:02] ============== drm_bridge_alloc (2 subtests) ===============
[07:07:02] [PASSED] drm_test_drm_bridge_alloc_basic
[07:07:02] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:07:02] ================ [PASSED] drm_bridge_alloc =================
[07:07:02] ============= drm_cmdline_parser (40 subtests) =============
[07:07:02] [PASSED] drm_test_cmdline_force_d_only
[07:07:02] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:07:02] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:07:02] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:07:02] [PASSED] drm_test_cmdline_force_e_only
[07:07:02] [PASSED] drm_test_cmdline_res
[07:07:02] [PASSED] drm_test_cmdline_res_vesa
[07:07:02] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:07:02] [PASSED] drm_test_cmdline_res_rblank
[07:07:02] [PASSED] drm_test_cmdline_res_bpp
[07:07:02] [PASSED] drm_test_cmdline_res_refresh
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:07:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:07:02] [PASSED] drm_test_cmdline_res_margins_force_on
[07:07:02] [PASSED] drm_test_cmdline_res_vesa_margins
[07:07:02] [PASSED] drm_test_cmdline_name
[07:07:02] [PASSED] drm_test_cmdline_name_bpp
[07:07:02] [PASSED] drm_test_cmdline_name_option
[07:07:02] [PASSED] drm_test_cmdline_name_bpp_option
[07:07:02] [PASSED] drm_test_cmdline_rotate_0
[07:07:02] [PASSED] drm_test_cmdline_rotate_90
[07:07:02] [PASSED] drm_test_cmdline_rotate_180
[07:07:02] [PASSED] drm_test_cmdline_rotate_270
[07:07:02] [PASSED] drm_test_cmdline_hmirror
[07:07:02] [PASSED] drm_test_cmdline_vmirror
[07:07:02] [PASSED] drm_test_cmdline_margin_options
[07:07:02] [PASSED] drm_test_cmdline_multiple_options
[07:07:02] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:07:02] [PASSED] drm_test_cmdline_extra_and_option
[07:07:02] [PASSED] drm_test_cmdline_freestanding_options
[07:07:02] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:07:02] [PASSED] drm_test_cmdline_panel_orientation
[07:07:02] ================ drm_test_cmdline_invalid =================
[07:07:02] [PASSED] margin_only
[07:07:02] [PASSED] interlace_only
[07:07:02] [PASSED] res_missing_x
[07:07:02] [PASSED] res_missing_y
[07:07:02] [PASSED] res_bad_y
[07:07:02] [PASSED] res_missing_y_bpp
[07:07:02] [PASSED] res_bad_bpp
[07:07:02] [PASSED] res_bad_refresh
[07:07:02] [PASSED] res_bpp_refresh_force_on_off
[07:07:02] [PASSED] res_invalid_mode
[07:07:02] [PASSED] res_bpp_wrong_place_mode
[07:07:02] [PASSED] name_bpp_refresh
[07:07:02] [PASSED] name_refresh
[07:07:02] [PASSED] name_refresh_wrong_mode
[07:07:02] [PASSED] name_refresh_invalid_mode
[07:07:02] [PASSED] rotate_multiple
[07:07:02] [PASSED] rotate_invalid_val
[07:07:02] [PASSED] rotate_truncated
[07:07:02] [PASSED] invalid_option
[07:07:02] [PASSED] invalid_tv_option
[07:07:02] [PASSED] truncated_tv_option
[07:07:02] ============ [PASSED] drm_test_cmdline_invalid =============
[07:07:02] =============== drm_test_cmdline_tv_options ===============
[07:07:02] [PASSED] NTSC
[07:07:02] [PASSED] NTSC_443
[07:07:02] [PASSED] NTSC_J
[07:07:02] [PASSED] PAL
[07:07:02] [PASSED] PAL_M
[07:07:02] [PASSED] PAL_N
[07:07:02] [PASSED] SECAM
[07:07:02] [PASSED] MONO_525
[07:07:02] [PASSED] MONO_625
[07:07:02] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:07:02] =============== [PASSED] drm_cmdline_parser ================
[07:07:02] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:07:02] [PASSED] drm_test_connector_hdmi_init_valid
[07:07:02] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:07:02] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:07:02] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:07:02] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:07:02] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:07:02] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:07:02] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:07:02] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:07:02] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:07:02] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:07:02] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:07:02] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:07:02] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:07:02] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:07:02] [PASSED] drm_test_connector_hdmi_init_null_product
[07:07:02] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:07:02] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:07:02] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:07:02] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:07:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:07:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:07:02] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:07:02] ========= drm_test_connector_hdmi_init_type_valid =========
[07:07:02] [PASSED] HDMI-A
[07:07:02] [PASSED] HDMI-B
[07:07:02] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:07:02] ======== drm_test_connector_hdmi_init_type_invalid ========
[07:07:02] [PASSED] Unknown
[07:07:02] [PASSED] VGA
[07:07:02] [PASSED] DVI-I
[07:07:02] [PASSED] DVI-D
[07:07:02] [PASSED] DVI-A
[07:07:02] [PASSED] Composite
[07:07:02] [PASSED] SVIDEO
[07:07:02] [PASSED] LVDS
[07:07:02] [PASSED] Component
[07:07:02] [PASSED] DIN
[07:07:02] [PASSED] DP
[07:07:02] [PASSED] TV
[07:07:02] [PASSED] eDP
[07:07:02] [PASSED] Virtual
[07:07:02] [PASSED] DSI
[07:07:02] [PASSED] DPI
[07:07:02] [PASSED] Writeback
[07:07:02] [PASSED] SPI
[07:07:02] [PASSED] USB
[07:07:02] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:07:02] ============ [PASSED] drmm_connector_hdmi_init =============
[07:07:02] ============= drmm_connector_init (3 subtests) =============
[07:07:02] [PASSED] drm_test_drmm_connector_init
[07:07:02] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:07:02] ========= drm_test_drmm_connector_init_type_valid =========
[07:07:02] [PASSED] Unknown
[07:07:02] [PASSED] VGA
[07:07:02] [PASSED] DVI-I
[07:07:02] [PASSED] DVI-D
[07:07:02] [PASSED] DVI-A
[07:07:02] [PASSED] Composite
[07:07:02] [PASSED] SVIDEO
[07:07:02] [PASSED] LVDS
[07:07:02] [PASSED] Component
[07:07:02] [PASSED] DIN
[07:07:02] [PASSED] DP
[07:07:02] [PASSED] HDMI-A
[07:07:02] [PASSED] HDMI-B
[07:07:02] [PASSED] TV
[07:07:02] [PASSED] eDP
[07:07:02] [PASSED] Virtual
[07:07:02] [PASSED] DSI
[07:07:02] [PASSED] DPI
[07:07:02] [PASSED] Writeback
[07:07:02] [PASSED] SPI
[07:07:02] [PASSED] USB
[07:07:02] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:07:02] =============== [PASSED] drmm_connector_init ===============
[07:07:02] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_init
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:07:02] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[07:07:02] [PASSED] Unknown
[07:07:02] [PASSED] VGA
[07:07:02] [PASSED] DVI-I
[07:07:02] [PASSED] DVI-D
[07:07:02] [PASSED] DVI-A
[07:07:02] [PASSED] Composite
[07:07:02] [PASSED] SVIDEO
[07:07:02] [PASSED] LVDS
[07:07:02] [PASSED] Component
[07:07:02] [PASSED] DIN
[07:07:02] [PASSED] DP
[07:07:02] [PASSED] HDMI-A
[07:07:02] [PASSED] HDMI-B
[07:07:02] [PASSED] TV
[07:07:02] [PASSED] eDP
[07:07:02] [PASSED] Virtual
[07:07:02] [PASSED] DSI
[07:07:02] [PASSED] DPI
[07:07:02] [PASSED] Writeback
[07:07:02] [PASSED] SPI
[07:07:02] [PASSED] USB
[07:07:02] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:07:02] ======== drm_test_drm_connector_dynamic_init_name =========
[07:07:02] [PASSED] Unknown
[07:07:02] [PASSED] VGA
[07:07:02] [PASSED] DVI-I
[07:07:02] [PASSED] DVI-D
[07:07:02] [PASSED] DVI-A
[07:07:02] [PASSED] Composite
[07:07:02] [PASSED] SVIDEO
[07:07:02] [PASSED] LVDS
[07:07:02] [PASSED] Component
[07:07:02] [PASSED] DIN
[07:07:02] [PASSED] DP
[07:07:02] [PASSED] HDMI-A
[07:07:02] [PASSED] HDMI-B
[07:07:02] [PASSED] TV
[07:07:02] [PASSED] eDP
[07:07:02] [PASSED] Virtual
[07:07:02] [PASSED] DSI
[07:07:02] [PASSED] DPI
[07:07:02] [PASSED] Writeback
[07:07:02] [PASSED] SPI
[07:07:02] [PASSED] USB
[07:07:02] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:07:02] =========== [PASSED] drm_connector_dynamic_init ============
[07:07:02] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:07:02] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:07:02] ======= drm_connector_dynamic_register (7 subtests) ========
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:07:02] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:07:02] ========= [PASSED] drm_connector_dynamic_register ==========
[07:07:02] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:07:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:07:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:07:02] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:07:02] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:07:02] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:07:02] [PASSED] NTSC
[07:07:02] [PASSED] NTSC-443
[07:07:02] [PASSED] NTSC-J
[07:07:02] [PASSED] PAL
[07:07:02] [PASSED] PAL-M
[07:07:02] [PASSED] PAL-N
[07:07:02] [PASSED] SECAM
[07:07:02] [PASSED] Mono
[07:07:02] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:07:02] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:07:02] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:07:02] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:07:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:07:02] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[07:07:02] [PASSED] VIC 96
[07:07:02] [PASSED] VIC 97
[07:07:02] [PASSED] VIC 101
[07:07:02] [PASSED] VIC 102
[07:07:02] [PASSED] VIC 106
[07:07:02] [PASSED] VIC 107
[07:07:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:07:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:07:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:07:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:07:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:07:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:07:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:07:02] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:07:02] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[07:07:02] [PASSED] Automatic
[07:07:02] [PASSED] Full
[07:07:02] [PASSED] Limited 16:235
[07:07:02] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:07:02] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:07:02] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:07:02] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:07:02] === drm_test_drm_hdmi_connector_get_output_format_name ====
[07:07:02] [PASSED] RGB
[07:07:02] [PASSED] YUV 4:2:0
[07:07:02] [PASSED] YUV 4:2:2
[07:07:02] [PASSED] YUV 4:4:4
[07:07:02] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:07:02] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:07:02] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:07:02] ============= drm_damage_helper (21 subtests) ==============
[07:07:02] [PASSED] drm_test_damage_iter_no_damage
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:07:02] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:07:02] [PASSED] drm_test_damage_iter_simple_damage
[07:07:02] [PASSED] drm_test_damage_iter_single_damage
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:07:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:07:02] [PASSED] drm_test_damage_iter_damage
[07:07:02] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:07:02] [PASSED] drm_test_damage_iter_damage_one_outside
[07:07:02] [PASSED] drm_test_damage_iter_damage_src_moved
[07:07:02] [PASSED] drm_test_damage_iter_damage_not_visible
[07:07:02] ================ [PASSED] drm_damage_helper ================
[07:07:02] ============== drm_dp_mst_helper (3 subtests) ==============
[07:07:02] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:07:02] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:07:02] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:07:02] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:07:02] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:07:02] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:07:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:07:02] ============== drm_test_dp_mst_calc_pbn_div ===============
[07:07:02] [PASSED] Link rate 2000000 lane count 4
[07:07:02] [PASSED] Link rate 2000000 lane count 2
[07:07:02] [PASSED] Link rate 2000000 lane count 1
[07:07:02] [PASSED] Link rate 1350000 lane count 4
[07:07:02] [PASSED] Link rate 1350000 lane count 2
[07:07:02] [PASSED] Link rate 1350000 lane count 1
[07:07:02] [PASSED] Link rate 1000000 lane count 4
[07:07:02] [PASSED] Link rate 1000000 lane count 2
[07:07:02] [PASSED] Link rate 1000000 lane count 1
[07:07:02] [PASSED] Link rate 810000 lane count 4
[07:07:02] [PASSED] Link rate 810000 lane count 2
[07:07:02] [PASSED] Link rate 810000 lane count 1
[07:07:02] [PASSED] Link rate 540000 lane count 4
[07:07:02] [PASSED] Link rate 540000 lane count 2
[07:07:02] [PASSED] Link rate 540000 lane count 1
[07:07:02] [PASSED] Link rate 270000 lane count 4
[07:07:02] [PASSED] Link rate 270000 lane count 2
[07:07:02] [PASSED] Link rate 270000 lane count 1
[07:07:02] [PASSED] Link rate 162000 lane count 4
[07:07:02] [PASSED] Link rate 162000 lane count 2
[07:07:02] [PASSED] Link rate 162000 lane count 1
[07:07:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:07:02] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:07:02] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:07:02] [PASSED] DP_POWER_UP_PHY with port number
[07:07:02] [PASSED] DP_POWER_DOWN_PHY with port number
[07:07:02] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:07:02] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:07:02] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:07:02] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:07:02] [PASSED] DP_QUERY_PAYLOAD with port number
[07:07:02] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:07:02] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:07:02] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:07:02] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:07:02] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:07:02] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:07:02] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:07:02] [PASSED] DP_REMOTE_I2C_READ with port number
[07:07:02] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:07:02] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:07:02] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:07:02] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:07:02] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:07:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:07:02] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:07:02] ================ [PASSED] drm_dp_mst_helper ================
[07:07:02] ================== drm_exec (7 subtests) ===================
[07:07:02] [PASSED] sanitycheck
[07:07:02] [PASSED] test_lock
[07:07:02] [PASSED] test_lock_unlock
[07:07:02] [PASSED] test_duplicates
[07:07:02] [PASSED] test_prepare
[07:07:02] [PASSED] test_prepare_array
[07:07:02] [PASSED] test_multiple_loops
[07:07:02] ==================== [PASSED] drm_exec =====================
[07:07:02] =========== drm_format_helper_test (17 subtests) ===========
[07:07:02] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:07:02] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:07:02] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:07:02] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:07:02] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:07:02] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:07:02] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:07:02] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:07:02] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:07:02] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:07:02] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:07:02] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:07:02] ==================== drm_test_fb_swab =====================
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ================ [PASSED] drm_test_fb_swab =================
[07:07:02] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:07:02] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[07:07:02] [PASSED] single_pixel_source_buffer
[07:07:02] [PASSED] single_pixel_clip_rectangle
[07:07:02] [PASSED] well_known_colors
[07:07:02] [PASSED] destination_pitch
[07:07:02] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:07:02] ================= drm_test_fb_clip_offset =================
[07:07:02] [PASSED] pass through
[07:07:02] [PASSED] horizontal offset
[07:07:02] [PASSED] vertical offset
[07:07:02] [PASSED] horizontal and vertical offset
[07:07:02] [PASSED] horizontal offset (custom pitch)
[07:07:02] [PASSED] vertical offset (custom pitch)
[07:07:02] [PASSED] horizontal and vertical offset (custom pitch)
[07:07:02] ============= [PASSED] drm_test_fb_clip_offset =============
[07:07:02] =================== drm_test_fb_memcpy ====================
[07:07:02] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:07:02] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:07:02] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:07:02] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:07:02] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:07:02] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:07:02] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:07:02] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:07:02] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:07:02] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:07:02] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:07:02] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:07:02] =============== [PASSED] drm_test_fb_memcpy ================
[07:07:02] ============= [PASSED] drm_format_helper_test ==============
[07:07:02] ================= drm_format (18 subtests) =================
[07:07:02] [PASSED] drm_test_format_block_width_invalid
[07:07:02] [PASSED] drm_test_format_block_width_one_plane
[07:07:02] [PASSED] drm_test_format_block_width_two_plane
[07:07:02] [PASSED] drm_test_format_block_width_three_plane
[07:07:02] [PASSED] drm_test_format_block_width_tiled
[07:07:02] [PASSED] drm_test_format_block_height_invalid
[07:07:02] [PASSED] drm_test_format_block_height_one_plane
[07:07:02] [PASSED] drm_test_format_block_height_two_plane
[07:07:02] [PASSED] drm_test_format_block_height_three_plane
[07:07:02] [PASSED] drm_test_format_block_height_tiled
[07:07:02] [PASSED] drm_test_format_min_pitch_invalid
[07:07:02] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:07:02] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:07:02] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:07:02] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:07:02] [PASSED] drm_test_format_min_pitch_two_plane
[07:07:02] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:07:02] [PASSED] drm_test_format_min_pitch_tiled
[07:07:02] =================== [PASSED] drm_format ====================
[07:07:02] ============== drm_framebuffer (10 subtests) ===============
[07:07:02] ========== drm_test_framebuffer_check_src_coords ==========
[07:07:02] [PASSED] Success: source fits into fb
[07:07:02] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:07:02] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:07:02] [PASSED] Fail: overflowing fb with source width
[07:07:02] [PASSED] Fail: overflowing fb with source height
[07:07:02] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:07:02] [PASSED] drm_test_framebuffer_cleanup
[07:07:02] =============== drm_test_framebuffer_create ===============
[07:07:02] [PASSED] ABGR8888 normal sizes
[07:07:02] [PASSED] ABGR8888 max sizes
[07:07:02] [PASSED] ABGR8888 pitch greater than min required
[07:07:02] [PASSED] ABGR8888 pitch less than min required
[07:07:02] [PASSED] ABGR8888 Invalid width
[07:07:02] [PASSED] ABGR8888 Invalid buffer handle
[07:07:02] [PASSED] No pixel format
[07:07:02] [PASSED] ABGR8888 Width 0
[07:07:02] [PASSED] ABGR8888 Height 0
[07:07:02] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:07:02] [PASSED] ABGR8888 Large buffer offset
[07:07:02] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:07:02] [PASSED] ABGR8888 Invalid flag
[07:07:02] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:07:02] [PASSED] ABGR8888 Valid buffer modifier
[07:07:02] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:07:02] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] NV12 Normal sizes
[07:07:02] [PASSED] NV12 Max sizes
[07:07:02] [PASSED] NV12 Invalid pitch
[07:07:02] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:07:02] [PASSED] NV12 different modifier per-plane
[07:07:02] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:07:02] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] NV12 Modifier for inexistent plane
[07:07:02] [PASSED] NV12 Handle for inexistent plane
[07:07:02] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:07:02] [PASSED] YVU420 Normal sizes
[07:07:02] [PASSED] YVU420 Max sizes
[07:07:02] [PASSED] YVU420 Invalid pitch
[07:07:02] [PASSED] YVU420 Different pitches
[07:07:02] [PASSED] YVU420 Different buffer offsets/pitches
[07:07:02] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:07:02] [PASSED] YVU420 Valid modifier
[07:07:02] [PASSED] YVU420 Different modifiers per plane
[07:07:02] [PASSED] YVU420 Modifier for inexistent plane
[07:07:02] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:07:02] [PASSED] X0L2 Normal sizes
[07:07:02] [PASSED] X0L2 Max sizes
[07:07:02] [PASSED] X0L2 Invalid pitch
[07:07:02] [PASSED] X0L2 Pitch greater than minimum required
[07:07:02] [PASSED] X0L2 Handle for inexistent plane
[07:07:02] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:07:02] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:07:02] [PASSED] X0L2 Valid modifier
[07:07:02] [PASSED] X0L2 Modifier for inexistent plane
[07:07:02] =========== [PASSED] drm_test_framebuffer_create ===========
[07:07:02] [PASSED] drm_test_framebuffer_free
[07:07:02] [PASSED] drm_test_framebuffer_init
[07:07:02] [PASSED] drm_test_framebuffer_init_bad_format
[07:07:02] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:07:02] [PASSED] drm_test_framebuffer_lookup
[07:07:02] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:07:02] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:07:02] ================= [PASSED] drm_framebuffer =================
[07:07:02] ================ drm_gem_shmem (8 subtests) ================
[07:07:02] [PASSED] drm_gem_shmem_test_obj_create
[07:07:02] [PASSED] drm_gem_shmem_test_obj_create_private
[07:07:02] [PASSED] drm_gem_shmem_test_pin_pages
[07:07:02] [PASSED] drm_gem_shmem_test_vmap
[07:07:02] [PASSED] drm_gem_shmem_test_get_sg_table
[07:07:02] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:07:02] [PASSED] drm_gem_shmem_test_madvise
[07:07:02] [PASSED] drm_gem_shmem_test_purge
[07:07:02] ================== [PASSED] drm_gem_shmem ==================
[07:07:02] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:07:02] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[07:07:02] [PASSED] Automatic
[07:07:02] [PASSED] Full
[07:07:02] [PASSED] Limited 16:235
[07:07:02] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:07:02] [PASSED] drm_test_check_disable_connector
[07:07:02] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:07:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:07:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:07:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:07:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:07:02] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:07:02] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:07:02] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:07:02] [PASSED] drm_test_check_output_bpc_dvi
[07:07:02] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:07:02] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:07:02] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:07:02] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:07:02] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:07:02] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:07:02] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:07:02] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:07:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:07:02] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:07:02] [PASSED] drm_test_check_broadcast_rgb_value
[07:07:02] [PASSED] drm_test_check_bpc_8_value
[07:07:02] [PASSED] drm_test_check_bpc_10_value
[07:07:02] [PASSED] drm_test_check_bpc_12_value
[07:07:02] [PASSED] drm_test_check_format_value
[07:07:02] [PASSED] drm_test_check_tmds_char_value
[07:07:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:07:02] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:07:02] [PASSED] drm_test_check_mode_valid
[07:07:02] [PASSED] drm_test_check_mode_valid_reject
[07:07:02] [PASSED] drm_test_check_mode_valid_reject_rate
[07:07:02] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:07:02] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:07:02] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:07:02] [PASSED] drm_test_check_infoframes
[07:07:02] [PASSED] drm_test_check_reject_avi_infoframe
[07:07:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:07:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:07:02] [PASSED] drm_test_check_reject_audio_infoframe
[07:07:02] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:07:02] ================= drm_managed (2 subtests) =================
[07:07:02] [PASSED] drm_test_managed_release_action
[07:07:02] [PASSED] drm_test_managed_run_action
[07:07:02] =================== [PASSED] drm_managed ===================
[07:07:02] =================== drm_mm (6 subtests) ====================
[07:07:02] [PASSED] drm_test_mm_init
[07:07:02] [PASSED] drm_test_mm_debug
[07:07:02] [PASSED] drm_test_mm_align32
[07:07:02] [PASSED] drm_test_mm_align64
[07:07:02] [PASSED] drm_test_mm_lowest
[07:07:02] [PASSED] drm_test_mm_highest
[07:07:02] ===================== [PASSED] drm_mm ======================
[07:07:02] ============= drm_modes_analog_tv (5 subtests) =============
[07:07:02] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:07:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:07:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:07:02] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:07:02] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:07:02] =============== [PASSED] drm_modes_analog_tv ===============
[07:07:02] ============== drm_plane_helper (2 subtests) ===============
[07:07:02] =============== drm_test_check_plane_state ================
[07:07:02] [PASSED] clipping_simple
[07:07:02] [PASSED] clipping_rotate_reflect
[07:07:02] [PASSED] positioning_simple
[07:07:02] [PASSED] upscaling
[07:07:02] [PASSED] downscaling
[07:07:02] [PASSED] rounding1
[07:07:02] [PASSED] rounding2
[07:07:02] [PASSED] rounding3
[07:07:02] [PASSED] rounding4
[07:07:02] =========== [PASSED] drm_test_check_plane_state ============
[07:07:02] =========== drm_test_check_invalid_plane_state ============
[07:07:02] [PASSED] positioning_invalid
[07:07:02] [PASSED] upscaling_invalid
[07:07:02] [PASSED] downscaling_invalid
[07:07:02] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:07:02] ================ [PASSED] drm_plane_helper =================
[07:07:02] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:07:02] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:07:02] [PASSED] None
[07:07:02] [PASSED] PAL
[07:07:02] [PASSED] NTSC
[07:07:02] [PASSED] Both, NTSC Default
[07:07:02] [PASSED] Both, PAL Default
[07:07:02] [PASSED] Both, NTSC Default, with PAL on command-line
[07:07:02] [PASSED] Both, PAL Default, with NTSC on command-line
[07:07:02] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:07:02] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:07:02] ================== drm_rect (9 subtests) ===================
[07:07:02] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:07:02] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:07:02] [PASSED] drm_test_rect_clip_scaled_clipped
[07:07:02] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:07:02] ================= drm_test_rect_intersect =================
[07:07:02] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:07:02] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:07:02] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:07:02] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:07:02] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:07:02] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:07:02] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:07:02] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:07:02] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:07:02] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:07:02] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:07:02] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:07:02] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:07:02] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:07:02] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:07:02] ============= [PASSED] drm_test_rect_intersect =============
[07:07:02] ================ drm_test_rect_calc_hscale ================
[07:07:02] [PASSED] normal use
[07:07:02] [PASSED] out of max range
[07:07:02] [PASSED] out of min range
[07:07:02] [PASSED] zero dst
[07:07:02] [PASSED] negative src
[07:07:02] [PASSED] negative dst
[07:07:02] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:07:02] ================ drm_test_rect_calc_vscale ================
[07:07:02] [PASSED] normal use
[07:07:02] [PASSED] out of max range
[07:07:02] [PASSED] out of min range
[07:07:02] [PASSED] zero dst
[07:07:02] [PASSED] negative src
[07:07:02] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[07:07:02] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:07:02] ================== drm_test_rect_rotate ===================
[07:07:02] [PASSED] reflect-x
[07:07:02] [PASSED] reflect-y
[07:07:02] [PASSED] rotate-0
[07:07:02] [PASSED] rotate-90
[07:07:02] [PASSED] rotate-180
[07:07:02] [PASSED] rotate-270
[07:07:02] ============== [PASSED] drm_test_rect_rotate ===============
[07:07:02] ================ drm_test_rect_rotate_inv =================
[07:07:02] [PASSED] reflect-x
[07:07:02] [PASSED] reflect-y
[07:07:02] [PASSED] rotate-0
[07:07:02] [PASSED] rotate-90
[07:07:02] [PASSED] rotate-180
[07:07:02] [PASSED] rotate-270
[07:07:02] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:07:02] ==================== [PASSED] drm_rect =====================
[07:07:02] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:07:02] ============ drm_test_sysfb_build_fourcc_list =============
[07:07:02] [PASSED] no native formats
[07:07:02] [PASSED] XRGB8888 as native format
[07:07:02] [PASSED] remove duplicates
[07:07:02] [PASSED] convert alpha formats
[07:07:02] [PASSED] random formats
[07:07:02] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:07:02] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:07:02] ================== drm_fixp (2 subtests) ===================
[07:07:02] [PASSED] drm_test_int2fixp
[07:07:02] [PASSED] drm_test_sm2fixp
[07:07:02] ==================== [PASSED] drm_fixp =====================
[07:07:02] ============================================================
[07:07:02] Testing complete. Ran 621 tests: passed: 621
[07:07:02] Elapsed time: 26.949s total, 1.679s configuring, 25.103s building, 0.131s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:07:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:07:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:07:13] Starting KUnit Kernel (1/1)...
[07:07:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:07:13] ================= ttm_device (5 subtests) ==================
[07:07:13] [PASSED] ttm_device_init_basic
[07:07:13] [PASSED] ttm_device_init_multiple
[07:07:13] [PASSED] ttm_device_fini_basic
[07:07:13] [PASSED] ttm_device_init_no_vma_man
[07:07:13] ================== ttm_device_init_pools ==================
[07:07:13] [PASSED] No DMA allocations, no DMA32 required
[07:07:13] [PASSED] DMA allocations, DMA32 required
[07:07:13] [PASSED] No DMA allocations, DMA32 required
[07:07:13] [PASSED] DMA allocations, no DMA32 required
[07:07:13] ============== [PASSED] ttm_device_init_pools ==============
[07:07:13] =================== [PASSED] ttm_device ====================
[07:07:13] ================== ttm_pool (8 subtests) ===================
[07:07:13] ================== ttm_pool_alloc_basic ===================
[07:07:13] [PASSED] One page
[07:07:13] [PASSED] More than one page
[07:07:13] [PASSED] Above the allocation limit
[07:07:13] [PASSED] One page, with coherent DMA mappings enabled
[07:07:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:07:13] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:07:13] ============== ttm_pool_alloc_basic_dma_addr ==============
[07:07:13] [PASSED] One page
[07:07:13] [PASSED] More than one page
[07:07:13] [PASSED] Above the allocation limit
[07:07:13] [PASSED] One page, with coherent DMA mappings enabled
[07:07:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:07:13] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:07:13] [PASSED] ttm_pool_alloc_order_caching_match
[07:07:13] [PASSED] ttm_pool_alloc_caching_mismatch
[07:07:13] [PASSED] ttm_pool_alloc_order_mismatch
[07:07:13] [PASSED] ttm_pool_free_dma_alloc
[07:07:13] [PASSED] ttm_pool_free_no_dma_alloc
[07:07:13] [PASSED] ttm_pool_fini_basic
[07:07:13] ==================== [PASSED] ttm_pool =====================
[07:07:13] ================ ttm_resource (8 subtests) =================
[07:07:13] ================= ttm_resource_init_basic =================
[07:07:13] [PASSED] Init resource in TTM_PL_SYSTEM
[07:07:13] [PASSED] Init resource in TTM_PL_VRAM
[07:07:13] [PASSED] Init resource in a private placement
[07:07:13] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:07:13] ============= [PASSED] ttm_resource_init_basic =============
[07:07:13] [PASSED] ttm_resource_init_pinned
[07:07:13] [PASSED] ttm_resource_fini_basic
[07:07:13] [PASSED] ttm_resource_manager_init_basic
[07:07:13] [PASSED] ttm_resource_manager_usage_basic
[07:07:13] [PASSED] ttm_resource_manager_set_used_basic
[07:07:13] [PASSED] ttm_sys_man_alloc_basic
[07:07:13] [PASSED] ttm_sys_man_free_basic
[07:07:13] ================== [PASSED] ttm_resource ===================
[07:07:13] =================== ttm_tt (15 subtests) ===================
[07:07:13] ==================== ttm_tt_init_basic ====================
[07:07:13] [PASSED] Page-aligned size
[07:07:13] [PASSED] Extra pages requested
[07:07:13] ================ [PASSED] ttm_tt_init_basic ================
[07:07:13] [PASSED] ttm_tt_init_misaligned
[07:07:13] [PASSED] ttm_tt_fini_basic
[07:07:13] [PASSED] ttm_tt_fini_sg
[07:07:13] [PASSED] ttm_tt_fini_shmem
[07:07:13] [PASSED] ttm_tt_create_basic
[07:07:13] [PASSED] ttm_tt_create_invalid_bo_type
[07:07:13] [PASSED] ttm_tt_create_ttm_exists
[07:07:13] [PASSED] ttm_tt_create_failed
[07:07:13] [PASSED] ttm_tt_destroy_basic
[07:07:13] [PASSED] ttm_tt_populate_null_ttm
[07:07:13] [PASSED] ttm_tt_populate_populated_ttm
[07:07:13] [PASSED] ttm_tt_unpopulate_basic
[07:07:13] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:07:13] [PASSED] ttm_tt_swapin_basic
[07:07:13] ===================== [PASSED] ttm_tt ======================
[07:07:13] =================== ttm_bo (14 subtests) ===================
[07:07:13] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[07:07:13] [PASSED] Cannot be interrupted and sleeps
[07:07:13] [PASSED] Cannot be interrupted, locks straight away
[07:07:13] [PASSED] Can be interrupted, sleeps
[07:07:13] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:07:13] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:07:13] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:07:13] [PASSED] ttm_bo_reserve_double_resv
[07:07:13] [PASSED] ttm_bo_reserve_interrupted
[07:07:13] [PASSED] ttm_bo_reserve_deadlock
[07:07:13] [PASSED] ttm_bo_unreserve_basic
[07:07:13] [PASSED] ttm_bo_unreserve_pinned
[07:07:13] [PASSED] ttm_bo_unreserve_bulk
[07:07:13] [PASSED] ttm_bo_fini_basic
[07:07:13] [PASSED] ttm_bo_fini_shared_resv
[07:07:13] [PASSED] ttm_bo_pin_basic
[07:07:13] [PASSED] ttm_bo_pin_unpin_resource
[07:07:13] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:07:13] ===================== [PASSED] ttm_bo ======================
[07:07:13] ============== ttm_bo_validate (21 subtests) ===============
[07:07:13] ============== ttm_bo_init_reserved_sys_man ===============
[07:07:13] [PASSED] Buffer object for userspace
[07:07:13] [PASSED] Kernel buffer object
[07:07:13] [PASSED] Shared buffer object
[07:07:13] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:07:13] ============== ttm_bo_init_reserved_mock_man ==============
[07:07:13] [PASSED] Buffer object for userspace
[07:07:13] [PASSED] Kernel buffer object
[07:07:13] [PASSED] Shared buffer object
[07:07:13] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:07:13] [PASSED] ttm_bo_init_reserved_resv
[07:07:13] ================== ttm_bo_validate_basic ==================
[07:07:13] [PASSED] Buffer object for userspace
[07:07:13] [PASSED] Kernel buffer object
[07:07:13] [PASSED] Shared buffer object
[07:07:13] ============== [PASSED] ttm_bo_validate_basic ==============
[07:07:13] [PASSED] ttm_bo_validate_invalid_placement
[07:07:13] ============= ttm_bo_validate_same_placement ==============
[07:07:13] [PASSED] System manager
[07:07:13] [PASSED] VRAM manager
[07:07:13] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:07:13] [PASSED] ttm_bo_validate_failed_alloc
[07:07:13] [PASSED] ttm_bo_validate_pinned
[07:07:13] [PASSED] ttm_bo_validate_busy_placement
[07:07:13] ================ ttm_bo_validate_multihop =================
[07:07:13] [PASSED] Buffer object for userspace
[07:07:13] [PASSED] Kernel buffer object
[07:07:13] [PASSED] Shared buffer object
[07:07:13] ============ [PASSED] ttm_bo_validate_multihop =============
[07:07:13] ========== ttm_bo_validate_no_placement_signaled ==========
[07:07:13] [PASSED] Buffer object in system domain, no page vector
[07:07:13] [PASSED] Buffer object in system domain with an existing page vector
[07:07:13] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:07:13] ======== ttm_bo_validate_no_placement_not_signaled ========
[07:07:13] [PASSED] Buffer object for userspace
[07:07:13] [PASSED] Kernel buffer object
[07:07:13] [PASSED] Shared buffer object
[07:07:13] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:07:13] [PASSED] ttm_bo_validate_move_fence_signaled
[07:07:13] ========= ttm_bo_validate_move_fence_not_signaled =========
[07:07:13] [PASSED] Waits for GPU
[07:07:13] [PASSED] Tries to lock straight away
[07:07:13] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:07:13] [PASSED] ttm_bo_validate_happy_evict
[07:07:13] [PASSED] ttm_bo_validate_all_pinned_evict
[07:07:13] [PASSED] ttm_bo_validate_allowed_only_evict
[07:07:13] [PASSED] ttm_bo_validate_deleted_evict
[07:07:13] [PASSED] ttm_bo_validate_busy_domain_evict
[07:07:13] [PASSED] ttm_bo_validate_evict_gutting
[07:07:13] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:07:13] ================= [PASSED] ttm_bo_validate =================
[07:07:13] ============================================================
[07:07:13] Testing complete. Ran 101 tests: passed: 101
[07:07:13] Elapsed time: 11.351s total, 1.640s configuring, 9.494s building, 0.180s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ Xe.CI.BAT: success for dGPU memory optimizations (rev2)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (6 preceding siblings ...)
2026-02-18 7:07 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev2) Patchwork
@ 2026-02-18 7:36 ` Patchwork
2026-02-18 7:53 ` ✓ Xe.CI.FULL: " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 7:36 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 853 bytes --]
== Series Details ==
Series: dGPU memory optimizations (rev2)
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
CI Bug Log - changes from xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d_BAT -> xe-pw-161737v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (0 -> 0)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d -> xe-pw-161737v2
IGT_8758: 8758
xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d: fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d
xe-pw-161737v2: 161737v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v2/index.html
[-- Attachment #2: Type: text/html, Size: 1401 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ Xe.CI.FULL: success for dGPU memory optimizations (rev2)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (7 preceding siblings ...)
2026-02-18 7:36 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-02-18 7:53 ` Patchwork
2026-02-18 12:29 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev3) Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 7:53 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 855 bytes --]
== Series Details ==
Series: dGPU memory optimizations (rev2)
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
CI Bug Log - changes from xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d_FULL -> xe-pw-161737v2_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (0 -> 0)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d -> xe-pw-161737v2
IGT_8758: 8758
xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d: fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d
xe-pw-161737v2: 161737v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v2/index.html
[-- Attachment #2: Type: text/html, Size: 1403 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ CI.KUnit: success for dGPU memory optimizations (rev3)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (8 preceding siblings ...)
2026-02-18 7:53 ` ✓ Xe.CI.FULL: " Patchwork
@ 2026-02-18 12:29 ` Patchwork
2026-02-18 13:09 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 14:08 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 12:29 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: dGPU memory optimizations (rev3)
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:28:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:28:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:28:37] Starting KUnit Kernel (1/1)...
[12:28:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:28:38] ================== guc_buf (11 subtests) ===================
[12:28:38] [PASSED] test_smallest
[12:28:38] [PASSED] test_largest
[12:28:38] [PASSED] test_granular
[12:28:38] [PASSED] test_unique
[12:28:38] [PASSED] test_overlap
[12:28:38] [PASSED] test_reusable
[12:28:38] [PASSED] test_too_big
[12:28:38] [PASSED] test_flush
[12:28:38] [PASSED] test_lookup
[12:28:38] [PASSED] test_data
[12:28:38] [PASSED] test_class
[12:28:38] ===================== [PASSED] guc_buf =====================
[12:28:38] =================== guc_dbm (7 subtests) ===================
[12:28:38] [PASSED] test_empty
[12:28:38] [PASSED] test_default
[12:28:38] ======================== test_size ========================
[12:28:38] [PASSED] 4
[12:28:38] [PASSED] 8
[12:28:38] [PASSED] 32
[12:28:38] [PASSED] 256
[12:28:38] ==================== [PASSED] test_size ====================
[12:28:38] ======================= test_reuse ========================
[12:28:38] [PASSED] 4
[12:28:38] [PASSED] 8
[12:28:38] [PASSED] 32
[12:28:38] [PASSED] 256
[12:28:38] =================== [PASSED] test_reuse ====================
[12:28:38] =================== test_range_overlap ====================
[12:28:38] [PASSED] 4
[12:28:38] [PASSED] 8
[12:28:38] [PASSED] 32
[12:28:38] [PASSED] 256
[12:28:38] =============== [PASSED] test_range_overlap ================
[12:28:38] =================== test_range_compact ====================
[12:28:38] [PASSED] 4
[12:28:38] [PASSED] 8
[12:28:38] [PASSED] 32
[12:28:38] [PASSED] 256
[12:28:38] =============== [PASSED] test_range_compact ================
[12:28:38] ==================== test_range_spare =====================
[12:28:38] [PASSED] 4
[12:28:38] [PASSED] 8
[12:28:38] [PASSED] 32
[12:28:38] [PASSED] 256
[12:28:38] ================ [PASSED] test_range_spare =================
[12:28:38] ===================== [PASSED] guc_dbm =====================
[12:28:38] =================== guc_idm (6 subtests) ===================
[12:28:38] [PASSED] bad_init
[12:28:38] [PASSED] no_init
[12:28:38] [PASSED] init_fini
[12:28:38] [PASSED] check_used
[12:28:38] [PASSED] check_quota
[12:28:38] [PASSED] check_all
[12:28:38] ===================== [PASSED] guc_idm =====================
[12:28:38] ================== no_relay (3 subtests) ===================
[12:28:38] [PASSED] xe_drops_guc2pf_if_not_ready
[12:28:38] [PASSED] xe_drops_guc2vf_if_not_ready
[12:28:38] [PASSED] xe_rejects_send_if_not_ready
[12:28:38] ==================== [PASSED] no_relay =====================
[12:28:38] ================== pf_relay (14 subtests) ==================
[12:28:38] [PASSED] pf_rejects_guc2pf_too_short
[12:28:38] [PASSED] pf_rejects_guc2pf_too_long
[12:28:38] [PASSED] pf_rejects_guc2pf_no_payload
[12:28:38] [PASSED] pf_fails_no_payload
[12:28:38] [PASSED] pf_fails_bad_origin
[12:28:38] [PASSED] pf_fails_bad_type
[12:28:38] [PASSED] pf_txn_reports_error
[12:28:38] [PASSED] pf_txn_sends_pf2guc
[12:28:38] [PASSED] pf_sends_pf2guc
[12:28:38] [SKIPPED] pf_loopback_nop
[12:28:38] [SKIPPED] pf_loopback_echo
[12:28:38] [SKIPPED] pf_loopback_fail
[12:28:38] [SKIPPED] pf_loopback_busy
[12:28:38] [SKIPPED] pf_loopback_retry
[12:28:38] ==================== [PASSED] pf_relay =====================
[12:28:38] ================== vf_relay (3 subtests) ===================
[12:28:38] [PASSED] vf_rejects_guc2vf_too_short
[12:28:38] [PASSED] vf_rejects_guc2vf_too_long
[12:28:38] [PASSED] vf_rejects_guc2vf_no_payload
[12:28:38] ==================== [PASSED] vf_relay =====================
[12:28:38] ================ pf_gt_config (6 subtests) =================
[12:28:38] [PASSED] fair_contexts_1vf
[12:28:38] [PASSED] fair_doorbells_1vf
[12:28:38] [PASSED] fair_ggtt_1vf
[12:28:38] ====================== fair_contexts ======================
[12:28:38] [PASSED] 1 VF
[12:28:38] [PASSED] 2 VFs
[12:28:38] [PASSED] 3 VFs
[12:28:38] [PASSED] 4 VFs
[12:28:38] [PASSED] 5 VFs
[12:28:38] [PASSED] 6 VFs
[12:28:38] [PASSED] 7 VFs
[12:28:38] [PASSED] 8 VFs
[12:28:38] [PASSED] 9 VFs
[12:28:38] [PASSED] 10 VFs
[12:28:38] [PASSED] 11 VFs
[12:28:38] [PASSED] 12 VFs
[12:28:38] [PASSED] 13 VFs
[12:28:38] [PASSED] 14 VFs
[12:28:38] [PASSED] 15 VFs
[12:28:38] [PASSED] 16 VFs
[12:28:38] [PASSED] 17 VFs
[12:28:38] [PASSED] 18 VFs
[12:28:38] [PASSED] 19 VFs
[12:28:38] [PASSED] 20 VFs
[12:28:38] [PASSED] 21 VFs
[12:28:38] [PASSED] 22 VFs
[12:28:38] [PASSED] 23 VFs
[12:28:38] [PASSED] 24 VFs
[12:28:38] [PASSED] 25 VFs
[12:28:38] [PASSED] 26 VFs
[12:28:38] [PASSED] 27 VFs
[12:28:38] [PASSED] 28 VFs
[12:28:38] [PASSED] 29 VFs
[12:28:38] [PASSED] 30 VFs
[12:28:38] [PASSED] 31 VFs
[12:28:38] [PASSED] 32 VFs
[12:28:38] [PASSED] 33 VFs
[12:28:38] [PASSED] 34 VFs
[12:28:38] [PASSED] 35 VFs
[12:28:38] [PASSED] 36 VFs
[12:28:38] [PASSED] 37 VFs
[12:28:38] [PASSED] 38 VFs
[12:28:38] [PASSED] 39 VFs
[12:28:38] [PASSED] 40 VFs
[12:28:38] [PASSED] 41 VFs
[12:28:38] [PASSED] 42 VFs
[12:28:38] [PASSED] 43 VFs
[12:28:38] [PASSED] 44 VFs
[12:28:38] [PASSED] 45 VFs
[12:28:38] [PASSED] 46 VFs
[12:28:38] [PASSED] 47 VFs
[12:28:38] [PASSED] 48 VFs
[12:28:38] [PASSED] 49 VFs
[12:28:38] [PASSED] 50 VFs
[12:28:38] [PASSED] 51 VFs
[12:28:38] [PASSED] 52 VFs
[12:28:38] [PASSED] 53 VFs
[12:28:38] [PASSED] 54 VFs
[12:28:38] [PASSED] 55 VFs
[12:28:38] [PASSED] 56 VFs
[12:28:38] [PASSED] 57 VFs
[12:28:38] [PASSED] 58 VFs
[12:28:38] [PASSED] 59 VFs
[12:28:38] [PASSED] 60 VFs
[12:28:38] [PASSED] 61 VFs
[12:28:38] [PASSED] 62 VFs
[12:28:38] [PASSED] 63 VFs
[12:28:38] ================== [PASSED] fair_contexts ==================
[12:28:38] ===================== fair_doorbells ======================
[12:28:38] [PASSED] 1 VF
[12:28:38] [PASSED] 2 VFs
[12:28:38] [PASSED] 3 VFs
[12:28:38] [PASSED] 4 VFs
[12:28:38] [PASSED] 5 VFs
[12:28:38] [PASSED] 6 VFs
[12:28:38] [PASSED] 7 VFs
[12:28:38] [PASSED] 8 VFs
[12:28:38] [PASSED] 9 VFs
[12:28:38] [PASSED] 10 VFs
[12:28:38] [PASSED] 11 VFs
[12:28:38] [PASSED] 12 VFs
[12:28:38] [PASSED] 13 VFs
[12:28:38] [PASSED] 14 VFs
[12:28:38] [PASSED] 15 VFs
[12:28:38] [PASSED] 16 VFs
[12:28:38] [PASSED] 17 VFs
[12:28:38] [PASSED] 18 VFs
[12:28:38] [PASSED] 19 VFs
[12:28:38] [PASSED] 20 VFs
[12:28:38] [PASSED] 21 VFs
[12:28:38] [PASSED] 22 VFs
[12:28:38] [PASSED] 23 VFs
[12:28:38] [PASSED] 24 VFs
[12:28:38] [PASSED] 25 VFs
[12:28:38] [PASSED] 26 VFs
[12:28:38] [PASSED] 27 VFs
[12:28:38] [PASSED] 28 VFs
[12:28:38] [PASSED] 29 VFs
[12:28:38] [PASSED] 30 VFs
[12:28:38] [PASSED] 31 VFs
[12:28:38] [PASSED] 32 VFs
[12:28:38] [PASSED] 33 VFs
[12:28:38] [PASSED] 34 VFs
[12:28:38] [PASSED] 35 VFs
[12:28:38] [PASSED] 36 VFs
[12:28:38] [PASSED] 37 VFs
[12:28:38] [PASSED] 38 VFs
[12:28:38] [PASSED] 39 VFs
[12:28:38] [PASSED] 40 VFs
[12:28:38] [PASSED] 41 VFs
[12:28:38] [PASSED] 42 VFs
[12:28:38] [PASSED] 43 VFs
[12:28:38] [PASSED] 44 VFs
[12:28:38] [PASSED] 45 VFs
[12:28:38] [PASSED] 46 VFs
[12:28:38] [PASSED] 47 VFs
[12:28:38] [PASSED] 48 VFs
[12:28:38] [PASSED] 49 VFs
[12:28:38] [PASSED] 50 VFs
[12:28:38] [PASSED] 51 VFs
[12:28:38] [PASSED] 52 VFs
[12:28:38] [PASSED] 53 VFs
[12:28:38] [PASSED] 54 VFs
[12:28:38] [PASSED] 55 VFs
[12:28:38] [PASSED] 56 VFs
[12:28:38] [PASSED] 57 VFs
[12:28:38] [PASSED] 58 VFs
[12:28:38] [PASSED] 59 VFs
[12:28:38] [PASSED] 60 VFs
[12:28:38] [PASSED] 61 VFs
[12:28:38] [PASSED] 62 VFs
[12:28:38] [PASSED] 63 VFs
[12:28:38] ================= [PASSED] fair_doorbells ==================
[12:28:38] ======================== fair_ggtt ========================
[12:28:38] [PASSED] 1 VF
[12:28:38] [PASSED] 2 VFs
[12:28:38] [PASSED] 3 VFs
[12:28:38] [PASSED] 4 VFs
[12:28:38] [PASSED] 5 VFs
[12:28:38] [PASSED] 6 VFs
[12:28:38] [PASSED] 7 VFs
[12:28:38] [PASSED] 8 VFs
[12:28:38] [PASSED] 9 VFs
[12:28:38] [PASSED] 10 VFs
[12:28:38] [PASSED] 11 VFs
[12:28:38] [PASSED] 12 VFs
[12:28:38] [PASSED] 13 VFs
[12:28:38] [PASSED] 14 VFs
[12:28:38] [PASSED] 15 VFs
[12:28:38] [PASSED] 16 VFs
[12:28:38] [PASSED] 17 VFs
[12:28:38] [PASSED] 18 VFs
[12:28:38] [PASSED] 19 VFs
[12:28:38] [PASSED] 20 VFs
[12:28:38] [PASSED] 21 VFs
[12:28:38] [PASSED] 22 VFs
[12:28:38] [PASSED] 23 VFs
[12:28:38] [PASSED] 24 VFs
[12:28:38] [PASSED] 25 VFs
[12:28:38] [PASSED] 26 VFs
[12:28:38] [PASSED] 27 VFs
[12:28:38] [PASSED] 28 VFs
[12:28:38] [PASSED] 29 VFs
[12:28:38] [PASSED] 30 VFs
[12:28:38] [PASSED] 31 VFs
[12:28:38] [PASSED] 32 VFs
[12:28:38] [PASSED] 33 VFs
[12:28:38] [PASSED] 34 VFs
[12:28:38] [PASSED] 35 VFs
[12:28:38] [PASSED] 36 VFs
[12:28:38] [PASSED] 37 VFs
[12:28:38] [PASSED] 38 VFs
[12:28:38] [PASSED] 39 VFs
[12:28:38] [PASSED] 40 VFs
[12:28:38] [PASSED] 41 VFs
[12:28:38] [PASSED] 42 VFs
[12:28:38] [PASSED] 43 VFs
[12:28:38] [PASSED] 44 VFs
[12:28:38] [PASSED] 45 VFs
[12:28:38] [PASSED] 46 VFs
[12:28:38] [PASSED] 47 VFs
[12:28:38] [PASSED] 48 VFs
[12:28:38] [PASSED] 49 VFs
[12:28:38] [PASSED] 50 VFs
[12:28:38] [PASSED] 51 VFs
[12:28:38] [PASSED] 52 VFs
[12:28:38] [PASSED] 53 VFs
[12:28:38] [PASSED] 54 VFs
[12:28:38] [PASSED] 55 VFs
[12:28:38] [PASSED] 56 VFs
[12:28:38] [PASSED] 57 VFs
[12:28:38] [PASSED] 58 VFs
[12:28:38] [PASSED] 59 VFs
[12:28:38] [PASSED] 60 VFs
[12:28:38] [PASSED] 61 VFs
[12:28:38] [PASSED] 62 VFs
[12:28:38] [PASSED] 63 VFs
[12:28:38] ==================== [PASSED] fair_ggtt ====================
[12:28:38] ================== [PASSED] pf_gt_config ===================
[12:28:38] ===================== lmtt (1 subtest) =====================
[12:28:38] ======================== test_ops =========================
[12:28:38] [PASSED] 2-level
[12:28:38] [PASSED] multi-level
[12:28:38] ==================== [PASSED] test_ops =====================
[12:28:38] ====================== [PASSED] lmtt =======================
[12:28:38] ================= pf_service (11 subtests) =================
[12:28:38] [PASSED] pf_negotiate_any
[12:28:38] [PASSED] pf_negotiate_base_match
[12:28:38] [PASSED] pf_negotiate_base_newer
[12:28:38] [PASSED] pf_negotiate_base_next
[12:28:38] [SKIPPED] pf_negotiate_base_older
[12:28:38] [PASSED] pf_negotiate_base_prev
[12:28:38] [PASSED] pf_negotiate_latest_match
[12:28:38] [PASSED] pf_negotiate_latest_newer
[12:28:38] [PASSED] pf_negotiate_latest_next
[12:28:38] [SKIPPED] pf_negotiate_latest_older
[12:28:38] [SKIPPED] pf_negotiate_latest_prev
[12:28:38] =================== [PASSED] pf_service ====================
[12:28:38] ================= xe_guc_g2g (2 subtests) ==================
[12:28:38] ============== xe_live_guc_g2g_kunit_default ==============
[12:28:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:28:38] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:28:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:28:38] =================== [SKIPPED] xe_guc_g2g ===================
[12:28:38] =================== xe_mocs (2 subtests) ===================
[12:28:38] ================ xe_live_mocs_kernel_kunit ================
[12:28:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:28:38] ================ xe_live_mocs_reset_kunit =================
[12:28:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:28:38] ==================== [SKIPPED] xe_mocs =====================
[12:28:38] ================= xe_migrate (2 subtests) ==================
[12:28:38] ================= xe_migrate_sanity_kunit =================
[12:28:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:28:38] ================== xe_validate_ccs_kunit ==================
[12:28:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:28:38] =================== [SKIPPED] xe_migrate ===================
[12:28:38] ================== xe_dma_buf (1 subtest) ==================
[12:28:38] ==================== xe_dma_buf_kunit =====================
[12:28:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:28:38] =================== [SKIPPED] xe_dma_buf ===================
[12:28:38] ================= xe_bo_shrink (1 subtest) =================
[12:28:38] =================== xe_bo_shrink_kunit ====================
[12:28:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:28:38] ================== [SKIPPED] xe_bo_shrink ==================
[12:28:38] ==================== xe_bo (2 subtests) ====================
[12:28:38] ================== xe_ccs_migrate_kunit ===================
[12:28:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:28:38] ==================== xe_bo_evict_kunit ====================
[12:28:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:28:38] ===================== [SKIPPED] xe_bo ======================
[12:28:38] ==================== args (13 subtests) ====================
[12:28:38] [PASSED] count_args_test
[12:28:38] [PASSED] call_args_example
[12:28:38] [PASSED] call_args_test
[12:28:38] [PASSED] drop_first_arg_example
[12:28:38] [PASSED] drop_first_arg_test
[12:28:38] [PASSED] first_arg_example
[12:28:38] [PASSED] first_arg_test
[12:28:38] [PASSED] last_arg_example
[12:28:38] [PASSED] last_arg_test
[12:28:38] [PASSED] pick_arg_example
[12:28:38] [PASSED] if_args_example
[12:28:38] [PASSED] if_args_test
[12:28:38] [PASSED] sep_comma_example
[12:28:38] ====================== [PASSED] args =======================
[12:28:38] =================== xe_pci (3 subtests) ====================
[12:28:38] ==================== check_graphics_ip ====================
[12:28:38] [PASSED] 12.00 Xe_LP
[12:28:38] [PASSED] 12.10 Xe_LP+
[12:28:38] [PASSED] 12.55 Xe_HPG
[12:28:38] [PASSED] 12.60 Xe_HPC
[12:28:38] [PASSED] 12.70 Xe_LPG
[12:28:38] [PASSED] 12.71 Xe_LPG
[12:28:38] [PASSED] 12.74 Xe_LPG+
[12:28:38] [PASSED] 20.01 Xe2_HPG
[12:28:38] [PASSED] 20.02 Xe2_HPG
[12:28:38] [PASSED] 20.04 Xe2_LPG
[12:28:38] [PASSED] 30.00 Xe3_LPG
[12:28:38] [PASSED] 30.01 Xe3_LPG
[12:28:38] [PASSED] 30.03 Xe3_LPG
[12:28:38] [PASSED] 30.04 Xe3_LPG
[12:28:38] [PASSED] 30.05 Xe3_LPG
[12:28:38] [PASSED] 35.10 Xe3p_LPG
[12:28:38] [PASSED] 35.11 Xe3p_XPC
[12:28:38] ================ [PASSED] check_graphics_ip ================
[12:28:38] ===================== check_media_ip ======================
[12:28:38] [PASSED] 12.00 Xe_M
[12:28:38] [PASSED] 12.55 Xe_HPM
[12:28:38] [PASSED] 13.00 Xe_LPM+
[12:28:38] [PASSED] 13.01 Xe2_HPM
[12:28:38] [PASSED] 20.00 Xe2_LPM
[12:28:38] [PASSED] 30.00 Xe3_LPM
[12:28:38] [PASSED] 30.02 Xe3_LPM
[12:28:38] [PASSED] 35.00 Xe3p_LPM
[12:28:38] [PASSED] 35.03 Xe3p_HPM
[12:28:38] ================= [PASSED] check_media_ip ==================
[12:28:38] =================== check_platform_desc ===================
[12:28:38] [PASSED] 0x9A60 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A68 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A70 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A40 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A49 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A59 (TIGERLAKE)
[12:28:38] [PASSED] 0x9A78 (TIGERLAKE)
[12:28:38] [PASSED] 0x9AC0 (TIGERLAKE)
[12:28:38] [PASSED] 0x9AC9 (TIGERLAKE)
[12:28:38] [PASSED] 0x9AD9 (TIGERLAKE)
[12:28:38] [PASSED] 0x9AF8 (TIGERLAKE)
[12:28:38] [PASSED] 0x4C80 (ROCKETLAKE)
[12:28:38] [PASSED] 0x4C8A (ROCKETLAKE)
[12:28:38] [PASSED] 0x4C8B (ROCKETLAKE)
[12:28:38] [PASSED] 0x4C8C (ROCKETLAKE)
[12:28:38] [PASSED] 0x4C90 (ROCKETLAKE)
[12:28:38] [PASSED] 0x4C9A (ROCKETLAKE)
[12:28:38] [PASSED] 0x4680 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4682 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4688 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x468A (ALDERLAKE_S)
[12:28:38] [PASSED] 0x468B (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4690 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4692 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4693 (ALDERLAKE_S)
[12:28:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46AA (ALDERLAKE_P)
[12:28:38] [PASSED] 0x462A (ALDERLAKE_P)
[12:28:38] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[12:28:38] [PASSED] 0x4628 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:28:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:28:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:28:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:28:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:28:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:28:38] [PASSED] 0xA721 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA720 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:28:38] [PASSED] 0xA780 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA781 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA782 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA783 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA788 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA789 (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA78A (ALDERLAKE_S)
[12:28:38] [PASSED] 0xA78B (ALDERLAKE_S)
[12:28:38] [PASSED] 0x4905 (DG1)
[12:28:38] [PASSED] 0x4906 (DG1)
[12:28:38] [PASSED] 0x4907 (DG1)
[12:28:38] [PASSED] 0x4908 (DG1)
[12:28:38] [PASSED] 0x4909 (DG1)
[12:28:38] [PASSED] 0x56C0 (DG2)
[12:28:38] [PASSED] 0x56C2 (DG2)
[12:28:38] [PASSED] 0x56C1 (DG2)
[12:28:38] [PASSED] 0x7D51 (METEORLAKE)
[12:28:38] [PASSED] 0x7DD1 (METEORLAKE)
[12:28:38] [PASSED] 0x7D41 (METEORLAKE)
[12:28:38] [PASSED] 0x7D67 (METEORLAKE)
[12:28:38] [PASSED] 0xB640 (METEORLAKE)
[12:28:38] [PASSED] 0x56A0 (DG2)
[12:28:38] [PASSED] 0x56A1 (DG2)
[12:28:38] [PASSED] 0x56A2 (DG2)
[12:28:38] [PASSED] 0x56BE (DG2)
[12:28:38] [PASSED] 0x56BF (DG2)
[12:28:38] [PASSED] 0x5690 (DG2)
[12:28:38] [PASSED] 0x5691 (DG2)
[12:28:38] [PASSED] 0x5692 (DG2)
[12:28:38] [PASSED] 0x56A5 (DG2)
[12:28:38] [PASSED] 0x56A6 (DG2)
[12:28:38] [PASSED] 0x56B0 (DG2)
[12:28:38] [PASSED] 0x56B1 (DG2)
[12:28:38] [PASSED] 0x56BA (DG2)
[12:28:38] [PASSED] 0x56BB (DG2)
[12:28:38] [PASSED] 0x56BC (DG2)
[12:28:38] [PASSED] 0x56BD (DG2)
[12:28:38] [PASSED] 0x5693 (DG2)
[12:28:38] [PASSED] 0x5694 (DG2)
[12:28:38] [PASSED] 0x5695 (DG2)
[12:28:38] [PASSED] 0x56A3 (DG2)
[12:28:38] [PASSED] 0x56A4 (DG2)
[12:28:38] [PASSED] 0x56B2 (DG2)
[12:28:38] [PASSED] 0x56B3 (DG2)
[12:28:38] [PASSED] 0x5696 (DG2)
[12:28:38] [PASSED] 0x5697 (DG2)
[12:28:38] [PASSED] 0xB69 (PVC)
[12:28:38] [PASSED] 0xB6E (PVC)
[12:28:38] [PASSED] 0xBD4 (PVC)
[12:28:38] [PASSED] 0xBD5 (PVC)
[12:28:38] [PASSED] 0xBD6 (PVC)
[12:28:38] [PASSED] 0xBD7 (PVC)
[12:28:38] [PASSED] 0xBD8 (PVC)
[12:28:38] [PASSED] 0xBD9 (PVC)
[12:28:38] [PASSED] 0xBDA (PVC)
[12:28:38] [PASSED] 0xBDB (PVC)
[12:28:38] [PASSED] 0xBE0 (PVC)
[12:28:38] [PASSED] 0xBE1 (PVC)
[12:28:38] [PASSED] 0xBE5 (PVC)
[12:28:38] [PASSED] 0x7D40 (METEORLAKE)
[12:28:38] [PASSED] 0x7D45 (METEORLAKE)
[12:28:38] [PASSED] 0x7D55 (METEORLAKE)
[12:28:38] [PASSED] 0x7D60 (METEORLAKE)
[12:28:38] [PASSED] 0x7DD5 (METEORLAKE)
[12:28:38] [PASSED] 0x6420 (LUNARLAKE)
[12:28:38] [PASSED] 0x64A0 (LUNARLAKE)
[12:28:38] [PASSED] 0x64B0 (LUNARLAKE)
[12:28:38] [PASSED] 0xE202 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE209 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE20B (BATTLEMAGE)
[12:28:38] [PASSED] 0xE20C (BATTLEMAGE)
[12:28:38] [PASSED] 0xE20D (BATTLEMAGE)
[12:28:38] [PASSED] 0xE210 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE211 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE212 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE216 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE220 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE221 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE222 (BATTLEMAGE)
[12:28:38] [PASSED] 0xE223 (BATTLEMAGE)
[12:28:38] [PASSED] 0xB080 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB081 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB082 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB083 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB084 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB085 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB086 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB087 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB08F (PANTHERLAKE)
[12:28:38] [PASSED] 0xB090 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:28:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:28:38] [PASSED] 0xFD80 (PANTHERLAKE)
[12:28:38] [PASSED] 0xFD81 (PANTHERLAKE)
[12:28:38] [PASSED] 0xD740 (NOVALAKE_S)
[12:28:38] [PASSED] 0xD741 (NOVALAKE_S)
[12:28:38] [PASSED] 0xD742 (NOVALAKE_S)
[12:28:38] [PASSED] 0xD743 (NOVALAKE_S)
[12:28:38] [PASSED] 0xD744 (NOVALAKE_S)
[12:28:38] [PASSED] 0xD745 (NOVALAKE_S)
[12:28:38] [PASSED] 0x674C (CRESCENTISLAND)
[12:28:38] [PASSED] 0xD750 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD751 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD752 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD753 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD754 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD755 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD756 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD757 (NOVALAKE_P)
[12:28:38] [PASSED] 0xD75F (NOVALAKE_P)
[12:28:38] =============== [PASSED] check_platform_desc ===============
[12:28:38] ===================== [PASSED] xe_pci ======================
[12:28:38] =================== xe_rtp (2 subtests) ====================
[12:28:38] =============== xe_rtp_process_to_sr_tests ================
[12:28:38] [PASSED] coalesce-same-reg
[12:28:38] [PASSED] no-match-no-add
[12:28:38] [PASSED] match-or
[12:28:38] [PASSED] match-or-xfail
[12:28:38] [PASSED] no-match-no-add-multiple-rules
[12:28:38] [PASSED] two-regs-two-entries
[12:28:38] [PASSED] clr-one-set-other
[12:28:38] [PASSED] set-field
[12:28:38] [PASSED] conflict-duplicate
[12:28:38] [PASSED] conflict-not-disjoint
[12:28:38] [PASSED] conflict-reg-type
[12:28:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:28:38] ================== xe_rtp_process_tests ===================
[12:28:38] [PASSED] active1
[12:28:38] [PASSED] active2
[12:28:38] [PASSED] active-inactive
[12:28:38] [PASSED] inactive-active
[12:28:38] [PASSED] inactive-1st_or_active-inactive
[12:28:38] [PASSED] inactive-2nd_or_active-inactive
[12:28:38] [PASSED] inactive-last_or_active-inactive
[12:28:38] [PASSED] inactive-no_or_active-inactive
[12:28:38] ============== [PASSED] xe_rtp_process_tests ===============
[12:28:38] ===================== [PASSED] xe_rtp ======================
[12:28:38] ==================== xe_wa (1 subtest) =====================
[12:28:38] ======================== xe_wa_gt =========================
[12:28:38] [PASSED] TIGERLAKE B0
[12:28:38] [PASSED] DG1 A0
[12:28:38] [PASSED] DG1 B0
[12:28:38] [PASSED] ALDERLAKE_S A0
[12:28:38] [PASSED] ALDERLAKE_S B0
[12:28:38] [PASSED] ALDERLAKE_S C0
[12:28:38] [PASSED] ALDERLAKE_S D0
[12:28:38] [PASSED] ALDERLAKE_P A0
[12:28:38] [PASSED] ALDERLAKE_P B0
[12:28:38] [PASSED] ALDERLAKE_P C0
[12:28:38] [PASSED] ALDERLAKE_S RPLS D0
[12:28:38] [PASSED] ALDERLAKE_P RPLU E0
[12:28:38] [PASSED] DG2 G10 C0
[12:28:38] [PASSED] DG2 G11 B1
[12:28:38] [PASSED] DG2 G12 A1
[12:28:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:28:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:28:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:28:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:28:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:28:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:28:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:28:38] ==================== [PASSED] xe_wa_gt =====================
[12:28:38] ====================== [PASSED] xe_wa ======================
[12:28:38] ============================================================
[12:28:38] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[12:28:38] Elapsed time: 36.313s total, 4.159s configuring, 31.638s building, 0.470s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:28:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:28:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:29:05] Starting KUnit Kernel (1/1)...
[12:29:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:29:05] ============ drm_test_pick_cmdline (2 subtests) ============
[12:29:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:29:05] =============== drm_test_pick_cmdline_named ===============
[12:29:05] [PASSED] NTSC
[12:29:05] [PASSED] NTSC-J
[12:29:05] [PASSED] PAL
[12:29:05] [PASSED] PAL-M
[12:29:05] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:29:05] ============== [PASSED] drm_test_pick_cmdline ==============
[12:29:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:29:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:29:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:29:05] =========== drm_validate_clone_mode (2 subtests) ===========
[12:29:05] ============== drm_test_check_in_clone_mode ===============
[12:29:05] [PASSED] in_clone_mode
[12:29:05] [PASSED] not_in_clone_mode
[12:29:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:29:05] =============== drm_test_check_valid_clones ===============
[12:29:05] [PASSED] not_in_clone_mode
[12:29:05] [PASSED] valid_clone
[12:29:05] [PASSED] invalid_clone
[12:29:05] =========== [PASSED] drm_test_check_valid_clones ===========
[12:29:05] ============= [PASSED] drm_validate_clone_mode =============
[12:29:05] ============= drm_validate_modeset (1 subtest) =============
[12:29:05] [PASSED] drm_test_check_connector_changed_modeset
[12:29:05] ============== [PASSED] drm_validate_modeset ===============
[12:29:05] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:29:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:29:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:29:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:29:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:29:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:29:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:29:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:29:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:29:05] ============== drm_bridge_alloc (2 subtests) ===============
[12:29:05] [PASSED] drm_test_drm_bridge_alloc_basic
[12:29:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:29:05] ================ [PASSED] drm_bridge_alloc =================
[12:29:05] ============= drm_cmdline_parser (40 subtests) =============
[12:29:05] [PASSED] drm_test_cmdline_force_d_only
[12:29:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:29:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:29:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:29:05] [PASSED] drm_test_cmdline_force_e_only
[12:29:05] [PASSED] drm_test_cmdline_res
[12:29:05] [PASSED] drm_test_cmdline_res_vesa
[12:29:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:29:05] [PASSED] drm_test_cmdline_res_rblank
[12:29:05] [PASSED] drm_test_cmdline_res_bpp
[12:29:05] [PASSED] drm_test_cmdline_res_refresh
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:29:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:29:05] [PASSED] drm_test_cmdline_res_margins_force_on
[12:29:05] [PASSED] drm_test_cmdline_res_vesa_margins
[12:29:05] [PASSED] drm_test_cmdline_name
[12:29:05] [PASSED] drm_test_cmdline_name_bpp
[12:29:05] [PASSED] drm_test_cmdline_name_option
[12:29:05] [PASSED] drm_test_cmdline_name_bpp_option
[12:29:05] [PASSED] drm_test_cmdline_rotate_0
[12:29:05] [PASSED] drm_test_cmdline_rotate_90
[12:29:05] [PASSED] drm_test_cmdline_rotate_180
[12:29:05] [PASSED] drm_test_cmdline_rotate_270
[12:29:05] [PASSED] drm_test_cmdline_hmirror
[12:29:05] [PASSED] drm_test_cmdline_vmirror
[12:29:05] [PASSED] drm_test_cmdline_margin_options
[12:29:05] [PASSED] drm_test_cmdline_multiple_options
[12:29:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:29:05] [PASSED] drm_test_cmdline_extra_and_option
[12:29:05] [PASSED] drm_test_cmdline_freestanding_options
[12:29:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:29:05] [PASSED] drm_test_cmdline_panel_orientation
[12:29:05] ================ drm_test_cmdline_invalid =================
[12:29:05] [PASSED] margin_only
[12:29:05] [PASSED] interlace_only
[12:29:05] [PASSED] res_missing_x
[12:29:05] [PASSED] res_missing_y
[12:29:05] [PASSED] res_bad_y
[12:29:05] [PASSED] res_missing_y_bpp
[12:29:05] [PASSED] res_bad_bpp
[12:29:05] [PASSED] res_bad_refresh
[12:29:05] [PASSED] res_bpp_refresh_force_on_off
[12:29:05] [PASSED] res_invalid_mode
[12:29:05] [PASSED] res_bpp_wrong_place_mode
[12:29:05] [PASSED] name_bpp_refresh
[12:29:05] [PASSED] name_refresh
[12:29:05] [PASSED] name_refresh_wrong_mode
[12:29:05] [PASSED] name_refresh_invalid_mode
[12:29:05] [PASSED] rotate_multiple
[12:29:05] [PASSED] rotate_invalid_val
[12:29:05] [PASSED] rotate_truncated
[12:29:05] [PASSED] invalid_option
[12:29:05] [PASSED] invalid_tv_option
[12:29:05] [PASSED] truncated_tv_option
[12:29:05] ============ [PASSED] drm_test_cmdline_invalid =============
[12:29:05] =============== drm_test_cmdline_tv_options ===============
[12:29:05] [PASSED] NTSC
[12:29:05] [PASSED] NTSC_443
[12:29:05] [PASSED] NTSC_J
[12:29:05] [PASSED] PAL
[12:29:05] [PASSED] PAL_M
[12:29:05] [PASSED] PAL_N
[12:29:05] [PASSED] SECAM
[12:29:05] [PASSED] MONO_525
[12:29:05] [PASSED] MONO_625
[12:29:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:29:05] =============== [PASSED] drm_cmdline_parser ================
[12:29:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:29:05] [PASSED] drm_test_connector_hdmi_init_valid
[12:29:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:29:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:29:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:29:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:29:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:29:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:29:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:29:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:29:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:29:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:29:05] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:29:05] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:29:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:29:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:29:05] [PASSED] drm_test_connector_hdmi_init_null_product
[12:29:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:29:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:29:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:29:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:29:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:29:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:29:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:29:05] ========= drm_test_connector_hdmi_init_type_valid =========
[12:29:05] [PASSED] HDMI-A
[12:29:05] [PASSED] HDMI-B
[12:29:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:29:05] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:29:05] [PASSED] Unknown
[12:29:05] [PASSED] VGA
[12:29:05] [PASSED] DVI-I
[12:29:05] [PASSED] DVI-D
[12:29:05] [PASSED] DVI-A
[12:29:05] [PASSED] Composite
[12:29:05] [PASSED] SVIDEO
[12:29:05] [PASSED] LVDS
[12:29:05] [PASSED] Component
[12:29:05] [PASSED] DIN
[12:29:05] [PASSED] DP
[12:29:05] [PASSED] TV
[12:29:05] [PASSED] eDP
[12:29:05] [PASSED] Virtual
[12:29:05] [PASSED] DSI
[12:29:05] [PASSED] DPI
[12:29:05] [PASSED] Writeback
[12:29:05] [PASSED] SPI
[12:29:05] [PASSED] USB
[12:29:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:29:05] ============ [PASSED] drmm_connector_hdmi_init =============
[12:29:05] ============= drmm_connector_init (3 subtests) =============
[12:29:05] [PASSED] drm_test_drmm_connector_init
[12:29:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:29:05] ========= drm_test_drmm_connector_init_type_valid =========
[12:29:05] [PASSED] Unknown
[12:29:05] [PASSED] VGA
[12:29:05] [PASSED] DVI-I
[12:29:05] [PASSED] DVI-D
[12:29:05] [PASSED] DVI-A
[12:29:05] [PASSED] Composite
[12:29:05] [PASSED] SVIDEO
[12:29:05] [PASSED] LVDS
[12:29:05] [PASSED] Component
[12:29:05] [PASSED] DIN
[12:29:05] [PASSED] DP
[12:29:05] [PASSED] HDMI-A
[12:29:05] [PASSED] HDMI-B
[12:29:05] [PASSED] TV
[12:29:05] [PASSED] eDP
[12:29:05] [PASSED] Virtual
[12:29:05] [PASSED] DSI
[12:29:05] [PASSED] DPI
[12:29:05] [PASSED] Writeback
[12:29:05] [PASSED] SPI
[12:29:05] [PASSED] USB
[12:29:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:29:05] =============== [PASSED] drmm_connector_init ===============
[12:29:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_init
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:29:05] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:29:05] [PASSED] Unknown
[12:29:05] [PASSED] VGA
[12:29:05] [PASSED] DVI-I
[12:29:05] [PASSED] DVI-D
[12:29:05] [PASSED] DVI-A
[12:29:05] [PASSED] Composite
[12:29:05] [PASSED] SVIDEO
[12:29:05] [PASSED] LVDS
[12:29:05] [PASSED] Component
[12:29:05] [PASSED] DIN
[12:29:05] [PASSED] DP
[12:29:05] [PASSED] HDMI-A
[12:29:05] [PASSED] HDMI-B
[12:29:05] [PASSED] TV
[12:29:05] [PASSED] eDP
[12:29:05] [PASSED] Virtual
[12:29:05] [PASSED] DSI
[12:29:05] [PASSED] DPI
[12:29:05] [PASSED] Writeback
[12:29:05] [PASSED] SPI
[12:29:05] [PASSED] USB
[12:29:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:29:05] ======== drm_test_drm_connector_dynamic_init_name =========
[12:29:05] [PASSED] Unknown
[12:29:05] [PASSED] VGA
[12:29:05] [PASSED] DVI-I
[12:29:05] [PASSED] DVI-D
[12:29:05] [PASSED] DVI-A
[12:29:05] [PASSED] Composite
[12:29:05] [PASSED] SVIDEO
[12:29:05] [PASSED] LVDS
[12:29:05] [PASSED] Component
[12:29:05] [PASSED] DIN
[12:29:05] [PASSED] DP
[12:29:05] [PASSED] HDMI-A
[12:29:05] [PASSED] HDMI-B
[12:29:05] [PASSED] TV
[12:29:05] [PASSED] eDP
[12:29:05] [PASSED] Virtual
[12:29:05] [PASSED] DSI
[12:29:05] [PASSED] DPI
[12:29:05] [PASSED] Writeback
[12:29:05] [PASSED] SPI
[12:29:05] [PASSED] USB
[12:29:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:29:05] =========== [PASSED] drm_connector_dynamic_init ============
[12:29:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:29:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:29:05] ======= drm_connector_dynamic_register (7 subtests) ========
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:29:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:29:05] ========= [PASSED] drm_connector_dynamic_register ==========
[12:29:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:29:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:29:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:29:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:29:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:29:05] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:29:05] [PASSED] NTSC
[12:29:05] [PASSED] NTSC-443
[12:29:05] [PASSED] NTSC-J
[12:29:05] [PASSED] PAL
[12:29:05] [PASSED] PAL-M
[12:29:05] [PASSED] PAL-N
[12:29:05] [PASSED] SECAM
[12:29:05] [PASSED] Mono
[12:29:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:29:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:29:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:29:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:29:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:29:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:29:05] [PASSED] VIC 96
[12:29:05] [PASSED] VIC 97
[12:29:05] [PASSED] VIC 101
[12:29:05] [PASSED] VIC 102
[12:29:05] [PASSED] VIC 106
[12:29:05] [PASSED] VIC 107
[12:29:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:29:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:29:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:29:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:29:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:29:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:29:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:29:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:29:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:29:05] [PASSED] Automatic
[12:29:05] [PASSED] Full
[12:29:05] [PASSED] Limited 16:235
[12:29:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:29:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:29:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:29:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:29:05] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:29:05] [PASSED] RGB
[12:29:05] [PASSED] YUV 4:2:0
[12:29:05] [PASSED] YUV 4:2:2
[12:29:05] [PASSED] YUV 4:4:4
[12:29:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:29:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:29:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:29:05] ============= drm_damage_helper (21 subtests) ==============
[12:29:05] [PASSED] drm_test_damage_iter_no_damage
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:29:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:29:05] [PASSED] drm_test_damage_iter_simple_damage
[12:29:05] [PASSED] drm_test_damage_iter_single_damage
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:29:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:29:05] [PASSED] drm_test_damage_iter_damage
[12:29:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:29:05] [PASSED] drm_test_damage_iter_damage_one_outside
[12:29:05] [PASSED] drm_test_damage_iter_damage_src_moved
[12:29:05] [PASSED] drm_test_damage_iter_damage_not_visible
[12:29:05] ================ [PASSED] drm_damage_helper ================
[12:29:05] ============== drm_dp_mst_helper (3 subtests) ==============
[12:29:05] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:29:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:29:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:29:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:29:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:29:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:29:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:29:05] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:29:05] [PASSED] Link rate 2000000 lane count 4
[12:29:05] [PASSED] Link rate 2000000 lane count 2
[12:29:05] [PASSED] Link rate 2000000 lane count 1
[12:29:05] [PASSED] Link rate 1350000 lane count 4
[12:29:05] [PASSED] Link rate 1350000 lane count 2
[12:29:05] [PASSED] Link rate 1350000 lane count 1
[12:29:05] [PASSED] Link rate 1000000 lane count 4
[12:29:05] [PASSED] Link rate 1000000 lane count 2
[12:29:05] [PASSED] Link rate 1000000 lane count 1
[12:29:05] [PASSED] Link rate 810000 lane count 4
[12:29:05] [PASSED] Link rate 810000 lane count 2
[12:29:05] [PASSED] Link rate 810000 lane count 1
[12:29:05] [PASSED] Link rate 540000 lane count 4
[12:29:05] [PASSED] Link rate 540000 lane count 2
[12:29:05] [PASSED] Link rate 540000 lane count 1
[12:29:05] [PASSED] Link rate 270000 lane count 4
[12:29:05] [PASSED] Link rate 270000 lane count 2
[12:29:05] [PASSED] Link rate 270000 lane count 1
[12:29:05] [PASSED] Link rate 162000 lane count 4
[12:29:05] [PASSED] Link rate 162000 lane count 2
[12:29:05] [PASSED] Link rate 162000 lane count 1
[12:29:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:29:05] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:29:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:29:05] [PASSED] DP_POWER_UP_PHY with port number
[12:29:05] [PASSED] DP_POWER_DOWN_PHY with port number
[12:29:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:29:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:29:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:29:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:29:05] [PASSED] DP_QUERY_PAYLOAD with port number
[12:29:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:29:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:29:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:29:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:29:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:29:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:29:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:29:05] [PASSED] DP_REMOTE_I2C_READ with port number
[12:29:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:29:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:29:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:29:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:29:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:29:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:29:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:29:05] ================ [PASSED] drm_dp_mst_helper ================
[12:29:05] ================== drm_exec (7 subtests) ===================
[12:29:05] [PASSED] sanitycheck
[12:29:05] [PASSED] test_lock
[12:29:05] [PASSED] test_lock_unlock
[12:29:05] [PASSED] test_duplicates
[12:29:05] [PASSED] test_prepare
[12:29:05] [PASSED] test_prepare_array
[12:29:05] [PASSED] test_multiple_loops
[12:29:05] ==================== [PASSED] drm_exec =====================
[12:29:05] =========== drm_format_helper_test (17 subtests) ===========
[12:29:05] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:29:05] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:29:05] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:29:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:29:05] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:29:05] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:29:05] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:29:05] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:29:05] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:29:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:29:05] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:29:05] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:29:05] ==================== drm_test_fb_swab =====================
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ================ [PASSED] drm_test_fb_swab =================
[12:29:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:29:05] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:29:05] [PASSED] single_pixel_source_buffer
[12:29:05] [PASSED] single_pixel_clip_rectangle
[12:29:05] [PASSED] well_known_colors
[12:29:05] [PASSED] destination_pitch
[12:29:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:29:05] ================= drm_test_fb_clip_offset =================
[12:29:05] [PASSED] pass through
[12:29:05] [PASSED] horizontal offset
[12:29:05] [PASSED] vertical offset
[12:29:05] [PASSED] horizontal and vertical offset
[12:29:05] [PASSED] horizontal offset (custom pitch)
[12:29:05] [PASSED] vertical offset (custom pitch)
[12:29:05] [PASSED] horizontal and vertical offset (custom pitch)
[12:29:05] ============= [PASSED] drm_test_fb_clip_offset =============
[12:29:05] =================== drm_test_fb_memcpy ====================
[12:29:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:29:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:29:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:29:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:29:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:29:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:29:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:29:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:29:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:29:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:29:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:29:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:29:05] =============== [PASSED] drm_test_fb_memcpy ================
[12:29:05] ============= [PASSED] drm_format_helper_test ==============
[12:29:05] ================= drm_format (18 subtests) =================
[12:29:05] [PASSED] drm_test_format_block_width_invalid
[12:29:05] [PASSED] drm_test_format_block_width_one_plane
[12:29:05] [PASSED] drm_test_format_block_width_two_plane
[12:29:05] [PASSED] drm_test_format_block_width_three_plane
[12:29:05] [PASSED] drm_test_format_block_width_tiled
[12:29:05] [PASSED] drm_test_format_block_height_invalid
[12:29:05] [PASSED] drm_test_format_block_height_one_plane
[12:29:05] [PASSED] drm_test_format_block_height_two_plane
[12:29:05] [PASSED] drm_test_format_block_height_three_plane
[12:29:05] [PASSED] drm_test_format_block_height_tiled
[12:29:05] [PASSED] drm_test_format_min_pitch_invalid
[12:29:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:29:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:29:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:29:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:29:05] [PASSED] drm_test_format_min_pitch_two_plane
[12:29:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:29:05] [PASSED] drm_test_format_min_pitch_tiled
[12:29:05] =================== [PASSED] drm_format ====================
[12:29:05] ============== drm_framebuffer (10 subtests) ===============
[12:29:05] ========== drm_test_framebuffer_check_src_coords ==========
[12:29:05] [PASSED] Success: source fits into fb
[12:29:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:29:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:29:05] [PASSED] Fail: overflowing fb with source width
[12:29:05] [PASSED] Fail: overflowing fb with source height
[12:29:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:29:05] [PASSED] drm_test_framebuffer_cleanup
[12:29:05] =============== drm_test_framebuffer_create ===============
[12:29:05] [PASSED] ABGR8888 normal sizes
[12:29:05] [PASSED] ABGR8888 max sizes
[12:29:05] [PASSED] ABGR8888 pitch greater than min required
[12:29:05] [PASSED] ABGR8888 pitch less than min required
[12:29:05] [PASSED] ABGR8888 Invalid width
[12:29:05] [PASSED] ABGR8888 Invalid buffer handle
[12:29:05] [PASSED] No pixel format
[12:29:05] [PASSED] ABGR8888 Width 0
[12:29:05] [PASSED] ABGR8888 Height 0
[12:29:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:29:05] [PASSED] ABGR8888 Large buffer offset
[12:29:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:29:05] [PASSED] ABGR8888 Invalid flag
[12:29:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:29:05] [PASSED] ABGR8888 Valid buffer modifier
[12:29:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:29:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] NV12 Normal sizes
[12:29:05] [PASSED] NV12 Max sizes
[12:29:05] [PASSED] NV12 Invalid pitch
[12:29:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:29:05] [PASSED] NV12 different modifier per-plane
[12:29:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:29:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] NV12 Modifier for inexistent plane
[12:29:05] [PASSED] NV12 Handle for inexistent plane
[12:29:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:29:05] [PASSED] YVU420 Normal sizes
[12:29:05] [PASSED] YVU420 Max sizes
[12:29:05] [PASSED] YVU420 Invalid pitch
[12:29:05] [PASSED] YVU420 Different pitches
[12:29:05] [PASSED] YVU420 Different buffer offsets/pitches
[12:29:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:29:05] [PASSED] YVU420 Valid modifier
[12:29:05] [PASSED] YVU420 Different modifiers per plane
[12:29:05] [PASSED] YVU420 Modifier for inexistent plane
[12:29:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:29:05] [PASSED] X0L2 Normal sizes
[12:29:05] [PASSED] X0L2 Max sizes
[12:29:05] [PASSED] X0L2 Invalid pitch
[12:29:05] [PASSED] X0L2 Pitch greater than minimum required
[12:29:05] [PASSED] X0L2 Handle for inexistent plane
[12:29:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:29:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:29:05] [PASSED] X0L2 Valid modifier
[12:29:05] [PASSED] X0L2 Modifier for inexistent plane
[12:29:05] =========== [PASSED] drm_test_framebuffer_create ===========
[12:29:05] [PASSED] drm_test_framebuffer_free
[12:29:05] [PASSED] drm_test_framebuffer_init
[12:29:05] [PASSED] drm_test_framebuffer_init_bad_format
[12:29:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:29:05] [PASSED] drm_test_framebuffer_lookup
[12:29:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:29:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:29:05] ================= [PASSED] drm_framebuffer =================
[12:29:05] ================ drm_gem_shmem (8 subtests) ================
[12:29:05] [PASSED] drm_gem_shmem_test_obj_create
[12:29:05] [PASSED] drm_gem_shmem_test_obj_create_private
[12:29:05] [PASSED] drm_gem_shmem_test_pin_pages
[12:29:05] [PASSED] drm_gem_shmem_test_vmap
[12:29:05] [PASSED] drm_gem_shmem_test_get_sg_table
[12:29:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:29:05] [PASSED] drm_gem_shmem_test_madvise
[12:29:05] [PASSED] drm_gem_shmem_test_purge
[12:29:05] ================== [PASSED] drm_gem_shmem ==================
[12:29:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:29:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:29:05] [PASSED] Automatic
[12:29:05] [PASSED] Full
[12:29:05] [PASSED] Limited 16:235
[12:29:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:29:05] [PASSED] drm_test_check_disable_connector
[12:29:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:29:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:29:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:29:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:29:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:29:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:29:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:29:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:29:05] [PASSED] drm_test_check_output_bpc_dvi
[12:29:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:29:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:29:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:29:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:29:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:29:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:29:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:29:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:29:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:29:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:29:05] [PASSED] drm_test_check_broadcast_rgb_value
[12:29:05] [PASSED] drm_test_check_bpc_8_value
[12:29:05] [PASSED] drm_test_check_bpc_10_value
[12:29:05] [PASSED] drm_test_check_bpc_12_value
[12:29:05] [PASSED] drm_test_check_format_value
[12:29:05] [PASSED] drm_test_check_tmds_char_value
[12:29:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:29:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:29:05] [PASSED] drm_test_check_mode_valid
[12:29:05] [PASSED] drm_test_check_mode_valid_reject
[12:29:05] [PASSED] drm_test_check_mode_valid_reject_rate
[12:29:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:29:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:29:05] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:29:05] [PASSED] drm_test_check_infoframes
[12:29:05] [PASSED] drm_test_check_reject_avi_infoframe
[12:29:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:29:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:29:05] [PASSED] drm_test_check_reject_audio_infoframe
[12:29:05] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:29:05] ================= drm_managed (2 subtests) =================
[12:29:05] [PASSED] drm_test_managed_release_action
[12:29:05] [PASSED] drm_test_managed_run_action
[12:29:05] =================== [PASSED] drm_managed ===================
[12:29:05] =================== drm_mm (6 subtests) ====================
[12:29:05] [PASSED] drm_test_mm_init
[12:29:05] [PASSED] drm_test_mm_debug
[12:29:05] [PASSED] drm_test_mm_align32
[12:29:05] [PASSED] drm_test_mm_align64
[12:29:05] [PASSED] drm_test_mm_lowest
[12:29:05] [PASSED] drm_test_mm_highest
[12:29:05] ===================== [PASSED] drm_mm ======================
[12:29:05] ============= drm_modes_analog_tv (5 subtests) =============
[12:29:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:29:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:29:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:29:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:29:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:29:05] =============== [PASSED] drm_modes_analog_tv ===============
[12:29:05] ============== drm_plane_helper (2 subtests) ===============
[12:29:05] =============== drm_test_check_plane_state ================
[12:29:05] [PASSED] clipping_simple
[12:29:05] [PASSED] clipping_rotate_reflect
[12:29:05] [PASSED] positioning_simple
[12:29:05] [PASSED] upscaling
[12:29:05] [PASSED] downscaling
[12:29:05] [PASSED] rounding1
[12:29:05] [PASSED] rounding2
[12:29:05] [PASSED] rounding3
[12:29:05] [PASSED] rounding4
[12:29:05] =========== [PASSED] drm_test_check_plane_state ============
[12:29:05] =========== drm_test_check_invalid_plane_state ============
[12:29:05] [PASSED] positioning_invalid
[12:29:05] [PASSED] upscaling_invalid
[12:29:05] [PASSED] downscaling_invalid
[12:29:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:29:05] ================ [PASSED] drm_plane_helper =================
[12:29:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:29:05] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:29:05] [PASSED] None
[12:29:05] [PASSED] PAL
[12:29:05] [PASSED] NTSC
[12:29:05] [PASSED] Both, NTSC Default
[12:29:05] [PASSED] Both, PAL Default
[12:29:05] [PASSED] Both, NTSC Default, with PAL on command-line
[12:29:05] [PASSED] Both, PAL Default, with NTSC on command-line
[12:29:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:29:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:29:05] ================== drm_rect (9 subtests) ===================
[12:29:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:29:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:29:05] [PASSED] drm_test_rect_clip_scaled_clipped
[12:29:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:29:05] ================= drm_test_rect_intersect =================
[12:29:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:29:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:29:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:29:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:29:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:29:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:29:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:29:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:29:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:29:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:29:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:29:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:29:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:29:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:29:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:29:05] ============= [PASSED] drm_test_rect_intersect =============
[12:29:05] ================ drm_test_rect_calc_hscale ================
[12:29:05] [PASSED] normal use
[12:29:05] [PASSED] out of max range
[12:29:05] [PASSED] out of min range
[12:29:05] [PASSED] zero dst
[12:29:05] [PASSED] negative src
[12:29:05] [PASSED] negative dst
[12:29:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:29:05] ================ drm_test_rect_calc_vscale ================
[12:29:05] [PASSED] normal use
[12:29:05] [PASSED] out of max range
[12:29:05] [PASSED] out of min range
[12:29:05] [PASSED] zero dst
[12:29:05] [PASSED] negative src
[12:29:05] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[12:29:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:29:05] ================== drm_test_rect_rotate ===================
[12:29:05] [PASSED] reflect-x
[12:29:05] [PASSED] reflect-y
[12:29:05] [PASSED] rotate-0
[12:29:05] [PASSED] rotate-90
[12:29:05] [PASSED] rotate-180
[12:29:05] [PASSED] rotate-270
[12:29:05] ============== [PASSED] drm_test_rect_rotate ===============
[12:29:05] ================ drm_test_rect_rotate_inv =================
[12:29:05] [PASSED] reflect-x
[12:29:05] [PASSED] reflect-y
[12:29:05] [PASSED] rotate-0
[12:29:05] [PASSED] rotate-90
[12:29:05] [PASSED] rotate-180
[12:29:05] [PASSED] rotate-270
[12:29:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:29:05] ==================== [PASSED] drm_rect =====================
[12:29:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:29:05] ============ drm_test_sysfb_build_fourcc_list =============
[12:29:05] [PASSED] no native formats
[12:29:05] [PASSED] XRGB8888 as native format
[12:29:05] [PASSED] remove duplicates
[12:29:05] [PASSED] convert alpha formats
[12:29:05] [PASSED] random formats
[12:29:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:29:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:29:05] ================== drm_fixp (2 subtests) ===================
[12:29:05] [PASSED] drm_test_int2fixp
[12:29:05] [PASSED] drm_test_sm2fixp
[12:29:05] ==================== [PASSED] drm_fixp =====================
[12:29:05] ============================================================
[12:29:05] Testing complete. Ran 621 tests: passed: 621
[12:29:05] Elapsed time: 27.269s total, 1.673s configuring, 25.429s building, 0.165s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:29:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:29:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:29:16] Starting KUnit Kernel (1/1)...
[12:29:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:29:16] ================= ttm_device (5 subtests) ==================
[12:29:16] [PASSED] ttm_device_init_basic
[12:29:16] [PASSED] ttm_device_init_multiple
[12:29:16] [PASSED] ttm_device_fini_basic
[12:29:16] [PASSED] ttm_device_init_no_vma_man
[12:29:16] ================== ttm_device_init_pools ==================
[12:29:16] [PASSED] No DMA allocations, no DMA32 required
[12:29:16] [PASSED] DMA allocations, DMA32 required
[12:29:16] [PASSED] No DMA allocations, DMA32 required
[12:29:16] [PASSED] DMA allocations, no DMA32 required
[12:29:16] ============== [PASSED] ttm_device_init_pools ==============
[12:29:16] =================== [PASSED] ttm_device ====================
[12:29:16] ================== ttm_pool (8 subtests) ===================
[12:29:16] ================== ttm_pool_alloc_basic ===================
[12:29:16] [PASSED] One page
[12:29:16] [PASSED] More than one page
[12:29:16] [PASSED] Above the allocation limit
[12:29:16] [PASSED] One page, with coherent DMA mappings enabled
[12:29:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:29:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:29:16] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:29:16] [PASSED] One page
[12:29:16] [PASSED] More than one page
[12:29:16] [PASSED] Above the allocation limit
[12:29:16] [PASSED] One page, with coherent DMA mappings enabled
[12:29:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:29:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:29:16] [PASSED] ttm_pool_alloc_order_caching_match
[12:29:16] [PASSED] ttm_pool_alloc_caching_mismatch
[12:29:16] [PASSED] ttm_pool_alloc_order_mismatch
[12:29:16] [PASSED] ttm_pool_free_dma_alloc
[12:29:16] [PASSED] ttm_pool_free_no_dma_alloc
[12:29:16] [PASSED] ttm_pool_fini_basic
[12:29:16] ==================== [PASSED] ttm_pool =====================
[12:29:16] ================ ttm_resource (8 subtests) =================
[12:29:16] ================= ttm_resource_init_basic =================
[12:29:16] [PASSED] Init resource in TTM_PL_SYSTEM
[12:29:16] [PASSED] Init resource in TTM_PL_VRAM
[12:29:16] [PASSED] Init resource in a private placement
[12:29:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:29:16] ============= [PASSED] ttm_resource_init_basic =============
[12:29:16] [PASSED] ttm_resource_init_pinned
[12:29:16] [PASSED] ttm_resource_fini_basic
[12:29:16] [PASSED] ttm_resource_manager_init_basic
[12:29:16] [PASSED] ttm_resource_manager_usage_basic
[12:29:16] [PASSED] ttm_resource_manager_set_used_basic
[12:29:16] [PASSED] ttm_sys_man_alloc_basic
[12:29:16] [PASSED] ttm_sys_man_free_basic
[12:29:16] ================== [PASSED] ttm_resource ===================
[12:29:16] =================== ttm_tt (15 subtests) ===================
[12:29:16] ==================== ttm_tt_init_basic ====================
[12:29:16] [PASSED] Page-aligned size
[12:29:16] [PASSED] Extra pages requested
[12:29:16] ================ [PASSED] ttm_tt_init_basic ================
[12:29:16] [PASSED] ttm_tt_init_misaligned
[12:29:16] [PASSED] ttm_tt_fini_basic
[12:29:16] [PASSED] ttm_tt_fini_sg
[12:29:16] [PASSED] ttm_tt_fini_shmem
[12:29:16] [PASSED] ttm_tt_create_basic
[12:29:16] [PASSED] ttm_tt_create_invalid_bo_type
[12:29:16] [PASSED] ttm_tt_create_ttm_exists
[12:29:16] [PASSED] ttm_tt_create_failed
[12:29:16] [PASSED] ttm_tt_destroy_basic
[12:29:16] [PASSED] ttm_tt_populate_null_ttm
[12:29:16] [PASSED] ttm_tt_populate_populated_ttm
[12:29:16] [PASSED] ttm_tt_unpopulate_basic
[12:29:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:29:16] [PASSED] ttm_tt_swapin_basic
[12:29:16] ===================== [PASSED] ttm_tt ======================
[12:29:16] =================== ttm_bo (14 subtests) ===================
[12:29:16] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:29:16] [PASSED] Cannot be interrupted and sleeps
[12:29:16] [PASSED] Cannot be interrupted, locks straight away
[12:29:16] [PASSED] Can be interrupted, sleeps
[12:29:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:29:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:29:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:29:16] [PASSED] ttm_bo_reserve_double_resv
[12:29:16] [PASSED] ttm_bo_reserve_interrupted
[12:29:16] [PASSED] ttm_bo_reserve_deadlock
[12:29:16] [PASSED] ttm_bo_unreserve_basic
[12:29:16] [PASSED] ttm_bo_unreserve_pinned
[12:29:16] [PASSED] ttm_bo_unreserve_bulk
[12:29:16] [PASSED] ttm_bo_fini_basic
[12:29:16] [PASSED] ttm_bo_fini_shared_resv
[12:29:16] [PASSED] ttm_bo_pin_basic
[12:29:16] [PASSED] ttm_bo_pin_unpin_resource
[12:29:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:29:16] ===================== [PASSED] ttm_bo ======================
[12:29:16] ============== ttm_bo_validate (21 subtests) ===============
[12:29:16] ============== ttm_bo_init_reserved_sys_man ===============
[12:29:16] [PASSED] Buffer object for userspace
[12:29:16] [PASSED] Kernel buffer object
[12:29:16] [PASSED] Shared buffer object
[12:29:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:29:16] ============== ttm_bo_init_reserved_mock_man ==============
[12:29:16] [PASSED] Buffer object for userspace
[12:29:16] [PASSED] Kernel buffer object
[12:29:16] [PASSED] Shared buffer object
[12:29:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:29:16] [PASSED] ttm_bo_init_reserved_resv
[12:29:16] ================== ttm_bo_validate_basic ==================
[12:29:16] [PASSED] Buffer object for userspace
[12:29:16] [PASSED] Kernel buffer object
[12:29:16] [PASSED] Shared buffer object
[12:29:16] ============== [PASSED] ttm_bo_validate_basic ==============
[12:29:16] [PASSED] ttm_bo_validate_invalid_placement
[12:29:16] ============= ttm_bo_validate_same_placement ==============
[12:29:16] [PASSED] System manager
[12:29:16] [PASSED] VRAM manager
[12:29:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:29:16] [PASSED] ttm_bo_validate_failed_alloc
[12:29:16] [PASSED] ttm_bo_validate_pinned
[12:29:16] [PASSED] ttm_bo_validate_busy_placement
[12:29:16] ================ ttm_bo_validate_multihop =================
[12:29:16] [PASSED] Buffer object for userspace
[12:29:16] [PASSED] Kernel buffer object
[12:29:16] [PASSED] Shared buffer object
[12:29:16] ============ [PASSED] ttm_bo_validate_multihop =============
[12:29:16] ========== ttm_bo_validate_no_placement_signaled ==========
[12:29:16] [PASSED] Buffer object in system domain, no page vector
[12:29:16] [PASSED] Buffer object in system domain with an existing page vector
[12:29:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:29:16] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:29:16] [PASSED] Buffer object for userspace
[12:29:16] [PASSED] Kernel buffer object
[12:29:16] [PASSED] Shared buffer object
[12:29:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:29:16] [PASSED] ttm_bo_validate_move_fence_signaled
[12:29:16] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:29:16] [PASSED] Waits for GPU
[12:29:16] [PASSED] Tries to lock straight away
[12:29:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:29:16] [PASSED] ttm_bo_validate_happy_evict
[12:29:16] [PASSED] ttm_bo_validate_all_pinned_evict
[12:29:16] [PASSED] ttm_bo_validate_allowed_only_evict
[12:29:16] [PASSED] ttm_bo_validate_deleted_evict
[12:29:16] [PASSED] ttm_bo_validate_busy_domain_evict
[12:29:16] [PASSED] ttm_bo_validate_evict_gutting
[12:29:16] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:29:16] ================= [PASSED] ttm_bo_validate =================
[12:29:16] ============================================================
[12:29:16] Testing complete. Ran 101 tests: passed: 101
[12:29:17] Elapsed time: 11.165s total, 1.574s configuring, 9.375s building, 0.179s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ Xe.CI.BAT: success for dGPU memory optimizations (rev3)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (9 preceding siblings ...)
2026-02-18 12:29 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev3) Patchwork
@ 2026-02-18 13:09 ` Patchwork
2026-02-18 14:08 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 13:09 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 898 bytes --]
== Series Details ==
Series: dGPU memory optimizations (rev3)
URL : https://patchwork.freedesktop.org/series/161737/
State : success
== Summary ==
CI Bug Log - changes from xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d_BAT -> xe-pw-161737v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 13)
------------------------------
Missing (1): bat-dg2-oem2
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8758 -> IGT_8760
* Linux: xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d -> xe-pw-161737v3
IGT_8758: 8758
IGT_8760: 8760
xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d: fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d
xe-pw-161737v3: 161737v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/index.html
[-- Attachment #2: Type: text/html, Size: 1460 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✗ Xe.CI.FULL: failure for dGPU memory optimizations (rev3)
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
` (10 preceding siblings ...)
2026-02-18 13:09 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-02-18 14:08 ` Patchwork
11 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2026-02-18 14:08 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 31618 bytes --]
== Series Details ==
Series: dGPU memory optimizations (rev3)
URL : https://patchwork.freedesktop.org/series/161737/
State : failure
== Summary ==
CI Bug Log - changes from xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d_FULL -> xe-pw-161737v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-161737v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-161737v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-161737v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
- shard-bmg: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early:
- shard-bmg: [PASS][2] -> [ABORT][3]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html
Known issues
------------
Here are the changes found in xe-pw-161737v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#2327]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#1124])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-3/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-bmg: [PASS][7] -> [SKIP][8] ([Intel XE#367])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-10/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3:
- shard-bmg: NOTRUN -> [INCOMPLETE][10] ([Intel XE#7084])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#3432])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +6 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs.html
* igt@kms_chamelium_color@ctm-negative:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2325]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-2/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2252]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-lnl: NOTRUN -> [SKIP][15] ([Intel XE#373])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-4/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@legacy@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][16] ([Intel XE#1178] / [Intel XE#3304])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@kms_content_protection@legacy@pipe-a-dp-2.html
* igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][17] ([Intel XE#3304]) +1 other test fail
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2321]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-64x21:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2320])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-2/igt@kms_cursor_crc@cursor-random-64x21.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: NOTRUN -> [DMESG-WARN][20] ([Intel XE#5354])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#1397] / [Intel XE#1745])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#1397])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#7178]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#7178])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#6312])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#4141]) +8 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#7061])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2311]) +14 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-move:
- shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#656]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2313]) +13 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#6912])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#6886]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#6886]) +4 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
* igt@kms_pm_rpm@package-g7:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#6814])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@kms_pm_rpm@package-g7.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#1406] / [Intel XE#2387])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-3/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-page-flip:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@kms_psr@fbc-pr-primary-page-flip.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#3414] / [Intel XE#3904])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_sharpness_filter@filter-formats:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#6503]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@kms_sharpness_filter@filter-formats.html
* igt@kms_vrr@flip-basic:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#1499]) +2 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-1/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [PASS][41] -> [FAIL][42] ([Intel XE#2142]) +1 other test fail
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_eudebug@basic-exec-queues:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#4837]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@xe_eudebug@basic-exec-queues.html
* igt@xe_eudebug_online@pagefault-write:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@xe_eudebug_online@pagefault-write.html
* igt@xe_evict@evict-beng-large-cm:
- shard-lnl: NOTRUN -> [SKIP][45] ([Intel XE#688])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-1/igt@xe_evict@evict-beng-large-cm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2322]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#7136]) +6 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind.html
* igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#6874]) +9 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html
* igt@xe_exec_multi_queue@priority:
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#6874]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-2/igt@xe_exec_multi_queue@priority.html
* igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#7138]) +5 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr.html
* igt@xe_multigpu_svm@mgpu-latency-copy-basic:
- shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#6964])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-4/igt@xe_multigpu_svm@mgpu-latency-copy-basic.html
* igt@xe_pm@d3cold-i2c:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#5694])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-2/igt@xe_pm@d3cold-i2c.html
* igt@xe_pm@s4-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2284])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-10/igt@xe_pm@s4-d3cold-basic-exec.html
* igt@xe_query@multigpu-query-config:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#944])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@xe_query@multigpu-query-config.html
#### Possible fixes ####
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [DMESG-WARN][55] ([Intel XE#5354]) -> [PASS][56] +1 other test pass
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-9/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][57] ([Intel XE#4633]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][59] ([Intel XE#301]) -> [PASS][60] +3 other tests pass
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-bmg: [INCOMPLETE][61] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][62] +1 other test pass
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][63] ([Intel XE#1503]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
* igt@kms_vrr@max-min@pipe-a-edp-1:
- shard-lnl: [FAIL][65] ([Intel XE#4227]) -> [PASS][66] +1 other test pass
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-lnl-1/igt@kms_vrr@max-min@pipe-a-edp-1.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-lnl-4/igt@kms_vrr@max-min@pipe-a-edp-1.html
* igt@xe_module_load@load:
- shard-bmg: ([PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [SKIP][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92]) ([Intel XE#2457]) -> ([PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-5/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-4/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-10/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-2/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-2/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-8/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-8/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-4/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-7/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-5/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-10/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-8/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-3/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-6/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-6/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-3/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-7/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-5/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-9/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-3/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-9/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-9/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-10/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-3/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-3/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-2/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-7/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-1/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-1/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-10/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-10/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-5/igt@xe_module_load@load.html
* igt@xe_pm_residency@aspm_link_residency:
- shard-bmg: [SKIP][117] ([Intel XE#7258]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-6/igt@xe_pm_residency@aspm_link_residency.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-8/igt@xe_pm_residency@aspm_link_residency.html
#### Warnings ####
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][119] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][120] ([Intel XE#3544])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][121] ([Intel XE#2426]) -> [FAIL][122] ([Intel XE#1729])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][123] ([Intel XE#5466]) -> [ABORT][124] ([Intel XE#5466] / [Intel XE#6652])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/shard-bmg-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7258]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7258
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8758 -> IGT_8760
* Linux: xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d -> xe-pw-161737v3
IGT_8758: 8758
IGT_8760: 8760
xe-4572-fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d: fc9512d31fa2c190f58c85dbdf7313d2d0ad4b0d
xe-pw-161737v3: 161737v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161737v3/index.html
[-- Attachment #2: Type: text/html, Size: 34716 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
@ 2026-02-18 23:12 ` Summers, Stuart
2026-02-19 3:46 ` Matthew Brost
2026-02-24 15:58 ` Thomas Hellström
1 sibling, 1 reply; 29+ messages in thread
From: Summers, Stuart @ 2026-02-18 23:12 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Brost, Matthew
Cc: Ceraolo Spurio, Daniele, Wajdeczko, Michal, Dugast, Francois
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> H2G and G2H buffers have different access patterns (H2G is CPU-write,
> GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> benefit from different memory placements: H2G in VRAM and G2H in
> system
> memory. Split the CT buffer into two separate buffers—one for H2G and
> one for G2H—and select the optimal placement for each.
>
> This provides a significant performance improvement on the G2H read
> path, reducing a single read from ~20 µs to under 1 µs on BMG.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>
> ---
> v3:
> - Move BO to ctbs h2g or g2h structure (Michal)
> ---
> drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++-------
> --
> drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> 2 files changed, 47 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 8a45573f8812..ea07a27757d5 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> g2h_fence *g2h_fence)
We should update the documentation above then also to note that this
isn't a single blob any more.
>
> #define CTB_DESC_SIZE ALIGN(sizeof(struct
> guc_ct_buffer_desc), SZ_2K)
> #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE / sizeof(u32))
> #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct
> xe_guc_ct *ct)
> return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> }
>
> -static size_t guc_ct_size(void)
> +static size_t guc_h2g_size(void)
> {
> - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> - CTB_G2H_BUFFER_SIZE;
> + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> +}
> +
> +static size_t guc_g2h_size(void)
> +{
> + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> }
>
> static void guc_ct_fini(struct drm_device *drm, void *arg)
> @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> struct xe_gt *gt = ct_to_gt(ct);
> int err;
>
> - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
For the h2g since we might relocate to device mem, should we use SZ_4K?
Maybe should append this to the discussion in that other series rev..
> + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
It would be nice to have a comment here after that discussion in the
previous rev around using PAGE_SIZE because of the system memory
allocation vs SZ_4K. Otherwise it seems likely we'll just run into that
again.
Thanks,
Stuart
>
> err = drmm_mutex_init(&xe->drm, &ct->lock);
> if (err)
> @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_bo *bo;
>
> - bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> + bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> + XE_BO_FLAG_SYSTEM |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE
> |
> +
> XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + ct->ctbs.h2g.bo = bo;
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> XE_BO_FLAG_SYSTEM |
> XE_BO_FLAG_GGTT |
> XE_BO_FLAG_GGTT_INVALIDATE
> |
> @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
> - ct->bo = bo;
> + ct->ctbs.g2h.bo = bo;
>
> return devm_add_action_or_reset(xe->drm.dev,
> guc_action_disable_ct, ct);
> }
> @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct
> *ct)
> xe_assert(xe, !xe_guc_ct_enabled(ct));
>
> if (IS_DGFX(xe)) {
> - ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> >bo);
> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> >ctbs.h2g.bo);
> if (ret)
> return ret;
> }
> @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device
> *xe, struct guc_ctb *g2h,
> g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> guc_ct_buffer_desc));
>
> - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET
> +
> - CTB_H2G_BUFFER_SIZE);
> + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> CTB_G2H_BUFFER_OFFSET);
> }
>
> static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> xe_guc_ct *ct)
> u32 desc_addr, ctb_addr, size;
> int err;
>
> - desc_addr = xe_bo_ggtt_addr(ct->bo);
> - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> CTB_H2G_BUFFER_OFFSET;
> size = ct->ctbs.h2g.info.size * sizeof(u32);
>
> err = xe_guc_self_cfg64(guc,
> @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> xe_guc_ct *ct)
> u32 desc_addr, ctb_addr, size;
> int err;
>
> - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> - CTB_H2G_BUFFER_SIZE;
> + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) + CTB_DESC_SIZE;
> + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> CTB_G2H_BUFFER_OFFSET;
> size = ct->ctbs.g2h.info.size * sizeof(u32);
>
> err = xe_guc_self_cfg64(guc,
> @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> *ct, bool needs_register)
> xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
>
> if (needs_register) {
> - xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct-
> >bo));
> - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> >vmap);
> - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> >vmap);
> + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> + xe_bo_size(ct->ctbs.h2g.bo));
> + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> + xe_bo_size(ct->ctbs.g2h.bo));
> + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> >ctbs.h2g.bo->vmap);
> + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> >ctbs.g2h.bo->vmap);
>
> err = guc_ct_ctb_h2g_register(ct);
> if (err)
> @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> *ct, bool needs_register)
> ct->ctbs.h2g.info.broken = false;
> ct->ctbs.g2h.info.broken = false;
> /* Skip everything in H2G buffer */
> - xe_map_memset(xe, &ct->bo->vmap,
> CTB_H2G_BUFFER_OFFSET, 0,
> + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> CTB_H2G_BUFFER_OFFSET, 0,
> CTB_H2G_BUFFER_SIZE);
> }
>
> @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> if (!snapshot)
> return NULL;
>
> - if (ct->bo && want_ctb) {
> - snapshot->ctb_size = xe_bo_size(ct->bo);
> + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo) +
> + xe_bo_size(ct->ctbs.g2h.bo);
> snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ?
> GFP_ATOMIC : GFP_KERNEL);
> }
>
> @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> &snapshot->g2h);
> }
>
> - if (ct->bo && snapshot->ctb)
> - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap,
> 0, snapshot->ctb_size);
> + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb) {
> + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> >ctbs.h2g.bo->vmap, 0,
> + xe_bo_size(ct->ctbs.h2g.bo));
> + xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct-
> >ctbs.h2g.bo),
> + &ct->ctbs.g2h.bo->vmap, 0,
> + xe_bo_size(ct->ctbs.g2h.bo));
> + }
>
> return snapshot;
> }
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> index 09d7ff1ef42a..46ad1402347d 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> @@ -39,6 +39,8 @@ struct guc_ctb_info {
> * struct guc_ctb - GuC command transport buffer (CTB)
> */
> struct guc_ctb {
> + /** @bo: Xe BO for CTB */
> + struct xe_bo *bo;
> /** @desc: dma buffer map for CTB descriptor */
> struct iosys_map desc;
> /** @cmds: dma buffer map for CTB commands */
> @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> * for the H2G and G2H requests sent and received through the
> buffers.
> */
> struct xe_guc_ct {
> - /** @bo: Xe BO for CT */
> - struct xe_bo *bo;
> /** @lock: protects everything in CT layer */
> struct mutex lock;
> /** @fast_lock: protects G2H channel and credits */
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path
2026-02-18 4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
@ 2026-02-18 23:20 ` Summers, Stuart
2026-02-26 12:47 ` Thomas Hellström
1 sibling, 0 replies; 29+ messages in thread
From: Summers, Stuart @ 2026-02-18 23:20 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Brost, Matthew
Cc: Ceraolo Spurio, Daniele, Wajdeczko, Michal, Dugast, Francois
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> desc_read() issues an VRAM read which serializes the CPU and drains
Few spelling nits in the commit message
/s/an/a/
> posted writes on dGPU platforms. The H2G tracepoint evaluated its
> arguments unconditionally, so even with tracing disabled the
> submission
> path paid the full VRAM readf latency. Guard the tracepoint with
> trace_xe_guc_ctb_h2g_enabled().
>
> Adso move the descriptor status verification under
/s/Adso/Also/
> CONFIG_DRM_XE_DEBUG.
> This removes another unnecessary VRAM read in non-debug builfds.
/s/builfds/builds/
>
> This results in ~10× faster H2G submission and significantly reduces
> lock contention across the driver.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ct.c | 25 ++++++++++++++++---------
> 1 file changed, 16 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index ea07a27757d5..37842c93e0ee 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
> u32 full_len;
> struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
> tail *
> sizeof(u32));
> - u32 desc_status;
>
> full_len = len + GUC_CTB_HDR_LEN;
>
> lockdep_assert_held(&ct->lock);
> xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
>
> - desc_status = desc_read(xe, h2g, status);
> - if (desc_status) {
> - xe_gt_err(gt, "CT write: non-zero status: %u\n",
> desc_status);
> - goto corrupted;
> - }
> -
> if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
Somehow in the previous rev I had read this as
CONFIG_DRM_XE_DEBUG_GUC... yeah no issue here. Mainly I want to be able
to see this in CI runs which should mostly have XE_DEBUG set.
So apart from the spelling fixes in the commit:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Thanks,
Stuart
> u32 desc_tail = desc_read(xe, h2g, tail);
> u32 desc_head = desc_read(xe, h2g, head);
> + u32 desc_status;
> +
> + desc_status = desc_read(xe, h2g, status);
> + if (desc_status) {
> + xe_gt_err(gt, "CT write: non-zero status:
> %u\n", desc_status);
> + goto corrupted;
> + }
>
> if (tail != desc_tail) {
> desc_write(xe, h2g, status, desc_status |
> GUC_CTB_STATUS_MISMATCH);
> @@ -1023,8 +1023,15 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
> /* Update descriptor */
> desc_write(xe, h2g, tail, h2g->info.tail);
>
> - trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> - desc_read(xe, h2g, head), h2g-
> >info.tail);
> + /*
> + * desc_read() performs an VRAM read which serializes the CPU
> and drains
> + * posted writes on dGPU platforms. Tracepoints evaluate
> arguments even
> + * when disabled, so guard the event to avoid adding µs-scale
> latency to
> + * the fast H2G submission path when tracing is not active.
> + */
> + if (trace_xe_guc_ctb_h2g_enabled())
> + trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> + desc_read(xe, h2g, head), h2g-
> >info.tail);
>
> return 0;
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-18 23:12 ` Summers, Stuart
@ 2026-02-19 3:46 ` Matthew Brost
0 siblings, 0 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-19 3:46 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Ceraolo Spurio, Daniele,
Wajdeczko, Michal, Dugast, Francois
On Wed, Feb 18, 2026 at 04:12:16PM -0700, Summers, Stuart wrote:
> On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > H2G and G2H buffers have different access patterns (H2G is CPU-write,
> > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> > benefit from different memory placements: H2G in VRAM and G2H in
> > system
> > memory. Split the CT buffer into two separate buffers—one for H2G and
> > one for G2H—and select the optimal placement for each.
> >
> > This provides a significant performance improvement on the G2H read
> > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >
> > ---
> > v3:
> > - Move BO to ctbs h2g or g2h structure (Michal)
> > ---
> > drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++-------
> > --
> > drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> > 2 files changed, 47 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > index 8a45573f8812..ea07a27757d5 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> > g2h_fence *g2h_fence)
>
> We should update the documentation above then also to note that this
> isn't a single blob any more.
>
Yes, will do.
> >
> > #define CTB_DESC_SIZE ALIGN(sizeof(struct
> > guc_ct_buffer_desc), SZ_2K)
> > #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> > #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE / sizeof(u32))
> > #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> > @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct
> > xe_guc_ct *ct)
> > return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> > }
> >
> > -static size_t guc_ct_size(void)
> > +static size_t guc_h2g_size(void)
> > {
> > - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > - CTB_G2H_BUFFER_SIZE;
> > + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > +}
> > +
> > +static size_t guc_g2h_size(void)
> > +{
> > + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> > }
> >
> > static void guc_ct_fini(struct drm_device *drm, void *arg)
> > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> > struct xe_gt *gt = ct_to_gt(ct);
> > int err;
> >
> > - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
>
> For the h2g since we might relocate to device mem, should we use SZ_4K?
> Maybe should append this to the discussion in that other series rev..
>
This is clearly broken for PAGE_SIZE != 4K. I'd rather leave the assert
as is for now for so we know this is broken and eventually fix this. It
is probably easy as changing guc_h2g_size/guc_g2h_size to align to
PAGE_SIZE. Also iGPU we never reallocate so PAGE_SIZE is actually
correct there.
> > + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
>
> It would be nice to have a comment here after that discussion in the
> previous rev around using PAGE_SIZE because of the system memory
> allocation vs SZ_4K. Otherwise it seems likely we'll just run into that
> again.
>
See above, IMO different/existing issue, thus should be addressed in a
different patch.
Matt
> Thanks,
> Stuart
>
> >
> > err = drmm_mutex_init(&xe->drm, &ct->lock);
> > if (err)
> > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > struct xe_tile *tile = gt_to_tile(gt);
> > struct xe_bo *bo;
> >
> > - bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> > + bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> > + XE_BO_FLAG_SYSTEM |
> > + XE_BO_FLAG_GGTT |
> > + XE_BO_FLAG_GGTT_INVALIDATE
> > |
> > +
> > XE_BO_FLAG_PINNED_NORESTORE);
> > + if (IS_ERR(bo))
> > + return PTR_ERR(bo);
> > +
> > + ct->ctbs.h2g.bo = bo;
> > +
> > + bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> > XE_BO_FLAG_SYSTEM |
> > XE_BO_FLAG_GGTT |
> > XE_BO_FLAG_GGTT_INVALIDATE
> > |
> > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > if (IS_ERR(bo))
> > return PTR_ERR(bo);
> >
> > - ct->bo = bo;
> > + ct->ctbs.g2h.bo = bo;
> >
> > return devm_add_action_or_reset(xe->drm.dev,
> > guc_action_disable_ct, ct);
> > }
> > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct
> > *ct)
> > xe_assert(xe, !xe_guc_ct_enabled(ct));
> >
> > if (IS_DGFX(xe)) {
> > - ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> > >bo);
> > + ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> > >ctbs.h2g.bo);
> > if (ret)
> > return ret;
> > }
> > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device
> > *xe, struct guc_ctb *g2h,
> > g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> > xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> > guc_ct_buffer_desc));
> >
> > - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET
> > +
> > - CTB_H2G_BUFFER_SIZE);
> > + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > CTB_G2H_BUFFER_OFFSET);
> > }
> >
> > static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> > xe_guc_ct *ct)
> > u32 desc_addr, ctb_addr, size;
> > int err;
> >
> > - desc_addr = xe_bo_ggtt_addr(ct->bo);
> > - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> > CTB_H2G_BUFFER_OFFSET;
> > size = ct->ctbs.h2g.info.size * sizeof(u32);
> >
> > err = xe_guc_self_cfg64(guc,
> > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> > xe_guc_ct *ct)
> > u32 desc_addr, ctb_addr, size;
> > int err;
> >
> > - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> > - CTB_H2G_BUFFER_SIZE;
> > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) + CTB_DESC_SIZE;
> > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > CTB_G2H_BUFFER_OFFSET;
> > size = ct->ctbs.g2h.info.size * sizeof(u32);
> >
> > err = xe_guc_self_cfg64(guc,
> > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > *ct, bool needs_register)
> > xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> >
> > if (needs_register) {
> > - xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct-
> > >bo));
> > - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> > >vmap);
> > - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> > >vmap);
> > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> > + xe_bo_size(ct->ctbs.h2g.bo));
> > + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> > + xe_bo_size(ct->ctbs.g2h.bo));
> > + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> > >ctbs.h2g.bo->vmap);
> > + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> > >ctbs.g2h.bo->vmap);
> >
> > err = guc_ct_ctb_h2g_register(ct);
> > if (err)
> > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > *ct, bool needs_register)
> > ct->ctbs.h2g.info.broken = false;
> > ct->ctbs.g2h.info.broken = false;
> > /* Skip everything in H2G buffer */
> > - xe_map_memset(xe, &ct->bo->vmap,
> > CTB_H2G_BUFFER_OFFSET, 0,
> > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> > CTB_H2G_BUFFER_OFFSET, 0,
> > CTB_H2G_BUFFER_SIZE);
> > }
> >
> > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> > *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> > if (!snapshot)
> > return NULL;
> >
> > - if (ct->bo && want_ctb) {
> > - snapshot->ctb_size = xe_bo_size(ct->bo);
> > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> > + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo) +
> > + xe_bo_size(ct->ctbs.g2h.bo);
> > snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ?
> > GFP_ATOMIC : GFP_KERNEL);
> > }
> >
> > @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> > *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> > guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> > &snapshot->g2h);
> > }
> >
> > - if (ct->bo && snapshot->ctb)
> > - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap,
> > 0, snapshot->ctb_size);
> > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb) {
> > + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> > >ctbs.h2g.bo->vmap, 0,
> > + xe_bo_size(ct->ctbs.h2g.bo));
> > + xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct-
> > >ctbs.h2g.bo),
> > + &ct->ctbs.g2h.bo->vmap, 0,
> > + xe_bo_size(ct->ctbs.g2h.bo));
> > + }
> >
> > return snapshot;
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > index 09d7ff1ef42a..46ad1402347d 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > @@ -39,6 +39,8 @@ struct guc_ctb_info {
> > * struct guc_ctb - GuC command transport buffer (CTB)
> > */
> > struct guc_ctb {
> > + /** @bo: Xe BO for CTB */
> > + struct xe_bo *bo;
> > /** @desc: dma buffer map for CTB descriptor */
> > struct iosys_map desc;
> > /** @cmds: dma buffer map for CTB commands */
> > @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> > * for the H2G and G2H requests sent and received through the
> > buffers.
> > */
> > struct xe_guc_ct {
> > - /** @bo: Xe BO for CT */
> > - struct xe_bo *bo;
> > /** @lock: protects everything in CT layer */
> > struct mutex lock;
> > /** @fast_lock: protects G2H channel and credits */
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
@ 2026-02-24 2:40 ` Matthew Brost
2026-02-26 12:25 ` Thomas Hellström
2026-02-26 12:43 ` Thomas Hellström
2 siblings, 0 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-24 2:40 UTC (permalink / raw)
To: intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, Feb 17, 2026 at 08:33:19PM -0800, Matthew Brost wrote:
> The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> that read can turn into a PCIe transaction when the seqno lives in the
> main LRC BO, making the hot-path poll/peek much more expensive.
>
> Allocate a small dedicated seqno BO in system memory and map the seqno
> and start_seqno fields from there instead. The GPU still updates the
> values, but CPU reads stay in cached system memory and avoid PCIe read
> latency.
>
> Update the LRC map/address helpers to accept a BO expression and use the
> new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> teardown.
>
I measured the fence latency, and it looks like fences in system memory
signal roughly 1.5µs faster than those in VRAM on BMG in a test case
with exactly one fence in the fence IRQ list per iteration.
Matt
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++------------
> drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> 2 files changed, 42 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 38f648b98868..d72146313424 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> #define __xe_lrc_regs_offset xe_lrc_regs_offset
>
> -#define LRC_SEQNO_PPHWSP_OFFSET 512
> -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
> +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> #define LRC_PARALLEL_PPHWSP_OFFSET 2048
>
> +#define LRC_SEQNO_OFFSET 0
> +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> +
> u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> {
> return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
>
> static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The seqno is stored in the driver-defined portion of PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> + return LRC_SEQNO_OFFSET;
> }
>
> static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The start seqno is stored in the driver-defined portion of PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) + LRC_START_SEQNO_PPHWSP_OFFSET;
> + return LRC_START_SEQNO_OFFSET;
> }
>
> static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct xe_lrc *lrc)
> return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> }
>
> -#define DECL_MAP_ADDR_HELPERS(elem) \
> +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> { \
> - struct iosys_map map = lrc->bo->vmap; \
> + struct xe_bo *bo = (bo_expr); \
> + struct iosys_map map = bo->vmap; \
> \
> xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> @@ -816,20 +816,22 @@ static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> } \
> static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct xe_lrc *lrc) \
> { \
> - return xe_bo_ggtt_addr(lrc->bo) + __xe_lrc_##elem##_offset(lrc); \
> + struct xe_bo *bo = (bo_expr); \
> +\
> + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc); \
> } \
>
> -DECL_MAP_ADDR_HELPERS(ring)
> -DECL_MAP_ADDR_HELPERS(pphwsp)
> -DECL_MAP_ADDR_HELPERS(seqno)
> -DECL_MAP_ADDR_HELPERS(regs)
> -DECL_MAP_ADDR_HELPERS(start_seqno)
> -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> -DECL_MAP_ADDR_HELPERS(parallel)
> -DECL_MAP_ADDR_HELPERS(indirect_ring)
> -DECL_MAP_ADDR_HELPERS(engine_id)
> +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
>
> #undef DECL_MAP_ADDR_HELPERS
>
> @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> {
> xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> xe_bo_unpin_map_no_vm(lrc->bo);
> + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> }
>
> /*
> @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_device *xe = gt_to_xe(gt);
> + struct xe_bo *seqno_bo;
> struct iosys_map map;
> u32 arb_enable;
> u32 bo_flags;
> @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> if (IS_ERR(lrc->bo))
> return PTR_ERR(lrc->bo);
>
> + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> + ttm_bo_type_kernel,
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_SYSTEM, false);
> + if (IS_ERR(seqno_bo)) {
> + err = PTR_ERR(lrc->bo);
> + goto err_lrc_finish;
> + }
> + lrc->seqno_bo = seqno_bo;
> +
> xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> hwe->fence_irq, hwe->name);
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
> index a4373d280c39..5a718f759ed6 100644
> --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> @@ -22,6 +22,12 @@ struct xe_lrc {
> */
> struct xe_bo *bo;
>
> + /**
> + * @seqno_bo: Buffer object (memory) for seqno numbers. Always in system
> + * memory as this a CPU read, GPU write path object.
> + */
> + struct xe_bo *seqno_bo;
> +
> /** @size: size of the lrc and optional indirect ring state */
> u32 size;
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-18 23:12 ` Summers, Stuart
@ 2026-02-24 15:58 ` Thomas Hellström
2026-02-24 16:12 ` Matthew Brost
1 sibling, 1 reply; 29+ messages in thread
From: Thomas Hellström @ 2026-02-24 15:58 UTC (permalink / raw)
To: Matthew Brost, intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> H2G and G2H buffers have different access patterns (H2G is CPU-write,
> GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> benefit from different memory placements: H2G in VRAM and G2H in
> system
> memory. Split the CT buffer into two separate buffers—one for H2G and
> one for G2H—and select the optimal placement for each.
>
> This provides a significant performance improvement on the G2H read
> path, reducing a single read from ~20 µs to under 1 µs on BMG.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Perhaps one could experiment with reading the data from the g2h bo
using MOVNTDQA, like the write-combining memcopy. That would avoid
caching the data and the GuC having to invalidate the cache line while
snooping on the next write.
But that should probably have a less impact, but perhaps speeding up
GuC writes.
/Thomas
>
> ---
> v3:
> - Move BO to ctbs h2g or g2h structure (Michal)
> ---
> drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++-------
> --
> drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> 2 files changed, 47 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 8a45573f8812..ea07a27757d5 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> g2h_fence *g2h_fence)
>
> #define CTB_DESC_SIZE ALIGN(sizeof(struct
> guc_ct_buffer_desc), SZ_2K)
> #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE / sizeof(u32))
> #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct
> xe_guc_ct *ct)
> return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> }
>
> -static size_t guc_ct_size(void)
> +static size_t guc_h2g_size(void)
> {
> - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> - CTB_G2H_BUFFER_SIZE;
> + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> +}
> +
> +static size_t guc_g2h_size(void)
> +{
> + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> }
>
> static void guc_ct_fini(struct drm_device *drm, void *arg)
> @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> struct xe_gt *gt = ct_to_gt(ct);
> int err;
>
> - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
>
> err = drmm_mutex_init(&xe->drm, &ct->lock);
> if (err)
> @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_bo *bo;
>
> - bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> + bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> + XE_BO_FLAG_SYSTEM |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE
> |
> +
> XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + ct->ctbs.h2g.bo = bo;
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> XE_BO_FLAG_SYSTEM |
> XE_BO_FLAG_GGTT |
> XE_BO_FLAG_GGTT_INVALIDATE
> |
> @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
> - ct->bo = bo;
> + ct->ctbs.g2h.bo = bo;
>
> return devm_add_action_or_reset(xe->drm.dev,
> guc_action_disable_ct, ct);
> }
> @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct
> *ct)
> xe_assert(xe, !xe_guc_ct_enabled(ct));
>
> if (IS_DGFX(xe)) {
> - ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> >bo);
> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> >ctbs.h2g.bo);
> if (ret)
> return ret;
> }
> @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device
> *xe, struct guc_ctb *g2h,
> g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> guc_ct_buffer_desc));
>
> - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET
> +
> - CTB_H2G_BUFFER_SIZE);
> + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> CTB_G2H_BUFFER_OFFSET);
> }
>
> static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> xe_guc_ct *ct)
> u32 desc_addr, ctb_addr, size;
> int err;
>
> - desc_addr = xe_bo_ggtt_addr(ct->bo);
> - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> CTB_H2G_BUFFER_OFFSET;
> size = ct->ctbs.h2g.info.size * sizeof(u32);
>
> err = xe_guc_self_cfg64(guc,
> @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> xe_guc_ct *ct)
> u32 desc_addr, ctb_addr, size;
> int err;
>
> - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> - CTB_H2G_BUFFER_SIZE;
> + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> CTB_DESC_SIZE;
> + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> CTB_G2H_BUFFER_OFFSET;
> size = ct->ctbs.g2h.info.size * sizeof(u32);
>
> err = xe_guc_self_cfg64(guc,
> @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> *ct, bool needs_register)
> xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
>
> if (needs_register) {
> - xe_map_memset(xe, &ct->bo->vmap, 0, 0,
> xe_bo_size(ct->bo));
> - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> >vmap);
> - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> >vmap);
> + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> + xe_bo_size(ct->ctbs.h2g.bo));
> + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> + xe_bo_size(ct->ctbs.g2h.bo));
> + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> >ctbs.h2g.bo->vmap);
> + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> >ctbs.g2h.bo->vmap);
>
> err = guc_ct_ctb_h2g_register(ct);
> if (err)
> @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> *ct, bool needs_register)
> ct->ctbs.h2g.info.broken = false;
> ct->ctbs.g2h.info.broken = false;
> /* Skip everything in H2G buffer */
> - xe_map_memset(xe, &ct->bo->vmap,
> CTB_H2G_BUFFER_OFFSET, 0,
> + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> CTB_H2G_BUFFER_OFFSET, 0,
> CTB_H2G_BUFFER_SIZE);
> }
>
> @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> if (!snapshot)
> return NULL;
>
> - if (ct->bo && want_ctb) {
> - snapshot->ctb_size = xe_bo_size(ct->bo);
> + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo) +
> + xe_bo_size(ct->ctbs.g2h.bo);
> snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ?
> GFP_ATOMIC : GFP_KERNEL);
> }
>
> @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> &snapshot->g2h);
> }
>
> - if (ct->bo && snapshot->ctb)
> - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap,
> 0, snapshot->ctb_size);
> + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb) {
> + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> >ctbs.h2g.bo->vmap, 0,
> + xe_bo_size(ct->ctbs.h2g.bo));
> + xe_map_memcpy_from(xe, snapshot->ctb +
> xe_bo_size(ct->ctbs.h2g.bo),
> + &ct->ctbs.g2h.bo->vmap, 0,
> + xe_bo_size(ct->ctbs.g2h.bo));
> + }
>
> return snapshot;
> }
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> index 09d7ff1ef42a..46ad1402347d 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> @@ -39,6 +39,8 @@ struct guc_ctb_info {
> * struct guc_ctb - GuC command transport buffer (CTB)
> */
> struct guc_ctb {
> + /** @bo: Xe BO for CTB */
> + struct xe_bo *bo;
> /** @desc: dma buffer map for CTB descriptor */
> struct iosys_map desc;
> /** @cmds: dma buffer map for CTB commands */
> @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> * for the H2G and G2H requests sent and received through the
> buffers.
> */
> struct xe_guc_ct {
> - /** @bo: Xe BO for CT */
> - struct xe_bo *bo;
> /** @lock: protects everything in CT layer */
> struct mutex lock;
> /** @fast_lock: protects G2H channel and credits */
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-24 15:58 ` Thomas Hellström
@ 2026-02-24 16:12 ` Matthew Brost
2026-02-25 10:55 ` Thomas Hellström
2026-02-26 12:08 ` Thomas Hellström
0 siblings, 2 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-24 16:12 UTC (permalink / raw)
To: Thomas Hellström
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, Feb 24, 2026 at 04:58:35PM +0100, Thomas Hellström wrote:
> On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > H2G and G2H buffers have different access patterns (H2G is CPU-write,
> > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> > benefit from different memory placements: H2G in VRAM and G2H in
> > system
> > memory. Split the CT buffer into two separate buffers—one for H2G and
> > one for G2H—and select the optimal placement for each.
> >
> > This provides a significant performance improvement on the G2H read
> > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>
> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>
> Perhaps one could experiment with reading the data from the g2h bo
> using MOVNTDQA, like the write-combining memcopy. That would avoid
> caching the data and the GuC having to invalidate the cache line while
> snooping on the next write.
We can try that, but G2H messages are variable-sized, so I believe it
will get a little tricky. Once these are system-memory reads, I recall
G2H handling being something like 15 per µs of page faults (maybe that
isn’t correct — I’ll double-check), and that included my not-yet-posted
caching implementation, which also takes a spinlock, examines the
page-fault cache, and chains the fault onto a list. So I don’t think
this will end up in the critical path.
>
> But that should probably have a less impact, but perhaps speeding up
> GuC writes.
We can play around with this and bounce ideas around. On the H2G side,
xe_device_wmb() before the tail update is actually fairly expensive, so
if we can use some asm instructions to avoid that, it might be
worthwhile.
Matt
>
> /Thomas
>
>
> >
> > ---
> > v3:
> > - Move BO to ctbs h2g or g2h structure (Michal)
> > ---
> > drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++-------
> > --
> > drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> > 2 files changed, 47 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > index 8a45573f8812..ea07a27757d5 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> > g2h_fence *g2h_fence)
> >
> > #define CTB_DESC_SIZE ALIGN(sizeof(struct
> > guc_ct_buffer_desc), SZ_2K)
> > #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> > #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE / sizeof(u32))
> > #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> > @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct
> > xe_guc_ct *ct)
> > return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> > }
> >
> > -static size_t guc_ct_size(void)
> > +static size_t guc_h2g_size(void)
> > {
> > - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > - CTB_G2H_BUFFER_SIZE;
> > + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > +}
> > +
> > +static size_t guc_g2h_size(void)
> > +{
> > + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> > }
> >
> > static void guc_ct_fini(struct drm_device *drm, void *arg)
> > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> > struct xe_gt *gt = ct_to_gt(ct);
> > int err;
> >
> > - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> > + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
> >
> > err = drmm_mutex_init(&xe->drm, &ct->lock);
> > if (err)
> > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > struct xe_tile *tile = gt_to_tile(gt);
> > struct xe_bo *bo;
> >
> > - bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> > + bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> > + XE_BO_FLAG_SYSTEM |
> > + XE_BO_FLAG_GGTT |
> > + XE_BO_FLAG_GGTT_INVALIDATE
> > |
> > +
> > XE_BO_FLAG_PINNED_NORESTORE);
> > + if (IS_ERR(bo))
> > + return PTR_ERR(bo);
> > +
> > + ct->ctbs.h2g.bo = bo;
> > +
> > + bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> > XE_BO_FLAG_SYSTEM |
> > XE_BO_FLAG_GGTT |
> > XE_BO_FLAG_GGTT_INVALIDATE
> > |
> > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > if (IS_ERR(bo))
> > return PTR_ERR(bo);
> >
> > - ct->bo = bo;
> > + ct->ctbs.g2h.bo = bo;
> >
> > return devm_add_action_or_reset(xe->drm.dev,
> > guc_action_disable_ct, ct);
> > }
> > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct
> > *ct)
> > xe_assert(xe, !xe_guc_ct_enabled(ct));
> >
> > if (IS_DGFX(xe)) {
> > - ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> > >bo);
> > + ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct-
> > >ctbs.h2g.bo);
> > if (ret)
> > return ret;
> > }
> > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device
> > *xe, struct guc_ctb *g2h,
> > g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> > xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> > guc_ct_buffer_desc));
> >
> > - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET
> > +
> > - CTB_H2G_BUFFER_SIZE);
> > + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > CTB_G2H_BUFFER_OFFSET);
> > }
> >
> > static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> > xe_guc_ct *ct)
> > u32 desc_addr, ctb_addr, size;
> > int err;
> >
> > - desc_addr = xe_bo_ggtt_addr(ct->bo);
> > - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> > CTB_H2G_BUFFER_OFFSET;
> > size = ct->ctbs.h2g.info.size * sizeof(u32);
> >
> > err = xe_guc_self_cfg64(guc,
> > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> > xe_guc_ct *ct)
> > u32 desc_addr, ctb_addr, size;
> > int err;
> >
> > - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > - ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> > - CTB_H2G_BUFFER_SIZE;
> > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > CTB_DESC_SIZE;
> > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > CTB_G2H_BUFFER_OFFSET;
> > size = ct->ctbs.g2h.info.size * sizeof(u32);
> >
> > err = xe_guc_self_cfg64(guc,
> > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > *ct, bool needs_register)
> > xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> >
> > if (needs_register) {
> > - xe_map_memset(xe, &ct->bo->vmap, 0, 0,
> > xe_bo_size(ct->bo));
> > - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> > >vmap);
> > - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> > >vmap);
> > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> > + xe_bo_size(ct->ctbs.h2g.bo));
> > + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> > + xe_bo_size(ct->ctbs.g2h.bo));
> > + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> > >ctbs.h2g.bo->vmap);
> > + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> > >ctbs.g2h.bo->vmap);
> >
> > err = guc_ct_ctb_h2g_register(ct);
> > if (err)
> > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > *ct, bool needs_register)
> > ct->ctbs.h2g.info.broken = false;
> > ct->ctbs.g2h.info.broken = false;
> > /* Skip everything in H2G buffer */
> > - xe_map_memset(xe, &ct->bo->vmap,
> > CTB_H2G_BUFFER_OFFSET, 0,
> > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> > CTB_H2G_BUFFER_OFFSET, 0,
> > CTB_H2G_BUFFER_SIZE);
> > }
> >
> > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> > *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> > if (!snapshot)
> > return NULL;
> >
> > - if (ct->bo && want_ctb) {
> > - snapshot->ctb_size = xe_bo_size(ct->bo);
> > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> > + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo) +
> > + xe_bo_size(ct->ctbs.g2h.bo);
> > snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ?
> > GFP_ATOMIC : GFP_KERNEL);
> > }
> >
> > @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> > *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> > guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> > &snapshot->g2h);
> > }
> >
> > - if (ct->bo && snapshot->ctb)
> > - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap,
> > 0, snapshot->ctb_size);
> > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb) {
> > + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> > >ctbs.h2g.bo->vmap, 0,
> > + xe_bo_size(ct->ctbs.h2g.bo));
> > + xe_map_memcpy_from(xe, snapshot->ctb +
> > xe_bo_size(ct->ctbs.h2g.bo),
> > + &ct->ctbs.g2h.bo->vmap, 0,
> > + xe_bo_size(ct->ctbs.g2h.bo));
> > + }
> >
> > return snapshot;
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > index 09d7ff1ef42a..46ad1402347d 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > @@ -39,6 +39,8 @@ struct guc_ctb_info {
> > * struct guc_ctb - GuC command transport buffer (CTB)
> > */
> > struct guc_ctb {
> > + /** @bo: Xe BO for CTB */
> > + struct xe_bo *bo;
> > /** @desc: dma buffer map for CTB descriptor */
> > struct iosys_map desc;
> > /** @cmds: dma buffer map for CTB commands */
> > @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> > * for the H2G and G2H requests sent and received through the
> > buffers.
> > */
> > struct xe_guc_ct {
> > - /** @bo: Xe BO for CT */
> > - struct xe_bo *bo;
> > /** @lock: protects everything in CT layer */
> > struct mutex lock;
> > /** @fast_lock: protects G2H channel and credits */
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-24 16:12 ` Matthew Brost
@ 2026-02-25 10:55 ` Thomas Hellström
2026-02-25 18:08 ` Matthew Brost
2026-02-26 12:08 ` Thomas Hellström
1 sibling, 1 reply; 29+ messages in thread
From: Thomas Hellström @ 2026-02-25 10:55 UTC (permalink / raw)
To: Matthew Brost
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-24 at 08:12 -0800, Matthew Brost wrote:
> On Tue, Feb 24, 2026 at 04:58:35PM +0100, Thomas Hellström wrote:
> > On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > > H2G and G2H buffers have different access patterns (H2G is CPU-
> > > write,
> > > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these
> > > patterns
> > > benefit from different memory placements: H2G in VRAM and G2H in
> > > system
> > > memory. Split the CT buffer into two separate buffers—one for H2G
> > > and
> > > one for G2H—and select the optimal placement for each.
> > >
> > > This provides a significant performance improvement on the G2H
> > > read
> > > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> > >
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >
> > Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> >
> > Perhaps one could experiment with reading the data from the g2h bo
> > using MOVNTDQA, like the write-combining memcopy. That would avoid
> > caching the data and the GuC having to invalidate the cache line
> > while
> > snooping on the next write.
>
> We can try that, but G2H messages are variable-sized, so I believe it
> will get a little tricky. Once these are system-memory reads, I
> recall
> G2H handling being something like 15 per µs of page faults (maybe
> that
> isn’t correct — I’ll double-check), and that included my not-yet-
> posted
> caching implementation, which also takes a spinlock, examines the
> page-fault cache, and chains the fault onto a list. So I don’t think
> this will end up in the critical path.
>
> >
> > But that should probably have a less impact, but perhaps speeding
> > up
> > GuC writes.
>
> We can play around with this and bounce ideas around. On the H2G
> side,
> xe_device_wmb() before the tail update is actually fairly expensive,
> so
> if we can use some asm instructions to avoid that, it might be
> worthwhile.
That is probably the latency of flushing out buffered writes. I don't
think there is much to be done on improving that.
/Thomas
>
> Matt
>
> >
> > /Thomas
> >
> >
> > >
> > > ---
> > > v3:
> > > - Move BO to ctbs h2g or g2h structure (Michal)
> > > ---
> > > drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++---
> > > ----
> > > --
> > > drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> > > 2 files changed, 47 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > index 8a45573f8812..ea07a27757d5 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> > > g2h_fence *g2h_fence)
> > >
> > > #define CTB_DESC_SIZE ALIGN(sizeof(struct
> > > guc_ct_buffer_desc), SZ_2K)
> > > #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > > +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > > #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> > > #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE /
> > > sizeof(u32))
> > > #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> > > @@ -279,10 +280,14 @@ long
> > > xe_guc_ct_queue_proc_time_jiffies(struct
> > > xe_guc_ct *ct)
> > > return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> > > }
> > >
> > > -static size_t guc_ct_size(void)
> > > +static size_t guc_h2g_size(void)
> > > {
> > > - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > > - CTB_G2H_BUFFER_SIZE;
> > > + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > > +}
> > > +
> > > +static size_t guc_g2h_size(void)
> > > +{
> > > + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> > > }
> > >
> > > static void guc_ct_fini(struct drm_device *drm, void *arg)
> > > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct
> > > *ct)
> > > struct xe_gt *gt = ct_to_gt(ct);
> > > int err;
> > >
> > > - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > > + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> > > + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
> > >
> > > err = drmm_mutex_init(&xe->drm, &ct->lock);
> > > if (err)
> > > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > > struct xe_tile *tile = gt_to_tile(gt);
> > > struct xe_bo *bo;
> > >
> > > - bo = xe_managed_bo_create_pin_map(xe, tile,
> > > guc_ct_size(),
> > > + bo = xe_managed_bo_create_pin_map(xe, tile,
> > > guc_h2g_size(),
> > > + XE_BO_FLAG_SYSTEM |
> > > + XE_BO_FLAG_GGTT |
> > > +
> > > XE_BO_FLAG_GGTT_INVALIDATE
> > > >
> > > +
> > > XE_BO_FLAG_PINNED_NORESTORE);
> > > + if (IS_ERR(bo))
> > > + return PTR_ERR(bo);
> > > +
> > > + ct->ctbs.h2g.bo = bo;
> > > +
> > > + bo = xe_managed_bo_create_pin_map(xe, tile,
> > > guc_g2h_size(),
> > > XE_BO_FLAG_SYSTEM |
> > > XE_BO_FLAG_GGTT |
> > >
> > > XE_BO_FLAG_GGTT_INVALIDATE
> > > >
> > > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > > if (IS_ERR(bo))
> > > return PTR_ERR(bo);
> > >
> > > - ct->bo = bo;
> > > + ct->ctbs.g2h.bo = bo;
> > >
> > > return devm_add_action_or_reset(xe->drm.dev,
> > > guc_action_disable_ct, ct);
> > > }
> > > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct
> > > xe_guc_ct
> > > *ct)
> > > xe_assert(xe, !xe_guc_ct_enabled(ct));
> > >
> > > if (IS_DGFX(xe)) {
> > > - ret = xe_managed_bo_reinit_in_vram(xe, tile,
> > > &ct-
> > > > bo);
> > > + ret = xe_managed_bo_reinit_in_vram(xe, tile,
> > > &ct-
> > > > ctbs.h2g.bo);
> > > if (ret)
> > > return ret;
> > > }
> > > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct
> > > xe_device
> > > *xe, struct guc_ctb *g2h,
> > > g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> > > xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> > > guc_ct_buffer_desc));
> > >
> > > - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > > CTB_H2G_BUFFER_OFFSET
> > > +
> > > -
> > > CTB_H2G_BUFFER_SIZE);
> > > + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > > CTB_G2H_BUFFER_OFFSET);
> > > }
> > >
> > > static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> > > xe_guc_ct *ct)
> > > u32 desc_addr, ctb_addr, size;
> > > int err;
> > >
> > > - desc_addr = xe_bo_ggtt_addr(ct->bo);
> > > - ctb_addr = xe_bo_ggtt_addr(ct->bo) +
> > > CTB_H2G_BUFFER_OFFSET;
> > > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> > > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> > > CTB_H2G_BUFFER_OFFSET;
> > > size = ct->ctbs.h2g.info.size * sizeof(u32);
> > >
> > > err = xe_guc_self_cfg64(guc,
> > > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> > > xe_guc_ct *ct)
> > > u32 desc_addr, ctb_addr, size;
> > > int err;
> > >
> > > - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > > - ctb_addr = xe_bo_ggtt_addr(ct->bo) +
> > > CTB_H2G_BUFFER_OFFSET +
> > > - CTB_H2G_BUFFER_SIZE;
> > > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > > CTB_DESC_SIZE;
> > > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > > CTB_G2H_BUFFER_OFFSET;
> > > size = ct->ctbs.g2h.info.size * sizeof(u32);
> > >
> > > err = xe_guc_self_cfg64(guc,
> > > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct
> > > xe_guc_ct
> > > *ct, bool needs_register)
> > > xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> > >
> > > if (needs_register) {
> > > - xe_map_memset(xe, &ct->bo->vmap, 0, 0,
> > > xe_bo_size(ct->bo));
> > > - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> > > > vmap);
> > > - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> > > > vmap);
> > > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> > > + xe_bo_size(ct->ctbs.h2g.bo));
> > > + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> > > + xe_bo_size(ct->ctbs.g2h.bo));
> > > + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> > > > ctbs.h2g.bo->vmap);
> > > + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> > > > ctbs.g2h.bo->vmap);
> > >
> > > err = guc_ct_ctb_h2g_register(ct);
> > > if (err)
> > > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > > *ct, bool needs_register)
> > > ct->ctbs.h2g.info.broken = false;
> > > ct->ctbs.g2h.info.broken = false;
> > > /* Skip everything in H2G buffer */
> > > - xe_map_memset(xe, &ct->bo->vmap,
> > > CTB_H2G_BUFFER_OFFSET, 0,
> > > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> > > CTB_H2G_BUFFER_OFFSET, 0,
> > > CTB_H2G_BUFFER_SIZE);
> > > }
> > >
> > > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> > > *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> > > if (!snapshot)
> > > return NULL;
> > >
> > > - if (ct->bo && want_ctb) {
> > > - snapshot->ctb_size = xe_bo_size(ct->bo);
> > > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> > > + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo)
> > > +
> > > + xe_bo_size(ct->ctbs.g2h.bo);
> > > snapshot->ctb = kmalloc(snapshot->ctb_size,
> > > atomic ?
> > > GFP_ATOMIC : GFP_KERNEL);
> > > }
> > >
> > > @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> > > *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> > > guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> > > &snapshot->g2h);
> > > }
> > >
> > > - if (ct->bo && snapshot->ctb)
> > > - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo-
> > > >vmap,
> > > 0, snapshot->ctb_size);
> > > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb)
> > > {
> > > + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> > > > ctbs.h2g.bo->vmap, 0,
> > > + xe_bo_size(ct->ctbs.h2g.bo));
> > > + xe_map_memcpy_from(xe, snapshot->ctb +
> > > xe_bo_size(ct->ctbs.h2g.bo),
> > > + &ct->ctbs.g2h.bo->vmap, 0,
> > > + xe_bo_size(ct->ctbs.g2h.bo));
> > > + }
> > >
> > > return snapshot;
> > > }
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > index 09d7ff1ef42a..46ad1402347d 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > @@ -39,6 +39,8 @@ struct guc_ctb_info {
> > > * struct guc_ctb - GuC command transport buffer (CTB)
> > > */
> > > struct guc_ctb {
> > > + /** @bo: Xe BO for CTB */
> > > + struct xe_bo *bo;
> > > /** @desc: dma buffer map for CTB descriptor */
> > > struct iosys_map desc;
> > > /** @cmds: dma buffer map for CTB commands */
> > > @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> > > * for the H2G and G2H requests sent and received through the
> > > buffers.
> > > */
> > > struct xe_guc_ct {
> > > - /** @bo: Xe BO for CT */
> > > - struct xe_bo *bo;
> > > /** @lock: protects everything in CT layer */
> > > struct mutex lock;
> > > /** @fast_lock: protects G2H channel and credits */
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-25 10:55 ` Thomas Hellström
@ 2026-02-25 18:08 ` Matthew Brost
0 siblings, 0 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-25 18:08 UTC (permalink / raw)
To: Thomas Hellström
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Wed, Feb 25, 2026 at 11:55:28AM +0100, Thomas Hellström wrote:
> On Tue, 2026-02-24 at 08:12 -0800, Matthew Brost wrote:
> > On Tue, Feb 24, 2026 at 04:58:35PM +0100, Thomas Hellström wrote:
> > > On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > > > H2G and G2H buffers have different access patterns (H2G is CPU-
> > > > write,
> > > > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these
> > > > patterns
> > > > benefit from different memory placements: H2G in VRAM and G2H in
> > > > system
> > > > memory. Split the CT buffer into two separate buffers—one for H2G
> > > > and
> > > > one for G2H—and select the optimal placement for each.
> > > >
> > > > This provides a significant performance improvement on the G2H
> > > > read
> > > > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> > > >
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > >
> > > Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > >
> > > Perhaps one could experiment with reading the data from the g2h bo
> > > using MOVNTDQA, like the write-combining memcopy. That would avoid
> > > caching the data and the GuC having to invalidate the cache line
> > > while
> > > snooping on the next write.
> >
> > We can try that, but G2H messages are variable-sized, so I believe it
> > will get a little tricky. Once these are system-memory reads, I
> > recall
> > G2H handling being something like 15 per µs of page faults (maybe
> > that
> > isn’t correct — I’ll double-check), and that included my not-yet-
> > posted
> > caching implementation, which also takes a spinlock, examines the
> > page-fault cache, and chains the fault onto a list. So I don’t think
> > this will end up in the critical path.
> >
> > >
> > > But that should probably have a less impact, but perhaps speeding
> > > up
> > > GuC writes.
> >
> > We can play around with this and bounce ideas around. On the H2G
> > side,
> > xe_device_wmb() before the tail update is actually fairly expensive,
> > so
> > if we can use some asm instructions to avoid that, it might be
> > worthwhile.
>
> That is probably the latency of flushing out buffered writes. I don't
> think there is much to be done on improving that.
>
I came up with periodically advancing the tail and issuing
xe_device_wmb() when acking a storm of faults. For example, if we need
to ack 40 faults at once, we send out the first few acks immediately,
then rate-control the rest. This gives roughly a 5× speedup (e.g.,
increasing from ~3 H2Gs per µs to ~15 H2Gs per µs).
I'm asking the GuC to apply the same strategy when generating G2Hs
during fault storms as well.
My KMD portion of this should be posted shortly as part of fault storm
caching.
Matt
> /Thomas
>
> >
> > Matt
> >
> > >
> > > /Thomas
> > >
> > >
> > > >
> > > > ---
> > > > v3:
> > > > - Move BO to ctbs h2g or g2h structure (Michal)
> > > > ---
> > > > drivers/gpu/drm/xe/xe_guc_ct.c | 67 +++++++++++++++++++---
> > > > ----
> > > > --
> > > > drivers/gpu/drm/xe/xe_guc_ct_types.h | 4 +-
> > > > 2 files changed, 47 insertions(+), 24 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > index 8a45573f8812..ea07a27757d5 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct
> > > > g2h_fence *g2h_fence)
> > > >
> > > > #define CTB_DESC_SIZE ALIGN(sizeof(struct
> > > > guc_ct_buffer_desc), SZ_2K)
> > > > #define CTB_H2G_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > > > +#define CTB_G2H_BUFFER_OFFSET (CTB_DESC_SIZE * 2)
> > > > #define CTB_H2G_BUFFER_SIZE (SZ_4K)
> > > > #define CTB_H2G_BUFFER_DWORDS (CTB_H2G_BUFFER_SIZE /
> > > > sizeof(u32))
> > > > #define CTB_G2H_BUFFER_SIZE (SZ_128K)
> > > > @@ -279,10 +280,14 @@ long
> > > > xe_guc_ct_queue_proc_time_jiffies(struct
> > > > xe_guc_ct *ct)
> > > > return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> > > > }
> > > >
> > > > -static size_t guc_ct_size(void)
> > > > +static size_t guc_h2g_size(void)
> > > > {
> > > > - return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > > > - CTB_G2H_BUFFER_SIZE;
> > > > + return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > > > +}
> > > > +
> > > > +static size_t guc_g2h_size(void)
> > > > +{
> > > > + return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> > > > }
> > > >
> > > > static void guc_ct_fini(struct drm_device *drm, void *arg)
> > > > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct
> > > > *ct)
> > > > struct xe_gt *gt = ct_to_gt(ct);
> > > > int err;
> > > >
> > > > - xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > > > + xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> > > > + xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
> > > >
> > > > err = drmm_mutex_init(&xe->drm, &ct->lock);
> > > > if (err)
> > > > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > > > struct xe_tile *tile = gt_to_tile(gt);
> > > > struct xe_bo *bo;
> > > >
> > > > - bo = xe_managed_bo_create_pin_map(xe, tile,
> > > > guc_ct_size(),
> > > > + bo = xe_managed_bo_create_pin_map(xe, tile,
> > > > guc_h2g_size(),
> > > > + XE_BO_FLAG_SYSTEM |
> > > > + XE_BO_FLAG_GGTT |
> > > > +
> > > > XE_BO_FLAG_GGTT_INVALIDATE
> > > > >
> > > > +
> > > > XE_BO_FLAG_PINNED_NORESTORE);
> > > > + if (IS_ERR(bo))
> > > > + return PTR_ERR(bo);
> > > > +
> > > > + ct->ctbs.h2g.bo = bo;
> > > > +
> > > > + bo = xe_managed_bo_create_pin_map(xe, tile,
> > > > guc_g2h_size(),
> > > > XE_BO_FLAG_SYSTEM |
> > > > XE_BO_FLAG_GGTT |
> > > >
> > > > XE_BO_FLAG_GGTT_INVALIDATE
> > > > >
> > > > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > > > if (IS_ERR(bo))
> > > > return PTR_ERR(bo);
> > > >
> > > > - ct->bo = bo;
> > > > + ct->ctbs.g2h.bo = bo;
> > > >
> > > > return devm_add_action_or_reset(xe->drm.dev,
> > > > guc_action_disable_ct, ct);
> > > > }
> > > > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct
> > > > xe_guc_ct
> > > > *ct)
> > > > xe_assert(xe, !xe_guc_ct_enabled(ct));
> > > >
> > > > if (IS_DGFX(xe)) {
> > > > - ret = xe_managed_bo_reinit_in_vram(xe, tile,
> > > > &ct-
> > > > > bo);
> > > > + ret = xe_managed_bo_reinit_in_vram(xe, tile,
> > > > &ct-
> > > > > ctbs.h2g.bo);
> > > > if (ret)
> > > > return ret;
> > > > }
> > > > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct
> > > > xe_device
> > > > *xe, struct guc_ctb *g2h,
> > > > g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> > > > xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct
> > > > guc_ct_buffer_desc));
> > > >
> > > > - g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > > > CTB_H2G_BUFFER_OFFSET
> > > > +
> > > > -
> > > > CTB_H2G_BUFFER_SIZE);
> > > > + g2h->cmds = IOSYS_MAP_INIT_OFFSET(map,
> > > > CTB_G2H_BUFFER_OFFSET);
> > > > }
> > > >
> > > > static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > > > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct
> > > > xe_guc_ct *ct)
> > > > u32 desc_addr, ctb_addr, size;
> > > > int err;
> > > >
> > > > - desc_addr = xe_bo_ggtt_addr(ct->bo);
> > > > - ctb_addr = xe_bo_ggtt_addr(ct->bo) +
> > > > CTB_H2G_BUFFER_OFFSET;
> > > > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo);
> > > > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.h2g.bo) +
> > > > CTB_H2G_BUFFER_OFFSET;
> > > > size = ct->ctbs.h2g.info.size * sizeof(u32);
> > > >
> > > > err = xe_guc_self_cfg64(guc,
> > > > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct
> > > > xe_guc_ct *ct)
> > > > u32 desc_addr, ctb_addr, size;
> > > > int err;
> > > >
> > > > - desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > > > - ctb_addr = xe_bo_ggtt_addr(ct->bo) +
> > > > CTB_H2G_BUFFER_OFFSET +
> > > > - CTB_H2G_BUFFER_SIZE;
> > > > + desc_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > > > CTB_DESC_SIZE;
> > > > + ctb_addr = xe_bo_ggtt_addr(ct->ctbs.g2h.bo) +
> > > > CTB_G2H_BUFFER_OFFSET;
> > > > size = ct->ctbs.g2h.info.size * sizeof(u32);
> > > >
> > > > err = xe_guc_self_cfg64(guc,
> > > > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct
> > > > xe_guc_ct
> > > > *ct, bool needs_register)
> > > > xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> > > >
> > > > if (needs_register) {
> > > > - xe_map_memset(xe, &ct->bo->vmap, 0, 0,
> > > > xe_bo_size(ct->bo));
> > > > - guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo-
> > > > > vmap);
> > > > - guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo-
> > > > > vmap);
> > > > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap, 0, 0,
> > > > + xe_bo_size(ct->ctbs.h2g.bo));
> > > > + xe_map_memset(xe, &ct->ctbs.g2h.bo->vmap, 0, 0,
> > > > + xe_bo_size(ct->ctbs.g2h.bo));
> > > > + guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct-
> > > > > ctbs.h2g.bo->vmap);
> > > > + guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct-
> > > > > ctbs.g2h.bo->vmap);
> > > >
> > > > err = guc_ct_ctb_h2g_register(ct);
> > > > if (err)
> > > > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct
> > > > *ct, bool needs_register)
> > > > ct->ctbs.h2g.info.broken = false;
> > > > ct->ctbs.g2h.info.broken = false;
> > > > /* Skip everything in H2G buffer */
> > > > - xe_map_memset(xe, &ct->bo->vmap,
> > > > CTB_H2G_BUFFER_OFFSET, 0,
> > > > + xe_map_memset(xe, &ct->ctbs.h2g.bo->vmap,
> > > > CTB_H2G_BUFFER_OFFSET, 0,
> > > > CTB_H2G_BUFFER_SIZE);
> > > > }
> > > >
> > > > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot
> > > > *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> > > > if (!snapshot)
> > > > return NULL;
> > > >
> > > > - if (ct->bo && want_ctb) {
> > > > - snapshot->ctb_size = xe_bo_size(ct->bo);
> > > > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && want_ctb) {
> > > > + snapshot->ctb_size = xe_bo_size(ct->ctbs.h2g.bo)
> > > > +
> > > > + xe_bo_size(ct->ctbs.g2h.bo);
> > > > snapshot->ctb = kmalloc(snapshot->ctb_size,
> > > > atomic ?
> > > > GFP_ATOMIC : GFP_KERNEL);
> > > > }
> > > >
> > > > @@ -2012,8 +2030,13 @@ static struct xe_guc_ct_snapshot
> > > > *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> > > > guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h,
> > > > &snapshot->g2h);
> > > > }
> > > >
> > > > - if (ct->bo && snapshot->ctb)
> > > > - xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo-
> > > > >vmap,
> > > > 0, snapshot->ctb_size);
> > > > + if (ct->ctbs.h2g.bo && ct->ctbs.g2h.bo && snapshot->ctb)
> > > > {
> > > > + xe_map_memcpy_from(xe, snapshot->ctb, &ct-
> > > > > ctbs.h2g.bo->vmap, 0,
> > > > + xe_bo_size(ct->ctbs.h2g.bo));
> > > > + xe_map_memcpy_from(xe, snapshot->ctb +
> > > > xe_bo_size(ct->ctbs.h2g.bo),
> > > > + &ct->ctbs.g2h.bo->vmap, 0,
> > > > + xe_bo_size(ct->ctbs.g2h.bo));
> > > > + }
> > > >
> > > > return snapshot;
> > > > }
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > > b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > > index 09d7ff1ef42a..46ad1402347d 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > > @@ -39,6 +39,8 @@ struct guc_ctb_info {
> > > > * struct guc_ctb - GuC command transport buffer (CTB)
> > > > */
> > > > struct guc_ctb {
> > > > + /** @bo: Xe BO for CTB */
> > > > + struct xe_bo *bo;
> > > > /** @desc: dma buffer map for CTB descriptor */
> > > > struct iosys_map desc;
> > > > /** @cmds: dma buffer map for CTB commands */
> > > > @@ -126,8 +128,6 @@ struct xe_fast_req_fence {
> > > > * for the H2G and G2H requests sent and received through the
> > > > buffers.
> > > > */
> > > > struct xe_guc_ct {
> > > > - /** @bo: Xe BO for CT */
> > > > - struct xe_bo *bo;
> > > > /** @lock: protects everything in CT layer */
> > > > struct mutex lock;
> > > > /** @fast_lock: protects G2H channel and credits */
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects
2026-02-24 16:12 ` Matthew Brost
2026-02-25 10:55 ` Thomas Hellström
@ 2026-02-26 12:08 ` Thomas Hellström
1 sibling, 0 replies; 29+ messages in thread
From: Thomas Hellström @ 2026-02-26 12:08 UTC (permalink / raw)
To: Matthew Brost
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-24 at 08:12 -0800, Matthew Brost wrote:
> On Tue, Feb 24, 2026 at 04:58:35PM +0100, Thomas Hellström wrote:
> > On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > > H2G and G2H buffers have different access patterns (H2G is CPU-
> > > write,
> > > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these
> > > patterns
> > > benefit from different memory placements: H2G in VRAM and G2H in
> > > system
> > > memory. Split the CT buffer into two separate buffers—one for H2G
> > > and
> > > one for G2H—and select the optimal placement for each.
> > >
> > > This provides a significant performance improvement on the G2H
> > > read
> > > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> > >
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >
> > Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> >
> > Perhaps one could experiment with reading the data from the g2h bo
> > using MOVNTDQA, like the write-combining memcopy. That would avoid
> > caching the data and the GuC having to invalidate the cache line
> > while
> > snooping on the next write.
>
> We can try that, but G2H messages are variable-sized, so I believe it
> will get a little tricky. Once these are system-memory reads, I
> recall
> G2H handling being something like 15 per µs of page faults (maybe
> that
> isn’t correct — I’ll double-check), and that included my not-yet-
> posted
> caching implementation, which also takes a spinlock, examines the
> page-fault cache, and chains the fault onto a list. So I don’t think
> this will end up in the critical path.
Actually DOCs say MOVNTDQA only has an effect on write-combining
mappings, so probably a dead end experimenting with that.
There's also PREFETCHNTA though, which may or may not have an effect.
/Thomas
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
2026-02-24 2:40 ` Matthew Brost
@ 2026-02-26 12:25 ` Thomas Hellström
2026-02-26 17:11 ` Matthew Brost
2026-02-26 12:43 ` Thomas Hellström
2 siblings, 1 reply; 29+ messages in thread
From: Thomas Hellström @ 2026-02-26 12:25 UTC (permalink / raw)
To: Matthew Brost, intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> that read can turn into a PCIe transaction when the seqno lives in
> the
> main LRC BO, making the hot-path poll/peek much more expensive.
>
> Allocate a small dedicated seqno BO in system memory and map the
> seqno
> and start_seqno fields from there instead. The GPU still updates the
> values, but CPU reads stay in cached system memory and avoid PCIe
> read
> latency.
>
> Update the LRC map/address helpers to accept a BO expression and use
> the
> new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> teardown.
I remember this was discussed also when enabling discrete for the i915
driver but we didn't have any timing information at that time.
Whether this is a good thing depends on the amount of cpu polling per
seqno bump, but I figure that's typically always at least one CPU read,
right?
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++----------
> --
> drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> 2 files changed, 42 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> b/drivers/gpu/drm/xe/xe_lrc.c
> index 38f648b98868..d72146313424 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> #define __xe_lrc_regs_offset xe_lrc_regs_offset
>
> -#define LRC_SEQNO_PPHWSP_OFFSET 512
> -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET
> + 8)
> +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> #define LRC_PARALLEL_PPHWSP_OFFSET 2048
>
> +#define LRC_SEQNO_OFFSET 0
> +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> +
> u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> {
> return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
>
> static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The seqno is stored in the driver-defined portion of
> PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> + return LRC_SEQNO_OFFSET;
> }
>
> static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The start seqno is stored in the driver-defined portion
> of PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) +
> LRC_START_SEQNO_PPHWSP_OFFSET;
> + return LRC_START_SEQNO_OFFSET;
> }
>
> static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct
> xe_lrc *lrc)
> return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> }
>
> -#define DECL_MAP_ADDR_HELPERS(elem) \
> +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc
> *lrc) \
> { \
> - struct iosys_map map = lrc->bo->vmap; \
> + struct xe_bo *bo = (bo_expr); \
> + struct iosys_map map = bo->vmap; \
> \
> xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> @@ -816,20 +816,22 @@ static inline struct iosys_map
> __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> } \
> static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct
> xe_lrc *lrc) \
> { \
> - return xe_bo_ggtt_addr(lrc->bo) +
> __xe_lrc_##elem##_offset(lrc); \
> + struct xe_bo *bo = (bo_expr); \
> +\
> + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc);
> \
> } \
>
> -DECL_MAP_ADDR_HELPERS(ring)
> -DECL_MAP_ADDR_HELPERS(pphwsp)
> -DECL_MAP_ADDR_HELPERS(seqno)
> -DECL_MAP_ADDR_HELPERS(regs)
> -DECL_MAP_ADDR_HELPERS(start_seqno)
> -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> -DECL_MAP_ADDR_HELPERS(parallel)
> -DECL_MAP_ADDR_HELPERS(indirect_ring)
> -DECL_MAP_ADDR_HELPERS(engine_id)
> +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
>
> #undef DECL_MAP_ADDR_HELPERS
>
> @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> {
> xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> xe_bo_unpin_map_no_vm(lrc->bo);
> + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> }
>
> /*
> @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe,
> u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_device *xe = gt_to_xe(gt);
> + struct xe_bo *seqno_bo;
> struct iosys_map map;
> u32 arb_enable;
> u32 bo_flags;
> @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe,
> if (IS_ERR(lrc->bo))
> return PTR_ERR(lrc->bo);
>
> + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> + ttm_bo_type_kernel,
> + XE_BO_FLAG_GGTT |
> +
> XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_SYSTEM,
> false);
XE_BO_FLAG_PINNED_NORESTORE?
Thanks,
Thomas
> + if (IS_ERR(seqno_bo)) {
> + err = PTR_ERR(lrc->bo);
> + goto err_lrc_finish;
> + }
> + lrc->seqno_bo = seqno_bo;
> +
> xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> hwe->fence_irq, hwe->name);
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> b/drivers/gpu/drm/xe/xe_lrc_types.h
> index a4373d280c39..5a718f759ed6 100644
> --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> @@ -22,6 +22,12 @@ struct xe_lrc {
> */
> struct xe_bo *bo;
>
> + /**
> + * @seqno_bo: Buffer object (memory) for seqno numbers.
> Always in system
> + * memory as this a CPU read, GPU write path object.
> + */
> + struct xe_bo *seqno_bo;
> +
> /** @size: size of the lrc and optional indirect ring state
> */
> u32 size;
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
2026-02-24 2:40 ` Matthew Brost
2026-02-26 12:25 ` Thomas Hellström
@ 2026-02-26 12:43 ` Thomas Hellström
2026-02-26 16:55 ` Matthew Brost
2 siblings, 1 reply; 29+ messages in thread
From: Thomas Hellström @ 2026-02-26 12:43 UTC (permalink / raw)
To: Matthew Brost, intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> that read can turn into a PCIe transaction when the seqno lives in
> the
> main LRC BO, making the hot-path poll/peek much more expensive.
>
> Allocate a small dedicated seqno BO in system memory and map the
> seqno
> and start_seqno fields from there instead. The GPU still updates the
> values, but CPU reads stay in cached system memory and avoid PCIe
> read
> latency.
>
> Update the LRC map/address helpers to accept a BO expression and use
> the
> new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> teardown.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++----------
> --
> drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> 2 files changed, 42 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> b/drivers/gpu/drm/xe/xe_lrc.c
> index 38f648b98868..d72146313424 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> #define __xe_lrc_regs_offset xe_lrc_regs_offset
>
> -#define LRC_SEQNO_PPHWSP_OFFSET 512
> -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET
> + 8)
> +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> #define LRC_PARALLEL_PPHWSP_OFFSET 2048
>
> +#define LRC_SEQNO_OFFSET 0
> +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> +
> u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> {
> return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
>
> static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The seqno is stored in the driver-defined portion of
> PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> + return LRC_SEQNO_OFFSET;
> }
>
> static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> {
> - /* The start seqno is stored in the driver-defined portion
> of PPHWSP */
> - return xe_lrc_pphwsp_offset(lrc) +
> LRC_START_SEQNO_PPHWSP_OFFSET;
> + return LRC_START_SEQNO_OFFSET;
> }
>
> static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct
> xe_lrc *lrc)
> return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> }
>
> -#define DECL_MAP_ADDR_HELPERS(elem) \
> +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc
> *lrc) \
> { \
> - struct iosys_map map = lrc->bo->vmap; \
> + struct xe_bo *bo = (bo_expr); \
> + struct iosys_map map = bo->vmap; \
> \
> xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> @@ -816,20 +816,22 @@ static inline struct iosys_map
> __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> } \
> static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct
> xe_lrc *lrc) \
> { \
> - return xe_bo_ggtt_addr(lrc->bo) +
> __xe_lrc_##elem##_offset(lrc); \
> + struct xe_bo *bo = (bo_expr); \
> +\
> + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc);
> \
> } \
>
> -DECL_MAP_ADDR_HELPERS(ring)
> -DECL_MAP_ADDR_HELPERS(pphwsp)
> -DECL_MAP_ADDR_HELPERS(seqno)
> -DECL_MAP_ADDR_HELPERS(regs)
> -DECL_MAP_ADDR_HELPERS(start_seqno)
> -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> -DECL_MAP_ADDR_HELPERS(parallel)
> -DECL_MAP_ADDR_HELPERS(indirect_ring)
> -DECL_MAP_ADDR_HELPERS(engine_id)
> +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
>
> #undef DECL_MAP_ADDR_HELPERS
>
> @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> {
> xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> xe_bo_unpin_map_no_vm(lrc->bo);
> + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> }
>
> /*
> @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe,
> u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_device *xe = gt_to_xe(gt);
> + struct xe_bo *seqno_bo;
> struct iosys_map map;
> u32 arb_enable;
> u32 bo_flags;
> @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe,
> if (IS_ERR(lrc->bo))
> return PTR_ERR(lrc->bo);
>
> + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> + ttm_bo_type_kernel,
> + XE_BO_FLAG_GGTT |
> +
> XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_SYSTEM,
> false);
> + if (IS_ERR(seqno_bo)) {
> + err = PTR_ERR(lrc->bo);
Claude found the above. Should be PTR_ERR(seqno_bo).
/Thomas
> + goto err_lrc_finish;
> + }
> + lrc->seqno_bo = seqno_bo;
> +
> xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> hwe->fence_irq, hwe->name);
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> b/drivers/gpu/drm/xe/xe_lrc_types.h
> index a4373d280c39..5a718f759ed6 100644
> --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> @@ -22,6 +22,12 @@ struct xe_lrc {
> */
> struct xe_bo *bo;
>
> + /**
> + * @seqno_bo: Buffer object (memory) for seqno numbers.
> Always in system
> + * memory as this a CPU read, GPU write path object.
> + */
> + struct xe_bo *seqno_bo;
> +
> /** @size: size of the lrc and optional indirect ring state
> */
> u32 size;
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path
2026-02-18 4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
2026-02-18 23:20 ` Summers, Stuart
@ 2026-02-26 12:47 ` Thomas Hellström
1 sibling, 0 replies; 29+ messages in thread
From: Thomas Hellström @ 2026-02-26 12:47 UTC (permalink / raw)
To: Matthew Brost, intel-xe
Cc: stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> desc_read() issues an VRAM read which serializes the CPU and drains
> posted writes on dGPU platforms. The H2G tracepoint evaluated its
> arguments unconditionally, so even with tracing disabled the
> submission
> path paid the full VRAM readf latency. Guard the tracepoint with
s/readf/read/
> trace_xe_guc_ctb_h2g_enabled().
>
> Adso move the descriptor status verification under
s/Adso/Also/
> CONFIG_DRM_XE_DEBUG.
> This removes another unnecessary VRAM read in non-debug builfds.
s/builfds/builds/
>
> This results in ~10× faster H2G submission and significantly reduces
> lock contention across the driver.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ct.c | 25 ++++++++++++++++---------
> 1 file changed, 16 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index ea07a27757d5..37842c93e0ee 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
> u32 full_len;
> struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
> tail *
> sizeof(u32));
> - u32 desc_status;
>
> full_len = len + GUC_CTB_HDR_LEN;
>
> lockdep_assert_held(&ct->lock);
> xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
>
> - desc_status = desc_read(xe, h2g, status);
> - if (desc_status) {
> - xe_gt_err(gt, "CT write: non-zero status: %u\n",
> desc_status);
> - goto corrupted;
> - }
> -
> if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
> u32 desc_tail = desc_read(xe, h2g, tail);
> u32 desc_head = desc_read(xe, h2g, head);
> + u32 desc_status;
> +
> + desc_status = desc_read(xe, h2g, status);
> + if (desc_status) {
> + xe_gt_err(gt, "CT write: non-zero status:
> %u\n", desc_status);
> + goto corrupted;
> + }
>
> if (tail != desc_tail) {
> desc_write(xe, h2g, status, desc_status |
> GUC_CTB_STATUS_MISMATCH);
> @@ -1023,8 +1023,15 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
> /* Update descriptor */
> desc_write(xe, h2g, tail, h2g->info.tail);
>
> - trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> - desc_read(xe, h2g, head), h2g-
> >info.tail);
> + /*
> + * desc_read() performs an VRAM read which serializes the
> CPU and drains
> + * posted writes on dGPU platforms. Tracepoints evaluate
> arguments even
> + * when disabled, so guard the event to avoid adding µs-
> scale latency to
> + * the fast H2G submission path when tracing is not active.
> + */
> + if (trace_xe_guc_ctb_h2g_enabled())
> + trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> + desc_read(xe, h2g, head), h2g-
> >info.tail);
>
> return 0;
>
With the typos fixed,
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-26 12:43 ` Thomas Hellström
@ 2026-02-26 16:55 ` Matthew Brost
0 siblings, 0 replies; 29+ messages in thread
From: Matthew Brost @ 2026-02-26 16:55 UTC (permalink / raw)
To: Thomas Hellström
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Thu, Feb 26, 2026 at 01:43:43PM +0100, Thomas Hellström wrote:
> On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> > that read can turn into a PCIe transaction when the seqno lives in
> > the
> > main LRC BO, making the hot-path poll/peek much more expensive.
> >
> > Allocate a small dedicated seqno BO in system memory and map the
> > seqno
> > and start_seqno fields from there instead. The GPU still updates the
> > values, but CPU reads stay in cached system memory and avoid PCIe
> > read
> > latency.
> >
> > Update the LRC map/address helpers to accept a BO expression and use
> > the
> > new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> > teardown.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++----------
> > --
> > drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> > 2 files changed, 42 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> > b/drivers/gpu/drm/xe/xe_lrc.c
> > index 38f648b98868..d72146313424 100644
> > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> > #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> > #define __xe_lrc_regs_offset xe_lrc_regs_offset
> >
> > -#define LRC_SEQNO_PPHWSP_OFFSET 512
> > -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> > -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET
> > + 8)
> > +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> > #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> > #define LRC_PARALLEL_PPHWSP_OFFSET 2048
> >
> > +#define LRC_SEQNO_OFFSET 0
> > +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> > +
> > u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> > {
> > return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> > @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
> >
> > static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> > {
> > - /* The seqno is stored in the driver-defined portion of
> > PPHWSP */
> > - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> > + return LRC_SEQNO_OFFSET;
> > }
> >
> > static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> > {
> > - /* The start seqno is stored in the driver-defined portion
> > of PPHWSP */
> > - return xe_lrc_pphwsp_offset(lrc) +
> > LRC_START_SEQNO_PPHWSP_OFFSET;
> > + return LRC_START_SEQNO_OFFSET;
> > }
> >
> > static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> > @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct
> > xe_lrc *lrc)
> > return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> > }
> >
> > -#define DECL_MAP_ADDR_HELPERS(elem) \
> > +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> > static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc
> > *lrc) \
> > { \
> > - struct iosys_map map = lrc->bo->vmap; \
> > + struct xe_bo *bo = (bo_expr); \
> > + struct iosys_map map = bo->vmap; \
> > \
> > xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> > iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> > @@ -816,20 +816,22 @@ static inline struct iosys_map
> > __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> > } \
> > static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct
> > xe_lrc *lrc) \
> > { \
> > - return xe_bo_ggtt_addr(lrc->bo) +
> > __xe_lrc_##elem##_offset(lrc); \
> > + struct xe_bo *bo = (bo_expr); \
> > +\
> > + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc);
> > \
> > } \
> >
> > -DECL_MAP_ADDR_HELPERS(ring)
> > -DECL_MAP_ADDR_HELPERS(pphwsp)
> > -DECL_MAP_ADDR_HELPERS(seqno)
> > -DECL_MAP_ADDR_HELPERS(regs)
> > -DECL_MAP_ADDR_HELPERS(start_seqno)
> > -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> > -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> > -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> > -DECL_MAP_ADDR_HELPERS(parallel)
> > -DECL_MAP_ADDR_HELPERS(indirect_ring)
> > -DECL_MAP_ADDR_HELPERS(engine_id)
> > +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> > +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
> >
> > #undef DECL_MAP_ADDR_HELPERS
> >
> > @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> > {
> > xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> > xe_bo_unpin_map_no_vm(lrc->bo);
> > + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> > }
> >
> > /*
> > @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > struct xe_hw_engine *hwe,
> > u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> > struct xe_tile *tile = gt_to_tile(gt);
> > struct xe_device *xe = gt_to_xe(gt);
> > + struct xe_bo *seqno_bo;
> > struct iosys_map map;
> > u32 arb_enable;
> > u32 bo_flags;
> > @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > struct xe_hw_engine *hwe,
> > if (IS_ERR(lrc->bo))
> > return PTR_ERR(lrc->bo);
> >
> > + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> > + ttm_bo_type_kernel,
> > + XE_BO_FLAG_GGTT |
> > +
> > XE_BO_FLAG_GGTT_INVALIDATE |
> > + XE_BO_FLAG_SYSTEM,
> > false);
> > + if (IS_ERR(seqno_bo)) {
> > + err = PTR_ERR(lrc->bo);
>
> Claude found the above. Should be PTR_ERR(seqno_bo).
>
Nice. I should take the time to set this up locally to save everyone
time.
Will fix.
Matt
> /Thomas
>
>
> > + goto err_lrc_finish;
> > + }
> > + lrc->seqno_bo = seqno_bo;
> > +
> > xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> > hwe->fence_irq, hwe->name);
> >
> > diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> > b/drivers/gpu/drm/xe/xe_lrc_types.h
> > index a4373d280c39..5a718f759ed6 100644
> > --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> > +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> > @@ -22,6 +22,12 @@ struct xe_lrc {
> > */
> > struct xe_bo *bo;
> >
> > + /**
> > + * @seqno_bo: Buffer object (memory) for seqno numbers.
> > Always in system
> > + * memory as this a CPU read, GPU write path object.
> > + */
> > + struct xe_bo *seqno_bo;
> > +
> > /** @size: size of the lrc and optional indirect ring state
> > */
> > u32 size;
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-26 12:25 ` Thomas Hellström
@ 2026-02-26 17:11 ` Matthew Brost
2026-02-26 17:26 ` Matthew Brost
0 siblings, 1 reply; 29+ messages in thread
From: Matthew Brost @ 2026-02-26 17:11 UTC (permalink / raw)
To: Thomas Hellström
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Thu, Feb 26, 2026 at 01:25:19PM +0100, Thomas Hellström wrote:
> On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> > that read can turn into a PCIe transaction when the seqno lives in
> > the
> > main LRC BO, making the hot-path poll/peek much more expensive.
> >
> > Allocate a small dedicated seqno BO in system memory and map the
> > seqno
> > and start_seqno fields from there instead. The GPU still updates the
> > values, but CPU reads stay in cached system memory and avoid PCIe
> > read
> > latency.
> >
> > Update the LRC map/address helpers to accept a BO expression and use
> > the
> > new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> > teardown.
>
> I remember this was discussed also when enabling discrete for the i915
> driver but we didn't have any timing information at that time.
>
> Whether this is a good thing depends on the amount of cpu polling per
> seqno bump, but I figure that's typically always at least one CPU read,
> right?
We store every pending fence in each engine class in a linked list, and
on every hardware IRQ we walk all pending fences to check whether they
have signaled (one hardware seqno read).
We do this because with virtual engines we don’t know which hardware
engine instance each submission will run on, and the GuC is free to
reorder anything. Thus, we can’t rely on a HOQ check to short-circuit
this or look at individual hardware engine instance. Perhaps we could
make the logic slightly more advanced to short-circuit redundant checks
on the same context, but let’s put that aside for now.
In bad cases, there may be quite a few fences we need to iterate over on
every IRQ. If hardware fences are in VRAM, this can add up quickly.
I arrived at the 1.5µs improvement in fence signaling by running
xe_exec_system_allocator plus a script that parses GT stats and outputs
the average time spent in xe_svm_copy—comparing the patched and
unpatched versions across 10 runs. Each run does roughly 2k copies and
provides very reliable data; I’ve been using this method for a number of
SVM optimizations I’ve been working on. I believe I also had
clear-on-free enabled in this branch, so in this case exactly one
hardware fence should have been in the linked list per IRQ.
I would think this is always a good thing given the disparity in read
speeds between SRAM and VRAM.
Matt
>
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++----------
> > --
> > drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> > 2 files changed, 42 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> > b/drivers/gpu/drm/xe/xe_lrc.c
> > index 38f648b98868..d72146313424 100644
> > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> > #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> > #define __xe_lrc_regs_offset xe_lrc_regs_offset
> >
> > -#define LRC_SEQNO_PPHWSP_OFFSET 512
> > -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> > -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET
> > + 8)
> > +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> > #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> > #define LRC_PARALLEL_PPHWSP_OFFSET 2048
> >
> > +#define LRC_SEQNO_OFFSET 0
> > +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> > +
> > u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> > {
> > return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> > @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
> >
> > static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> > {
> > - /* The seqno is stored in the driver-defined portion of
> > PPHWSP */
> > - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> > + return LRC_SEQNO_OFFSET;
> > }
> >
> > static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> > {
> > - /* The start seqno is stored in the driver-defined portion
> > of PPHWSP */
> > - return xe_lrc_pphwsp_offset(lrc) +
> > LRC_START_SEQNO_PPHWSP_OFFSET;
> > + return LRC_START_SEQNO_OFFSET;
> > }
> >
> > static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> > @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct
> > xe_lrc *lrc)
> > return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> > }
> >
> > -#define DECL_MAP_ADDR_HELPERS(elem) \
> > +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> > static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc
> > *lrc) \
> > { \
> > - struct iosys_map map = lrc->bo->vmap; \
> > + struct xe_bo *bo = (bo_expr); \
> > + struct iosys_map map = bo->vmap; \
> > \
> > xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> > iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> > @@ -816,20 +816,22 @@ static inline struct iosys_map
> > __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> > } \
> > static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct
> > xe_lrc *lrc) \
> > { \
> > - return xe_bo_ggtt_addr(lrc->bo) +
> > __xe_lrc_##elem##_offset(lrc); \
> > + struct xe_bo *bo = (bo_expr); \
> > +\
> > + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc);
> > \
> > } \
> >
> > -DECL_MAP_ADDR_HELPERS(ring)
> > -DECL_MAP_ADDR_HELPERS(pphwsp)
> > -DECL_MAP_ADDR_HELPERS(seqno)
> > -DECL_MAP_ADDR_HELPERS(regs)
> > -DECL_MAP_ADDR_HELPERS(start_seqno)
> > -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> > -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> > -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> > -DECL_MAP_ADDR_HELPERS(parallel)
> > -DECL_MAP_ADDR_HELPERS(indirect_ring)
> > -DECL_MAP_ADDR_HELPERS(engine_id)
> > +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> > +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> > +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
> >
> > #undef DECL_MAP_ADDR_HELPERS
> >
> > @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> > {
> > xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> > xe_bo_unpin_map_no_vm(lrc->bo);
> > + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> > }
> >
> > /*
> > @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > struct xe_hw_engine *hwe,
> > u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> > struct xe_tile *tile = gt_to_tile(gt);
> > struct xe_device *xe = gt_to_xe(gt);
> > + struct xe_bo *seqno_bo;
> > struct iosys_map map;
> > u32 arb_enable;
> > u32 bo_flags;
> > @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > struct xe_hw_engine *hwe,
> > if (IS_ERR(lrc->bo))
> > return PTR_ERR(lrc->bo);
> >
> > + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> > + ttm_bo_type_kernel,
> > + XE_BO_FLAG_GGTT |
> > +
> > XE_BO_FLAG_GGTT_INVALIDATE |
> > + XE_BO_FLAG_SYSTEM,
> > false);
>
> XE_BO_FLAG_PINNED_NORESTORE?
>
> Thanks,
> Thomas
>
>
> > + if (IS_ERR(seqno_bo)) {
> > + err = PTR_ERR(lrc->bo);
> > + goto err_lrc_finish;
> > + }
> > + lrc->seqno_bo = seqno_bo;
> > +
> > xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> > hwe->fence_irq, hwe->name);
> >
> > diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> > b/drivers/gpu/drm/xe/xe_lrc_types.h
> > index a4373d280c39..5a718f759ed6 100644
> > --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> > +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> > @@ -22,6 +22,12 @@ struct xe_lrc {
> > */
> > struct xe_bo *bo;
> >
> > + /**
> > + * @seqno_bo: Buffer object (memory) for seqno numbers.
> > Always in system
> > + * memory as this a CPU read, GPU write path object.
> > + */
> > + struct xe_bo *seqno_bo;
> > +
> > /** @size: size of the lrc and optional indirect ring state
> > */
> > u32 size;
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-26 17:11 ` Matthew Brost
@ 2026-02-26 17:26 ` Matthew Brost
2026-02-26 17:56 ` Thomas Hellström
0 siblings, 1 reply; 29+ messages in thread
From: Matthew Brost @ 2026-02-26 17:26 UTC (permalink / raw)
To: Thomas Hellström
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Thu, Feb 26, 2026 at 09:11:20AM -0800, Matthew Brost wrote:
Missed a comment.
> On Thu, Feb 26, 2026 at 01:25:19PM +0100, Thomas Hellström wrote:
> > On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> > > The LRC seqno is read by the CPU in the fence signaling path. On dGPU
> > > that read can turn into a PCIe transaction when the seqno lives in
> > > the
> > > main LRC BO, making the hot-path poll/peek much more expensive.
> > >
> > > Allocate a small dedicated seqno BO in system memory and map the
> > > seqno
> > > and start_seqno fields from there instead. The GPU still updates the
> > > values, but CPU reads stay in cached system memory and avoid PCIe
> > > read
> > > latency.
> > >
> > > Update the LRC map/address helpers to accept a BO expression and use
> > > the
> > > new lrc->seqno_bo for seqno mappings. Unpin/unmap seqno_bo during
> > > teardown.
> >
> > I remember this was discussed also when enabling discrete for the i915
> > driver but we didn't have any timing information at that time.
> >
> > Whether this is a good thing depends on the amount of cpu polling per
> > seqno bump, but I figure that's typically always at least one CPU read,
> > right?
>
> We store every pending fence in each engine class in a linked list, and
> on every hardware IRQ we walk all pending fences to check whether they
> have signaled (one hardware seqno read).
>
> We do this because with virtual engines we don’t know which hardware
> engine instance each submission will run on, and the GuC is free to
> reorder anything. Thus, we can’t rely on a HOQ check to short-circuit
> this or look at individual hardware engine instance. Perhaps we could
> make the logic slightly more advanced to short-circuit redundant checks
> on the same context, but let’s put that aside for now.
>
> In bad cases, there may be quite a few fences we need to iterate over on
> every IRQ. If hardware fences are in VRAM, this can add up quickly.
>
> I arrived at the 1.5µs improvement in fence signaling by running
> xe_exec_system_allocator plus a script that parses GT stats and outputs
> the average time spent in xe_svm_copy—comparing the patched and
> unpatched versions across 10 runs. Each run does roughly 2k copies and
> provides very reliable data; I’ve been using this method for a number of
> SVM optimizations I’ve been working on. I believe I also had
> clear-on-free enabled in this branch, so in this case exactly one
> hardware fence should have been in the linked list per IRQ.
>
> I would think this is always a good thing given the disparity in read
> speeds between SRAM and VRAM.
>
> Matt
>
> >
> > >
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_lrc.c | 57 +++++++++++++++++++----------
> > > --
> > > drivers/gpu/drm/xe/xe_lrc_types.h | 6 ++++
> > > 2 files changed, 42 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> > > b/drivers/gpu/drm/xe/xe_lrc.c
> > > index 38f648b98868..d72146313424 100644
> > > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > > @@ -715,12 +715,13 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> > > #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset
> > > #define __xe_lrc_regs_offset xe_lrc_regs_offset
> > >
> > > -#define LRC_SEQNO_PPHWSP_OFFSET 512
> > > -#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> > > -#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET
> > > + 8)
> > > +#define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
> > > #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> > > #define LRC_PARALLEL_PPHWSP_OFFSET 2048
> > >
> > > +#define LRC_SEQNO_OFFSET 0
> > > +#define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> > > +
> > > u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> > > {
> > > return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;
> > > @@ -747,14 +748,12 @@ size_t xe_lrc_skip_size(struct xe_device *xe)
> > >
> > > static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)
> > > {
> > > - /* The seqno is stored in the driver-defined portion of
> > > PPHWSP */
> > > - return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;
> > > + return LRC_SEQNO_OFFSET;
> > > }
> > >
> > > static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
> > > {
> > > - /* The start seqno is stored in the driver-defined portion
> > > of PPHWSP */
> > > - return xe_lrc_pphwsp_offset(lrc) +
> > > LRC_START_SEQNO_PPHWSP_OFFSET;
> > > + return LRC_START_SEQNO_OFFSET;
> > > }
> > >
> > > static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
> > > @@ -805,10 +804,11 @@ static inline u32 __xe_lrc_wa_bb_offset(struct
> > > xe_lrc *lrc)
> > > return xe_bo_size(lrc->bo) - LRC_WA_BB_SIZE;
> > > }
> > >
> > > -#define DECL_MAP_ADDR_HELPERS(elem) \
> > > +#define DECL_MAP_ADDR_HELPERS(elem, bo_expr) \
> > > static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc
> > > *lrc) \
> > > { \
> > > - struct iosys_map map = lrc->bo->vmap; \
> > > + struct xe_bo *bo = (bo_expr); \
> > > + struct iosys_map map = bo->vmap; \
> > > \
> > > xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \
> > > iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \
> > > @@ -816,20 +816,22 @@ static inline struct iosys_map
> > > __xe_lrc_##elem##_map(struct xe_lrc *lrc) \
> > > } \
> > > static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct
> > > xe_lrc *lrc) \
> > > { \
> > > - return xe_bo_ggtt_addr(lrc->bo) +
> > > __xe_lrc_##elem##_offset(lrc); \
> > > + struct xe_bo *bo = (bo_expr); \
> > > +\
> > > + return xe_bo_ggtt_addr(bo) + __xe_lrc_##elem##_offset(lrc);
> > > \
> > > } \
> > >
> > > -DECL_MAP_ADDR_HELPERS(ring)
> > > -DECL_MAP_ADDR_HELPERS(pphwsp)
> > > -DECL_MAP_ADDR_HELPERS(seqno)
> > > -DECL_MAP_ADDR_HELPERS(regs)
> > > -DECL_MAP_ADDR_HELPERS(start_seqno)
> > > -DECL_MAP_ADDR_HELPERS(ctx_job_timestamp)
> > > -DECL_MAP_ADDR_HELPERS(ctx_timestamp)
> > > -DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw)
> > > -DECL_MAP_ADDR_HELPERS(parallel)
> > > -DECL_MAP_ADDR_HELPERS(indirect_ring)
> > > -DECL_MAP_ADDR_HELPERS(engine_id)
> > > +DECL_MAP_ADDR_HELPERS(ring, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(pphwsp, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(seqno, lrc->seqno_bo)
> > > +DECL_MAP_ADDR_HELPERS(regs, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(start_seqno, lrc->seqno_bo)
> > > +DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
> > > +DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
> > >
> > > #undef DECL_MAP_ADDR_HELPERS
> > >
> > > @@ -1036,6 +1038,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
> > > {
> > > xe_hw_fence_ctx_finish(&lrc->fence_ctx);
> > > xe_bo_unpin_map_no_vm(lrc->bo);
> > > + xe_bo_unpin_map_no_vm(lrc->seqno_bo);
> > > }
> > >
> > > /*
> > > @@ -1445,6 +1448,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > > struct xe_hw_engine *hwe,
> > > u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE;
> > > struct xe_tile *tile = gt_to_tile(gt);
> > > struct xe_device *xe = gt_to_xe(gt);
> > > + struct xe_bo *seqno_bo;
> > > struct iosys_map map;
> > > u32 arb_enable;
> > > u32 bo_flags;
> > > @@ -1479,6 +1483,17 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> > > struct xe_hw_engine *hwe,
> > > if (IS_ERR(lrc->bo))
> > > return PTR_ERR(lrc->bo);
> > >
> > > + seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,
> > > + ttm_bo_type_kernel,
> > > + XE_BO_FLAG_GGTT |
> > > +
> > > XE_BO_FLAG_GGTT_INVALIDATE |
> > > + XE_BO_FLAG_SYSTEM,
> > > false);
> >
> > XE_BO_FLAG_PINNED_NORESTORE?
> >
Maybe (?), but this seems dangerous… Can’t fences be pending during
hibernate? We also check whether a job has started (by looking at the
start seqno) in the TDR, and if the seqno is in VRAM, nonsensical reads
could confuse those checks. Also consider the case where the fence seqno
is clobbered—we could end up with values in memory that indicate the
next job we run is already signaled.
So after typing this out, I actually think the answer is no to this
flag.
Matt
> > Thanks,
> > Thomas
> >
> >
> > > + if (IS_ERR(seqno_bo)) {
> > > + err = PTR_ERR(lrc->bo);
> > > + goto err_lrc_finish;
> > > + }
> > > + lrc->seqno_bo = seqno_bo;
> > > +
> > > xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> > > hwe->fence_irq, hwe->name);
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> > > b/drivers/gpu/drm/xe/xe_lrc_types.h
> > > index a4373d280c39..5a718f759ed6 100644
> > > --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> > > @@ -22,6 +22,12 @@ struct xe_lrc {
> > > */
> > > struct xe_bo *bo;
> > >
> > > + /**
> > > + * @seqno_bo: Buffer object (memory) for seqno numbers.
> > > Always in system
> > > + * memory as this a CPU read, GPU write path object.
> > > + */
> > > + struct xe_bo *seqno_bo;
> > > +
> > > /** @size: size of the lrc and optional indirect ring state
> > > */
> > > u32 size;
> > >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads
2026-02-26 17:26 ` Matthew Brost
@ 2026-02-26 17:56 ` Thomas Hellström
0 siblings, 0 replies; 29+ messages in thread
From: Thomas Hellström @ 2026-02-26 17:56 UTC (permalink / raw)
To: Matthew Brost
Cc: intel-xe, stuart.summers, francois.dugast, daniele.ceraolospurio,
michal.wajdeczko
On Thu, 2026-02-26 at 09:26 -0800, Matthew Brost wrote:
> On Thu, Feb 26, 2026 at 09:11:20AM -0800, Matthew Brost wrote:
>
> Missed a comment.
>
> >
8<------------------------
> > > > struct xe_hw_engine *hwe,
> > > > if (IS_ERR(lrc->bo))
> > > > return PTR_ERR(lrc->bo);
> > > >
> > > > + seqno_bo = xe_bo_create_pin_map_novm(xe, tile,
> > > > PAGE_SIZE,
> > > > +
> > > > ttm_bo_type_kernel,
> > > > + XE_BO_FLAG_GGTT |
> > > > +
> > > > XE_BO_FLAG_GGTT_INVALIDATE |
> > > > +
> > > > XE_BO_FLAG_SYSTEM,
> > > > false);
> > >
> > > XE_BO_FLAG_PINNED_NORESTORE?
> > >
>
> Maybe (?), but this seems dangerous… Can’t fences be pending during
> hibernate? We also check whether a job has started (by looking at the
> start seqno) in the TDR, and if the seqno is in VRAM, nonsensical
> reads
> could confuse those checks. Also consider the case where the fence
> seqno
> is clobbered—we could end up with values in memory that indicate the
> next job we run is already signaled.
>
> So after typing this out, I actually think the answer is no to this
> flag.
>
> Matt
OK, I wasn't sure exactly what happens on suspend / resume with LR
jobs. The !LR jobs are idled AFAIR.
We have an issure registered somewhere with LR Jobs WRT Suspend /
Resume, since if we change the spinner to preemptible in
xe_exec_compute_mode@lr-mode-workload and suspend while it's running it
doesn't complete on resume, even if the VM gets properly preempted
during the VRAM eviction.
But that's ofc beyond this patch.
With the IS_ERR() fix,
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>
> > > Thanks,
> > > Thomas
> > >
> > >
> > > > + if (IS_ERR(seqno_bo)) {
> > > > + err = PTR_ERR(lrc->bo);
> > > > + goto err_lrc_finish;
> > > > + }
> > > > + lrc->seqno_bo = seqno_bo;
> > > > +
> > > > xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> > > > hwe->fence_irq, hwe->name);
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h
> > > > b/drivers/gpu/drm/xe/xe_lrc_types.h
> > > > index a4373d280c39..5a718f759ed6 100644
> > > > --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> > > > @@ -22,6 +22,12 @@ struct xe_lrc {
> > > > */
> > > > struct xe_bo *bo;
> > > >
> > > > + /**
> > > > + * @seqno_bo: Buffer object (memory) for seqno
> > > > numbers.
> > > > Always in system
> > > > + * memory as this a CPU read, GPU write path object.
> > > > + */
> > > > + struct xe_bo *seqno_bo;
> > > > +
> > > > /** @size: size of the lrc and optional indirect ring
> > > > state
> > > > */
> > > > u32 size;
> > > >
^ permalink raw reply [flat|nested] 29+ messages in thread
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2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-18 23:12 ` Summers, Stuart
2026-02-19 3:46 ` Matthew Brost
2026-02-24 15:58 ` Thomas Hellström
2026-02-24 16:12 ` Matthew Brost
2026-02-25 10:55 ` Thomas Hellström
2026-02-25 18:08 ` Matthew Brost
2026-02-26 12:08 ` Thomas Hellström
2026-02-18 4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
2026-02-18 23:20 ` Summers, Stuart
2026-02-26 12:47 ` Thomas Hellström
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
2026-02-24 2:40 ` Matthew Brost
2026-02-26 12:25 ` Thomas Hellström
2026-02-26 17:11 ` Matthew Brost
2026-02-26 17:26 ` Matthew Brost
2026-02-26 17:56 ` Thomas Hellström
2026-02-26 12:43 ` Thomas Hellström
2026-02-26 16:55 ` Matthew Brost
2026-02-18 4:40 ` ✓ CI.KUnit: success for dGPU memory optimizations Patchwork
2026-02-18 5:23 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-18 6:15 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-18 7:07 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev2) Patchwork
2026-02-18 7:36 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 7:53 ` ✓ Xe.CI.FULL: " Patchwork
2026-02-18 12:29 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev3) Patchwork
2026-02-18 13:09 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 14:08 ` ✗ Xe.CI.FULL: failure " Patchwork
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