[PATCH v6 0/9] Enable CMRR in fixed-RR VRR path

[PATCH v6 0/9] Enable CMRR in fixed-RR VRR path

[Mitul Golani]

The existing CMRR fractional-timing code was permanently
disabled (if (!HAS_CMRR || true)), eDP-only, and relied
on a heuristic to guess when the fractional path was needed.
This series reworks it into a generic, debugfs-driven feature,
which later will be controlled via userspace when respective
uapi will be in-palce.

Mitul Golani (9):
  drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled
  drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default
    platforms
  drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control
  drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config
    request
  drm/i915/display: Move CMRR crtc_state members under VRR
  drm/i915/vrr: Compute CMRR fractional timings generically
  drm/i915/vrr: Dump CMRR state in the crtc state dump
  drm/i915/vrr: Program CMRR enable/disable from transcoder timings
  drm/i915/vrr: Enable cmrr

 drivers/gpu/drm/i915/display/intel_cmtg.c     |   2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |   3 +
 drivers/gpu/drm/i915/display/intel_display.c  |  10 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   9 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 316 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 9 files changed, 270 insertions(+), 97 deletions(-)

-- 
2.48.1

[PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled

[Mitul Golani]

CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is
enabled.

--v2:
- Restrict selective update config check (Ankit)
- Commit message change

--v3:
- Commit changes

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 40e3d7095996..6a90ded5d1fa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1587,6 +1587,12 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 
+	if (crtc_state->cmrr.enable) {
+		drm_dbg_kms(display->drm,
+			    "Selective update cannot be enabled when CMRR is enabled\n");
+		goto unsupported;
+	}
+
 	if (HAS_PSR2_SEL_FETCH(display) &&
 	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 	    !HAS_PSR_HW_TRACKING(display)) {
-- 
2.48.1

Re: [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is
> enabled.
> 
> --v2:
> - Restrict selective update config check (Ankit)
> - Commit message change
> 
> --v3:
> - Commit changes
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 40e3d7095996..6a90ded5d1fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1587,6 +1587,12 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>   	struct intel_dp *intel_dp = intel_attached_dp(connector);
>   	struct intel_display *display = to_intel_display(intel_dp);
>   
> +	if (crtc_state->cmrr.enable) {
> +		drm_dbg_kms(display->drm,
> +			    "Selective update cannot be enabled when CMRR is enabled\n");
> +		goto unsupported;
> +	}

This also disables panel replay, please make sure that this is desired. 
If so, add it in commit message.

> +
>   	if (HAS_PSR2_SEL_FETCH(display) &&
>   	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
>   	    !HAS_PSR_HW_TRACKING(display)) {

RE: [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 23 July 2026 21:45
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in
> case of CMRR enabled
> 
> 
> 
> On 7/22/2026 10:09 AM, Mitul Golani wrote:
> > CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is
> > enabled.
> >
> > --v2:
> > - Restrict selective update config check (Ankit)
> > - Commit message change
> >
> > --v3:
> > - Commit changes
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 40e3d7095996..6a90ded5d1fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1587,6 +1587,12 @@ static bool intel_sel_update_config_valid(struct
> intel_crtc_state *crtc_state,
> >   	struct intel_dp *intel_dp = intel_attached_dp(connector);
> >   	struct intel_display *display = to_intel_display(intel_dp);
> >
> > +	if (crtc_state->cmrr.enable) {
> > +		drm_dbg_kms(display->drm,
> > +			    "Selective update cannot be enabled when CMRR is
> enabled\n");
> > +		goto unsupported;
> > +	}
> 
> This also disables panel replay, please make sure that this is desired.
> If so, add it in commit message.

Thanks for the review,

The check is placed in intel_sel_update_config_valid(), whose return value only feeds has_sel_update. has_panel_replay is computed independently beforehand, so Panel Replay is not disabled, only Selective Update (PSR2 and Panel Replay Selective Update) is. 

*  has_psr (alone):					PSR1
 *  has_psr + has_sel_update:				PSR2
 *  has_psr + has_panel_replay:				Panel Replay
 *  has_psr + has_panel_replay + has_sel_update:	Panel Replay Selective Update


Per the mode table in intel_psr.c at start, disabling has_sel_update when CMRR is enabled turns off case 2 (PSR2) and case 4 (Panel Replay SU), while PSR1 and Panel Replay remain functional. This is the desired behaviour since CMRR is incompatible with selective update.

Although this is explicitly called out as part of code comment at start of this file.

Regards,
Mitul

> 
> > +
> >   	if (HAS_PSR2_SEL_FETCH(display) &&
> >   	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> >   	    !HAS_PSR_HW_TRACKING(display)) {

Re: [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled

[Borah, Chaitanya Kumar]

On 7/24/2026 3:52 PM, Golani, Mitulkumar Ajitkumar wrote:
> 
> 
>> -----Original Message-----
>> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
>> Sent: 23 July 2026 21:45
>> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Subject: Re: [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in
>> case of CMRR enabled
>>
>>
>>
>> On 7/22/2026 10:09 AM, Mitul Golani wrote:
>>> CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is
>>> enabled.
>>>
>>> --v2:
>>> - Restrict selective update config check (Ankit)
>>> - Commit message change
>>>
>>> --v3:
>>> - Commit changes
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 40e3d7095996..6a90ded5d1fa 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -1587,6 +1587,12 @@ static bool intel_sel_update_config_valid(struct
>> intel_crtc_state *crtc_state,
>>>    	struct intel_dp *intel_dp = intel_attached_dp(connector);
>>>    	struct intel_display *display = to_intel_display(intel_dp);
>>>
>>> +	if (crtc_state->cmrr.enable) {
>>> +		drm_dbg_kms(display->drm,
>>> +			    "Selective update cannot be enabled when CMRR is
>> enabled\n");
>>> +		goto unsupported;
>>> +	}
>>
>> This also disables panel replay, please make sure that this is desired.
>> If so, add it in commit message.
> 
> Thanks for the review,
> 
> The check is placed in intel_sel_update_config_valid(), whose return value only feeds has_sel_update. has_panel_replay is computed independently beforehand, so Panel Replay is not disabled, only Selective Update (PSR2 and Panel Replay Selective Update) is.
> 
> *  has_psr (alone):					PSR1
>   *  has_psr + has_sel_update:				PSR2
>   *  has_psr + has_panel_replay:				Panel Replay
>   *  has_psr + has_panel_replay + has_sel_update:	Panel Replay Selective Update
> 
> 
> Per the mode table in intel_psr.c at start, disabling has_sel_update when CMRR is enabled turns off case 2 (PSR2) and case 4 (Panel Replay SU), while PSR1 and Panel Replay remain functional.
> This is the desired behaviour since CMRR is incompatible with selective update.

Are we sure?

Bspec only ever calls out PSR2 as incompatible. It never calls out 
selective update.

> 
> Although this is explicitly called out as part of code comment at start of this file.
> 
> Regards,
> Mitul
> 
>>
>>> +
>>>    	if (HAS_PSR2_SEL_FETCH(display) &&
>>>    	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
>>>    	    !HAS_PSR_HW_TRACKING(display)) {
> 

[PATCH v6 2/9] drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default platforms

[Mitul Golani]

CMRR is reported as supported from DISPLAY_VER >= 20 (HAS_CMRR), but it
is built on top of the VRR timing generator running as the default
timing generator, for now this only happens from DISPLAY_VER >= 30.
Gate the CMRR enable condition (and its readout) on both,
so CMRR is only ever enabled on platforms where the VRR timing
generator is the default.

This is a preparation patch for the upcoming CMRR enable sequence: CMRR
remains disabled for now (the "avoid CMRR" short-circuit above is kept),
and this only refines the condition so that when the enable sequence
lands, CMRR is correctly restricted to VRR-TG-default platforms. This is
in line with the comment above, which keeps CMRR disabled until VRR with
fixed timings is working.

No functional change.

--v2:
- Create a separate function to check if CMRR possible

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..14f8ac07c911 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -187,15 +187,21 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
+static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));
+}
+
 static bool
 is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!HAS_CMRR(display) || true)
+	if (!intel_vrr_cmrr_possible(crtc_state) || true)
 		return false;
 
 	actual_refresh_k =
@@ -1066,7 +1072,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	if (HAS_CMRR(display))
+	if (intel_vrr_cmrr_possible(crtc_state))
 		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
 	if (crtc_state->cmrr.enable) {
-- 
2.48.1

Re: [PATCH v6 2/9] drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default platforms

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> CMRR is reported as supported from DISPLAY_VER >= 20 (HAS_CMRR), but it
> is built on top of the VRR timing generator running as the default
> timing generator, for now this only happens from DISPLAY_VER >= 30.
> Gate the CMRR enable condition (and its readout) on both,
> so CMRR is only ever enabled on platforms where the VRR timing
> generator is the default.
> 
> This is a preparation patch for the upcoming CMRR enable sequence: CMRR
> remains disabled for now (the "avoid CMRR" short-circuit above is kept),
> and this only refines the condition so that when the enable sequence
> lands, CMRR is correctly restricted to VRR-TG-default platforms. This is
> in line with the comment above, which keeps CMRR disabled until VRR with
> fixed timings is working.
> 
> No functional change.

nit: commit message is quite of obfuscated, can be simpler.

> 
> --v2:
> - Create a separate function to check if CMRR possible
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>   1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..14f8ac07c911 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -187,15 +187,21 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>   }
>   
> +static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));

redundant outer parenthesis.

With these,

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> +}
> +
>   static bool
>   is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
>   {
> -	struct intel_display *display = to_intel_display(crtc_state);
>   	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>   
>   	/* Avoid CMRR for now till we have VRR with fixed timings working */
> -	if (!HAS_CMRR(display) || true)
> +	if (!intel_vrr_cmrr_possible(crtc_state) || true)
>   		return false;
>   
>   	actual_refresh_k =
> @@ -1066,7 +1072,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   	trans_vrr_ctl = intel_de_read(display,
>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>   
> -	if (HAS_CMRR(display))
> +	if (intel_vrr_cmrr_possible(crtc_state))
>   		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>   
>   	if (crtc_state->cmrr.enable) {

[PATCH v6 3/9] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Mitul Golani]

Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
CMRR target refresh rate and video-mode requirement.

The file uses a "numerator/denominator" format:
  - numerator:   requested refresh rate in milli-Hz
                 (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
  - denominator: 1000 for a 1:1 ratio (no video timing) or
                 1001 for the 1000/1001 video timing

Reading the file reports the currently stored values; writing updates
them. The file is created only on platforms with VRR and CMRR support.

--v2:
- Drop the "vrr" debugfs subdirectory and expose a single flat,
  intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
- Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
  explicit (Chaitanya)
- Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
- Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
- Expand commit message with debugfs entry semantics (Chaitanya)

--v3:
- Rename debugfs function and file name (Chaitanya)
- Remove railing new line at EOF (Chaitanya)
- Update CMRR guard conditions (Chaitanya)
- Add 0/0 default case. (Ramanaidu)

--v4:
- Correct CMRR guard check while creating debugfs

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 108 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 4 files changed, 117 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3f02868ef105..2bbf4760dc30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -49,6 +49,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "intel_tc.h"
 
@@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
 	intel_drrs_crtc_debugfs_add(crtc);
 	intel_fbc_crtc_debugfs_add(crtc);
 	hsw_ips_crtc_debugfs_add(crtc);
+	intel_vrr_crtc_debugfs_add(crtc);
 
 	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
 			    &i915_current_bpc_fops);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..46dd980b315a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1553,6 +1553,11 @@ struct intel_crtc {
 		u64 flip_count;
 	} dc_balance;
 
+	struct {
+		u32 numerator;
+		u32 denominator;
+	} force_cmrr;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 14f8ac07c911..267c65d9245f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -4,6 +4,10 @@
  *
  */
 
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+
 #include <drm/drm_print.h>
 #include <drm/intel/step.h>
 
@@ -1237,3 +1241,107 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
 
 	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
 }
+
+static
+int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
+{
+	char *sep;
+	int ret;
+
+	/*
+	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
+	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
+	 * and the denominator selects the timing: 1000 for a 1:1 ratio
+	 * (no video timing) or 1001 for the 1000/1001 video timing.
+	 */
+
+	sep = strchr(str, '/');
+	if (!sep)
+		return -EINVAL;
+
+	*sep = '\0';
+
+	ret = kstrtou32(strim(str), 10, numerator);
+	if (ret)
+		return ret;
+
+	ret = kstrtou32(strim(sep + 1), 10, denominator);
+	if (ret)
+		return ret;
+	/*
+	 * "0/0" clears any previously configured CMRR override.
+	 * A zero numerator already means "CMRR not requested" in
+	 * intel_vrr_cmrr_compute_config(), so just let it through.
+	 */
+	if (*numerator == 0 && *denominator == 0)
+		return 0;
+
+	if (*numerator == 0)
+		return -EINVAL;
+
+	if (*denominator != 1000 && *denominator != 1001)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_target_rr_show(struct seq_file *m, void *data)
+{
+	struct intel_crtc *crtc = m->private;
+
+	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_target_rr_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, intel_vrr_debugfs_target_rr_show, inode->i_private);
+}
+
+static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char __user *ubuf,
+						 size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct intel_crtc *crtc = m->private;
+	u32 numerator, denominator;
+	char kbuf[32];
+	int ret;
+
+	if (len >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, ubuf, len))
+		return -EFAULT;
+
+	kbuf[len] = '\0';
+
+	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
+	if (ret)
+		return ret;
+
+	crtc->force_cmrr.numerator = numerator;
+	crtc->force_cmrr.denominator = denominator;
+
+	return len;
+}
+
+static const struct file_operations intel_vrr_debugfs_target_rr_fops = {
+	.owner = THIS_MODULE,
+	.open = intel_vrr_debugfs_target_rr_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = intel_vrr_debugfs_target_rr_write,
+};
+
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
+
+	debugfs_create_file("intel_vrr_target_refresh_rate", 0600, crtc->base.debugfs_entry,
+			    crtc, &intel_vrr_debugfs_target_rr_fops);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 55e9c429f579..19c7990be1b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
 
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

Re: [PATCH v6 3/9] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
> CMRR target refresh rate and video-mode requirement.
> 
> The file uses a "numerator/denominator" format:
>    - numerator:   requested refresh rate in milli-Hz
>                   (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
>    - denominator: 1000 for a 1:1 ratio (no video timing) or
>                   1001 for the 1000/1001 video timing
> 
> Reading the file reports the currently stored values; writing updates
> them. The file is created only on platforms with VRR and CMRR support.
> 

The commit message is not updated with the new debugfs name.


> --v2:
> - Drop the "vrr" debugfs subdirectory and expose a single flat,
>    intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
> - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
>    explicit (Chaitanya)
> - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
> - Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
> - Expand commit message with debugfs entry semantics (Chaitanya)
> 
> --v3:
> - Rename debugfs function and file name (Chaitanya)
> - Remove railing new line at EOF (Chaitanya)
> - Update CMRR guard conditions (Chaitanya)
> - Add 0/0 default case. (Ramanaidu)
> 
> --v4:
> - Correct CMRR guard check while creating debugfs
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>   .../drm/i915/display/intel_display_types.h    |   5 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 108 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>   4 files changed, 117 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3f02868ef105..2bbf4760dc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -49,6 +49,7 @@
>   #include "intel_psr.h"
>   #include "intel_psr_regs.h"
>   #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>   #include "intel_wm.h"
>   #include "intel_tc.h"
>   
> @@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>   	intel_drrs_crtc_debugfs_add(crtc);
>   	intel_fbc_crtc_debugfs_add(crtc);
>   	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>   
>   	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>   			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b7cc361fd955..46dd980b315a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1553,6 +1553,11 @@ struct intel_crtc {
>   		u64 flip_count;
>   	} dc_balance;
>   
> +	struct {
> +		u32 numerator;
> +		u32 denominator;
> +	} force_cmrr;
> +
>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 14f8ac07c911..267c65d9245f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -4,6 +4,10 @@
>    *
>    */
>   
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/string.h>
> +
>   #include <drm/drm_print.h>
>   #include <drm/intel/step.h>
>   
> @@ -1237,3 +1241,107 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>   
>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>   }
> +
> +static
> +int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
> +{
> +	char *sep;
> +	int ret;
> +
> +	/*
> +	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
> +	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
> +	 * and the denominator selects the timing: 1000 for a 1:1 ratio
> +	 * (no video timing) or 1001 for the 1000/1001 video timing.
> +	 */
> +
> +	sep = strchr(str, '/');
> +	if (!sep)
> +		return -EINVAL;
> +
> +	*sep = '\0';
> +
> +	ret = kstrtou32(strim(str), 10, numerator);
> +	if (ret)
> +		return ret;
> +
> +	ret = kstrtou32(strim(sep + 1), 10, denominator);
> +	if (ret)
> +		return ret;
> +	/*
> +	 * "0/0" clears any previously configured CMRR override.
> +	 * A zero numerator already means "CMRR not requested" in
> +	 * intel_vrr_cmrr_compute_config(), so just let it through.
> +	 */
> +	if (*numerator == 0 && *denominator == 0)
> +		return 0;
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_target_rr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_target_rr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_debugfs_target_rr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char __user *ubuf,
> +						 size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->force_cmrr.numerator = numerator;
> +	crtc->force_cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +
> +static const struct file_operations intel_vrr_debugfs_target_rr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_debugfs_target_rr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_debugfs_target_rr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> +	if (!intel_vrr_cmrr_possible(crtc_state))
> +		return;
> +
> +	debugfs_create_file("intel_vrr_target_refresh_rate", 0600, crtc->base.debugfs_entry,
> +			    crtc, &intel_vrr_debugfs_target_rr_fops);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_VRR_H__ */

[PATCH v6 4/9] drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config request

[Mitul Golani]

Compute AS_SDP target_rr_divider based on actual CMRR request
requirement.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1915d376b943..23e169d8db7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3111,6 +3111,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	/*
 	 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new
@@ -3131,7 +3132,11 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	if (crtc_state->cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
+
+		if (crtc->force_cmrr.denominator == 1001)
+			as_sdp->target_rr_divider = true;
+		else
+			as_sdp->target_rr_divider = false;
 	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
 	} else {
-- 
2.48.1

Re: [PATCH v6 4/9] drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config request

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Compute AS_SDP target_rr_divider based on actual CMRR request
> requirement.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1915d376b943..23e169d8db7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3111,6 +3111,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>   	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
>   	const struct drm_display_mode *adjusted_mode =
>   		&crtc_state->hw.adjusted_mode;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   
>   	/*
>   	 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new
> @@ -3131,7 +3132,11 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>   	if (crtc_state->cmrr.enable) {
>   		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>   		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
> -		as_sdp->target_rr_divider = true;
> +
> +		if (crtc->force_cmrr.denominator == 1001)
> +			as_sdp->target_rr_divider = true;
> +		else
> +			as_sdp->target_rr_divider = false;

This should eventually move to state tracking. But for now works.

One fragility is that we use den == 1001 here and den != 1000 in compute 
config. Not a blocker though.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

>   	} else if (crtc_state->vrr.enable) {
>   		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
>   	} else {

[PATCH v6 5/9] drm/i915/display: Move CMRR crtc_state members under VRR

[Mitul Golani]

Move CMRR crtc state members under VRR infrastructure as
it is enabled during fix refresh rate  VRR timing generator
is enabled.

--v2:
- Move cmrr structure under vrr umbrella.
- Remove dups. (Jani)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 10 +++----
 .../drm/i915/display/intel_display_types.h    | 12 ++++----
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 30 +++++++++----------
 6 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c8e0f90af910..3c0f5b2fb2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
 
 	/* TODO: The code below may need to be revisited once CMRR is enabled */
-	if (crtc_state->cmrr.enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2c55a4818ad7..5baa9602b86e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 				const struct intel_crtc_state *new_crtc_state)
 {
-	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
-		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
+		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
 }
 
 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@@ -5523,9 +5523,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.flipline);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
-		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
+		PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 46dd980b315a..20a07ea06b5e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1408,13 +1408,13 @@ struct intel_crtc_state {
 			u16 max_increase, max_decrease;
 			u16 vblank_target;
 		} dc_balance;
-	} vrr;
 
-	/* Content Match Refresh Rate state */
-	struct {
-		bool enable;
-		u64 cmrr_n, cmrr_m;
-	} cmrr;
+		/* Content Match Refresh Rate state */
+		struct {
+			bool enable;
+			u64 cmrr_n, cmrr_m;
+		} cmrr;
+	} vrr;
 
 	/* Stream Splitter for eDP MSO */
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 23e169d8db7b..51afe519073f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3129,7 +3129,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6a90ded5d1fa..e9e47522495d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1587,7 +1587,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		drm_dbg_kms(display->drm,
 			    "Selective update cannot be enabled when CMRR is enabled\n");
 		goto unsupported;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 267c65d9245f..84b1ec7f1616 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -235,12 +235,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
 		multiplier_n = 1000;
 	}
 
-	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-					      multiplier_n);
+	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
+						  multiplier_n);
 	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->cmrr.cmrr_n);
+				  crtc_state->vrr.cmrr.cmrr_n);
 	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
 
 	return vtotal;
 }
@@ -258,7 +258,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 
-	crtc_state->cmrr.enable = true;
+	crtc_state->vrr.cmrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
@@ -651,15 +651,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	}
 
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
@@ -980,7 +980,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
+		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1077,12 +1077,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (intel_vrr_cmrr_possible(crtc_state))
-		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+		crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
-	if (crtc_state->cmrr.enable) {
-		crtc_state->cmrr.cmrr_n =
+	if (crtc_state->vrr.cmrr.enable) {
+		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
-		crtc_state->cmrr.cmrr_m =
+		crtc_state->vrr.cmrr.cmrr_m =
 			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
 	}
 
-- 
2.48.1

Re: [PATCH v6 5/9] drm/i915/display: Move CMRR crtc_state members under VRR

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Move CMRR crtc state members under VRR infrastructure as
> it is enabled during fix refresh rate  VRR timing generator
> is enabled.
> 

The RB was contintgent on changing the commit message.

"it is enabled when the fixed-refresh-rate VRR timing generator is enabled
"

Please don't ignore the *conditions* in a *conditional* RB.

> --v2:
> - Move cmrr structure under vrr umbrella.
> - Remove dups. (Jani)
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c     |  2 +-
>   drivers/gpu/drm/i915/display/intel_display.c  | 10 +++----
>   .../drm/i915/display/intel_display_types.h    | 12 ++++----
>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>   drivers/gpu/drm/i915/display/intel_psr.c      |  2 +-
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 30 +++++++++----------
>   6 files changed, 29 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index c8e0f90af910..3c0f5b2fb2e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
>   		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
>   
>   	/* TODO: The code below may need to be revisited once CMRR is enabled */
> -	if (crtc_state->cmrr.enable)
> +	if (crtc_state->vrr.cmrr.enable)
>   		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2c55a4818ad7..5baa9602b86e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>   static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>   				const struct intel_crtc_state *new_crtc_state)
>   {
> -	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> -		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> +	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
> +		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
>   }
>   
>   static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
> @@ -5523,9 +5523,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		PIPE_CONF_CHECK_I(vrr.flipline);
>   		PIPE_CONF_CHECK_I(vrr.vsync_start);
>   		PIPE_CONF_CHECK_I(vrr.vsync_end);
> -		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> -		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> -		PIPE_CONF_CHECK_BOOL(cmrr.enable);
> +		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
> +		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
> +		PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 46dd980b315a..20a07ea06b5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1408,13 +1408,13 @@ struct intel_crtc_state {
>   			u16 max_increase, max_decrease;
>   			u16 vblank_target;
>   		} dc_balance;
> -	} vrr;
>   
> -	/* Content Match Refresh Rate state */
> -	struct {
> -		bool enable;
> -		u64 cmrr_n, cmrr_m;
> -	} cmrr;
> +		/* Content Match Refresh Rate state */
> +		struct {
> +			bool enable;
> +			u64 cmrr_n, cmrr_m;
> +		} cmrr;
> +	} vrr;
>   
>   	/* Stream Splitter for eDP MSO */
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23e169d8db7b..51afe519073f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3129,7 +3129,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>   	as_sdp->revision = 0x2;
>   	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>   
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>   		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>   		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6a90ded5d1fa..e9e47522495d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1587,7 +1587,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>   	struct intel_dp *intel_dp = intel_attached_dp(connector);
>   	struct intel_display *display = to_intel_display(intel_dp);
>   
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>   		drm_dbg_kms(display->drm,
>   			    "Selective update cannot be enabled when CMRR is enabled\n");
>   		goto unsupported;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 267c65d9245f..84b1ec7f1616 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -235,12 +235,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
>   		multiplier_n = 1000;
>   	}
>   
> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -					      multiplier_n);
> +	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> +						  multiplier_n);
>   	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->cmrr.cmrr_n);
> +				  crtc_state->vrr.cmrr.cmrr_n);
>   	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
>   
>   	return vtotal;
>   }
> @@ -258,7 +258,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
>   	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>   
> -	crtc_state->cmrr.enable = true;
> +	crtc_state->vrr.cmrr.enable = true;
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
>   
> @@ -651,15 +651,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   		return;
>   	}
>   
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>   		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->cmrr.cmrr_m));
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>   		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->cmrr.cmrr_m));
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>   		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->cmrr.cmrr_n));
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>   		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->cmrr.cmrr_n));
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>   	}
>   
>   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> @@ -980,7 +980,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> +		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1077,12 +1077,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>   
>   	if (intel_vrr_cmrr_possible(crtc_state))
> -		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
> +		crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>   
> -	if (crtc_state->cmrr.enable) {
> -		crtc_state->cmrr.cmrr_n =
> +	if (crtc_state->vrr.cmrr.enable) {
> +		crtc_state->vrr.cmrr.cmrr_n =
>   			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
> -		crtc_state->cmrr.cmrr_m =
> +		crtc_state->vrr.cmrr.cmrr_m =
>   			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
>   	}
>   

[PATCH v6 6/9] drm/i915/vrr: Compute CMRR fractional timings generically

[Mitul Golani]

Rework the fractional-CMRR computation into a generic,
transcoder-agnostic helper driven by an explicit per-CRTC debugfs
target, replacing the previous disabled, eDP-only code path. Compute
CMRR_M and CMRR_N timings based on the video mode requirement. Note the
CMRR enable path is wired up separately; this patch only lays down the
generic computation. Remove computing mode_flags, I915_MODE_FLAG_VRR
as we are moving CMRR to fixed refresh rate path. Also return early
from CMRR computation if existing computation is well sufficient.

--v2:
- Derive video_mode locally instead of caching it in persistent
  struct intel_crtc state (Jani, Chaitanya)
- Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
- Fix "reqirement" typo and clarify CMRR is not yet enabled in the
  commit message (Chaitanya)
- Fix precision issue while computing M/N ration (Chaitanya)
- Multiplier_m and n naming update to increase readability. (Chaitanya)
- Compute vtotal as it is required to deither as per algo
implementation. (Chaitanya)
- Replace misleading adjusted_pixel_rate to dividend which is somewhat
relatable.

--v3:
- Mention rationale for not to compute I915_MODE_FLAG_VRR. (Chaitanya)
- Remove redundant return statement from last line of cmrr compute.
(Chaitanya)
- Correct cmrr_n calculation. (Chaitanya)
- Add early return condition is current computaion is well sufficient
to drive without CMRR. (Chaitanya)
- Take round up for requested_refresh_rate. (Validation)
- Correct integer overflow

--v4:
- Update cmrr_n calculation to aviod aggressive dithering
- Use div64_u64 to truncate value to floor value, as DIV_ROUND_UP_ULL
rounding to ceil value.
- Add TODO comment at cmrr_n calculation
- Add condition for custom refresh rate request
- Update CMRR computational comment block in copute config

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 138 ++++++++++++-----------
 1 file changed, 72 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 84b1ec7f1616..e8c6516fd36a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -27,9 +27,6 @@
 #include "skl_prefill.h"
 #include "skl_watermark.h"
 
-#define FIXED_POINT_PRECISION		100
-#define CMRR_PRECISION_TOLERANCE	10
-
 /*
  * Tunable parameters for DC Balance correction.
  * These are captured based on experimentations.
@@ -198,68 +195,79 @@ static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
 	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));
 }
 
-static bool
-is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+static void
+intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 {
-	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	u64 dividend;
+	int requested_refresh_rate, current_refresh_rate;
+	int rr_multiplier = 1, rr_divider = 1;
+	bool video_mode;
 
-	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!intel_vrr_cmrr_possible(crtc_state) || true)
-		return false;
-
-	actual_refresh_k =
-		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
-	pixel_clock_per_line =
-		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
-	calculated_refresh_k =
-		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
-
-	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
-		return false;
-
-	return true;
-}
-
-static unsigned int
-cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
-{
-	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
-	u64 adjusted_pixel_rate;
-	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
 
-	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+	/* No CMRR ratio configured through debugfs */
+	if (!crtc->force_cmrr.numerator)
+		return;
 
-	if (video_mode_required) {
-		multiplier_m = 1001;
-		multiplier_n = 1000;
+	/*
+	 * The numerator encodes the requested refresh rate in milli-Hz, so the
+	 * requested refresh rate in Hz is numerator / 1000. It must match the
+	 * refresh rate of the current mode.
+	 */
+	requested_refresh_rate = DIV_ROUND_UP_ULL(crtc->force_cmrr.numerator, 1000);
+	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+
+	if (requested_refresh_rate != current_refresh_rate) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
+				crtc->base.base.id, crtc->base.name,
+				requested_refresh_rate, current_refresh_rate);
+		return;
 	}
 
-	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-						  multiplier_n);
-	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->vrr.cmrr.cmrr_n);
-	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
-
-	return vtotal;
-}
-
-static
-void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
-{
 	/*
-	 * TODO: Compute precise target refresh rate to determine
-	 * if video_mode_required should be true. Currently set to
-	 * false due to uncertainty about the precise target
-	 * refresh Rate.
+	 * A 1:1 ratio (denominator == 1000) means no video timing is required
+	 * Any other ratio (e.g. 1000/1001) requires the video timing.
 	 */
-	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
-	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+	video_mode = crtc->force_cmrr.denominator != 1000;
+	if (video_mode) {
+		rr_multiplier = 1000;
+		rr_divider = 1001;
+	} else if (crtc->force_cmrr.numerator == current_refresh_rate * 1000) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] Requested mode refresh rate %d Hz can be driven without CMRR\n",
+				crtc->base.base.id, crtc->base.name,
+				requested_refresh_rate);
+		return;
+	}
 
-	crtc_state->vrr.cmrr.enable = true;
-	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+	/*
+	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
+	 *
+	 * cmrr_n = (numerator_mHz x htotal x rr_multiplier) / 1000
+	 * cmrr_m = (pixel_clock_hz x rr_divider) % cmrr_n
+	 *
+	 * where numerator_mHz is the requested refresh rate in milli-Hz
+	 * and rr_multiplier/rr_divider = 1000/1001 when the video timing
+	 * is required, else 1/1. The integer vtotal term is tracked in SW
+	 * (it is the programmed mode vtotal) while the fractional part
+	 * represented by cmrr_m/cmrr_n is tracked in HW.
+	 *
+	 * TODO: Using the actual desired rate for cmrr_n in video
+	 * mode produces more aggressive vtotal dithering than
+	 * expected; revisit once the Bspec algorithm is clarified.
+	 */
+	crtc_state->vrr.cmrr.cmrr_n =
+		div64_u64((u64)crtc->force_cmrr.numerator *
+			   adjusted_mode->crtc_htotal * rr_multiplier, 1000);
+	dividend = (u64)adjusted_mode->crtc_clock * rr_divider * 1000;
+	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
+						   crtc_state->vrr.cmrr.cmrr_n,
+						   &crtc_state->vrr.cmrr.cmrr_m);
 }
 
 static
@@ -435,8 +443,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int vmin, vmax;
 
@@ -470,12 +476,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		vmax = vmin;
 	}
 
-	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
+	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
-	else if (is_cmrr_frac_required(crtc_state) && is_edp)
-		intel_vrr_compute_cmrr_timings(crtc_state);
-	else
+	} else {
+		/*
+		 * CMRR is a fixed average Vtotal mode and is only computed on
+		 * the fixed refresh rate path. It is generic across transcoders
+		 * and gated on platform support and a valid debugfs ratio.
+		 */
+		intel_vrr_cmrr_compute_config(crtc_state);
 		intel_vrr_compute_fixed_rr_timings(crtc_state);
+	}
 
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
@@ -1142,11 +1153,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_vrr_get_dc_balance_config(crtc_state);
 
-	/*
-	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
-	 * Since CMRR is currently disabled, set this flag for VRR for now.
-	 * Need to keep this in mind while re-enabling CMRR.
-	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 
-- 
2.48.1

Re: [PATCH v6 6/9] drm/i915/vrr: Compute CMRR fractional timings generically

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Rework the fractional-CMRR computation into a generic,
> transcoder-agnostic helper driven by an explicit per-CRTC debugfs
> target, replacing the previous disabled, eDP-only code path. Compute
> CMRR_M and CMRR_N timings based on the video mode requirement. Note the
> CMRR enable path is wired up separately; this patch only lays down the
> generic computation. Remove computing mode_flags, I915_MODE_FLAG_VRR
> as we are moving CMRR to fixed refresh rate path. Also return early
> from CMRR computation if existing computation is well sufficient.
> 
> --v2:
> - Derive video_mode locally instead of caching it in persistent
>    struct intel_crtc state (Jani, Chaitanya)
> - Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
> - Fix "reqirement" typo and clarify CMRR is not yet enabled in the
>    commit message (Chaitanya)
> - Fix precision issue while computing M/N ration (Chaitanya)

typo: ratio

> - Multiplier_m and n naming update to increase readability. (Chaitanya)
> - Compute vtotal as it is required to deither as per algo

typo: dither

> implementation. (Chaitanya)
> - Replace misleading adjusted_pixel_rate to dividend which is somewhat
> relatable.
> 
> --v3:
> - Mention rationale for not to compute I915_MODE_FLAG_VRR. (Chaitanya)
> - Remove redundant return statement from last line of cmrr compute.
> (Chaitanya)
> - Correct cmrr_n calculation. (Chaitanya)
> - Add early return condition is current computaion is well sufficient

typo: computation


> to drive without CMRR. (Chaitanya)
> - Take round up for requested_refresh_rate. (Validation)
> - Correct integer overflow
> 
> --v4:
> - Update cmrr_n calculation to aviod aggressive dithering

typo: avoid

> - Use div64_u64 to truncate value to floor value, as DIV_ROUND_UP_ULL
> rounding to ceil value.
> - Add TODO comment at cmrr_n calculation
> - Add condition for custom refresh rate request
> - Update CMRR computational comment block in copute config

typo: compute

> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 138 ++++++++++++-----------
>   1 file changed, 72 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 84b1ec7f1616..e8c6516fd36a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -27,9 +27,6 @@
>   #include "skl_prefill.h"
>   #include "skl_watermark.h"
>   
> -#define FIXED_POINT_PRECISION		100
> -#define CMRR_PRECISION_TOLERANCE	10
> -
>   /*
>    * Tunable parameters for DC Balance correction.
>    * These are captured based on experimentations.
> @@ -198,68 +195,79 @@ static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
>   	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));
>   }
>   
> -static bool
> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> +static void
> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   {
> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	u64 dividend;
> +	int requested_refresh_rate, current_refresh_rate;
> +	int rr_multiplier = 1, rr_divider = 1;
> +	bool video_mode;
>   
> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> -	if (!intel_vrr_cmrr_possible(crtc_state) || true)
> -		return false;
> -
> -	actual_refresh_k =
> -		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
> -	pixel_clock_per_line =
> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
> -	calculated_refresh_k =
> -		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
> -
> -	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
> -		return false;
> -
> -	return true;
> -}
> -
> -static unsigned int
> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
> -{
> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> -	u64 adjusted_pixel_rate;
> -	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	if (!intel_vrr_cmrr_possible(crtc_state))
> +		return;
>   
> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +	/* No CMRR ratio configured through debugfs */
> +	if (!crtc->force_cmrr.numerator)
> +		return;
>   
> -	if (video_mode_required) {
> -		multiplier_m = 1001;
> -		multiplier_n = 1000;
> +	/*
> +	 * The numerator encodes the requested refresh rate in milli-Hz, so the
> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> +	 * refresh rate of the current mode.
> +	 */
> +	requested_refresh_rate = DIV_ROUND_UP_ULL(crtc->force_cmrr.numerator, 1000);
> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +
> +	if (requested_refresh_rate != current_refresh_rate) {
> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
> +				crtc->base.base.id, crtc->base.name,
> +				requested_refresh_rate, current_refresh_rate);
> +		return;
>   	}
>   
> -	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -						  multiplier_n);
> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->vrr.cmrr.cmrr_n);
> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
> -
> -	return vtotal;
> -}
> -
> -static
> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
> -{
>   	/*
> -	 * TODO: Compute precise target refresh rate to determine
> -	 * if video_mode_required should be true. Currently set to
> -	 * false due to uncertainty about the precise target
> -	 * refresh Rate.
> +	 * A 1:1 ratio (denominator == 1000) means no video timing is required
> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
>   	 */
> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> +	video_mode = crtc->force_cmrr.denominator != 1000;
> +	if (video_mode) {
> +		rr_multiplier = 1000;
> +		rr_divider = 1001;
> +	} else if (crtc->force_cmrr.numerator == current_refresh_rate * 1000) {

As discussed this should be a comparision between num/den and actual 
refresh rate derived from the mode line. Moreover, this check should be 
done for both video and non video mode branches.

> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] Requested mode refresh rate %d Hz can be driven without CMRR\n",
> +				crtc->base.base.id, crtc->base.name,
> +				requested_refresh_rate);
> +		return;
> +	}
>   
> -	crtc_state->vrr.cmrr.enable = true;
> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +	/*
> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> +	 *
> +	 * cmrr_n = (numerator_mHz x htotal x rr_multiplier) / 1000
> +	 * cmrr_m = (pixel_clock_hz x rr_divider) % cmrr_n
> +	 *
> +	 * where numerator_mHz is the requested refresh rate in milli-Hz
> +	 * and rr_multiplier/rr_divider = 1000/1001 when the video timing
> +	 * is required, else 1/1. The integer vtotal term is tracked in SW
> +	 * (it is the programmed mode vtotal) while the fractional part
> +	 * represented by cmrr_m/cmrr_n is tracked in HW.
> +	 *
> +	 * TODO: Using the actual desired rate for cmrr_n in video
> +	 * mode produces more aggressive vtotal dithering than
> +	 * expected; revisit once the Bspec algorithm is clarified.
> +	 */
> +	crtc_state->vrr.cmrr.cmrr_n =
> +		div64_u64((u64)crtc->force_cmrr.numerator *
> +			   adjusted_mode->crtc_htotal * rr_multiplier, 1000);
> +	dividend = (u64)adjusted_mode->crtc_clock * rr_divider * 1000;
> +	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
> +						   crtc_state->vrr.cmrr.cmrr_n,
> +						   &crtc_state->vrr.cmrr.cmrr_m);
>   }
>   
>   static
> @@ -435,8 +443,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	struct intel_connector *connector =
>   		to_intel_connector(conn_state->connector);
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -	bool is_edp = intel_dp_is_edp(intel_dp);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>   	int vmin, vmax;
>   
> @@ -470,12 +476,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   		vmax = vmin;
>   	}
>   
> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> -		intel_vrr_compute_cmrr_timings(crtc_state);
> -	else
> +	} else {
> +		/*
> +		 * CMRR is a fixed average Vtotal mode and is only computed on
> +		 * the fixed refresh rate path. It is generic across transcoders
> +		 * and gated on platform support and a valid debugfs ratio.
> +		 */
> +		intel_vrr_cmrr_compute_config(crtc_state);
>   		intel_vrr_compute_fixed_rr_timings(crtc_state);
> +	}
>   
>   	if (HAS_AS_SDP(display)) {
>   		crtc_state->vrr.vsync_start =
> @@ -1142,11 +1153,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   
>   	intel_vrr_get_dc_balance_config(crtc_state);
>   
> -	/*
> -	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
> -	 * Since CMRR is currently disabled, set this flag for VRR for now.
> -	 * Need to keep this in mind while re-enabling CMRR.
> -	 */
>   	if (crtc_state->vrr.enable)
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   

[PATCH v6 7/9] drm/i915/vrr: Dump CMRR state in the crtc state dump

[Mitul Golani]

Add crtc state dump for CMRR.

--v2:
- Remove video mode state checker.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4493483f10a9..ad4f362e0c09 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -311,6 +311,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->vrr.dc_balance.max_increase,
 		   pipe_config->vrr.dc_balance.max_decrease,
 		   pipe_config->vrr.dc_balance.vblank_target);
+	drm_printf(&p, "cmrr: %s, cmrr_m: %llu, cmrr_n: %llu\n",
+		   str_yes_no(pipe_config->vrr.cmrr.enable),
+		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v6 8/9] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Mitul Golani]

Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
and intel_vrr_disable_cmrr(), and drive them from
intel_vrr_set_fixed_rr_timings() based on crtc_state->vrr.cmrr.enable.

VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
arms CMRR in hardware. Drop the now-unused cmrr_enable
argument to intel_vrr_tg_enable().

No functional change intended for non-CMRR configurations.

--v2:
- Commit message changes.
- Added Simplified enable/disable sequence. (Chaitanya)

--v3:
- Guard CMRR enable condition (Chaitanya)
- Comment changes updated (Chaitanya)
- Squash register write commits together and
avoid double writing issue. (Chaitanya)

--v4:
- Guard CMRR enable/disable with platform check

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Assisted-by: Claude:claude-opus-4-8
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 66 +++++++++++++++++-------
 1 file changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e8c6516fd36a..6bc3ccd62513 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -195,6 +195,40 @@ static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
 	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));
 }
 
+static void
+intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+}
+
+static void
+intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
+}
+
 static void
 intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 {
@@ -351,6 +385,11 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	if (crtc_state->vrr.cmrr.enable)
+		intel_vrr_enable_cmrr(crtc_state);
+	else
+		intel_vrr_disable_cmrr(crtc_state);
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
@@ -662,17 +701,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->vrr.cmrr.enable) {
-		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-	}
-
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 	intel_cmtg_set_vrr_timings(crtc_state);
 
@@ -938,8 +966,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
-static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
-				bool cmrr_enable)
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -951,11 +978,12 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
 	/*
-	 * FIXME this might be broken as bspec seems to imply that
-	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
-	 * when enabling CMRR (but not when disabling CMRR?).
+	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
+	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing TRANS_CMRR_N_HI
+	 * arms the bit in hardware, but this later write would otherwise clear
+	 * it again.
 	 */
-	if (cmrr_enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
@@ -991,7 +1019,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1018,7 +1046,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	if (intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, false);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.48.1

Re: [PATCH v6 8/9] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
> and intel_vrr_disable_cmrr(), and drive them from
> intel_vrr_set_fixed_rr_timings() based on crtc_state->vrr.cmrr.enable.
> 
> VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
> arms CMRR in hardware. Drop the now-unused cmrr_enable
> argument to intel_vrr_tg_enable().
> 
> No functional change intended for non-CMRR configurations.
> 
> --v2:
> - Commit message changes.
> - Added Simplified enable/disable sequence. (Chaitanya)
> 
> --v3:
> - Guard CMRR enable condition (Chaitanya)
> - Comment changes updated (Chaitanya)
> - Squash register write commits together and
> avoid double writing issue. (Chaitanya)
> 
> --v4:
> - Guard CMRR enable/disable with platform check
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Assisted-by: Claude:claude-opus-4-8
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 66 +++++++++++++++++-------
>   1 file changed, 47 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e8c6516fd36a..6bc3ccd62513 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -195,6 +195,40 @@ static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
>   	return (HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display));
>   }
>   
> +static void
> +intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +

This will result in CMTG instances of the registers remain unwritten. 
Transcoder should be passed as an argument, similar to 
intel_vrr_set_fixed_rr_timings()

> +	if (!intel_vrr_cmrr_possible(crtc_state))
> +		return;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +}
> +
> +static void
> +intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!intel_vrr_cmrr_possible(crtc_state))
> +		return;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
> +}
> +
>   static void
>   intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   {
> @@ -351,6 +385,11 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> +	if (crtc_state->vrr.cmrr.enable)
> +		intel_vrr_enable_cmrr(crtc_state);
> +	else
> +		intel_vrr_disable_cmrr(crtc_state);
> +

Is there a specific reason for having the enable/disable mechanics? 
Can't we just make it part of a function similar to 
intel_vrr_set_fixed_rr_timings() and let it program the registers with 
whatever value the compute config comes up with? some relevant values 
for enable and 0 for disable.

>   	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
>   		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
>   	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
> @@ -662,17 +701,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   		return;
>   	}
>   
> -	if (crtc_state->vrr.cmrr.enable) {
> -		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> -		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> -		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> -		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> -	}
> -
>   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
>   	intel_cmtg_set_vrr_timings(crtc_state);
>   
> @@ -938,8 +966,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
>   }
>   
> -static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
> -				bool cmrr_enable)
> +static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> @@ -951,11 +978,12 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
>   
>   	/*
> -	 * FIXME this might be broken as bspec seems to imply that
> -	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
> -	 * when enabling CMRR (but not when disabling CMRR?).
> +	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
> +	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing TRANS_CMRR_N_HI
> +	 * arms the bit in hardware, but this later write would otherwise clear
> +	 * it again.
>   	 */
> -	if (cmrr_enable)
> +	if (crtc_state->vrr.cmrr.enable)
>   		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>

Will this path ever reach through a fastset?

Another thing related to the modeset/fastset semantics. In cmmr_compute 
config we might end up with votal different from the mode line. If we 
need something similar to LRR where vtotal change can be achieved 
through a fastset is worth checking.
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
> @@ -991,7 +1019,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
> +		intel_vrr_tg_enable(crtc_state);
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1018,7 +1046,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	if (intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, false);
> +		intel_vrr_tg_enable(crtc_state);
>   }
>   
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)

RE: [PATCH v6 8/9] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Golani, Mitulkumar Ajitkumar]

Thanks for the review,

I have consolidated this into a single intel_vrr_set_cmrr_timings() helper that always programs the CMRR registers (valid values when enabled, 0 when disabled), removing the separate enable/disable helpers. The helper is now called unconditionally from intel_vrr_set_fixed_rr_timings(). I also made intel_vrr_cmrr_compute_config() explicitly clear the CMRR state on non-requested paths so the disable behavior is deterministic rather than relying on pre-zeroing.

I will flaot change with next revision.

Thanks

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 23 July 2026 21:51
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v6 8/9] drm/i915/vrr: Program CMRR enable/disable from
> transcoder timings
> 
> 
> 
> On 7/22/2026 10:09 AM, Mitul Golani wrote:
> > Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
> > and intel_vrr_disable_cmrr(), and drive them from
> > intel_vrr_set_fixed_rr_timings() based on crtc_state->vrr.cmrr.enable.
> >
> > VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
> > arms CMRR in hardware. Drop the now-unused cmrr_enable argument to
> > intel_vrr_tg_enable().
> >
> > No functional change intended for non-CMRR configurations.
> >
> > --v2:
> > - Commit message changes.
> > - Added Simplified enable/disable sequence. (Chaitanya)
> >
> > --v3:
> > - Guard CMRR enable condition (Chaitanya)
> > - Comment changes updated (Chaitanya)
> > - Squash register write commits together and avoid double writing
> > issue. (Chaitanya)
> >
> > --v4:
> > - Guard CMRR enable/disable with platform check
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > Assisted-by: Claude:claude-opus-4-8
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 66 +++++++++++++++++-------
> >   1 file changed, 47 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index e8c6516fd36a..6bc3ccd62513 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -195,6 +195,40 @@ static bool intel_vrr_cmrr_possible(const struct
> intel_crtc_state *crtc_state)
> >   	return (HAS_CMRR(display) &&
> intel_vrr_always_use_vrr_tg(display));
> >   }
> >
> > +static void
> > +intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> 
> This will result in CMTG instances of the registers remain unwritten.
> Transcoder should be passed as an argument, similar to
> intel_vrr_set_fixed_rr_timings()
> 
> > +	if (!intel_vrr_cmrr_possible(crtc_state))
> > +		return;
> > +
> > +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> > +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> > +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> > +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> > +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > +}
> > +
> > +static void
> > +intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	if (!intel_vrr_cmrr_possible(crtc_state))
> > +		return;
> > +
> > +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> > +0); }
> > +
> >   static void
> >   intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
> >   {
> > @@ -351,6 +385,11 @@ void intel_vrr_set_fixed_rr_timings(const struct
> intel_crtc_state *crtc_state,
> >   	if (!intel_vrr_possible(crtc_state))
> >   		return;
> >
> > +	if (crtc_state->vrr.cmrr.enable)
> > +		intel_vrr_enable_cmrr(crtc_state);
> > +	else
> > +		intel_vrr_disable_cmrr(crtc_state);
> > +
> 
> Is there a specific reason for having the enable/disable mechanics?
> Can't we just make it part of a function similar to
> intel_vrr_set_fixed_rr_timings() and let it program the registers with whatever
> value the compute config comes up with? some relevant values for enable
> and 0 for disable.
> 
> >   	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
> >   		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> >   	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@
> > -662,17 +701,6 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> >   		return;
> >   	}
> >
> > -	if (crtc_state->vrr.cmrr.enable) {
> > -		intel_de_write(display, TRANS_CMRR_M_HI(display,
> cpu_transcoder),
> > -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > -		intel_de_write(display, TRANS_CMRR_M_LO(display,
> cpu_transcoder),
> > -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > -		intel_de_write(display, TRANS_CMRR_N_HI(display,
> cpu_transcoder),
> > -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > -		intel_de_write(display, TRANS_CMRR_N_LO(display,
> cpu_transcoder),
> > -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > -	}
> > -
> >   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> >   	intel_cmtg_set_vrr_timings(crtc_state);
> >
> > @@ -938,8 +966,7 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> >   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);
> >   }
> >
> > -static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
> > -				bool cmrr_enable)
> > +static void intel_vrr_tg_enable(const struct intel_crtc_state
> > +*crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> >   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@
> > -951,11 +978,12 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
> >   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
> >
> >   	/*
> > -	 * FIXME this might be broken as bspec seems to imply that
> > -	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
> > -	 * when enabling CMRR (but not when disabling CMRR?).
> > +	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
> > +	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing
> TRANS_CMRR_N_HI
> > +	 * arms the bit in hardware, but this later write would otherwise clear
> > +	 * it again.
> >   	 */
> > -	if (cmrr_enable)
> > +	if (crtc_state->vrr.cmrr.enable)
> >   		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> >
> 
> Will this path ever reach through a fastset?
> 
> Another thing related to the modeset/fastset semantics. In cmmr_compute
> config we might end up with votal different from the mode line. If we need
> something similar to LRR where vtotal change can be achieved through a
> fastset is worth checking.
> >   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > vrr_ctl); @@ -991,7 +1019,7 @@ void intel_vrr_enable(const struct
> intel_crtc_state *crtc_state)
> >   	intel_vrr_enable_dc_balancing(crtc_state);
> >
> >   	if (!intel_vrr_always_use_vrr_tg(display))
> > -		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
> > +		intel_vrr_tg_enable(crtc_state);
> >   }
> >
> >   void intel_vrr_disable(const struct intel_crtc_state
> > *old_crtc_state) @@ -1018,7 +1046,7 @@ void
> intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
> >   		return;
> >
> >   	if (intel_vrr_always_use_vrr_tg(display))
> > -		intel_vrr_tg_enable(crtc_state, false);
> > +		intel_vrr_tg_enable(crtc_state);
> >   }
> >
> >   void intel_vrr_transcoder_disable(const struct intel_crtc_state
> > *old_crtc_state)

[PATCH v6 9/9] drm/i915/vrr: Enable cmrr

[Mitul Golani]

Enable CMRR during compute config and add related state
checker for the same.

--v2:
- Everything else except enable compute to handle before this patch
(Chaitanya)

--v3:
- Remove redundant return from compute config

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6bc3ccd62513..ed23a03b0d3d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -302,6 +302,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
 						   crtc_state->vrr.cmrr.cmrr_n,
 						   &crtc_state->vrr.cmrr.cmrr_m);
+
+	crtc_state->vrr.cmrr.enable = true;
 }
 
 static
-- 
2.48.1

Re: [PATCH v6 9/9] drm/i915/vrr: Enable cmrr

[Borah, Chaitanya Kumar]

On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Enable CMRR during compute config and add related state
> checker for the same.
> 
> --v2:
> - Everything else except enable compute to handle before this patch
> (Chaitanya)
> 
> --v3:
> - Remove redundant return from compute config
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6bc3ccd62513..ed23a03b0d3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -302,6 +302,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
>   						   crtc_state->vrr.cmrr.cmrr_n,
>   						   &crtc_state->vrr.cmrr.cmrr_m);
> +
> +	crtc_state->vrr.cmrr.enable = true;

We will also need to clear it (and cmrr_n, cmrr_m ) at the beginning of 
the compute config. If we only have this statement cmrr.enable will 
always remain true once set as it propagates through duplicated crtc states.

>   }
>   
>   static

Re: [PATCH v6 9/9] drm/i915/vrr: Enable cmrr

[Borah, Chaitanya Kumar]

On 7/23/2026 9:51 PM, Borah, Chaitanya Kumar wrote:
> 
> 
> On 7/22/2026 10:09 AM, Mitul Golani wrote:
>> Enable CMRR during compute config and add related state
>> checker for the same.
>>
>> --v2:
>> - Everything else except enable compute to handle before this patch
>> (Chaitanya)
>>
>> --v3:
>> - Remove redundant return from compute config
>>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/ 
>> drm/i915/display/intel_vrr.c
>> index 6bc3ccd62513..ed23a03b0d3d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -302,6 +302,8 @@ intel_vrr_cmrr_compute_config(struct 
>> intel_crtc_state *crtc_state)
>>       adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
>>                              crtc_state->vrr.cmrr.cmrr_n,
>>                              &crtc_state->vrr.cmrr.cmrr_m);
>> +
>> +    crtc_state->vrr.cmrr.enable = true;
> 
> We will also need to clear it (and cmrr_n, cmrr_m ) at the beginning of 
> the compute config. If we only have this statement cmrr.enable will 
> always remain true once set as it propagates through duplicated crtc 
> states.
> 

Spoke too soon, intel_crtc_prepare_cleared_state() zeroes the crtc_state 
right before intel_modeset_pipe_config() runs compute. So we should be 
good at that front.

The problem will still lie with CMRR_ENABLE not getting programmed 
during a fastset. It will leave the CMRR registers programmed (to 0s in 
disabled case) but CMRR_ENABLE bit in TRANS_VRR_CTL will not be updated 
as enable_vrr_tg (except in lrr case) and disable_vrr_tg are called only 
on modeset.

>>   }
>>   static
> 

RE: [PATCH v6 9/9] drm/i915/vrr: Enable cmrr

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 24 July 2026 15:20
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v6 9/9] drm/i915/vrr: Enable cmrr
> 
> 
> 
> On 7/23/2026 9:51 PM, Borah, Chaitanya Kumar wrote:
> >
> >
> > On 7/22/2026 10:09 AM, Mitul Golani wrote:
> >> Enable CMRR during compute config and add related state checker for
> >> the same.
> >>
> >> --v2:
> >> - Everything else except enable compute to handle before this patch
> >> (Chaitanya)
> >>
> >> --v3:
> >> - Remove redundant return from compute config
> >>
> >> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/
> >> drm/i915/display/intel_vrr.c index 6bc3ccd62513..ed23a03b0d3d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -302,6 +302,8 @@ intel_vrr_cmrr_compute_config(struct
> >> intel_crtc_state *crtc_state)
> >>       adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
> >>                              crtc_state->vrr.cmrr.cmrr_n,
> >>                              &crtc_state->vrr.cmrr.cmrr_m);
> >> +
> >> +    crtc_state->vrr.cmrr.enable = true;
> >
> > We will also need to clear it (and cmrr_n, cmrr_m ) at the beginning
> > of the compute config. If we only have this statement cmrr.enable will
> > always remain true once set as it propagates through duplicated crtc
> > states.
> >
> 
> Spoke too soon, intel_crtc_prepare_cleared_state() zeroes the crtc_state right
> before intel_modeset_pipe_config() runs compute. So we should be good at
> that front.
> 
> The problem will still lie with CMRR_ENABLE not getting programmed during a
> fastset. It will leave the CMRR registers programmed (to 0s in disabled case)
> but CMRR_ENABLE bit in TRANS_VRR_CTL will not be updated as
> enable_vrr_tg (except in lrr case) and disable_vrr_tg are called only on
> modeset.

Right, since intel_crtc_prepare_cleared_state() already clears the state, explicit reset is not required. 

With latest revision I will  update VRR_CTL_CMRR_ENABLE from intel_vrr_set_cmrr_timings() (New Function instead of separate enable/disable), so both enable and disable transitions are handled correctly on the fastset path.

> 
> >>   }
> >>   static
> >

✓ CI.KUnit: success for Enable CMRR in fixed-RR VRR path (rev5)

[Patchwork]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev5)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:57:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:57:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:57:41] Starting KUnit Kernel (1/1)...
[04:57:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:57:41] ================== guc_buf (11 subtests) ===================
[04:57:41] [PASSED] test_smallest
[04:57:41] [PASSED] test_largest
[04:57:41] [PASSED] test_granular
[04:57:41] [PASSED] test_unique
[04:57:41] [PASSED] test_overlap
[04:57:41] [PASSED] test_reusable
[04:57:41] [PASSED] test_too_big
[04:57:41] [PASSED] test_flush
[04:57:41] [PASSED] test_lookup
[04:57:41] [PASSED] test_data
[04:57:41] [PASSED] test_class
[04:57:41] ===================== [PASSED] guc_buf =====================
[04:57:41] =================== guc_dbm (7 subtests) ===================
[04:57:41] [PASSED] test_empty
[04:57:41] [PASSED] test_default
[04:57:41] ======================== test_size  ========================
[04:57:41] [PASSED] 4
[04:57:41] [PASSED] 8
[04:57:41] [PASSED] 32
[04:57:41] [PASSED] 256
[04:57:41] ==================== [PASSED] test_size ====================
[04:57:41] ======================= test_reuse  ========================
[04:57:41] [PASSED] 4
[04:57:41] [PASSED] 8
[04:57:41] [PASSED] 32
[04:57:41] [PASSED] 256
[04:57:41] =================== [PASSED] test_reuse ====================
[04:57:41] =================== test_range_overlap  ====================
[04:57:41] [PASSED] 4
[04:57:41] [PASSED] 8
[04:57:41] [PASSED] 32
[04:57:41] [PASSED] 256
[04:57:41] =============== [PASSED] test_range_overlap ================
[04:57:41] =================== test_range_compact  ====================
[04:57:41] [PASSED] 4
[04:57:41] [PASSED] 8
[04:57:41] [PASSED] 32
[04:57:41] [PASSED] 256
[04:57:41] =============== [PASSED] test_range_compact ================
[04:57:41] ==================== test_range_spare  =====================
[04:57:41] [PASSED] 4
[04:57:41] [PASSED] 8
[04:57:41] [PASSED] 32
[04:57:41] [PASSED] 256
[04:57:41] ================ [PASSED] test_range_spare =================
[04:57:41] ===================== [PASSED] guc_dbm =====================
[04:57:41] =================== guc_idm (6 subtests) ===================
[04:57:41] [PASSED] bad_init
[04:57:41] [PASSED] no_init
[04:57:41] [PASSED] init_fini
[04:57:41] [PASSED] check_used
[04:57:41] [PASSED] check_quota
[04:57:41] [PASSED] check_all
[04:57:41] ===================== [PASSED] guc_idm =====================
[04:57:41] =============== guc_klv_helpers (9 subtests) ===============
[04:57:41] [PASSED] test_count
[04:57:41] [PASSED] test_encode_u32
[04:57:41] [PASSED] test_encode_u64
[04:57:41] [PASSED] test_encode_string
[04:57:41] [PASSED] test_encode_object_raw
[04:57:41] [PASSED] test_encode_object_klv
[04:57:41] [PASSED] test_encode_object_nested
[04:57:41] [PASSED] test_encode_object_basic
[04:57:41] [PASSED] test_print
[04:57:41] ================= [PASSED] guc_klv_helpers =================
[04:57:41] ================== no_relay (3 subtests) ===================
[04:57:41] [PASSED] xe_drops_guc2pf_if_not_ready
[04:57:41] [PASSED] xe_drops_guc2vf_if_not_ready
[04:57:41] [PASSED] xe_rejects_send_if_not_ready
[04:57:41] ==================== [PASSED] no_relay =====================
[04:57:41] ================== pf_relay (14 subtests) ==================
[04:57:41] [PASSED] pf_rejects_guc2pf_too_short
[04:57:41] [PASSED] pf_rejects_guc2pf_too_long
[04:57:41] [PASSED] pf_rejects_guc2pf_no_payload
[04:57:41] [PASSED] pf_fails_no_payload
[04:57:41] [PASSED] pf_fails_bad_origin
[04:57:41] [PASSED] pf_fails_bad_type
[04:57:41] [PASSED] pf_txn_reports_error
[04:57:41] [PASSED] pf_txn_sends_pf2guc
[04:57:41] [PASSED] pf_sends_pf2guc
[04:57:41] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:57:41] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:57:41] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:57:41] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:57:41] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:57:41] ==================== [PASSED] pf_relay =====================
[04:57:41] ================== vf_relay (3 subtests) ===================
[04:57:41] [PASSED] vf_rejects_guc2vf_too_short
[04:57:41] [PASSED] vf_rejects_guc2vf_too_long
[04:57:41] [PASSED] vf_rejects_guc2vf_no_payload
[04:57:41] ==================== [PASSED] vf_relay =====================
[04:57:41] ================ pf_gt_config (9 subtests) =================
[04:57:41] [PASSED] fair_contexts_1vf
[04:57:41] [PASSED] fair_doorbells_1vf
[04:57:41] [PASSED] fair_ggtt_1vf
[04:57:41] ====================== fair_vram_1vf  ======================
[04:57:41] [PASSED] 3.50 GiB
[04:57:41] [PASSED] 11.5 GiB
[04:57:41] [PASSED] 15.5 GiB
[04:57:41] [PASSED] 31.5 GiB
[04:57:41] [PASSED] 63.5 GiB
[04:57:41] [PASSED] 1.91 GiB
[04:57:41] ================== [PASSED] fair_vram_1vf ==================
[04:57:41] ================ fair_vram_1vf_admin_only  =================
[04:57:41] [PASSED] 3.50 GiB
[04:57:41] [PASSED] 11.5 GiB
[04:57:41] [PASSED] 15.5 GiB
[04:57:41] [PASSED] 31.5 GiB
[04:57:41] [PASSED] 63.5 GiB
[04:57:41] [PASSED] 1.91 GiB
[04:57:41] ============ [PASSED] fair_vram_1vf_admin_only =============
[04:57:41] ====================== fair_contexts  ======================
[04:57:41] [PASSED] 1 VF
[04:57:41] [PASSED] 2 VFs
[04:57:41] [PASSED] 3 VFs
[04:57:41] [PASSED] 4 VFs
[04:57:41] [PASSED] 5 VFs
[04:57:41] [PASSED] 6 VFs
[04:57:41] [PASSED] 7 VFs
[04:57:41] [PASSED] 8 VFs
[04:57:41] [PASSED] 9 VFs
[04:57:41] [PASSED] 10 VFs
[04:57:41] [PASSED] 11 VFs
[04:57:41] [PASSED] 12 VFs
[04:57:41] [PASSED] 13 VFs
[04:57:41] [PASSED] 14 VFs
[04:57:41] [PASSED] 15 VFs
[04:57:41] [PASSED] 16 VFs
[04:57:41] [PASSED] 17 VFs
[04:57:41] [PASSED] 18 VFs
[04:57:41] [PASSED] 19 VFs
[04:57:41] [PASSED] 20 VFs
[04:57:41] [PASSED] 21 VFs
[04:57:41] [PASSED] 22 VFs
[04:57:41] [PASSED] 23 VFs
[04:57:41] [PASSED] 24 VFs
[04:57:41] [PASSED] 25 VFs
[04:57:41] [PASSED] 26 VFs
[04:57:41] [PASSED] 27 VFs
[04:57:41] [PASSED] 28 VFs
[04:57:41] [PASSED] 29 VFs
[04:57:41] [PASSED] 30 VFs
[04:57:41] [PASSED] 31 VFs
[04:57:41] [PASSED] 32 VFs
[04:57:41] [PASSED] 33 VFs
[04:57:41] [PASSED] 34 VFs
[04:57:41] [PASSED] 35 VFs
[04:57:41] [PASSED] 36 VFs
[04:57:41] [PASSED] 37 VFs
[04:57:41] [PASSED] 38 VFs
[04:57:41] [PASSED] 39 VFs
[04:57:41] [PASSED] 40 VFs
[04:57:41] [PASSED] 41 VFs
[04:57:41] [PASSED] 42 VFs
[04:57:41] [PASSED] 43 VFs
[04:57:41] [PASSED] 44 VFs
[04:57:41] [PASSED] 45 VFs
[04:57:41] [PASSED] 46 VFs
[04:57:41] [PASSED] 47 VFs
[04:57:41] [PASSED] 48 VFs
[04:57:41] [PASSED] 49 VFs
[04:57:41] [PASSED] 50 VFs
[04:57:41] [PASSED] 51 VFs
[04:57:41] [PASSED] 52 VFs
[04:57:41] [PASSED] 53 VFs
[04:57:41] [PASSED] 54 VFs
[04:57:41] [PASSED] 55 VFs
[04:57:41] [PASSED] 56 VFs
[04:57:41] [PASSED] 57 VFs
[04:57:41] [PASSED] 58 VFs
[04:57:41] [PASSED] 59 VFs
[04:57:41] [PASSED] 60 VFs
[04:57:41] [PASSED] 61 VFs
[04:57:41] [PASSED] 62 VFs
[04:57:41] [PASSED] 63 VFs
[04:57:41] ================== [PASSED] fair_contexts ==================
[04:57:41] ===================== fair_doorbells  ======================
[04:57:41] [PASSED] 1 VF
[04:57:41] [PASSED] 2 VFs
[04:57:41] [PASSED] 3 VFs
[04:57:41] [PASSED] 4 VFs
[04:57:41] [PASSED] 5 VFs
[04:57:41] [PASSED] 6 VFs
[04:57:41] [PASSED] 7 VFs
[04:57:41] [PASSED] 8 VFs
[04:57:41] [PASSED] 9 VFs
[04:57:41] [PASSED] 10 VFs
[04:57:41] [PASSED] 11 VFs
[04:57:41] [PASSED] 12 VFs
[04:57:41] [PASSED] 13 VFs
[04:57:41] [PASSED] 14 VFs
[04:57:41] [PASSED] 15 VFs
[04:57:41] [PASSED] 16 VFs
[04:57:41] [PASSED] 17 VFs
[04:57:41] [PASSED] 18 VFs
[04:57:41] [PASSED] 19 VFs
[04:57:41] [PASSED] 20 VFs
[04:57:41] [PASSED] 21 VFs
[04:57:41] [PASSED] 22 VFs
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[04:57:41] [PASSED] 24 VFs
[04:57:41] [PASSED] 25 VFs
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[04:57:41] [PASSED] 27 VFs
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[04:57:41] [PASSED] 29 VFs
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[04:57:41] [PASSED] 31 VFs
[04:57:41] [PASSED] 32 VFs
[04:57:41] [PASSED] 33 VFs
[04:57:41] [PASSED] 34 VFs
[04:57:41] [PASSED] 35 VFs
[04:57:41] [PASSED] 36 VFs
[04:57:41] [PASSED] 37 VFs
[04:57:41] [PASSED] 38 VFs
[04:57:41] [PASSED] 39 VFs
[04:57:41] [PASSED] 40 VFs
[04:57:41] [PASSED] 41 VFs
[04:57:41] [PASSED] 42 VFs
[04:57:41] [PASSED] 43 VFs
[04:57:41] [PASSED] 44 VFs
[04:57:41] [PASSED] 45 VFs
[04:57:41] [PASSED] 46 VFs
[04:57:41] [PASSED] 47 VFs
[04:57:41] [PASSED] 48 VFs
[04:57:41] [PASSED] 49 VFs
[04:57:41] [PASSED] 50 VFs
[04:57:41] [PASSED] 51 VFs
[04:57:41] [PASSED] 52 VFs
[04:57:41] [PASSED] 53 VFs
[04:57:41] [PASSED] 54 VFs
[04:57:41] [PASSED] 55 VFs
[04:57:41] [PASSED] 56 VFs
[04:57:41] [PASSED] 57 VFs
[04:57:41] [PASSED] 58 VFs
[04:57:41] [PASSED] 59 VFs
[04:57:41] [PASSED] 60 VFs
[04:57:41] [PASSED] 61 VFs
[04:57:41] [PASSED] 62 VFs
[04:57:41] [PASSED] 63 VFs
[04:57:41] ================= [PASSED] fair_doorbells ==================
[04:57:41] ======================== fair_ggtt  ========================
[04:57:41] [PASSED] 1 VF
[04:57:41] [PASSED] 2 VFs
[04:57:41] [PASSED] 3 VFs
[04:57:41] [PASSED] 4 VFs
[04:57:41] [PASSED] 5 VFs
[04:57:41] [PASSED] 6 VFs
[04:57:41] [PASSED] 7 VFs
[04:57:41] [PASSED] 8 VFs
[04:57:41] [PASSED] 9 VFs
[04:57:41] [PASSED] 10 VFs
[04:57:41] [PASSED] 11 VFs
[04:57:41] [PASSED] 12 VFs
[04:57:41] [PASSED] 13 VFs
[04:57:41] [PASSED] 14 VFs
[04:57:41] [PASSED] 15 VFs
[04:57:41] [PASSED] 16 VFs
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[04:57:41] [PASSED] 18 VFs
[04:57:41] [PASSED] 19 VFs
[04:57:41] [PASSED] 20 VFs
[04:57:41] [PASSED] 21 VFs
[04:57:41] [PASSED] 22 VFs
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[04:57:41] [PASSED] 24 VFs
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[04:57:41] [PASSED] 26 VFs
[04:57:41] [PASSED] 27 VFs
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[04:57:41] [PASSED] 33 VFs
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[04:57:41] [PASSED] 35 VFs
[04:57:41] [PASSED] 36 VFs
[04:57:41] [PASSED] 37 VFs
[04:57:41] [PASSED] 38 VFs
[04:57:41] [PASSED] 39 VFs
[04:57:41] [PASSED] 40 VFs
[04:57:41] [PASSED] 41 VFs
[04:57:41] [PASSED] 42 VFs
[04:57:41] [PASSED] 43 VFs
[04:57:41] [PASSED] 44 VFs
[04:57:41] [PASSED] 45 VFs
[04:57:41] [PASSED] 46 VFs
[04:57:41] [PASSED] 47 VFs
[04:57:41] [PASSED] 48 VFs
[04:57:41] [PASSED] 49 VFs
[04:57:41] [PASSED] 50 VFs
[04:57:41] [PASSED] 51 VFs
[04:57:41] [PASSED] 52 VFs
[04:57:41] [PASSED] 53 VFs
[04:57:41] [PASSED] 54 VFs
[04:57:41] [PASSED] 55 VFs
[04:57:41] [PASSED] 56 VFs
[04:57:41] [PASSED] 57 VFs
[04:57:41] [PASSED] 58 VFs
[04:57:41] [PASSED] 59 VFs
[04:57:41] [PASSED] 60 VFs
[04:57:41] [PASSED] 61 VFs
[04:57:41] [PASSED] 62 VFs
[04:57:41] [PASSED] 63 VFs
[04:57:41] ==================== [PASSED] fair_ggtt ====================
[04:57:41] ======================== fair_vram  ========================
[04:57:41] [PASSED] 1 VF
[04:57:41] [PASSED] 2 VFs
[04:57:41] [PASSED] 3 VFs
[04:57:41] [PASSED] 4 VFs
[04:57:41] [PASSED] 5 VFs
[04:57:41] [PASSED] 6 VFs
[04:57:41] [PASSED] 7 VFs
[04:57:41] [PASSED] 8 VFs
[04:57:41] [PASSED] 9 VFs
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[04:57:41] [PASSED] 11 VFs
[04:57:41] [PASSED] 12 VFs
[04:57:41] [PASSED] 13 VFs
[04:57:41] [PASSED] 14 VFs
[04:57:41] [PASSED] 15 VFs
[04:57:41] [PASSED] 16 VFs
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[04:57:41] [PASSED] 18 VFs
[04:57:41] [PASSED] 19 VFs
[04:57:41] [PASSED] 20 VFs
[04:57:41] [PASSED] 21 VFs
[04:57:41] [PASSED] 22 VFs
[04:57:41] [PASSED] 23 VFs
[04:57:41] [PASSED] 24 VFs
[04:57:41] [PASSED] 25 VFs
[04:57:41] [PASSED] 26 VFs
[04:57:41] [PASSED] 27 VFs
[04:57:41] [PASSED] 28 VFs
[04:57:41] [PASSED] 29 VFs
[04:57:41] [PASSED] 30 VFs
[04:57:41] [PASSED] 31 VFs
[04:57:41] [PASSED] 32 VFs
[04:57:41] [PASSED] 33 VFs
[04:57:41] [PASSED] 34 VFs
[04:57:41] [PASSED] 35 VFs
[04:57:41] [PASSED] 36 VFs
[04:57:41] [PASSED] 37 VFs
[04:57:41] [PASSED] 38 VFs
[04:57:41] [PASSED] 39 VFs
[04:57:41] [PASSED] 40 VFs
[04:57:41] [PASSED] 41 VFs
[04:57:41] [PASSED] 42 VFs
[04:57:41] [PASSED] 43 VFs
[04:57:41] [PASSED] 44 VFs
[04:57:41] [PASSED] 45 VFs
[04:57:41] [PASSED] 46 VFs
[04:57:41] [PASSED] 47 VFs
[04:57:41] [PASSED] 48 VFs
[04:57:41] [PASSED] 49 VFs
[04:57:41] [PASSED] 50 VFs
[04:57:41] [PASSED] 51 VFs
[04:57:41] [PASSED] 52 VFs
[04:57:41] [PASSED] 53 VFs
[04:57:41] [PASSED] 54 VFs
[04:57:41] [PASSED] 55 VFs
[04:57:41] [PASSED] 56 VFs
[04:57:41] [PASSED] 57 VFs
[04:57:41] [PASSED] 58 VFs
[04:57:41] [PASSED] 59 VFs
[04:57:41] [PASSED] 60 VFs
[04:57:41] [PASSED] 61 VFs
[04:57:41] [PASSED] 62 VFs
[04:57:41] [PASSED] 63 VFs
[04:57:41] ==================== [PASSED] fair_vram ====================
[04:57:41] ================== [PASSED] pf_gt_config ===================
[04:57:41] ===================== lmtt (1 subtest) =====================
[04:57:41] ======================== test_ops  =========================
[04:57:41] [PASSED] 2-level
[04:57:41] [PASSED] multi-level
[04:57:41] ==================== [PASSED] test_ops =====================
[04:57:41] ====================== [PASSED] lmtt =======================
[04:57:41] ================= sriov_packet (1 subtest) =================
[04:57:41] [PASSED] test_descriptor_init
[04:57:41] ================== [PASSED] sriov_packet ===================
[04:57:41] ================= pf_service (11 subtests) =================
[04:57:41] [PASSED] pf_negotiate_any
[04:57:41] [PASSED] pf_negotiate_base_match
[04:57:41] [PASSED] pf_negotiate_base_newer
[04:57:41] [PASSED] pf_negotiate_base_next
[04:57:41] [SKIPPED] pf_negotiate_base_older (no older minor)
[04:57:41] [PASSED] pf_negotiate_base_prev
[04:57:41] [PASSED] pf_negotiate_latest_match
[04:57:41] [PASSED] pf_negotiate_latest_newer
[04:57:41] [PASSED] pf_negotiate_latest_next
[04:57:41] [SKIPPED] pf_negotiate_latest_older (no older minor)
[04:57:41] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[04:57:41] =================== [PASSED] pf_service ====================
[04:57:41] ================= xe_guc_g2g (2 subtests) ==================
[04:57:41] ============== xe_live_guc_g2g_kunit_default  ==============
[04:57:41] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:57:41] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:57:41] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:57:41] =================== [SKIPPED] xe_guc_g2g ===================
[04:57:41] =================== xe_mocs (2 subtests) ===================
[04:57:41] ================ xe_live_mocs_kernel_kunit  ================
[04:57:41] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:57:41] ================ xe_live_mocs_reset_kunit  =================
[04:57:41] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:57:41] ==================== [SKIPPED] xe_mocs =====================
[04:57:41] ================= xe_migrate (2 subtests) ==================
[04:57:41] ================= xe_migrate_sanity_kunit  =================
[04:57:41] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:57:41] ================== xe_validate_ccs_kunit  ==================
[04:57:41] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:57:41] =================== [SKIPPED] xe_migrate ===================
[04:57:41] ================== xe_dma_buf (1 subtest) ==================
[04:57:41] ==================== xe_dma_buf_kunit  =====================
[04:57:41] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:57:41] =================== [SKIPPED] xe_dma_buf ===================
[04:57:41] ================= xe_bo_shrink (1 subtest) =================
[04:57:41] =================== xe_bo_shrink_kunit  ====================
[04:57:41] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:57:41] ================== [SKIPPED] xe_bo_shrink ==================
[04:57:41] ==================== xe_bo (2 subtests) ====================
[04:57:41] ================== xe_ccs_migrate_kunit  ===================
[04:57:41] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:57:41] ==================== xe_bo_evict_kunit  ====================
[04:57:41] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:57:41] ===================== [SKIPPED] xe_bo ======================
[04:57:41] ==================== args (13 subtests) ====================
[04:57:41] [PASSED] count_args_test
[04:57:41] [PASSED] call_args_example
[04:57:41] [PASSED] call_args_test
[04:57:41] [PASSED] drop_first_arg_example
[04:57:41] [PASSED] drop_first_arg_test
[04:57:41] [PASSED] first_arg_example
[04:57:41] [PASSED] first_arg_test
[04:57:41] [PASSED] last_arg_example
[04:57:41] [PASSED] last_arg_test
[04:57:41] [PASSED] pick_arg_example
[04:57:41] [PASSED] if_args_example
[04:57:41] [PASSED] if_args_test
[04:57:41] [PASSED] sep_comma_example
[04:57:41] ====================== [PASSED] args =======================
[04:57:41] =================== xe_pci (3 subtests) ====================
[04:57:41] ==================== check_graphics_ip  ====================
[04:57:41] [PASSED] 12.00 Xe_LP
[04:57:41] [PASSED] 12.10 Xe_LP+
[04:57:41] [PASSED] 12.55 Xe_HPG
[04:57:41] [PASSED] 12.60 Xe_HPC
[04:57:41] [PASSED] 12.70 Xe_LPG
[04:57:41] [PASSED] 12.71 Xe_LPG
[04:57:41] [PASSED] 12.74 Xe_LPG+
[04:57:41] [PASSED] 20.01 Xe2_HPG
[04:57:41] [PASSED] 20.02 Xe2_HPG
[04:57:41] [PASSED] 20.04 Xe2_LPG
[04:57:41] [PASSED] 30.00 Xe3_LPG
[04:57:41] [PASSED] 30.01 Xe3_LPG
[04:57:41] [PASSED] 30.03 Xe3_LPG
[04:57:41] [PASSED] 30.04 Xe3_LPG
[04:57:41] [PASSED] 30.05 Xe3_LPG
[04:57:41] [PASSED] 35.10 Xe3p_LPG
[04:57:41] [PASSED] 35.11 Xe3p_XPC
[04:57:41] ================ [PASSED] check_graphics_ip ================
[04:57:41] ===================== check_media_ip  ======================
[04:57:41] [PASSED] 12.00 Xe_M
[04:57:41] [PASSED] 12.55 Xe_HPM
[04:57:41] [PASSED] 13.00 Xe_LPM+
[04:57:41] [PASSED] 13.01 Xe2_HPM
[04:57:41] [PASSED] 20.00 Xe2_LPM
[04:57:41] [PASSED] 30.00 Xe3_LPM
[04:57:41] [PASSED] 30.02 Xe3_LPM
[04:57:41] [PASSED] 35.00 Xe3p_LPM
[04:57:41] [PASSED] 35.03 Xe3p_HPM
[04:57:41] ================= [PASSED] check_media_ip ==================
[04:57:41] =================== check_platform_desc  ===================
[04:57:41] [PASSED] 0x9A60 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A68 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A70 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A40 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A49 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A59 (TIGERLAKE)
[04:57:41] [PASSED] 0x9A78 (TIGERLAKE)
[04:57:41] [PASSED] 0x9AC0 (TIGERLAKE)
[04:57:41] [PASSED] 0x9AC9 (TIGERLAKE)
[04:57:41] [PASSED] 0x9AD9 (TIGERLAKE)
[04:57:41] [PASSED] 0x9AF8 (TIGERLAKE)
[04:57:41] [PASSED] 0x4C80 (ROCKETLAKE)
[04:57:41] [PASSED] 0x4C8A (ROCKETLAKE)
[04:57:41] [PASSED] 0x4C8B (ROCKETLAKE)
[04:57:41] [PASSED] 0x4C8C (ROCKETLAKE)
[04:57:41] [PASSED] 0x4C90 (ROCKETLAKE)
[04:57:41] [PASSED] 0x4C9A (ROCKETLAKE)
[04:57:41] [PASSED] 0x4680 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4682 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4688 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x468A (ALDERLAKE_S)
[04:57:41] [PASSED] 0x468B (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4690 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4692 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4693 (ALDERLAKE_S)
[04:57:41] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46AA (ALDERLAKE_P)
[04:57:41] [PASSED] 0x462A (ALDERLAKE_P)
[04:57:41] [PASSED] 0x4626 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x4628 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:57:41] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:57:41] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:57:41] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:57:41] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:57:41] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:57:41] [PASSED] 0xA721 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA720 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:57:41] [PASSED] 0xA780 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA781 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA782 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA783 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA788 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA789 (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA78A (ALDERLAKE_S)
[04:57:41] [PASSED] 0xA78B (ALDERLAKE_S)
[04:57:41] [PASSED] 0x4905 (DG1)
[04:57:41] [PASSED] 0x4906 (DG1)
[04:57:41] [PASSED] 0x4907 (DG1)
[04:57:41] [PASSED] 0x4908 (DG1)
[04:57:41] [PASSED] 0x4909 (DG1)
[04:57:41] [PASSED] 0x56C0 (DG2)
[04:57:41] [PASSED] 0x56C2 (DG2)
[04:57:41] [PASSED] 0x56C1 (DG2)
[04:57:41] [PASSED] 0x7D51 (METEORLAKE)
[04:57:41] [PASSED] 0x7DD1 (METEORLAKE)
[04:57:41] [PASSED] 0x7D41 (METEORLAKE)
[04:57:41] [PASSED] 0x7D67 (METEORLAKE)
[04:57:41] [PASSED] 0xB640 (METEORLAKE)
[04:57:41] [PASSED] 0x56A0 (DG2)
[04:57:41] [PASSED] 0x56A1 (DG2)
[04:57:41] [PASSED] 0x56A2 (DG2)
[04:57:41] [PASSED] 0x56BE (DG2)
[04:57:41] [PASSED] 0x56BF (DG2)
[04:57:41] [PASSED] 0x5690 (DG2)
[04:57:41] [PASSED] 0x5691 (DG2)
[04:57:41] [PASSED] 0x5692 (DG2)
[04:57:41] [PASSED] 0x56A5 (DG2)
[04:57:41] [PASSED] 0x56A6 (DG2)
[04:57:41] [PASSED] 0x56B0 (DG2)
[04:57:41] [PASSED] 0x56B1 (DG2)
[04:57:41] [PASSED] 0x56BA (DG2)
[04:57:41] [PASSED] 0x56BB (DG2)
[04:57:41] [PASSED] 0x56BC (DG2)
[04:57:41] [PASSED] 0x56BD (DG2)
[04:57:41] [PASSED] 0x5693 (DG2)
[04:57:41] [PASSED] 0x5694 (DG2)
[04:57:41] [PASSED] 0x5695 (DG2)
[04:57:41] [PASSED] 0x56A3 (DG2)
[04:57:41] [PASSED] 0x56A4 (DG2)
[04:57:41] [PASSED] 0x56B2 (DG2)
[04:57:41] [PASSED] 0x56B3 (DG2)
[04:57:41] [PASSED] 0x5696 (DG2)
[04:57:41] [PASSED] 0x5697 (DG2)
[04:57:41] [PASSED] 0xB69 (PVC)
[04:57:41] [PASSED] 0xB6E (PVC)
[04:57:41] [PASSED] 0xBD4 (PVC)
[04:57:41] [PASSED] 0xBD5 (PVC)
[04:57:41] [PASSED] 0xBD6 (PVC)
[04:57:41] [PASSED] 0xBD7 (PVC)
[04:57:41] [PASSED] 0xBD8 (PVC)
[04:57:41] [PASSED] 0xBD9 (PVC)
[04:57:41] [PASSED] 0xBDA (PVC)
[04:57:41] [PASSED] 0xBDB (PVC)
[04:57:41] [PASSED] 0xBE0 (PVC)
[04:57:41] [PASSED] 0xBE1 (PVC)
[04:57:41] [PASSED] 0xBE5 (PVC)
[04:57:41] [PASSED] 0x7D40 (METEORLAKE)
[04:57:41] [PASSED] 0x7D45 (METEORLAKE)
[04:57:41] [PASSED] 0x7D55 (METEORLAKE)
[04:57:41] [PASSED] 0x7D60 (METEORLAKE)
[04:57:41] [PASSED] 0x7DD5 (METEORLAKE)
[04:57:41] [PASSED] 0x6420 (LUNARLAKE)
[04:57:41] [PASSED] 0x64A0 (LUNARLAKE)
[04:57:41] [PASSED] 0x64B0 (LUNARLAKE)
[04:57:41] [PASSED] 0xE202 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE209 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE20B (BATTLEMAGE)
[04:57:41] [PASSED] 0xE20C (BATTLEMAGE)
[04:57:41] [PASSED] 0xE20D (BATTLEMAGE)
[04:57:41] [PASSED] 0xE210 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE211 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE212 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE216 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE220 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE221 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE222 (BATTLEMAGE)
[04:57:41] [PASSED] 0xE223 (BATTLEMAGE)
[04:57:41] [PASSED] 0xB080 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB081 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB082 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB083 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB084 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB085 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB086 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB087 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB08F (PANTHERLAKE)
[04:57:41] [PASSED] 0xB090 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:57:41] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:57:41] [PASSED] 0xFD80 (PANTHERLAKE)
[04:57:41] [PASSED] 0xFD81 (PANTHERLAKE)
[04:57:41] [PASSED] 0xD740 (NOVALAKE_S)
[04:57:41] [PASSED] 0xD741 (NOVALAKE_S)
[04:57:41] [PASSED] 0xD742 (NOVALAKE_S)
[04:57:41] [PASSED] 0xD743 (NOVALAKE_S)
[04:57:41] [PASSED] 0xD745 (NOVALAKE_S)
[04:57:41] [PASSED] 0xD74A (NOVALAKE_S)
[04:57:41] [PASSED] 0xD74B (NOVALAKE_S)
[04:57:41] [PASSED] 0x674C (CRESCENTISLAND)
[04:57:41] [PASSED] 0x674D (CRESCENTISLAND)
[04:57:41] [PASSED] 0x674E (CRESCENTISLAND)
[04:57:41] [PASSED] 0x674F (CRESCENTISLAND)
[04:57:41] [PASSED] 0x6750 (CRESCENTISLAND)
[04:57:41] [PASSED] 0xD750 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD751 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD752 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD753 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD754 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD755 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD756 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD757 (NOVALAKE_P)
[04:57:41] [PASSED] 0xD75F (NOVALAKE_P)
[04:57:41] =============== [PASSED] check_platform_desc ===============
[04:57:41] ===================== [PASSED] xe_pci ======================
[04:57:41] ============= xe_rtp_tables_test (5 subtests) ==============
[04:57:41] ================== xe_rtp_table_gt_test  ===================
[04:57:41] [PASSED] gt_was/14011060649
[04:57:41] [PASSED] gt_was/14011059788
[04:57:41] [PASSED] gt_was/14015795083
[04:57:41] [PASSED] gt_was/16021867713
[04:57:41] [PASSED] gt_was/14019449301
[04:57:41] [PASSED] gt_was/16028005424
[04:57:41] [PASSED] gt_was/14026578760
[04:57:41] [PASSED] gt_was/1409420604
[04:57:41] [PASSED] gt_was/1408615072
[04:57:41] [PASSED] gt_was/22010523718
[04:57:41] [PASSED] gt_was/14011006942
[04:57:41] [PASSED] gt_was/14014830051
[04:57:41] [PASSED] gt_was/18018781329
[04:57:41] [PASSED] gt_was/1509235366
[04:57:41] [PASSED] gt_was/18018781329
[04:57:41] [PASSED] gt_was/16016694945
[04:57:41] [PASSED] gt_was/14018575942
[04:57:41] [PASSED] gt_was/22016670082
[04:57:41] [PASSED] gt_was/22016670082
[04:57:41] [PASSED] gt_was/14017421178
[04:57:41] [PASSED] gt_was/16025250150
[04:57:41] [PASSED] gt_was/14021871409
[04:57:41] [PASSED] gt_was/16021865536
[04:57:41] [PASSED] gt_was/14021486841
[04:57:41] [PASSED] gt_was/14025160223
[04:57:41] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[04:57:41] [PASSED] gt_was/14025635424
[04:57:41] [PASSED] gt_was/16028005424
[04:57:41] ============== [PASSED] xe_rtp_table_gt_test ===============
[04:57:41] ================== xe_rtp_table_gt_test  ===================
[04:57:41] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[04:57:41] [PASSED] gt_tunings/Tuning: 32B Access Enable
[04:57:41] [PASSED] gt_tunings/Tuning: L3 cache
[04:57:41] [PASSED] gt_tunings/Tuning: L3 cache - media
[04:57:41] [PASSED] gt_tunings/Tuning: Compression Overfetch
[04:57:41] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[04:57:41] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[04:57:41] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[04:57:41] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[04:57:41] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[04:57:41] [PASSED] gt_tunings/Tuning: Stateless compression control
[04:57:41] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[04:57:41] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[04:57:41] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[04:57:41] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[04:57:41] ============== [PASSED] xe_rtp_table_gt_test ===============
[04:57:41] ================== xe_rtp_table_oob_test  ==================
[04:57:41] [PASSED] oob_was/1607983814
[04:57:41] [PASSED] oob_was/16010904313
[04:57:41] [PASSED] oob_was/18022495364
[04:57:41] [PASSED] oob_was/22012773006
[04:57:41] [PASSED] oob_was/14014475959
[04:57:41] [PASSED] oob_was/22011391025
[04:57:41] [PASSED] oob_was/22012727170
[04:57:41] [PASSED] oob_was/22012727685
[04:57:41] [PASSED] oob_was/22016596838
[04:57:41] [PASSED] oob_was/18020744125
[04:57:41] [PASSED] oob_was/1409600907
[04:57:41] [PASSED] oob_was/22014953428
[04:57:41] [PASSED] oob_was/16017236439
[04:57:41] [PASSED] oob_was/14019821291
[04:57:41] [PASSED] oob_was/14015076503
[04:57:41] [PASSED] oob_was/14018913170
[04:57:41] [PASSED] oob_was/14018094691
[04:57:41] [PASSED] oob_was/18024947630
[04:57:41] [PASSED] oob_was/16022287689
[04:57:41] [PASSED] oob_was/13011645652
[04:57:41] [PASSED] oob_was/14022293748
[04:57:41] [PASSED] oob_was/22019794406
[04:57:41] [PASSED] oob_was/22019338487
[04:57:41] [PASSED] oob_was/16023588340
[04:57:41] [PASSED] oob_was/14019789679
[04:57:41] [PASSED] oob_was/14022866841
[04:57:41] [PASSED] oob_was/16021333562
[04:57:41] [PASSED] oob_was/14016712196
[04:57:41] [PASSED] oob_was/14015568240
[04:57:41] [PASSED] oob_was/18013179988
[04:57:41] [PASSED] oob_was/1508761755
[04:57:41] [PASSED] oob_was/16023105232
[04:57:41] [PASSED] oob_was/16026508708
[04:57:41] [PASSED] oob_was/14020001231
[04:57:41] [PASSED] oob_was/16023683509
[04:57:41] [PASSED] oob_was/14025515070
[04:57:41] [PASSED] oob_was/15015404425_disable
[04:57:41] [PASSED] oob_was/16026007364
[04:57:41] [PASSED] oob_was/14020316580
[04:57:41] [PASSED] oob_was/14025883347
[04:57:41] [PASSED] oob_was/16029380221
[04:57:41] [PASSED] oob_was/22022079272
[04:57:41] [PASSED] oob_was/16029897822
[04:57:41] ============== [PASSED] xe_rtp_table_oob_test ==============
[04:57:41] ================ xe_rtp_table_dev_oob_test  ================
[04:57:41] [PASSED] device_oob_was/22010954014
[04:57:41] [PASSED] device_oob_was/15015404425
[04:57:41] [PASSED] device_oob_was/22019338487_display
[04:57:41] [PASSED] device_oob_was/14022085890
[04:57:41] [PASSED] device_oob_was/14026539277
[04:57:41] [PASSED] device_oob_was/14026633728
[04:57:41] [PASSED] device_oob_was/14026746987
[04:57:41] [PASSED] device_oob_was/14026779378
[04:57:41] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[04:57:41] ========== xe_rtp_table_missing_upper_bound_test  ==========
[04:57:41] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[04:57:41] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[04:57:41] [PASSED] register_whitelist/1806527549
[04:57:41] [PASSED] register_whitelist/allow_read_ctx_timestamp
[04:57:41] [PASSED] register_whitelist/allow_read_queue_timestamp
[04:57:41] [PASSED] register_whitelist/16014440446
[04:57:41] [PASSED] register_whitelist/16017236439
[04:57:41] [PASSED] register_whitelist/16020183090
[04:57:41] [PASSED] register_whitelist/14024997852
[04:57:41] [PASSED] register_whitelist/14024997852
[04:57:41] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[04:57:41] =============== [PASSED] xe_rtp_tables_test ================
[04:57:41] =================== xe_rtp (3 subtests) ====================
[04:57:41] =================== xe_rtp_rules_tests  ====================
[04:57:41] [PASSED] no
[04:57:41] [PASSED] yes
[04:57:41] [PASSED] no-and-no
[04:57:41] [PASSED] no-and-yes
[04:57:41] [PASSED] yes-and-no
[04:57:41] [PASSED] yes-and-yes
[04:57:41] [PASSED] no-or-no
[04:57:41] [PASSED] no-or-yes
[04:57:41] [PASSED] yes-or-no
[04:57:41] [PASSED] yes-or-yes
[04:57:41] [PASSED] no-yes-or-yes-no
[04:57:41] [PASSED] no-yes-or-yes-yes
[04:57:41] [PASSED] yes-yes-or-no-yes
[04:57:41] [PASSED] yes-yes-or-yes-yes
[04:57:41] [PASSED] no-no-or-yes-or-no
[04:57:41] [PASSED] or
[04:57:41] [PASSED] or-yes
[04:57:41] [PASSED] or-no
[04:57:41] [PASSED] yes-or
[04:57:41] [PASSED] no-or
[04:57:41] [PASSED] no-or-or-yes
[04:57:41] [PASSED] yes-or-or-no
[04:57:41] [PASSED] no-or-or-no
[04:57:41] [PASSED] missing-context-engine-class
[04:57:41] [PASSED] missing-context-engine-class-or-yes
[04:57:41] [PASSED] missing-context-engine-class-or-or-yes
[04:57:41] =============== [PASSED] xe_rtp_rules_tests ================
[04:57:41] =============== xe_rtp_process_to_sr_tests  ================
[04:57:41] [PASSED] coalesce-same-reg
[04:57:41] [PASSED] coalesce-same-reg-literal-and-func
[04:57:41] [PASSED] no-match-no-add
[04:57:41] [PASSED] two-regs-two-entries
[04:57:41] [PASSED] clr-one-set-other
[04:57:41] [PASSED] set-field
[04:57:41] [PASSED] conflict-duplicate
[04:57:41] [PASSED] conflict-not-disjoint
[04:57:41] [PASSED] conflict-not-disjoint-literal-and-func
[04:57:41] [PASSED] conflict-reg-type
[04:57:41] [PASSED] bad-mcr-reg-forced-to-regular
[04:57:41] [PASSED] bad-regular-reg-forced-to-mcr
[04:57:41] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:57:41] ================== xe_rtp_process_tests  ===================
[04:57:41] [PASSED] active1
[04:57:41] [PASSED] active2
[04:57:41] [PASSED] active-inactive
[04:57:41] [PASSED] inactive-active
[04:57:41] [PASSED] inactive-active-inactive
[04:57:41] [PASSED] inactive-inactive-inactive
[04:57:41] ============== [PASSED] xe_rtp_process_tests ===============
[04:57:41] ===================== [PASSED] xe_rtp ======================
[04:57:41] ==================== xe_wa (1 subtest) =====================
[04:57:41] ======================== xe_wa_gt  =========================
[04:57:41] [PASSED] TIGERLAKE B0
[04:57:41] [PASSED] DG1 A0
[04:57:41] [PASSED] DG1 B0
[04:57:41] [PASSED] ALDERLAKE_S A0
[04:57:41] [PASSED] ALDERLAKE_S B0
[04:57:41] [PASSED] ALDERLAKE_S C0
[04:57:41] [PASSED] ALDERLAKE_S D0
[04:57:41] [PASSED] ALDERLAKE_P A0
[04:57:41] [PASSED] ALDERLAKE_P B0
[04:57:41] [PASSED] ALDERLAKE_P C0
[04:57:41] [PASSED] ALDERLAKE_S RPLS D0
[04:57:41] [PASSED] ALDERLAKE_P RPLU E0
[04:57:41] [PASSED] DG2 G10 C0
[04:57:41] [PASSED] DG2 G11 B1
[04:57:41] [PASSED] DG2 G12 A1
[04:57:41] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:57:41] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:57:41] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:57:41] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:57:41] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:57:41] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:57:41] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:57:41] ==================== [PASSED] xe_wa_gt =====================
[04:57:41] ====================== [PASSED] xe_wa ======================
[04:57:41] ============================================================
[04:57:41] Testing complete. Ran 741 tests: passed: 723, skipped: 18
[04:57:41] Elapsed time: 36.712s total, 4.362s configuring, 31.684s building, 0.648s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:57:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:57:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:58:08] Starting KUnit Kernel (1/1)...
[04:58:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:58:08] ============ drm_test_pick_cmdline (2 subtests) ============
[04:58:08] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:58:08] =============== drm_test_pick_cmdline_named  ===============
[04:58:08] [PASSED] NTSC
[04:58:08] [PASSED] NTSC-J
[04:58:08] [PASSED] PAL
[04:58:08] [PASSED] PAL-M
[04:58:08] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:58:08] ============== [PASSED] drm_test_pick_cmdline ==============
[04:58:08] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:58:08] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:58:08] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:58:08] =========== drm_validate_clone_mode (2 subtests) ===========
[04:58:08] ============== drm_test_check_in_clone_mode  ===============
[04:58:08] [PASSED] in_clone_mode
[04:58:08] [PASSED] not_in_clone_mode
[04:58:08] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:58:08] =============== drm_test_check_valid_clones  ===============
[04:58:08] [PASSED] not_in_clone_mode
[04:58:08] [PASSED] valid_clone
[04:58:08] [PASSED] invalid_clone
[04:58:08] =========== [PASSED] drm_test_check_valid_clones ===========
[04:58:08] ============= [PASSED] drm_validate_clone_mode =============
[04:58:08] ============= drm_validate_modeset (1 subtest) =============
[04:58:08] [PASSED] drm_test_check_connector_changed_modeset
[04:58:08] ============== [PASSED] drm_validate_modeset ===============
[04:58:08] ====== drm_test_bridge_get_current_state (1 subtest) =======
[04:58:08] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:58:08] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:58:08] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:58:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:58:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:58:08] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[04:58:08] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:58:08] ============== drm_bridge_alloc (2 subtests) ===============
[04:58:08] [PASSED] drm_test_drm_bridge_alloc_basic
[04:58:08] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:58:08] ================ [PASSED] drm_bridge_alloc =================
[04:58:08] ============= drm_bridge_bus_fmt (5 subtests) ==============
[04:58:08] [PASSED] drm_test_bridge_rgb_yuv_rgb
[04:58:08] [PASSED] drm_test_bridge_must_convert_to_yuv444
[04:58:08] [PASSED] drm_test_bridge_hdmi_auto_rgb
[04:58:08] [PASSED] drm_test_bridge_auto_first
[04:58:08] [PASSED] drm_test_bridge_rgb_yuv_no_path
[04:58:08] =============== [PASSED] drm_bridge_bus_fmt ================
[04:58:08] ============= drm_cmdline_parser (40 subtests) =============
[04:58:08] [PASSED] drm_test_cmdline_force_d_only
[04:58:08] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:58:08] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:58:08] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:58:08] [PASSED] drm_test_cmdline_force_e_only
[04:58:08] [PASSED] drm_test_cmdline_res
[04:58:08] [PASSED] drm_test_cmdline_res_vesa
[04:58:08] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:58:08] [PASSED] drm_test_cmdline_res_rblank
[04:58:08] [PASSED] drm_test_cmdline_res_bpp
[04:58:08] [PASSED] drm_test_cmdline_res_refresh
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:58:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:58:08] [PASSED] drm_test_cmdline_res_margins_force_on
[04:58:08] [PASSED] drm_test_cmdline_res_vesa_margins
[04:58:08] [PASSED] drm_test_cmdline_name
[04:58:08] [PASSED] drm_test_cmdline_name_bpp
[04:58:08] [PASSED] drm_test_cmdline_name_option
[04:58:08] [PASSED] drm_test_cmdline_name_bpp_option
[04:58:08] [PASSED] drm_test_cmdline_rotate_0
[04:58:08] [PASSED] drm_test_cmdline_rotate_90
[04:58:08] [PASSED] drm_test_cmdline_rotate_180
[04:58:08] [PASSED] drm_test_cmdline_rotate_270
[04:58:08] [PASSED] drm_test_cmdline_hmirror
[04:58:08] [PASSED] drm_test_cmdline_vmirror
[04:58:08] [PASSED] drm_test_cmdline_margin_options
[04:58:08] [PASSED] drm_test_cmdline_multiple_options
[04:58:08] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:58:08] [PASSED] drm_test_cmdline_extra_and_option
[04:58:08] [PASSED] drm_test_cmdline_freestanding_options
[04:58:08] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:58:08] [PASSED] drm_test_cmdline_panel_orientation
[04:58:08] ================ drm_test_cmdline_invalid  =================
[04:58:08] [PASSED] margin_only
[04:58:08] [PASSED] interlace_only
[04:58:08] [PASSED] res_missing_x
[04:58:08] [PASSED] res_missing_y
[04:58:08] [PASSED] res_bad_y
[04:58:08] [PASSED] res_missing_y_bpp
[04:58:08] [PASSED] res_bad_bpp
[04:58:08] [PASSED] res_bad_refresh
[04:58:08] [PASSED] res_bpp_refresh_force_on_off
[04:58:08] [PASSED] res_invalid_mode
[04:58:08] [PASSED] res_bpp_wrong_place_mode
[04:58:08] [PASSED] name_bpp_refresh
[04:58:08] [PASSED] name_refresh
[04:58:08] [PASSED] name_refresh_wrong_mode
[04:58:08] [PASSED] name_refresh_invalid_mode
[04:58:08] [PASSED] rotate_multiple
[04:58:08] [PASSED] rotate_invalid_val
[04:58:08] [PASSED] rotate_truncated
[04:58:08] [PASSED] invalid_option
[04:58:08] [PASSED] invalid_tv_option
[04:58:08] [PASSED] truncated_tv_option
[04:58:08] ============ [PASSED] drm_test_cmdline_invalid =============
[04:58:08] =============== drm_test_cmdline_tv_options  ===============
[04:58:08] [PASSED] NTSC
[04:58:08] [PASSED] NTSC_443
[04:58:08] [PASSED] NTSC_J
[04:58:08] [PASSED] PAL
[04:58:08] [PASSED] PAL_M
[04:58:08] [PASSED] PAL_N
[04:58:08] [PASSED] SECAM
[04:58:08] [PASSED] MONO_525
[04:58:08] [PASSED] MONO_625
[04:58:08] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:58:08] =============== [PASSED] drm_cmdline_parser ================
[04:58:08] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:58:08] [PASSED] drm_test_connector_hdmi_init_valid
[04:58:08] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:58:08] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:58:08] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:58:08] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:58:08] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:58:08] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:58:08] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:58:08] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:58:08] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:58:08] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:58:08] [PASSED] supported_formats=0x5 yuv420_allowed=1
[04:58:08] [PASSED] supported_formats=0x5 yuv420_allowed=0
[04:58:08] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:58:08] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:58:08] [PASSED] drm_test_connector_hdmi_init_null_product
[04:58:08] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:58:08] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:58:08] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:58:08] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:58:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:58:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:58:08] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:58:08] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:58:08] [PASSED] HDMI-A
[04:58:08] [PASSED] HDMI-B
[04:58:08] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:58:08] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:58:08] [PASSED] Unknown
[04:58:08] [PASSED] VGA
[04:58:08] [PASSED] DVI-I
[04:58:08] [PASSED] DVI-D
[04:58:08] [PASSED] DVI-A
[04:58:08] [PASSED] Composite
[04:58:08] [PASSED] SVIDEO
[04:58:08] [PASSED] LVDS
[04:58:08] [PASSED] Component
[04:58:08] [PASSED] DIN
[04:58:08] [PASSED] DP
[04:58:08] [PASSED] TV
[04:58:08] [PASSED] eDP
[04:58:08] [PASSED] Virtual
[04:58:08] [PASSED] DSI
[04:58:08] [PASSED] DPI
[04:58:08] [PASSED] Writeback
[04:58:08] [PASSED] SPI
[04:58:08] [PASSED] USB
[04:58:08] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:58:08] ============ [PASSED] drmm_connector_hdmi_init =============
[04:58:08] ============= drmm_connector_init (3 subtests) =============
[04:58:08] [PASSED] drm_test_drmm_connector_init
[04:58:08] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:58:08] ========= drm_test_drmm_connector_init_type_valid  =========
[04:58:08] [PASSED] Unknown
[04:58:08] [PASSED] VGA
[04:58:08] [PASSED] DVI-I
[04:58:08] [PASSED] DVI-D
[04:58:08] [PASSED] DVI-A
[04:58:08] [PASSED] Composite
[04:58:08] [PASSED] SVIDEO
[04:58:08] [PASSED] LVDS
[04:58:08] [PASSED] Component
[04:58:08] [PASSED] DIN
[04:58:08] [PASSED] DP
[04:58:08] [PASSED] HDMI-A
[04:58:08] [PASSED] HDMI-B
[04:58:08] [PASSED] TV
[04:58:08] [PASSED] eDP
[04:58:08] [PASSED] Virtual
[04:58:08] [PASSED] DSI
[04:58:08] [PASSED] DPI
[04:58:08] [PASSED] Writeback
[04:58:08] [PASSED] SPI
[04:58:08] [PASSED] USB
[04:58:08] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:58:08] =============== [PASSED] drmm_connector_init ===============
[04:58:08] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_init
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:58:08] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:58:08] [PASSED] Unknown
[04:58:08] [PASSED] VGA
[04:58:08] [PASSED] DVI-I
[04:58:08] [PASSED] DVI-D
[04:58:08] [PASSED] DVI-A
[04:58:08] [PASSED] Composite
[04:58:08] [PASSED] SVIDEO
[04:58:08] [PASSED] LVDS
[04:58:08] [PASSED] Component
[04:58:08] [PASSED] DIN
[04:58:08] [PASSED] DP
[04:58:08] [PASSED] HDMI-A
[04:58:08] [PASSED] HDMI-B
[04:58:08] [PASSED] TV
[04:58:08] [PASSED] eDP
[04:58:08] [PASSED] Virtual
[04:58:08] [PASSED] DSI
[04:58:08] [PASSED] DPI
[04:58:08] [PASSED] Writeback
[04:58:08] [PASSED] SPI
[04:58:08] [PASSED] USB
[04:58:08] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:58:08] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:58:08] [PASSED] Unknown
[04:58:08] [PASSED] VGA
[04:58:08] [PASSED] DVI-I
[04:58:08] [PASSED] DVI-D
[04:58:08] [PASSED] DVI-A
[04:58:08] [PASSED] Composite
[04:58:08] [PASSED] SVIDEO
[04:58:08] [PASSED] LVDS
[04:58:08] [PASSED] Component
[04:58:08] [PASSED] DIN
[04:58:08] [PASSED] DP
[04:58:08] [PASSED] HDMI-A
[04:58:08] [PASSED] HDMI-B
[04:58:08] [PASSED] TV
[04:58:08] [PASSED] eDP
[04:58:08] [PASSED] Virtual
[04:58:08] [PASSED] DSI
[04:58:08] [PASSED] DPI
[04:58:08] [PASSED] Writeback
[04:58:08] [PASSED] SPI
[04:58:08] [PASSED] USB
[04:58:08] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:58:08] =========== [PASSED] drm_connector_dynamic_init ============
[04:58:08] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:58:08] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:58:08] ======= drm_connector_dynamic_register (7 subtests) ========
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:58:08] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:58:08] ========= [PASSED] drm_connector_dynamic_register ==========
[04:58:08] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:58:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:58:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:58:08] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:58:08] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:58:08] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:58:08] [PASSED] NTSC
[04:58:08] [PASSED] NTSC-443
[04:58:08] [PASSED] NTSC-J
[04:58:08] [PASSED] PAL
[04:58:08] [PASSED] PAL-M
[04:58:08] [PASSED] PAL-N
[04:58:08] [PASSED] SECAM
[04:58:08] [PASSED] Mono
[04:58:08] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:58:08] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:58:08] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:58:08] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:58:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:58:08] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:58:08] [PASSED] VIC 96
[04:58:08] [PASSED] VIC 97
[04:58:08] [PASSED] VIC 101
[04:58:08] [PASSED] VIC 102
[04:58:08] [PASSED] VIC 106
[04:58:08] [PASSED] VIC 107
[04:58:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:58:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:58:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:58:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:58:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:58:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:58:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:58:08] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:58:08] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:58:08] [PASSED] Automatic
[04:58:08] [PASSED] Full
[04:58:08] [PASSED] Limited 16:235
[04:58:08] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:58:08] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:58:08] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:58:08] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:58:08] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:58:08] [PASSED] RGB
[04:58:08] [PASSED] YUV 4:2:0
[04:58:08] [PASSED] YUV 4:2:2
[04:58:08] [PASSED] YUV 4:4:4
[04:58:08] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:58:08] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:58:08] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:58:08] ============= drm_damage_helper (21 subtests) ==============
[04:58:08] [PASSED] drm_test_damage_iter_no_damage
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:58:08] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:58:08] [PASSED] drm_test_damage_iter_simple_damage
[04:58:08] [PASSED] drm_test_damage_iter_single_damage
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:58:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:58:08] [PASSED] drm_test_damage_iter_damage
[04:58:08] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:58:08] [PASSED] drm_test_damage_iter_damage_one_outside
[04:58:08] [PASSED] drm_test_damage_iter_damage_src_moved
[04:58:08] [PASSED] drm_test_damage_iter_damage_not_visible
[04:58:08] ================ [PASSED] drm_damage_helper ================
[04:58:08] ============== drm_dp_mst_helper (3 subtests) ==============
[04:58:08] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:58:08] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:58:08] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:58:08] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:58:08] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:58:08] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:58:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:58:08] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:58:08] [PASSED] Link rate 2000000 lane count 4
[04:58:08] [PASSED] Link rate 2000000 lane count 2
[04:58:08] [PASSED] Link rate 2000000 lane count 1
[04:58:08] [PASSED] Link rate 1350000 lane count 4
[04:58:08] [PASSED] Link rate 1350000 lane count 2
[04:58:08] [PASSED] Link rate 1350000 lane count 1
[04:58:08] [PASSED] Link rate 1000000 lane count 4
[04:58:08] [PASSED] Link rate 1000000 lane count 2
[04:58:08] [PASSED] Link rate 1000000 lane count 1
[04:58:08] [PASSED] Link rate 810000 lane count 4
[04:58:08] [PASSED] Link rate 810000 lane count 2
[04:58:08] [PASSED] Link rate 810000 lane count 1
[04:58:08] [PASSED] Link rate 540000 lane count 4
[04:58:08] [PASSED] Link rate 540000 lane count 2
[04:58:08] [PASSED] Link rate 540000 lane count 1
[04:58:08] [PASSED] Link rate 270000 lane count 4
[04:58:08] [PASSED] Link rate 270000 lane count 2
[04:58:08] [PASSED] Link rate 270000 lane count 1
[04:58:08] [PASSED] Link rate 162000 lane count 4
[04:58:08] [PASSED] Link rate 162000 lane count 2
[04:58:08] [PASSED] Link rate 162000 lane count 1
[04:58:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:58:08] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:58:08] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:58:08] [PASSED] DP_POWER_UP_PHY with port number
[04:58:08] [PASSED] DP_POWER_DOWN_PHY with port number
[04:58:08] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:58:08] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:58:08] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:58:08] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:58:08] [PASSED] DP_QUERY_PAYLOAD with port number
[04:58:08] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:58:08] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:58:08] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:58:08] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:58:08] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:58:08] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:58:08] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:58:08] [PASSED] DP_REMOTE_I2C_READ with port number
[04:58:08] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:58:08] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:58:08] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:58:08] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:58:08] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:58:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:58:08] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:58:08] ================ [PASSED] drm_dp_mst_helper ================
[04:58:08] ================== drm_exec (7 subtests) ===================
[04:58:08] [PASSED] sanitycheck
[04:58:08] [PASSED] test_lock
[04:58:08] [PASSED] test_lock_unlock
[04:58:08] [PASSED] test_duplicates
[04:58:08] [PASSED] test_prepare
[04:58:08] [PASSED] test_prepare_array
[04:58:08] [PASSED] test_multiple_loops
[04:58:08] ==================== [PASSED] drm_exec =====================
[04:58:08] =========== drm_format_helper_test (17 subtests) ===========
[04:58:08] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:58:08] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:58:08] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:58:08] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:58:08] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:58:08] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:58:08] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:58:08] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:58:08] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:58:08] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:58:08] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:58:08] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:58:08] ==================== drm_test_fb_swab  =====================
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ================ [PASSED] drm_test_fb_swab =================
[04:58:08] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:58:08] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:58:08] [PASSED] single_pixel_source_buffer
[04:58:08] [PASSED] single_pixel_clip_rectangle
[04:58:08] [PASSED] well_known_colors
[04:58:08] [PASSED] destination_pitch
[04:58:08] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:58:08] ================= drm_test_fb_clip_offset  =================
[04:58:08] [PASSED] pass through
[04:58:08] [PASSED] horizontal offset
[04:58:08] [PASSED] vertical offset
[04:58:08] [PASSED] horizontal and vertical offset
[04:58:08] [PASSED] horizontal offset (custom pitch)
[04:58:08] [PASSED] vertical offset (custom pitch)
[04:58:08] [PASSED] horizontal and vertical offset (custom pitch)
[04:58:08] ============= [PASSED] drm_test_fb_clip_offset =============
[04:58:08] =================== drm_test_fb_memcpy  ====================
[04:58:08] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:58:08] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:58:08] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:58:08] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:58:08] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:58:08] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:58:08] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:58:08] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:58:08] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:58:08] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:58:08] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:58:08] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:58:08] =============== [PASSED] drm_test_fb_memcpy ================
[04:58:08] ============= [PASSED] drm_format_helper_test ==============
[04:58:08] ================= drm_format (18 subtests) =================
[04:58:08] [PASSED] drm_test_format_block_width_invalid
[04:58:08] [PASSED] drm_test_format_block_width_one_plane
[04:58:08] [PASSED] drm_test_format_block_width_two_plane
[04:58:08] [PASSED] drm_test_format_block_width_three_plane
[04:58:08] [PASSED] drm_test_format_block_width_tiled
[04:58:08] [PASSED] drm_test_format_block_height_invalid
[04:58:08] [PASSED] drm_test_format_block_height_one_plane
[04:58:08] [PASSED] drm_test_format_block_height_two_plane
[04:58:08] [PASSED] drm_test_format_block_height_three_plane
[04:58:08] [PASSED] drm_test_format_block_height_tiled
[04:58:08] [PASSED] drm_test_format_min_pitch_invalid
[04:58:08] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:58:08] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:58:08] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:58:08] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:58:08] [PASSED] drm_test_format_min_pitch_two_plane
[04:58:08] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:58:08] [PASSED] drm_test_format_min_pitch_tiled
[04:58:08] =================== [PASSED] drm_format ====================
[04:58:08] ============== drm_framebuffer (10 subtests) ===============
[04:58:08] ========== drm_test_framebuffer_check_src_coords  ==========
[04:58:08] [PASSED] Success: source fits into fb
[04:58:08] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:58:08] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:58:08] [PASSED] Fail: overflowing fb with source width
[04:58:08] [PASSED] Fail: overflowing fb with source height
[04:58:08] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:58:08] [PASSED] drm_test_framebuffer_cleanup
[04:58:08] =============== drm_test_framebuffer_create  ===============
[04:58:08] [PASSED] ABGR8888 normal sizes
[04:58:08] [PASSED] ABGR8888 max sizes
[04:58:08] [PASSED] ABGR8888 pitch greater than min required
[04:58:08] [PASSED] ABGR8888 pitch less than min required
[04:58:08] [PASSED] ABGR8888 Invalid width
[04:58:08] [PASSED] ABGR8888 Invalid buffer handle
[04:58:08] [PASSED] No pixel format
[04:58:08] [PASSED] ABGR8888 Width 0
[04:58:08] [PASSED] ABGR8888 Height 0
[04:58:08] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:58:08] [PASSED] ABGR8888 Large buffer offset
[04:58:08] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:58:08] [PASSED] ABGR8888 Invalid flag
[04:58:08] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:58:08] [PASSED] ABGR8888 Valid buffer modifier
[04:58:08] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:58:08] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] NV12 Normal sizes
[04:58:08] [PASSED] NV12 Max sizes
[04:58:08] [PASSED] NV12 Invalid pitch
[04:58:08] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:58:08] [PASSED] NV12 different  modifier per-plane
[04:58:08] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:58:08] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] NV12 Modifier for inexistent plane
[04:58:08] [PASSED] NV12 Handle for inexistent plane
[04:58:08] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:58:08] [PASSED] YVU420 Normal sizes
[04:58:08] [PASSED] YVU420 Max sizes
[04:58:08] [PASSED] YVU420 Invalid pitch
[04:58:08] [PASSED] YVU420 Different pitches
[04:58:08] [PASSED] YVU420 Different buffer offsets/pitches
[04:58:08] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:58:08] [PASSED] YVU420 Valid modifier
[04:58:08] [PASSED] YVU420 Different modifiers per plane
[04:58:08] [PASSED] YVU420 Modifier for inexistent plane
[04:58:08] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:58:08] [PASSED] X0L2 Normal sizes
[04:58:08] [PASSED] X0L2 Max sizes
[04:58:08] [PASSED] X0L2 Invalid pitch
[04:58:08] [PASSED] X0L2 Pitch greater than minimum required
[04:58:08] [PASSED] X0L2 Handle for inexistent plane
[04:58:08] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:58:08] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:58:08] [PASSED] X0L2 Valid modifier
[04:58:08] [PASSED] X0L2 Modifier for inexistent plane
[04:58:08] =========== [PASSED] drm_test_framebuffer_create ===========
[04:58:08] [PASSED] drm_test_framebuffer_free
[04:58:08] [PASSED] drm_test_framebuffer_init
[04:58:08] [PASSED] drm_test_framebuffer_init_bad_format
[04:58:08] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:58:08] [PASSED] drm_test_framebuffer_lookup
[04:58:08] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:58:08] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:58:08] ================= [PASSED] drm_framebuffer =================
[04:58:08] ================ drm_gem_shmem (8 subtests) ================
[04:58:08] [PASSED] drm_gem_shmem_test_obj_create
[04:58:08] [PASSED] drm_gem_shmem_test_obj_create_private
[04:58:08] [PASSED] drm_gem_shmem_test_pin_pages
[04:58:08] [PASSED] drm_gem_shmem_test_vmap
[04:58:08] [PASSED] drm_gem_shmem_test_get_sg_table
[04:58:08] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:58:08] [PASSED] drm_gem_shmem_test_madvise
[04:58:08] [PASSED] drm_gem_shmem_test_purge
[04:58:08] ================== [PASSED] drm_gem_shmem ==================
[04:58:08] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:58:08] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:58:08] [PASSED] Automatic
[04:58:08] [PASSED] Full
[04:58:08] [PASSED] Limited 16:235
[04:58:08] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:58:08] [PASSED] drm_test_check_disable_connector
[04:58:08] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:58:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:58:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:58:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:58:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:58:08] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:58:08] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:58:08] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:58:08] [PASSED] drm_test_check_output_bpc_dvi
[04:58:08] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:58:08] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:58:08] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:58:08] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:58:08] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:58:08] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:58:08] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:58:08] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:58:08] ============ drm_test_check_hdmi_color_format  =============
[04:58:08] [PASSED] AUTO -> RGB
[04:58:08] [PASSED] YCBCR422 -> YUV422
[04:58:08] [PASSED] YCBCR420 -> YUV420
[04:58:08] [PASSED] YCBCR444 -> YUV444
[04:58:08] [PASSED] RGB -> RGB
[04:58:08] ======== [PASSED] drm_test_check_hdmi_color_format =========
[04:58:08] ======== drm_test_check_hdmi_color_format_420_only  ========
[04:58:08] [PASSED] RGB should fail
[04:58:08] [PASSED] YUV444 should fail
[04:58:08] [PASSED] YUV422 should fail
[04:58:08] [PASSED] YUV420 should work
[04:58:08] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[04:58:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:58:08] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:58:08] [PASSED] drm_test_check_broadcast_rgb_value
[04:58:08] [PASSED] drm_test_check_bpc_8_value
[04:58:08] [PASSED] drm_test_check_bpc_10_value
[04:58:08] [PASSED] drm_test_check_bpc_12_value
[04:58:08] [PASSED] drm_test_check_format_value
[04:58:08] [PASSED] drm_test_check_tmds_char_value
[04:58:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:58:08] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[04:58:08] [PASSED] drm_test_check_mode_valid
[04:58:08] [PASSED] drm_test_check_mode_valid_reject
[04:58:08] [PASSED] drm_test_check_mode_valid_reject_rate
[04:58:08] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:58:08] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[04:58:08] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[04:58:08] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[04:58:08] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:58:08] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[04:58:08] [PASSED] drm_test_check_infoframes
[04:58:08] [PASSED] drm_test_check_reject_avi_infoframe
[04:58:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[04:58:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[04:58:08] [PASSED] drm_test_check_reject_audio_infoframe
[04:58:08] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[04:58:08] ================= drm_managed (2 subtests) =================
[04:58:08] [PASSED] drm_test_managed_release_action
[04:58:08] [PASSED] drm_test_managed_run_action
[04:58:08] =================== [PASSED] drm_managed ===================
[04:58:08] =================== drm_mm (6 subtests) ====================
[04:58:08] [PASSED] drm_test_mm_init
[04:58:08] [PASSED] drm_test_mm_debug
[04:58:08] [PASSED] drm_test_mm_align32
[04:58:08] [PASSED] drm_test_mm_align64
[04:58:08] [PASSED] drm_test_mm_lowest
[04:58:08] [PASSED] drm_test_mm_highest
[04:58:08] ===================== [PASSED] drm_mm ======================
[04:58:08] ============= drm_modes_analog_tv (5 subtests) =============
[04:58:08] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:58:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:58:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:58:08] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:58:08] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:58:08] =============== [PASSED] drm_modes_analog_tv ===============
[04:58:08] ============== drm_plane_helper (2 subtests) ===============
[04:58:08] =============== drm_test_check_plane_state  ================
[04:58:08] [PASSED] clipping_simple
[04:58:08] [PASSED] clipping_rotate_reflect
[04:58:08] [PASSED] positioning_simple
[04:58:08] [PASSED] upscaling
[04:58:08] [PASSED] downscaling
[04:58:08] [PASSED] rounding1
[04:58:08] [PASSED] rounding2
[04:58:08] [PASSED] rounding3
[04:58:08] [PASSED] rounding4
[04:58:08] =========== [PASSED] drm_test_check_plane_state ============
[04:58:08] =========== drm_test_check_invalid_plane_state  ============
[04:58:08] [PASSED] positioning_invalid
[04:58:08] [PASSED] upscaling_invalid
[04:58:08] [PASSED] downscaling_invalid
[04:58:08] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:58:08] ================ [PASSED] drm_plane_helper =================
[04:58:08] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:58:08] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:58:08] [PASSED] None
[04:58:08] [PASSED] PAL
[04:58:08] [PASSED] NTSC
[04:58:08] [PASSED] Both, NTSC Default
[04:58:08] [PASSED] Both, PAL Default
[04:58:08] [PASSED] Both, NTSC Default, with PAL on command-line
[04:58:08] [PASSED] Both, PAL Default, with NTSC on command-line
[04:58:08] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:58:08] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:58:08] ================== drm_rect (9 subtests) ===================
[04:58:08] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:58:08] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:58:08] [PASSED] drm_test_rect_clip_scaled_clipped
[04:58:08] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:58:08] ================= drm_test_rect_intersect  =================
[04:58:08] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:58:08] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:58:08] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:58:08] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:58:08] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:58:08] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:58:08] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:58:08] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:58:08] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:58:08] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:58:08] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:58:08] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:58:08] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:58:08] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:58:08] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:58:08] ============= [PASSED] drm_test_rect_intersect =============
[04:58:08] ================ drm_test_rect_calc_hscale  ================
[04:58:08] [PASSED] normal use
[04:58:08] [PASSED] out of max range
[04:58:08] [PASSED] out of min range
[04:58:08] [PASSED] zero dst
[04:58:08] [PASSED] negative src
[04:58:08] [PASSED] negative dst
[04:58:08] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:58:08] ================ drm_test_rect_calc_vscale  ================
[04:58:08] [PASSED] normal use
[04:58:08] [PASSED] out of max range
[04:58:08] [PASSED] out of min range
[04:58:08] [PASSED] zero dst
[04:58:08] [PASSED] negative src
[04:58:08] [PASSED] negative dst
[04:58:08] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:58:08] ================== drm_test_rect_rotate  ===================
[04:58:08] [PASSED] reflect-x
[04:58:08] [PASSED] reflect-y
[04:58:08] [PASSED] rotate-0
[04:58:08] [PASSED] rotate-90
[04:58:08] [PASSED] rotate-180
[04:58:08] [PASSED] rotate-270
[04:58:08] ============== [PASSED] drm_test_rect_rotate ===============
[04:58:08] ================ drm_test_rect_rotate_inv  =================
[04:58:08] [PASSED] reflect-x
[04:58:08] [PASSED] reflect-y
[04:58:08] [PASSED] rotate-0
[04:58:08] [PASSED] rotate-90
[04:58:08] [PASSED] rotate-180
[04:58:08] [PASSED] rotate-270
[04:58:08] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:58:08] ==================== [PASSED] drm_rect =====================
[04:58:08] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:58:08] ============ drm_test_sysfb_build_fourcc_list  =============
[04:58:08] [PASSED] no native formats
[04:58:08] [PASSED] XRGB8888 as native format
[04:58:08] [PASSED] remove duplicates
[04:58:08] [PASSED] convert alpha formats
[04:58:08] [PASSED] random formats
[04:58:08] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:58:08] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:58:08] ================== drm_fixp (2 subtests) ===================
[04:58:08] [PASSED] drm_test_int2fixp
[04:58:08] [PASSED] drm_test_sm2fixp
[04:58:08] ==================== [PASSED] drm_fixp =====================
[04:58:08] ============================================================
[04:58:08] Testing complete. Ran 637 tests: passed: 637
[04:58:08] Elapsed time: 26.261s total, 1.790s configuring, 24.304s building, 0.148s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:58:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:58:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:58:20] Starting KUnit Kernel (1/1)...
[04:58:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:58:20] ================= ttm_device (5 subtests) ==================
[04:58:20] [PASSED] ttm_device_init_basic
[04:58:20] [PASSED] ttm_device_init_multiple
[04:58:20] [PASSED] ttm_device_fini_basic
[04:58:20] [PASSED] ttm_device_init_no_vma_man
[04:58:20] ================== ttm_device_init_pools  ==================
[04:58:20] [PASSED] No DMA allocations, no DMA32 required
[04:58:20] [PASSED] DMA allocations, DMA32 required
[04:58:20] [PASSED] No DMA allocations, DMA32 required
[04:58:20] [PASSED] DMA allocations, no DMA32 required
[04:58:20] ============== [PASSED] ttm_device_init_pools ==============
[04:58:20] =================== [PASSED] ttm_device ====================
[04:58:20] ================== ttm_pool (8 subtests) ===================
[04:58:20] ================== ttm_pool_alloc_basic  ===================
[04:58:20] [PASSED] One page
[04:58:20] [PASSED] More than one page
[04:58:20] [PASSED] Above the allocation limit
[04:58:20] [PASSED] One page, with coherent DMA mappings enabled
[04:58:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:58:20] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:58:20] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:58:20] [PASSED] One page
[04:58:20] [PASSED] More than one page
[04:58:20] [PASSED] Above the allocation limit
[04:58:20] [PASSED] One page, with coherent DMA mappings enabled
[04:58:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:58:20] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:58:20] [PASSED] ttm_pool_alloc_order_caching_match
[04:58:20] [PASSED] ttm_pool_alloc_caching_mismatch
[04:58:20] [PASSED] ttm_pool_alloc_order_mismatch
[04:58:20] [PASSED] ttm_pool_free_dma_alloc
[04:58:20] [PASSED] ttm_pool_free_no_dma_alloc
[04:58:20] [PASSED] ttm_pool_fini_basic
[04:58:20] ==================== [PASSED] ttm_pool =====================
[04:58:20] ================ ttm_resource (8 subtests) =================
[04:58:20] ================= ttm_resource_init_basic  =================
[04:58:20] [PASSED] Init resource in TTM_PL_SYSTEM
[04:58:20] [PASSED] Init resource in TTM_PL_VRAM
[04:58:20] [PASSED] Init resource in a private placement
[04:58:20] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:58:20] ============= [PASSED] ttm_resource_init_basic =============
[04:58:20] [PASSED] ttm_resource_init_pinned
[04:58:20] [PASSED] ttm_resource_fini_basic
[04:58:20] [PASSED] ttm_resource_manager_init_basic
[04:58:20] [PASSED] ttm_resource_manager_usage_basic
[04:58:20] [PASSED] ttm_resource_manager_set_used_basic
[04:58:20] [PASSED] ttm_sys_man_alloc_basic
[04:58:20] [PASSED] ttm_sys_man_free_basic
[04:58:20] ================== [PASSED] ttm_resource ===================
[04:58:20] =================== ttm_tt (15 subtests) ===================
[04:58:20] ==================== ttm_tt_init_basic  ====================
[04:58:20] [PASSED] Page-aligned size
[04:58:20] [PASSED] Extra pages requested
[04:58:20] ================ [PASSED] ttm_tt_init_basic ================
[04:58:20] [PASSED] ttm_tt_init_misaligned
[04:58:20] [PASSED] ttm_tt_fini_basic
[04:58:20] [PASSED] ttm_tt_fini_sg
[04:58:20] [PASSED] ttm_tt_fini_shmem
[04:58:20] [PASSED] ttm_tt_create_basic
[04:58:20] [PASSED] ttm_tt_create_invalid_bo_type
[04:58:20] [PASSED] ttm_tt_create_ttm_exists
[04:58:20] [PASSED] ttm_tt_create_failed
[04:58:20] [PASSED] ttm_tt_destroy_basic
[04:58:20] [PASSED] ttm_tt_populate_null_ttm
[04:58:20] [PASSED] ttm_tt_populate_populated_ttm
[04:58:20] [PASSED] ttm_tt_unpopulate_basic
[04:58:20] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:58:20] [PASSED] ttm_tt_swapin_basic
[04:58:20] ===================== [PASSED] ttm_tt ======================
[04:58:20] =================== ttm_bo (14 subtests) ===================
[04:58:20] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:58:20] [PASSED] Cannot be interrupted and sleeps
[04:58:20] [PASSED] Cannot be interrupted, locks straight away
[04:58:20] [PASSED] Can be interrupted, sleeps
[04:58:20] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:58:20] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:58:20] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:58:20] [PASSED] ttm_bo_reserve_double_resv
[04:58:20] [PASSED] ttm_bo_reserve_interrupted
[04:58:20] [PASSED] ttm_bo_reserve_deadlock
[04:58:20] [PASSED] ttm_bo_unreserve_basic
[04:58:20] [PASSED] ttm_bo_unreserve_pinned
[04:58:20] [PASSED] ttm_bo_unreserve_bulk
[04:58:20] [PASSED] ttm_bo_fini_basic
[04:58:20] [PASSED] ttm_bo_fini_shared_resv
[04:58:20] [PASSED] ttm_bo_pin_basic
[04:58:20] [PASSED] ttm_bo_pin_unpin_resource
[04:58:20] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:58:20] ===================== [PASSED] ttm_bo ======================
[04:58:20] ============== ttm_bo_validate (22 subtests) ===============
[04:58:20] ============== ttm_bo_init_reserved_sys_man  ===============
[04:58:20] [PASSED] Buffer object for userspace
[04:58:20] [PASSED] Kernel buffer object
[04:58:20] [PASSED] Shared buffer object
[04:58:20] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:58:20] ============== ttm_bo_init_reserved_mock_man  ==============
[04:58:20] [PASSED] Buffer object for userspace
[04:58:20] [PASSED] Kernel buffer object
[04:58:20] [PASSED] Shared buffer object
[04:58:20] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:58:20] [PASSED] ttm_bo_init_reserved_resv
[04:58:20] ================== ttm_bo_validate_basic  ==================
[04:58:20] [PASSED] Buffer object for userspace
[04:58:20] [PASSED] Kernel buffer object
[04:58:20] [PASSED] Shared buffer object
[04:58:20] ============== [PASSED] ttm_bo_validate_basic ==============
[04:58:20] [PASSED] ttm_bo_validate_invalid_placement
[04:58:20] ============= ttm_bo_validate_same_placement  ==============
[04:58:20] [PASSED] System manager
[04:58:20] [PASSED] VRAM manager
[04:58:20] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:58:20] [PASSED] ttm_bo_validate_failed_alloc
[04:58:20] [PASSED] ttm_bo_validate_pinned
[04:58:20] [PASSED] ttm_bo_validate_busy_placement
[04:58:20] ================ ttm_bo_validate_multihop  =================
[04:58:20] [PASSED] Buffer object for userspace
[04:58:20] [PASSED] Kernel buffer object
[04:58:20] [PASSED] Shared buffer object
[04:58:20] ============ [PASSED] ttm_bo_validate_multihop =============
[04:58:20] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:58:20] [PASSED] Buffer object in system domain, no page vector
[04:58:20] [PASSED] Buffer object in system domain with an existing page vector
[04:58:20] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:58:20] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:58:20] [PASSED] Buffer object for userspace
[04:58:20] [PASSED] Kernel buffer object
[04:58:20] [PASSED] Shared buffer object
[04:58:20] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:58:20] [PASSED] ttm_bo_validate_move_fence_signaled
[04:58:20] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:58:20] [PASSED] Waits for GPU
[04:58:20] [PASSED] Tries to lock straight away
[04:58:20] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:58:20] [PASSED] ttm_bo_validate_swapout
[04:58:20] [PASSED] ttm_bo_validate_happy_evict
[04:58:20] [PASSED] ttm_bo_validate_all_pinned_evict
[04:58:20] [PASSED] ttm_bo_validate_allowed_only_evict
[04:58:20] [PASSED] ttm_bo_validate_deleted_evict
[04:58:20] [PASSED] ttm_bo_validate_busy_domain_evict
[04:58:20] [PASSED] ttm_bo_validate_evict_gutting
[04:58:20] [PASSED] ttm_bo_validate_recrusive_evict
[04:58:20] ================= [PASSED] ttm_bo_validate =================
[04:58:20] ============================================================
[04:58:20] Testing complete. Ran 102 tests: passed: 102
[04:58:20] Elapsed time: 12.075s total, 1.795s configuring, 10.064s building, 0.182s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable CMRR in fixed-RR VRR path (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1000 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev5)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c_BAT -> xe-pw-168613v5_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9017 -> IGT_9018
  * Linux: xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c -> xe-pw-168613v5

  IGT_9017: 9017
  IGT_9018: f4345861cbd5d97fd50b73bf7af5fe3286fca056 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c: 5726f9c4bde0290e5e60e636b9632bb03a57498c
  xe-pw-168613v5: 168613v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/index.html

[-- Attachment #2: Type: text/html, Size: 1562 bytes --]

✗ Xe.CI.FULL: failure for Enable CMRR in fixed-RR VRR path (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 25089 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev5)
URL   : https://patchwork.freedesktop.org/series/168613/
State : failure

== Summary ==

CI Bug Log - changes from xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c_FULL -> xe-pw-168613v5_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-168613v5_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-168613v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-168613v5_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@runner@aborted:
    - shard-lnl:          NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-lnl-5/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in xe-pw-168613v5_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#7059] / [Intel XE#7085])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +6 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#7679])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#367])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2887]) +6 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2652]) +8 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7358]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2252]) +4 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#6974])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][11] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +3 other tests fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2320]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2286] / [Intel XE#6035])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#1508])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#4354] / [Intel XE#5882])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#8265]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-6/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][17] -> [FAIL][18] ([Intel XE#301]) +2 other tests fail
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][19] -> [FAIL][20] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7178] / [Intel XE#7349])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4141]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2311]) +28 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7399])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#7061]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2313]) +30 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7308])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#1503])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7283]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2938] / [Intel XE#7376] / [Intel XE#7760])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          [PASS][33] -> [FAIL][34] ([Intel XE#8399]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-2/igt@kms_pm_dc@dc6-dpms.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-lnl-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7794])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1489]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2234])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@kms_psr@psr2-primary-render.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2450] / [Intel XE#5857])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-4/igt@kms_tv_load_detect@load-detect.html

  * igt@xe_configfs@gt-types-allowed:
    - shard-bmg:          [PASS][40] -> [ABORT][41] ([Intel XE#8007]) +2 other tests abort
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-9/igt@xe_configfs@gt-types-allowed.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-3/igt@xe_configfs@gt-types-allowed.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][42] -> [INCOMPLETE][43] ([Intel XE#6321] / [Intel XE#8355])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#8370])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@xe_evict@evict-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#8374]) +5 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#8364]) +13 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-7/igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority-smem.html

  * igt@xe_exec_reset@multi-queue-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#8369])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-7/igt@xe_exec_reset@multi-queue-close-fd.html

  * igt@xe_exec_threads@threads-multi-queue-rebind-err:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#8378]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-rebind-err.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6964])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2284] / [Intel XE#7370])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-stale-queue-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html

  * igt@xe_query@multigpu-query-gt-list:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#944]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@xe_query@multigpu-query-gt-list.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-bmg:          [PASS][54] -> [FAIL][55] ([Intel XE#6569])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-9/igt@xe_sriov_flr@flr-twice.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-8/igt@xe_sriov_flr@flr-twice.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][56] ([Intel XE#7571]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-bmg:          [FAIL][58] ([Intel XE#3098]) -> [PASS][59] +1 other test pass
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][60] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@atomic-many:
    - shard-bmg:          [FAIL][62] ([Intel XE#8578]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-6/igt@xe_exec_fault_mode@atomic-many.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@xe_exec_fault_mode@atomic-many.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:
    - shard-bmg:          [ABORT][64] ([Intel XE#8007]) -> [PASS][65] +1 other test pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0:
    - shard-bmg:          [FAIL][66] ([Intel XE#8639]) -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-2/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-3/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1:
    - shard-bmg:          [ABORT][68] ([Intel XE#8637]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-2/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-3/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][70] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][71] ([Intel XE#1729] / [Intel XE#7424])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][72] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][73] ([Intel XE#2426] / [Intel XE#5848])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8578
  [Intel XE#8637]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8637
  [Intel XE#8639]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8639
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_9017 -> IGT_9018
  * Linux: xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c -> xe-pw-168613v5

  IGT_9017: 9017
  IGT_9018: f4345861cbd5d97fd50b73bf7af5fe3286fca056 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c: 5726f9c4bde0290e5e60e636b9632bb03a57498c
  xe-pw-168613v5: 168613v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v5/index.html

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