Re: [PATCH v3 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp: mode_valid allows modes that will fail atomic_check due to decoupled M/N and bandwidth checks
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commit 0616c11329b8f8c5ca25700eb71cd2152a14fe54
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date:   Wed Sep 16 09:09:38 2026 +0000

    drm/i915/dp: Limit M/N ratio for DP SST

This commit restricts DisplayPort link configurations to those satisfying the
hardware limitation for the Link M/Link N ratio limit in the transcoder's
timing generator DDA. The constraint is checked during link rate configuration
and modes failing this check are pruned in mode_valid.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034cf..f6a2152c4432a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
[ ... ]
> @@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>  	return target_clock <= effective_dotclk_limit;
>  }
>  
> +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_dp_link_caps_order order = {
> +		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> +	};
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
> +			found = true;
> +
> +			break;
> +		}
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	return found;
> +}

[Severity: Medium]
Will this loop cause modes to falsely pass mode_valid checks but later fail
during atomic_check?

Because HBR3 uses 8b/10b encoding, it has a higher symbol clock (810 MHz) than
UHBR20 (625 MHz, 128b/132b). This means HBR3 can satisfy the M/N ratio limit
for a higher pixel clock than UHBR20.

If a high-resolution mode (e.g., 3.0 GHz pixel clock needing 40 Gbps) is tested,
this function passes because HBR3 satisfies the M/N ratio. Subsequently,
intel_dp_mode_valid_format() passes because it independently checks bandwidth
against the absolute max link rate (UHBR20).

However, during atomic_check, UHBR20 gets filtered out due to the M/N ratio
limit, and HBR3 gets rejected for lacking bandwidth, causing the modeset to
fail. Does mode_valid need to verify that the specific link rate satisfying the
M/N ratio also provides enough bandwidth for the mode?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-suraj.kandpal@intel.com?part=2