[PATCH v3 00/10] Implement Wa_14021768792 to bypass m_n ratio limit

[PATCH v3 00/10] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check with warning for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (2):
  drm/i915/dp: Limit M/N ratio for DP SST
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 drivers/gpu/drm/i915/display/intel_display.c  | 122 +++++++++++--
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |   9 +
 .../gpu/drm/i915/display/intel_display_wa.h   |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 167 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 9 files changed, 319 insertions(+), 11 deletions(-)

-- 
2.34.1

[PATCH v3 01/10] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_display_compute_link_m_n() to compute the link M/N ratio
from the pixel clock and the link symbol clock. This logic was
previously embedded within intel_link_compute_m_n().

The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation.

No functional changes intended.

v2:
- Rename function (Jani)
- The link symbol clock is passed in rather than derived here, so that the
DP specific conversion from the link rate stays with the caller. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9151ea6c15ab..f04a6f97e05a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2641,13 +2641,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
+static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+					   int pixel_clock, int link_symbol_clock)
+{
+	compute_m_n(link_m, link_n,
+		    pixel_clock, link_symbol_clock,
+		    0x80000);
+}
+
 void
 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
 						  bw_overhead);
 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2664,9 +2671,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		    data_m, data_n,
 		    0x8000000);
 
-	compute_m_n(&m_n->link_m, &m_n->link_n,
-		    pixel_clock, link_symbol_clock,
-		    0x80000);
+	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
+				       pixel_clock,
+				       intel_dp_link_symbol_clock(link_clock));
 }
 
 void intel_panel_sanitize_ssc(struct intel_display *display)
-- 
2.34.1

[PATCH v3 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[Suraj Kandpal]

The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
timing generator DDA can track. This limitation has always existed, but
it typically wasn't encountered without the use of joiners and DSC.

With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.

Restrict the link configurations to those satisfying the constraint
while computing the link config limits, so that the SST and the MST
paths both get it, and so that a mode which no link rate can support
fails early rather than deep inside link config selection.

Also prune such modes in mode_valid. Note the ratio is the pixel clock
over the link symbol clock, and the symbol clock is not monotonic in the
link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
8b/10b, so e.g. HBR3 has a higher symbol clock than UHBR20. There is
therefore no single best link rate to evaluate against, and mode_valid
walks the link configurations instead, only rejecting the mode if none
of them can satisfy the ratio.

Note: This change applies the check only for SST. Support for MST will
be added in a subsequent commit.

v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
v3:
-Rebase on the link caps iterator based link config selection.
-Set the constraint up in intel_dp_compute_config_limits() by narrowing
the link config filter, and fail there if no config qualifies, instead
of skipping configs while iterating them. (Imre)
-Use a limit of 4 on DG2. (Wa_14014191401)
-Walk the link configurations in mode_valid rather than evaluating the
ratio at the highest link rate, which is not the best case for it.
v4:
-Add iterator for all dp configs in intel_dp_mode_valid_m_n() so
that we do not prune any mode that could have been supported (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 101 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 4 files changed, 107 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f04a6f97e05a..c53163d7c082 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2641,8 +2641,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
-static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
-					   int pixel_clock, int link_symbol_clock)
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock)
 {
 	compute_m_n(link_m, link_n,
 		    pixel_clock, link_symbol_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index eecafff167d3..404168f4213b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cd5e6b5034c..f6a2152c4432 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -61,6 +61,7 @@
 #include "intel_cx0_phy.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
+#include "intel_display.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -1265,6 +1266,34 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static int
+intel_dp_get_max_m_n_ratio(struct intel_display *display)
+{
+	if (display->platform.dg2)
+		return 4;
+
+	return 10;
+}
+
+static bool
+intel_dp_can_support_m_n(struct intel_display *display,
+			 int pixel_clock, int link_rate)
+{
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	u32 link_m, link_n;
+	int m_n_ratio;
+
+	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
+				       intel_dp_link_symbol_clock(link_rate));
+
+	if (!link_n)
+		return true;
+
+	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
+
+	return m_n_ratio <= max_m_n_ratio;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 	return target_clock <= effective_dotclk_limit;
 }
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
+			found = true;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return found;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_format(struct intel_connector *connector,
 			   const struct drm_display_mode *mode,
@@ -1454,6 +1508,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 			return status;
 	}
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
+		return MODE_CLOCK_HIGH;
+
 	/*
 	 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format()
 	 * will always choose a 4:4:4 output_format if the DFP can do the
@@ -2654,6 +2711,47 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
 	return true;
 }
 
+static bool
+intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
+				  struct drm_connector_state *conn_state,
+				  const struct intel_crtc_state *crtc_state,
+				  struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
+			    connector->base.base.id, connector->base.name,
+			    intel_dp_get_max_m_n_ratio(display));
+
+		return false;
+	}
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
 bool
 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct drm_connector_state *conn_state,
@@ -2770,6 +2868,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
+	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
+		return false;
+
 	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..aa58833a405b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 u8 intel_dp_as_sdp_transmission_time(void);
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
+
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
-- 
2.34.1

Re: [PATCH v3 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp: mode_valid allows modes that will fail atomic_check due to decoupled M/N and bandwidth checks
--

commit 0616c11329b8f8c5ca25700eb71cd2152a14fe54
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date:   Wed Sep 16 09:09:38 2026 +0000

    drm/i915/dp: Limit M/N ratio for DP SST

This commit restricts DisplayPort link configurations to those satisfying the
hardware limitation for the Link M/Link N ratio limit in the transcoder's
timing generator DDA. The constraint is checked during link rate configuration
and modes failing this check are pruned in mode_valid.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034cf..f6a2152c4432a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
[ ... ]
> @@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>  	return target_clock <= effective_dotclk_limit;
>  }
>  
> +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_dp_link_caps_order order = {
> +		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> +	};
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
> +			found = true;
> +
> +			break;
> +		}
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	return found;
> +}

[Severity: Medium]
Will this loop cause modes to falsely pass mode_valid checks but later fail
during atomic_check?

Because HBR3 uses 8b/10b encoding, it has a higher symbol clock (810 MHz) than
UHBR20 (625 MHz, 128b/132b). This means HBR3 can satisfy the M/N ratio limit
for a higher pixel clock than UHBR20.

If a high-resolution mode (e.g., 3.0 GHz pixel clock needing 40 Gbps) is tested,
this function passes because HBR3 satisfies the M/N ratio. Subsequently,
intel_dp_mode_valid_format() passes because it independently checks bandwidth
against the absolute max link rate (UHBR20).

However, during atomic_check, UHBR20 gets filtered out due to the M/N ratio
limit, and HBR3 gets rejected for lacking bandwidth, causing the modeset to
fail. Does mode_valid need to verify that the specific link rate satisfying the
M/N ratio also provides enough bandwidth for the mode?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-suraj.kandpal@intel.com?part=2

RE: [PATCH v3 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[Kandpal, Suraj]

> Subject: Re: [PATCH v3 02/10] drm/i915/dp: Limit M/N ratio for DP SST
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to
> consider:
> - [Medium] drm/i915/dp: mode_valid allows modes that will fail atomic_check
> due to decoupled M/N and bandwidth checks
> --
> 
> commit 0616c11329b8f8c5ca25700eb71cd2152a14fe54
> Author: Suraj Kandpal <suraj.kandpal@intel.com>
> Date:   Wed Sep 16 09:09:38 2026 +0000
> 
>     drm/i915/dp: Limit M/N ratio for DP SST
> 
> This commit restricts DisplayPort link configurations to those satisfying the
> hardware limitation for the Link M/Link N ratio limit in the transcoder's timing
> generator DDA. The constraint is checked during link rate configuration and
> modes failing this check are pruned in mode_valid.
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0cd5e6b5034cf..f6a2152c4432a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> [ ... ]
> > @@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display
> *display,
> >  	return target_clock <= effective_dotclk_limit;  }
> >
> > +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> > +pixel_clock) {
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +	struct intel_dp_link_caps_order order = {
> > +		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> > +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> > +	};
> > +	struct intel_dp_link_config link_config;
> > +	struct intel_dp_link_caps_iter iter;
> > +	bool found = false;
> > +
> > +	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> > +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> > +	for_each_dp_link_config(&iter, &link_config) {
> > +		if (intel_dp_can_support_m_n(display, pixel_clock,
> link_config.rate)) {
> > +			found = true;
> > +
> > +			break;
> > +		}
> > +	}
> > +	intel_dp_link_caps_iter_end(&iter);
> > +
> > +	return found;
> > +}
> 
> [Severity: Medium]
> Will this loop cause modes to falsely pass mode_valid checks but later fail
> during atomic_check?
> 
> Because HBR3 uses 8b/10b encoding, it has a higher symbol clock (810 MHz)
> than
> UHBR20 (625 MHz, 128b/132b). This means HBR3 can satisfy the M/N ratio
> limit for a higher pixel clock than UHBR20.
> 
> If a high-resolution mode (e.g., 3.0 GHz pixel clock needing 40 Gbps) is tested,
> this function passes because HBR3 satisfies the M/N ratio. Subsequently,
> intel_dp_mode_valid_format() passes because it independently checks
> bandwidth against the absolute max link rate (UHBR20).
> 
> However, during atomic_check, UHBR20 gets filtered out due to the M/N ratio
> limit, and HBR3 gets rejected for lacking bandwidth, causing the modeset to
> fail. Does mode_valid need to verify that the specific link rate satisfying the
> M/N ratio also provides enough bandwidth for the mode?

Yes it can, but I think that's the right way round for mode_valid, and the
example doesn't actually hit it - at 3.0 GHz UHBR20's ratio is 4.8, so it
isn't filtered out and the mode works fine. You need over 6.25 GHz pixel clock
before UHBR20 fails the ratio, and by then HBR3 passes the ratio but can't
carry the bandwidth.
Checking both per config would mean duplicating the bpp/DSC/joiner logic from
compute config inside mode_valid. intel_dp_mode_valid() already carries a TODO
for the same kind of divergence, so I'd rather not add a second copy of it.
The earlier comment on this patch was the opposite case, pruning modes that a
narrower but faster config could drive. That one is user visible, so I've erred
away from false rejects.

Regards,
Suraj Kandpal

> 
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-
> suraj.kandpal@intel.com?part=2

[PATCH v3 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 6a869d0f6ffc..430ba1230c5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1564,6 +1564,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1

[PATCH v3 04/10] drm/i915/dp: Add M/N ratio check with warning for DP link config

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_dp_check_m_n_ratio() to validate the computed link
M/N ratio against the maximum allowed value. If the ratio exceeds the
limit, a warning is issued via drm_WARN().

The link config limits computed in the previous patches only restrict
the configurations that may be selected; this catches anything that
still slips through and turns a silently broken link into a loud
warning.

This check works off the M/N values as actually computed, which exposes
a mismatch with the prediction done while computing the limits: the
pixel clock there is the one before intel_dp_compute_config() divides
adjusted_mode->crtc_clock by the MSO link count. Divide in the
prediction too, so both agree. The joiner needs no such handling, as
intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
adjusted mode the link M/N is derived from untouched.

v2:
-Use the platform specific ratio limit. (Wa_14014191401)
-Use the MSO adjusted pixel clock when predicting the ratio, matching
what the link M/N is actually computed from. (Imre)
-Drop the check from ilk_fdi_compute_config(): it was passing dp_m_n
rather than the fdi_m_n it had just computed, and an FDI link cannot get
anywhere near the ratio limit anyway.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 37 +++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h     |  4 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f6a2152c4432..8de51582d18c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1294,6 +1294,14 @@ intel_dp_can_support_m_n(struct intel_display *display,
 	return m_n_ratio <= max_m_n_ratio;
 }
 
+static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
+{
+	if (!intel_dp->mso_link_count)
+		return pixel_clock;
+
+	return pixel_clock / intel_dp->mso_link_count;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1332,6 +1340,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp, pixel_clock);
 	struct intel_dp_link_caps_order order = {
 		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
 		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
@@ -1343,7 +1352,8 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
+		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+					     link_config.rate)) {
 			found = true;
 
 			break;
@@ -2723,7 +2733,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 	struct intel_dp_link_caps_order order =
 		intel_dp_link_caps_connector_compute_order(connector);
 	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
-	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
+	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
+						  intel_dp_mode_clock(crtc_state, conn_state));
 	struct intel_dp_link_config link_config;
 	struct intel_dp_link_caps_iter iter;
 	bool found = false;
@@ -3382,6 +3393,24 @@ static bool can_enable_drrs(struct intel_connector *connector,
 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
 }
 
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+			      struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int m_n_ratio;
+
+	if (!m_n || !m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (m_n_ratio > max_m_n_ratio)
+		drm_WARN(display->drm, 1,
+			 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+			 m_n_ratio, max_m_n_ratio);
+}
+
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
 			     struct intel_crtc_state *pipe_config,
@@ -3420,6 +3449,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 			       &pipe_config->dp_m2_n2);
 
+	intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m2_n2);
+
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
@@ -3739,6 +3770,8 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 				       pipe_config->port_clock,
 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 				       &pipe_config->dp_m_n);
+
+		intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
 	}
 
 	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aa58833a405b..4c975358ab96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,6 +26,7 @@ struct intel_display;
 struct intel_dp;
 struct intel_dp_link_config;
 struct intel_encoder;
+struct intel_link_m_n;
 
 struct link_config_limits {
 	struct intel_dp_link_caps_filter link_config_filter;
@@ -244,4 +245,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+			      struct intel_link_m_n *m_n);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 430ba1230c5a..364f62563f90 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -347,6 +347,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 					 link_bpp_x16,
 					 &crtc_state->dp_m_n);
 
+		intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
 		if (is_mst) {
 			int remote_bw_overhead;
 			int remote_tu;
-- 
2.34.1

Re: [PATCH v3 04/10] drm/i915/dp: Add M/N ratio check with warning for DP link config

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm: log spam and DoS vector due to invariant drm_WARN inside bpp_x16 loop
--

commit cb9847e0babf613d9ed13f234a331025ee93ec9c
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/dp: Add M/N ratio check with warning for DP link config

This commit introduces intel_dp_check_m_n_ratio() to validate the computed
link M/N ratio against the maximum allowed value. It issues a warning via
drm_WARN() if the limit is exceeded.

[ ... ]
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 430ba1230c5ae..364f62563f904 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -347,6 +347,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>  					 link_bpp_x16,
>  					 &crtc_state->dp_m_n);
>  
> +		intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
		^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: Medium]
Will this evaluate a loop-invariant condition on every iteration of the
bpp_x16 loop in intel_dp_mtp_tu_compute_config() in intel_dp_mst.c?

Because intel_dp_check_m_n_ratio() uses drm_WARN() and is called inside this
loop, a KMS client requesting an MST mode where the link_m / link_n ratio
exceeds max_m_n_ratio could trigger a full kernel stack trace for every failed
loop iteration.

When DSC is used, bpp_step_x16 can be as small as 1/16 bpp. Could this cause
the loop to run potentially hundreds of times for an un-fittable mode, flooding
the kernel log and leading to dmesg rollover or console lockups?

> +
>  		if (is_mst) {
>  			int remote_bw_overhead;
>  			int remote_tu;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-suraj.kandpal@intel.com?part=4

[PATCH v3 05/10] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.

Add support for these extra bits.

For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.

v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.

Bspec:50488
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c53163d7c082..6d2025e10995 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2711,14 +2711,22 @@ void intel_set_m_n(struct intel_display *display,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
+	u32 link_n = m_n->link_n;
+
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
+
+	if (DISPLAY_VER(display) >= 14)
+		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		link_n &= DATA_LINK_M_N_MASK;
+
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write(display, link_n_reg, link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3475,7 +3483,13 @@ void intel_get_m_n(struct intel_display *display,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(display, link_n_reg);
+
+	if (DISPLAY_VER(display) >= 14)
+		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		m_n->link_n &= DATA_LINK_M_N_MASK;
+
 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 8251ec15190b..57f388c958b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
 
 #define _PIPEA_LINK_N1		0x60044
 #define _PIPEB_LINK_N1		0x61044
+#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
+#define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
-- 
2.34.1

[PATCH v3 06/10] drm/i915/display_wa: Add support for Wa_14021768792

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.

Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_TRANS and the extended bits in the LINK_N register.

Add the necessary logic to enable the workaround on applicable platforms.
The underlying mechanism comes from the display C0,
so it is gated on display stepping C0 and later.

v2:
-Don't include i915_drv.h and don't use struct drm_i915_private under
display/. Use display->platform.battlemage, which names the affected
platform directly, instead of IS_DGFX() combined with a display version
check. (Jani)
-Rebase on the reworked display WA framework, where the condition goes
directly into the __intel_display_wa() switch.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 888676693f5e..7456194216be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -111,6 +111,15 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return DISPLAY_VERx100(display) == 3000 ||
 			DISPLAY_VERx100(display) == 2000 ||
 			DISPLAY_VERx100(display) == 1401;
+	/*
+	 * Wa_14021768792:
+	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N
+	 * registers to support LINK M/N ratios from > 10 but < 15.
+	 */
+	case INTEL_DISPLAY_WA_14021768792:
+		return display->platform.battlemage &&
+			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
 	case INTEL_DISPLAY_WA_14025769978:
 		return DISPLAY_VER(display) == 35;
 	case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 425a300840aa..b8f2f9363498 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -33,6 +33,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14014143976,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
+	INTEL_DISPLAY_WA_14021768792,
 	INTEL_DISPLAY_WA_14025769978,
 	INTEL_DISPLAY_WA_14026643300,
 	INTEL_DISPLAY_WA_15013987218,
-- 
2.34.1

[PATCH v3 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792.

To bypass the hardware limitation within the Timing Generator DDA
(TGDDA), we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
and CHICKEN_TRANS.

Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in the
intel_link_m_n structure.

Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).

CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N, since
writing LINK_N arms the double buffered update of the M/N registers, and
all of the programming has to be done before the transcoder is enabled.
Both are also explicitly cleared when the mechanism is not in use, so
that state cannot leak from a previous modeset.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 91 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +
 .../gpu/drm/i915/display/intel_display_regs.h | 10 ++
 .../drm/i915/display/intel_display_types.h    |  2 +
 4 files changed, 100 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6d2025e10995..2b226620de0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2706,6 +2706,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 	m_n->tu = 1;
 }
 
+static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+	if (!m_n->link_n)
+		return 0;
+
+	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
+		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m, m_n->link_n));
+}
+
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
@@ -2717,7 +2726,9 @@ void intel_set_m_n(struct intel_display *display,
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+		link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+	else if (DISPLAY_VER(display) >= 14)
 		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
 	else
 		link_n &= DATA_LINK_M_N_MASK;
@@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
 }
 
+static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
+				     enum transcoder transcoder,
+				     const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
+	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
+
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return;
+
+	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
+		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
+
+	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
+		     DP_ENHANCED_TGDDA_ENABLE,
+		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
+}
+
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    const struct intel_link_m_n *m_n)
@@ -2745,6 +2776,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
 
+	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
+
 	if (DISPLAY_VER(display) >= 5)
 		intel_set_m_n(display, m_n,
 			      PIPE_DATA_M1(display, transcoder),
@@ -3495,6 +3528,49 @@ void intel_get_m_n(struct intel_display *display,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
 }
 
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio,
+					enum pipe pipe)
+{
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return false;
+
+	if (m_n_ratio > 15)
+		return false;
+
+	if (pipe != PIPE_A)
+		return false;
+
+	return true;
+}
+
+static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
+				    enum transcoder transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	u32 link_m_frac;
+	int m_n_ratio;
+
+	if (!m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe))
+		return;
+
+	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
+	      DP_ENHANCED_TGDDA_ENABLE))
+		return;
+
+	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
+
+	if (link_m_frac == m_n->link_m % m_n->link_n)
+		m_n->bypass_m_n_ratio_limit = true;
+}
+
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    struct intel_link_m_n *m_n)
@@ -3512,6 +3588,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(display, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
 }
 
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -5002,7 +5080,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
 		m_n->data_m == m2_n2->data_m &&
 		m_n->data_n == m2_n2->data_n &&
 		m_n->link_m == m2_n2->link_m &&
-		m_n->link_n == m2_n2->link_n;
+		m_n->link_n == m2_n2->link_n &&
+		m_n->bypass_m_n_ratio_limit == m2_n2->bypass_m_n_ratio_limit;
 }
 
 static bool
@@ -5277,18 +5356,20 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (!intel_compare_link_m_n(&current_config->name, \
 				    &pipe_config->name)) { \
 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
-				     "(expected tu %i data %i/%i link %i/%i, " \
-				     "found tu %i, data %i/%i link %i/%i)", \
+				     "(expected tu %i data %i/%i link %i/%i m_n_bypass %s, " \
+				     "found tu %i, data %i/%i link %i/%i m_n_bypass %s)", \
 				     current_config->name.tu, \
 				     current_config->name.data_m, \
 				     current_config->name.data_n, \
 				     current_config->name.link_m, \
 				     current_config->name.link_n, \
+				     str_yes_no(current_config->name.bypass_m_n_ratio_limit), \
 				     pipe_config->name.tu, \
 				     pipe_config->name.data_m, \
 				     pipe_config->name.data_n, \
 				     pipe_config->name.link_m, \
-				     pipe_config->name.link_n); \
+				     pipe_config->name.link_n, \
+				     str_yes_no(pipe_config->name.bypass_m_n_ratio_limit)); \
 		ret = false; \
 	} \
 } while (0)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 404168f4213b..55e676655120 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
 				    int pixel_clock, int link_symbol_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio, enum pipe pipe);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 57f388c958b4..81f9661357b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,11 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _HDMI_EMP_DATA_A	0x600d8
+#define _HDMI_EMP_DATA_B	0x610d8
+#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
+#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display), (trans), _HDMI_EMP_DATA_A)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
@@ -1192,6 +1197,10 @@
 #define _PIPEB_LINK_N1		0x61044
 #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
 #define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
+#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
+#define  PIPE_LINK_N1_EXT_CEIL(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
+#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
+#define  PIPE_LINK_N1_EXT_INT(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
@@ -1710,6 +1719,7 @@
 #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
 #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
+#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
 #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
 #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a5f18ac8a7d0..7a5286db977e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,8 @@ struct intel_link_m_n {
 	u32 data_n;
 	u32 link_m;
 	u32 link_n;
+	/* Wa_14021768792 for linkm/n ratio > 10 */
+	bool bypass_m_n_ratio_limit;
 };
 
 struct intel_csc_matrix {
-- 
2.34.1

Re: [PATCH v3 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915: CHICKEN_TRANS modified during fastset violates HW sequence
- [Medium] drm/i915: TGDDA bypass readout masks invalid hardware state
--

commit 0462c93350e8b8ead0d7c6de9d75c2b9a0868707
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792. This commit programs the LINKM and
LINKN registers, along with relevant bits in HDMI_EMP_DATA and CHICKEN_TRANS,
to bypass the hardware limitation within the Timing Generator DDA (TGDDA).

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6d2025e109956..2b226620de0fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
[ ... ]
> @@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
>  	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
>  }
>  
> +static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
> +				     enum transcoder transcoder,
> +				     const struct intel_link_m_n *m_n)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
> +	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
> +
> +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> +		return;
> +
> +	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
> +		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> +		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
> +
> +	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
> +		     DP_ENHANCED_TGDDA_ENABLE,
> +		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);

[Severity: High]
When reached via intel_update_crtc() during a fastset, can these
non-double-buffered registers be modified while the transcoder is already
enabled?

If userspace requests a modeset that lowers the pixel clock on an eDP panel
(which supports seamless M/N updates) such that the M/N ratio drops below the
workaround threshold, the new state will have bypass_m_n_ratio_limit = false.

Because the M/N struct check is skipped when update_m_n is true:

drivers/gpu/drm/i915/display/intel_display.c:intel_pipe_config_compare() {
    ...
		if (!fastset || !pipe_config->update_m_n)
			PIPE_CONF_CHECK_M_N(dp_m_n);
    ...
}

And because intel_crtc_check_fastset() leaves update_m_n true despite the
bypass_m_n_ratio_limit mismatch:

drivers/gpu/drm/i915/display/intel_display.c:intel_crtc_check_fastset() {
    ...
	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
				   &new_crtc_state->dp_m_n))
		new_crtc_state->update_m_n = false;
    ...
}

This authorizes a fastset. During the fastset, bmg_enhanced_tgdda_write() will
then clear the workaround bits in the live transcoder. Modifying CHICKEN_TRANS
and HDMI_EMP_DATA while the transcoder is active violates the explicit hardware
programming sequence. This can lead to transcoder hangs, blank screens, or
display corruption, and is reachable by a local unprivileged user requesting
specific modes/refresh rates on supported eDP displays.

> +}
> +
[ ... ]
> @@ -3495,6 +3528,49 @@ void intel_get_m_n(struct intel_display *display,
>  	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
>  }
>  
> +bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
> +					int m_n_ratio,
> +					enum pipe pipe)
> +{
> +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> +		return false;
> +
> +	if (m_n_ratio > 15)
> +		return false;
> +
> +	if (pipe != PIPE_A)
> +		return false;
> +
> +	return true;
> +}
> +
> +static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
> +				    enum transcoder transcoder,
> +				    struct intel_link_m_n *m_n)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	u32 link_m_frac;
> +	int m_n_ratio;
> +
> +	if (!m_n->link_n)
> +		return;
> +
> +	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> +
> +	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe))
> +		return;

[Severity: Medium]
Does this early return apply software policy during hardware readout, masking
the fact that the hardware workaround is physically enabled on a disallowed
pipe?

If DP_ENHANCED_TGDDA_ENABLE is erroneously left enabled on an invalid pipe
(e.g., PIPE B) or with a corrupted fractional value, bmg_enhanced_tgdda_read()
returns early. The state checker compares this readout (false) against the
computed software state (false) and incorrectly declares a match, blinding the
state checker to the actual hardware configuration. If the hardware is
misprogrammed (e.g., by BIOS), it will not be detected and healed, potentially
causing display corruption or blank screens.

> +
> +	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
> +	      DP_ENHANCED_TGDDA_ENABLE))
> +		return;
> +
> +	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> +				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
> +
> +	if (link_m_frac == m_n->link_m % m_n->link_n)
> +		m_n->bypass_m_n_ratio_limit = true;

[Severity: Medium]
Does requiring a perfect fractional match to report the enable bit mask cases
where the workaround is enabled but incorrectly configured?

If the fractional value is corrupted, bmg_enhanced_tgdda_read() refuses to set
bypass_m_n_ratio_limit = true, causing the same state checker mismatch issue
described above.

> +}
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-suraj.kandpal@intel.com?part=7

[PATCH v3 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.

The workaround is only intended for 128b/132b links, so restrict it to
those.

Bspec also restricts the Link M/N values from changing outside of a
modeset while the mechanism is active, so disable DRRS and the seamless
M/N fastset path for such a configuration.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8de51582d18c..3911942de8e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3373,6 +3373,9 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
+	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
+		return false;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
@@ -3397,6 +3400,7 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
 			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
 	int m_n_ratio;
 
@@ -3405,10 +3409,21 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
 
 	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
 
-	if (m_n_ratio > max_m_n_ratio)
-		drm_WARN(display->drm, 1,
-			 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
-			 m_n_ratio, max_m_n_ratio);
+	if (m_n_ratio <= max_m_n_ratio)
+		return;
+
+	if (intel_dp_is_uhbr(crtc_state) &&
+	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe)) {
+		m_n->bypass_m_n_ratio_limit = true;
+		drm_dbg_kms(display->drm,
+			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
+			    m_n_ratio);
+		return;
+	}
+
+	drm_WARN(display->drm, 1,
+		 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+		 m_n_ratio, max_m_n_ratio);
 }
 
 static void
@@ -3425,7 +3440,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	 * FIXME all joined pipes share the same transcoder.
 	 * Need to account for that when updating M/N live.
 	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
+	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
 		pipe_config->update_m_n = true;
 
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
-- 
2.34.1

Re: [PATCH v3 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp: state leak of bypass_m_n_ratio_limit disables DRRS
--

commit 0e4fb34450fd70c4ab5e5e995c5d7cab890c8cac
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

Handle the bypass logic for the M/N ratio limit for DP. Calculate the
M/N ratio, check if it can bypass the limit, and set the appropriate
flags for the workaround to restrict DRRS and seamless M/N fastsets.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8de51582d18c8..3911942de8e53 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c

[ ... ]

> @@ -3405,10 +3409,21 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
>  
>  	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
>  
> -	if (m_n_ratio > max_m_n_ratio)
> -		drm_WARN(display->drm, 1,
> -			 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> -			 m_n_ratio, max_m_n_ratio);
> +	if (m_n_ratio <= max_m_n_ratio)
> +		return;

[Severity: Medium]
If a previous iteration or modeset evaluated an M/N ratio > 10 and set the
bypass_m_n_ratio_limit flag to true, does returning early here leave the flag
incorrectly set?

For example, when this function is called during the MST BPP fallback loop:

drivers/gpu/drm/i915/display/intel_dp_mst.c:intel_dp_mtp_tu_compute_config() {
    ...
		intel_dp_mst_compute_m_n(crtc_state,
					 local_bw_overhead,
					 link_bpp_x16,
					 &crtc_state->dp_m_n);

		intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
    ...
}

The crtc_state->dp_m_n struct is reused across fallback iterations. If a
rejected high-ratio configuration sets bypass_m_n_ratio_limit to true, it
appears a subsequent accepted lower-ratio configuration will return early
without clearing it. This would permanently disable DRRS for the CRTC.
Should we set m_n->bypass_m_n_ratio_limit = false before returning?

> +
> +	if (intel_dp_is_uhbr(crtc_state) &&
> +	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe)) {
> +		m_n->bypass_m_n_ratio_limit = true;
> +		drm_dbg_kms(display->drm,
> +			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
> +			    m_n_ratio);
> +		return;
> +	}
> +
> +	drm_WARN(display->drm, 1,
> +		 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> +		 m_n_ratio, max_m_n_ratio);
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916090946.677564-1-suraj.kandpal@intel.com?part=8

[PATCH v3 09/10] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.

Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit. The
workaround is only intended for 128b/132b links, so restrict it to
those.

During the mode_valid phase, the check assumes that PIPE_A will be used,
to allow the mode where the M/N ratio is within the limits for the
workaround.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3911942de8e5..04a492a0b369 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1277,9 +1277,11 @@ intel_dp_get_max_m_n_ratio(struct intel_display *display)
 
 static bool
 intel_dp_can_support_m_n(struct intel_display *display,
+			 const struct intel_crtc_state *crtc_state,
 			 int pixel_clock, int link_rate)
 {
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	enum pipe pipe = PIPE_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
 
@@ -1291,7 +1293,16 @@ intel_dp_can_support_m_n(struct intel_display *display,
 
 	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
 
-	return m_n_ratio <= max_m_n_ratio;
+	if (m_n_ratio <= max_m_n_ratio)
+		return true;
+
+	if (!drm_dp_is_uhbr_rate(link_rate))
+		return false;
+
+	if (crtc_state)
+		pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+	return intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe);
 }
 
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
@@ -1352,7 +1363,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+		if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock,
 					     link_config.rate)) {
 			found = true;
 
@@ -2741,7 +2752,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+		if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock,
+					      link_config.rate))
 			continue;
 
 		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
-- 
2.34.1

[PATCH v3 10/10] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

[Suraj Kandpal]

Starting Xe3p max M/N ratio has been increased to 22.

Bspec: 68922
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 04a492a0b369..2610c33565a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1269,6 +1269,9 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
+	if (DISPLAY_VER(display) >= 35)
+		return 22;
+
 	if (display->platform.dg2)
 		return 4;
 
-- 
2.34.1

✓ CI.KUnit: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev8)

[Patchwork]

== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev8)
URL   : https://patchwork.freedesktop.org/series/138256/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[09:16:34] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:16:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:16:58] Starting KUnit Kernel (1/1)...
[09:16:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:16:58] ============= refcount_interrupt (4 subtests) ==============
[09:16:58] [PASSED] test_single_irq_change
[09:16:58] [PASSED] test_nested_irq_change
[09:16:58] [PASSED] test_multiple_irq_change
[09:16:58] [PASSED] test_irq_save
[09:16:58] =============== [PASSED] refcount_interrupt ================
[09:16:58] ================= gpu_buddy (14 subtests) ==================
[09:16:58] [PASSED] gpu_test_buddy_alloc_limit
[09:16:58] [PASSED] gpu_test_buddy_alloc_optimistic
[09:16:58] [PASSED] gpu_test_buddy_alloc_pessimistic
[09:16:58] [PASSED] gpu_test_buddy_alloc_pathological
[09:16:58] [PASSED] gpu_test_buddy_alloc_contiguous
[09:16:58] [PASSED] gpu_test_buddy_alloc_clear
[09:16:58] [PASSED] gpu_test_buddy_alloc_range
[09:16:59] [PASSED] gpu_test_buddy_alloc_range_bias
[09:16:59] [PASSED] gpu_test_buddy_fragmentation_performance
[09:17:00] [PASSED] gpu_test_buddy_dirty_tracker_performance
[09:17:00] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[09:17:00] [PASSED] gpu_test_buddy_offset_aligned_allocation
[09:17:00] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[09:17:00] [PASSED] gpu_test_buddy_addr_to_block
[09:17:00] ==================== [PASSED] gpu_buddy ====================
[09:17:00] ============================================================
[09:17:00] Testing complete. Ran 18 tests: passed: 18
[09:17:00] Elapsed time: 26.438s total, 4.356s configuring, 20.164s building, 1.873s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:17:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:17:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:17:36] Starting KUnit Kernel (1/1)...
[09:17:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:17:36] ============= refcount_interrupt (4 subtests) ==============
[09:17:36] [PASSED] test_single_irq_change
[09:17:36] [PASSED] test_nested_irq_change
[09:17:36] [PASSED] test_multiple_irq_change
[09:17:36] [PASSED] test_irq_save
[09:17:36] =============== [PASSED] refcount_interrupt ================
[09:17:36] ================== guc_buf (11 subtests) ===================
[09:17:36] [PASSED] test_smallest
[09:17:36] [PASSED] test_largest
[09:17:36] [PASSED] test_granular
[09:17:36] [PASSED] test_unique
[09:17:36] [PASSED] test_overlap
[09:17:36] [PASSED] test_reusable
[09:17:36] [PASSED] test_too_big
[09:17:36] [PASSED] test_flush
[09:17:36] [PASSED] test_lookup
[09:17:36] [PASSED] test_data
[09:17:36] [PASSED] test_class
[09:17:36] ===================== [PASSED] guc_buf =====================
[09:17:36] =================== guc_dbm (7 subtests) ===================
[09:17:36] [PASSED] test_empty
[09:17:36] [PASSED] test_default
[09:17:36] ======================== test_size  ========================
[09:17:36] [PASSED] 4
[09:17:36] [PASSED] 8
[09:17:36] [PASSED] 32
[09:17:36] [PASSED] 256
[09:17:36] ==================== [PASSED] test_size ====================
[09:17:36] ======================= test_reuse  ========================
[09:17:36] [PASSED] 4
[09:17:36] [PASSED] 8
[09:17:36] [PASSED] 32
[09:17:36] [PASSED] 256
[09:17:36] =================== [PASSED] test_reuse ====================
[09:17:36] =================== test_range_overlap  ====================
[09:17:36] [PASSED] 4
[09:17:36] [PASSED] 8
[09:17:36] [PASSED] 32
[09:17:36] [PASSED] 256
[09:17:36] =============== [PASSED] test_range_overlap ================
[09:17:36] =================== test_range_compact  ====================
[09:17:36] [PASSED] 4
[09:17:36] [PASSED] 8
[09:17:36] [PASSED] 32
[09:17:36] [PASSED] 256
[09:17:36] =============== [PASSED] test_range_compact ================
[09:17:36] ==================== test_range_spare  =====================
[09:17:36] [PASSED] 4
[09:17:36] [PASSED] 8
[09:17:36] [PASSED] 32
[09:17:36] [PASSED] 256
[09:17:36] ================ [PASSED] test_range_spare =================
[09:17:36] ===================== [PASSED] guc_dbm =====================
[09:17:36] =================== guc_idm (6 subtests) ===================
[09:17:36] [PASSED] bad_init
[09:17:36] [PASSED] no_init
[09:17:36] [PASSED] init_fini
[09:17:36] [PASSED] check_used
[09:17:36] [PASSED] check_quota
[09:17:36] [PASSED] check_all
[09:17:36] ===================== [PASSED] guc_idm =====================
[09:17:36] =============== guc_klv_helpers (9 subtests) ===============
[09:17:36] [PASSED] test_count
[09:17:36] [PASSED] test_encode_u32
[09:17:36] [PASSED] test_encode_u64
[09:17:36] [PASSED] test_encode_string
[09:17:36] [PASSED] test_encode_object_raw
[09:17:36] [PASSED] test_encode_object_klv
[09:17:36] [PASSED] test_encode_object_nested
[09:17:36] [PASSED] test_encode_object_basic
[09:17:36] [PASSED] test_print
[09:17:36] ================= [PASSED] guc_klv_helpers =================
[09:17:36] =================== xe_log (4 subtests) ====================
[09:17:36] [PASSED] demo_cper
[09:17:36] [PASSED] demo_dmesg
[09:17:36] ======================= test_dmesg  ========================
[09:17:36] [PASSED] test_fatal
[09:17:36] [PASSED] test_fatal_tile
[09:17:36] [PASSED] test_fatal_gt
[09:17:36] [PASSED] test_fatal_comp
[09:17:36] [PASSED] test_fatal_comp_tile
[09:17:36] [PASSED] test_fatal_comp_gt
[09:17:36] [PASSED] test_fatal_all
[09:17:36] [PASSED] test_recoverable
[09:17:36] [PASSED] test_recoverable_tile
[09:17:36] [PASSED] test_recoverable_gt
[09:17:36] [PASSED] test_recoverable_comp
[09:17:36] [PASSED] test_recoverable_comp_tile
[09:17:36] [PASSED] test_recoverable_comp_gt
[09:17:36] [PASSED] test_recoverable_all
[09:17:36] [PASSED] test_info
[09:17:36] [PASSED] test_info_tile
[09:17:36] [PASSED] test_info_gt
[09:17:36] [PASSED] test_info_err
[09:17:36] [PASSED] test_info_comp
[09:17:36] [PASSED] test_info_comp_tile
[09:17:36] [PASSED] test_info_comp_gt
[09:17:36] [PASSED] test_info_all
[09:17:36] [PASSED] test_hw_fatal
[09:17:36] [PASSED] test_hw_recoverable
[09:17:36] [PASSED] test_hw_corrected
[09:17:36] [PASSED] test_hw_informational
[09:17:36] =================== [PASSED] test_dmesg ====================
[09:17:36] ====================== test_invalid  =======================
[09:17:36] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[09:17:36] ================== [SKIPPED] test_invalid ==================
[09:17:36] ===================== [PASSED] xe_log ======================
[09:17:36] ================== no_relay (3 subtests) ===================
[09:17:36] [PASSED] xe_drops_guc2pf_if_not_ready
[09:17:36] [PASSED] xe_drops_guc2vf_if_not_ready
[09:17:36] [PASSED] xe_rejects_send_if_not_ready
[09:17:36] ==================== [PASSED] no_relay =====================
[09:17:36] ================== pf_relay (14 subtests) ==================
[09:17:36] [PASSED] pf_rejects_guc2pf_too_short
[09:17:36] [PASSED] pf_rejects_guc2pf_too_long
[09:17:36] [PASSED] pf_rejects_guc2pf_no_payload
[09:17:36] [PASSED] pf_fails_no_payload
[09:17:36] [PASSED] pf_fails_bad_origin
[09:17:36] [PASSED] pf_fails_bad_type
[09:17:36] [PASSED] pf_txn_reports_error
[09:17:36] [PASSED] pf_txn_sends_pf2guc
[09:17:36] [PASSED] pf_sends_pf2guc
[09:17:36] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[09:17:36] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[09:17:36] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[09:17:36] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[09:17:36] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[09:17:36] ==================== [PASSED] pf_relay =====================
[09:17:36] ================== vf_relay (3 subtests) ===================
[09:17:36] [PASSED] vf_rejects_guc2vf_too_short
[09:17:36] [PASSED] vf_rejects_guc2vf_too_long
[09:17:36] [PASSED] vf_rejects_guc2vf_no_payload
[09:17:36] ==================== [PASSED] vf_relay =====================
[09:17:36] ================ pf_gt_config (9 subtests) =================
[09:17:36] [PASSED] fair_contexts_1vf
[09:17:36] [PASSED] fair_doorbells_1vf
[09:17:36] [PASSED] fair_ggtt_1vf
[09:17:36] ====================== fair_vram_1vf  ======================
[09:17:36] [PASSED] 3.50 GiB
[09:17:36] [PASSED] 11.5 GiB
[09:17:36] [PASSED] 15.5 GiB
[09:17:36] [PASSED] 31.5 GiB
[09:17:36] [PASSED] 63.5 GiB
[09:17:36] [PASSED] 1.91 GiB
[09:17:36] ================== [PASSED] fair_vram_1vf ==================
[09:17:36] ================ fair_vram_1vf_admin_only  =================
[09:17:36] [PASSED] 3.50 GiB
[09:17:36] [PASSED] 11.5 GiB
[09:17:36] [PASSED] 15.5 GiB
[09:17:36] [PASSED] 31.5 GiB
[09:17:36] [PASSED] 63.5 GiB
[09:17:36] [PASSED] 1.91 GiB
[09:17:36] ============ [PASSED] fair_vram_1vf_admin_only =============
[09:17:36] ====================== fair_contexts  ======================
[09:17:36] [PASSED] 1 VF
[09:17:36] [PASSED] 2 VFs
[09:17:36] [PASSED] 3 VFs
[09:17:36] [PASSED] 4 VFs
[09:17:36] [PASSED] 5 VFs
[09:17:36] [PASSED] 6 VFs
[09:17:36] [PASSED] 7 VFs
[09:17:36] [PASSED] 8 VFs
[09:17:36] [PASSED] 9 VFs
[09:17:36] [PASSED] 10 VFs
[09:17:36] [PASSED] 11 VFs
[09:17:36] [PASSED] 12 VFs
[09:17:36] [PASSED] 13 VFs
[09:17:36] [PASSED] 14 VFs
[09:17:36] [PASSED] 15 VFs
[09:17:36] [PASSED] 16 VFs
[09:17:36] [PASSED] 17 VFs
[09:17:36] [PASSED] 18 VFs
[09:17:36] [PASSED] 19 VFs
[09:17:36] [PASSED] 20 VFs
[09:17:36] [PASSED] 21 VFs
[09:17:36] [PASSED] 22 VFs
[09:17:36] [PASSED] 23 VFs
[09:17:36] [PASSED] 24 VFs
[09:17:36] [PASSED] 25 VFs
[09:17:36] [PASSED] 26 VFs
[09:17:36] [PASSED] 27 VFs
[09:17:36] [PASSED] 28 VFs
[09:17:36] [PASSED] 29 VFs
[09:17:36] [PASSED] 30 VFs
[09:17:36] [PASSED] 31 VFs
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[09:17:36] [PASSED] 33 VFs
[09:17:36] [PASSED] 34 VFs
[09:17:36] [PASSED] 35 VFs
[09:17:36] [PASSED] 36 VFs
[09:17:36] [PASSED] 37 VFs
[09:17:36] [PASSED] 38 VFs
[09:17:36] [PASSED] 39 VFs
[09:17:36] [PASSED] 40 VFs
[09:17:36] [PASSED] 41 VFs
[09:17:36] [PASSED] 42 VFs
[09:17:36] [PASSED] 43 VFs
[09:17:36] [PASSED] 44 VFs
[09:17:36] [PASSED] 45 VFs
[09:17:36] [PASSED] 46 VFs
[09:17:36] [PASSED] 47 VFs
[09:17:36] [PASSED] 48 VFs
[09:17:36] [PASSED] 49 VFs
[09:17:36] [PASSED] 50 VFs
[09:17:36] [PASSED] 51 VFs
[09:17:36] [PASSED] 52 VFs
[09:17:36] [PASSED] 53 VFs
[09:17:36] [PASSED] 54 VFs
[09:17:36] [PASSED] 55 VFs
[09:17:36] [PASSED] 56 VFs
[09:17:36] [PASSED] 57 VFs
[09:17:36] [PASSED] 58 VFs
[09:17:36] [PASSED] 59 VFs
[09:17:36] [PASSED] 60 VFs
[09:17:36] [PASSED] 61 VFs
[09:17:36] [PASSED] 62 VFs
[09:17:36] [PASSED] 63 VFs
[09:17:36] ================== [PASSED] fair_contexts ==================
[09:17:36] ===================== fair_doorbells  ======================
[09:17:36] [PASSED] 1 VF
[09:17:36] [PASSED] 2 VFs
[09:17:36] [PASSED] 3 VFs
[09:17:36] [PASSED] 4 VFs
[09:17:36] [PASSED] 5 VFs
[09:17:36] [PASSED] 6 VFs
[09:17:36] [PASSED] 7 VFs
[09:17:36] [PASSED] 8 VFs
[09:17:36] [PASSED] 9 VFs
[09:17:36] [PASSED] 10 VFs
[09:17:36] [PASSED] 11 VFs
[09:17:36] [PASSED] 12 VFs
[09:17:36] [PASSED] 13 VFs
[09:17:36] [PASSED] 14 VFs
[09:17:36] [PASSED] 15 VFs
[09:17:36] [PASSED] 16 VFs
[09:17:36] [PASSED] 17 VFs
[09:17:36] [PASSED] 18 VFs
[09:17:36] [PASSED] 19 VFs
[09:17:36] [PASSED] 20 VFs
[09:17:36] [PASSED] 21 VFs
[09:17:36] [PASSED] 22 VFs
[09:17:36] [PASSED] 23 VFs
[09:17:36] [PASSED] 24 VFs
[09:17:36] [PASSED] 25 VFs
[09:17:36] [PASSED] 26 VFs
[09:17:36] [PASSED] 27 VFs
[09:17:36] [PASSED] 28 VFs
[09:17:36] [PASSED] 29 VFs
[09:17:36] [PASSED] 30 VFs
[09:17:36] [PASSED] 31 VFs
[09:17:36] [PASSED] 32 VFs
[09:17:36] [PASSED] 33 VFs
[09:17:36] [PASSED] 34 VFs
[09:17:36] [PASSED] 35 VFs
[09:17:36] [PASSED] 36 VFs
[09:17:36] [PASSED] 37 VFs
[09:17:36] [PASSED] 38 VFs
[09:17:36] [PASSED] 39 VFs
[09:17:36] [PASSED] 40 VFs
[09:17:36] [PASSED] 41 VFs
[09:17:36] [PASSED] 42 VFs
[09:17:36] [PASSED] 43 VFs
[09:17:36] [PASSED] 44 VFs
[09:17:36] [PASSED] 45 VFs
[09:17:36] [PASSED] 46 VFs
[09:17:36] [PASSED] 47 VFs
[09:17:36] [PASSED] 48 VFs
[09:17:36] [PASSED] 49 VFs
[09:17:36] [PASSED] 50 VFs
[09:17:36] [PASSED] 51 VFs
[09:17:36] [PASSED] 52 VFs
[09:17:36] [PASSED] 53 VFs
[09:17:36] [PASSED] 54 VFs
[09:17:36] [PASSED] 55 VFs
[09:17:36] [PASSED] 56 VFs
[09:17:36] [PASSED] 57 VFs
[09:17:36] [PASSED] 58 VFs
[09:17:36] [PASSED] 59 VFs
[09:17:36] [PASSED] 60 VFs
[09:17:36] [PASSED] 61 VFs
[09:17:36] [PASSED] 62 VFs
[09:17:36] [PASSED] 63 VFs
[09:17:36] ================= [PASSED] fair_doorbells ==================
[09:17:36] ======================== fair_ggtt  ========================
[09:17:36] [PASSED] 1 VF
[09:17:36] [PASSED] 2 VFs
[09:17:36] [PASSED] 3 VFs
[09:17:36] [PASSED] 4 VFs
[09:17:36] [PASSED] 5 VFs
[09:17:36] [PASSED] 6 VFs
[09:17:36] [PASSED] 7 VFs
[09:17:36] [PASSED] 8 VFs
[09:17:36] [PASSED] 9 VFs
[09:17:36] [PASSED] 10 VFs
[09:17:36] [PASSED] 11 VFs
[09:17:36] [PASSED] 12 VFs
[09:17:36] [PASSED] 13 VFs
[09:17:36] [PASSED] 14 VFs
[09:17:36] [PASSED] 15 VFs
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[09:17:36] [PASSED] 18 VFs
[09:17:36] [PASSED] 19 VFs
[09:17:36] [PASSED] 20 VFs
[09:17:36] [PASSED] 21 VFs
[09:17:36] [PASSED] 22 VFs
[09:17:36] [PASSED] 23 VFs
[09:17:36] [PASSED] 24 VFs
[09:17:36] [PASSED] 25 VFs
[09:17:36] [PASSED] 26 VFs
[09:17:36] [PASSED] 27 VFs
[09:17:36] [PASSED] 28 VFs
[09:17:36] [PASSED] 29 VFs
[09:17:36] [PASSED] 30 VFs
[09:17:36] [PASSED] 31 VFs
[09:17:36] [PASSED] 32 VFs
[09:17:36] [PASSED] 33 VFs
[09:17:36] [PASSED] 34 VFs
[09:17:36] [PASSED] 35 VFs
[09:17:36] [PASSED] 36 VFs
[09:17:36] [PASSED] 37 VFs
[09:17:36] [PASSED] 38 VFs
[09:17:36] [PASSED] 39 VFs
[09:17:36] [PASSED] 40 VFs
[09:17:36] [PASSED] 41 VFs
[09:17:36] [PASSED] 42 VFs
[09:17:36] [PASSED] 43 VFs
[09:17:36] [PASSED] 44 VFs
[09:17:36] [PASSED] 45 VFs
[09:17:36] [PASSED] 46 VFs
[09:17:36] [PASSED] 47 VFs
[09:17:36] [PASSED] 48 VFs
[09:17:36] [PASSED] 49 VFs
[09:17:36] [PASSED] 50 VFs
[09:17:36] [PASSED] 51 VFs
[09:17:36] [PASSED] 52 VFs
[09:17:36] [PASSED] 53 VFs
[09:17:36] [PASSED] 54 VFs
[09:17:36] [PASSED] 55 VFs
[09:17:36] [PASSED] 56 VFs
[09:17:36] [PASSED] 57 VFs
[09:17:36] [PASSED] 58 VFs
[09:17:36] [PASSED] 59 VFs
[09:17:36] [PASSED] 60 VFs
[09:17:36] [PASSED] 61 VFs
[09:17:36] [PASSED] 62 VFs
[09:17:36] [PASSED] 63 VFs
[09:17:36] ==================== [PASSED] fair_ggtt ====================
[09:17:36] ======================== fair_vram  ========================
[09:17:36] [PASSED] 1 VF
[09:17:36] [PASSED] 2 VFs
[09:17:36] [PASSED] 3 VFs
[09:17:36] [PASSED] 4 VFs
[09:17:36] [PASSED] 5 VFs
[09:17:36] [PASSED] 6 VFs
[09:17:36] [PASSED] 7 VFs
[09:17:36] [PASSED] 8 VFs
[09:17:36] [PASSED] 9 VFs
[09:17:36] [PASSED] 10 VFs
[09:17:36] [PASSED] 11 VFs
[09:17:36] [PASSED] 12 VFs
[09:17:36] [PASSED] 13 VFs
[09:17:36] [PASSED] 14 VFs
[09:17:36] [PASSED] 15 VFs
[09:17:36] [PASSED] 16 VFs
[09:17:36] [PASSED] 17 VFs
[09:17:36] [PASSED] 18 VFs
[09:17:36] [PASSED] 19 VFs
[09:17:36] [PASSED] 20 VFs
[09:17:36] [PASSED] 21 VFs
[09:17:36] [PASSED] 22 VFs
[09:17:36] [PASSED] 23 VFs
[09:17:36] [PASSED] 24 VFs
[09:17:36] [PASSED] 25 VFs
[09:17:36] [PASSED] 26 VFs
[09:17:36] [PASSED] 27 VFs
[09:17:36] [PASSED] 28 VFs
[09:17:36] [PASSED] 29 VFs
[09:17:36] [PASSED] 30 VFs
[09:17:36] [PASSED] 31 VFs
[09:17:36] [PASSED] 32 VFs
[09:17:36] [PASSED] 33 VFs
[09:17:36] [PASSED] 34 VFs
[09:17:36] [PASSED] 35 VFs
[09:17:36] [PASSED] 36 VFs
[09:17:36] [PASSED] 37 VFs
[09:17:36] [PASSED] 38 VFs
[09:17:36] [PASSED] 39 VFs
[09:17:36] [PASSED] 40 VFs
[09:17:36] [PASSED] 41 VFs
[09:17:36] [PASSED] 42 VFs
[09:17:36] [PASSED] 43 VFs
[09:17:36] [PASSED] 44 VFs
[09:17:36] [PASSED] 45 VFs
[09:17:36] [PASSED] 46 VFs
[09:17:36] [PASSED] 47 VFs
[09:17:36] [PASSED] 48 VFs
[09:17:36] [PASSED] 49 VFs
[09:17:36] [PASSED] 50 VFs
[09:17:36] [PASSED] 51 VFs
[09:17:36] [PASSED] 52 VFs
[09:17:36] [PASSED] 53 VFs
[09:17:36] [PASSED] 54 VFs
[09:17:36] [PASSED] 55 VFs
[09:17:36] [PASSED] 56 VFs
[09:17:36] [PASSED] 57 VFs
[09:17:36] [PASSED] 58 VFs
[09:17:36] [PASSED] 59 VFs
[09:17:36] [PASSED] 60 VFs
[09:17:36] [PASSED] 61 VFs
[09:17:36] [PASSED] 62 VFs
[09:17:36] [PASSED] 63 VFs
[09:17:36] ==================== [PASSED] fair_vram ====================
[09:17:36] ================== [PASSED] pf_gt_config ===================
[09:17:36] ===================== lmtt (1 subtest) =====================
[09:17:36] ======================== test_ops  =========================
[09:17:36] [PASSED] 2-level
[09:17:36] [PASSED] multi-level
[09:17:36] ==================== [PASSED] test_ops =====================
[09:17:36] ====================== [PASSED] lmtt =======================
[09:17:36] ================= sriov_packet (1 subtest) =================
[09:17:36] [PASSED] test_descriptor_init
[09:17:36] ================== [PASSED] sriov_packet ===================
[09:17:36] ================= pf_service (11 subtests) =================
[09:17:36] [PASSED] pf_negotiate_any
[09:17:36] [PASSED] pf_negotiate_base_match
[09:17:36] [PASSED] pf_negotiate_base_newer
[09:17:36] [PASSED] pf_negotiate_base_next
[09:17:36] [SKIPPED] pf_negotiate_base_older (no older minor)
[09:17:36] [PASSED] pf_negotiate_base_prev
[09:17:36] [PASSED] pf_negotiate_latest_match
[09:17:36] [PASSED] pf_negotiate_latest_newer
[09:17:36] [PASSED] pf_negotiate_latest_next
[09:17:36] [SKIPPED] pf_negotiate_latest_older (no older minor)
[09:17:36] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[09:17:36] =================== [PASSED] pf_service ====================
[09:17:36] ================= xe_guc_g2g (2 subtests) ==================
[09:17:36] ============== xe_live_guc_g2g_kunit_default  ==============
[09:17:36] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[09:17:36] ============== xe_live_guc_g2g_kunit_allmem  ===============
[09:17:36] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[09:17:36] =================== [SKIPPED] xe_guc_g2g ===================
[09:17:36] =================== xe_mocs (2 subtests) ===================
[09:17:36] ================ xe_live_mocs_kernel_kunit  ================
[09:17:36] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:17:36] ================ xe_live_mocs_reset_kunit  =================
[09:17:36] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:17:36] ==================== [SKIPPED] xe_mocs =====================
[09:17:36] ================= xe_migrate (2 subtests) ==================
[09:17:36] ================= xe_migrate_sanity_kunit  =================
[09:17:36] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:17:36] ================== xe_validate_ccs_kunit  ==================
[09:17:36] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:17:36] =================== [SKIPPED] xe_migrate ===================
[09:17:36] ================== xe_dma_buf (1 subtest) ==================
[09:17:36] ==================== xe_dma_buf_kunit  =====================
[09:17:36] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:17:36] =================== [SKIPPED] xe_dma_buf ===================
[09:17:36] ================= xe_bo_shrink (1 subtest) =================
[09:17:36] =================== xe_bo_shrink_kunit  ====================
[09:17:36] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:17:36] ================== [SKIPPED] xe_bo_shrink ==================
[09:17:36] ==================== xe_bo (2 subtests) ====================
[09:17:36] ================== xe_ccs_migrate_kunit  ===================
[09:17:36] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:17:36] ==================== xe_bo_evict_kunit  ====================
[09:17:36] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:17:36] ===================== [SKIPPED] xe_bo ======================
[09:17:36] =================== xe_any (9 subtests) ====================
[09:17:36] [PASSED] test_to_xe
[09:17:36] [PASSED] test_to_dev
[09:17:36] [PASSED] test_to_pdev
[09:17:36] [PASSED] test_to_drm
[09:17:36] [PASSED] test_if_pdev
[09:17:36] [PASSED] test_if_xe
[09:17:36] [PASSED] test_if_tile
[09:17:36] [PASSED] test_if_gt
[09:17:36] [PASSED] test_to_id
[09:17:36] ===================== [PASSED] xe_any ======================
[09:17:36] ==================== args (13 subtests) ====================
[09:17:36] [PASSED] count_args_test
[09:17:36] [PASSED] call_args_example
[09:17:36] [PASSED] call_args_test
[09:17:36] [PASSED] drop_first_arg_example
[09:17:36] [PASSED] drop_first_arg_test
[09:17:36] [PASSED] first_arg_example
[09:17:36] [PASSED] first_arg_test
[09:17:36] [PASSED] last_arg_example
[09:17:36] [PASSED] last_arg_test
[09:17:36] [PASSED] pick_arg_example
[09:17:36] [PASSED] if_args_example
[09:17:36] [PASSED] if_args_test
[09:17:36] [PASSED] sep_comma_example
[09:17:36] ====================== [PASSED] args =======================
[09:17:36] =================== xe_pci (3 subtests) ====================
[09:17:36] ==================== check_graphics_ip  ====================
[09:17:36] [PASSED] 12.00 Xe_LP
[09:17:36] [PASSED] 12.10 Xe_LP+
[09:17:36] [PASSED] 12.55 Xe_HPG
[09:17:36] [PASSED] 12.60 Xe_HPC
[09:17:36] [PASSED] 12.70 Xe_LPG
[09:17:36] [PASSED] 12.71 Xe_LPG
[09:17:36] [PASSED] 12.74 Xe_LPG+
[09:17:36] [PASSED] 20.01 Xe2_HPG
[09:17:36] [PASSED] 20.02 Xe2_HPG
[09:17:36] [PASSED] 20.04 Xe2_LPG
[09:17:36] [PASSED] 30.00 Xe3_LPG
[09:17:36] [PASSED] 30.01 Xe3_LPG
[09:17:36] [PASSED] 30.03 Xe3_LPG
[09:17:36] [PASSED] 30.04 Xe3_LPG
[09:17:36] [PASSED] 30.05 Xe3_LPG
[09:17:36] [PASSED] 35.10 Xe3p_LPG
[09:17:36] [PASSED] 35.11 Xe3p_XPC
[09:17:36] ================ [PASSED] check_graphics_ip ================
[09:17:36] ===================== check_media_ip  ======================
[09:17:36] [PASSED] 12.00 Xe_M
[09:17:36] [PASSED] 12.55 Xe_HPM
[09:17:36] [PASSED] 13.00 Xe_LPM+
[09:17:36] [PASSED] 13.01 Xe2_HPM
[09:17:36] [PASSED] 20.00 Xe2_LPM
[09:17:36] [PASSED] 30.00 Xe3_LPM
[09:17:36] [PASSED] 30.02 Xe3_LPM
[09:17:36] [PASSED] 35.00 Xe3p_LPM
[09:17:36] [PASSED] 35.03 Xe3p_HPM
[09:17:36] ================= [PASSED] check_media_ip ==================
[09:17:36] =================== check_platform_desc  ===================
[09:17:36] [PASSED] 0x9A60 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A68 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A70 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A40 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A49 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A59 (TIGERLAKE)
[09:17:36] [PASSED] 0x9A78 (TIGERLAKE)
[09:17:36] [PASSED] 0x9AC0 (TIGERLAKE)
[09:17:36] [PASSED] 0x9AC9 (TIGERLAKE)
[09:17:36] [PASSED] 0x9AD9 (TIGERLAKE)
[09:17:36] [PASSED] 0x9AF8 (TIGERLAKE)
[09:17:36] [PASSED] 0x4C80 (ROCKETLAKE)
[09:17:36] [PASSED] 0x4C8A (ROCKETLAKE)
[09:17:36] [PASSED] 0x4C8B (ROCKETLAKE)
[09:17:36] [PASSED] 0x4C8C (ROCKETLAKE)
[09:17:36] [PASSED] 0x4C90 (ROCKETLAKE)
[09:17:36] [PASSED] 0x4C9A (ROCKETLAKE)
[09:17:36] [PASSED] 0x4680 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4682 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4688 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x468A (ALDERLAKE_S)
[09:17:36] [PASSED] 0x468B (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4690 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4692 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4693 (ALDERLAKE_S)
[09:17:36] [PASSED] 0x46A0 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46A1 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46A2 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46A3 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46A6 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46A8 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46AA (ALDERLAKE_P)
[09:17:36] [PASSED] 0x462A (ALDERLAKE_P)
[09:17:36] [PASSED] 0x4626 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x4628 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46B0 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46B1 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46B2 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46B3 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46C0 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46C1 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46C2 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46C3 (ALDERLAKE_P)
[09:17:36] [PASSED] 0x46D0 (ALDERLAKE_N)
[09:17:36] [PASSED] 0x46D1 (ALDERLAKE_N)
[09:17:36] [PASSED] 0x46D2 (ALDERLAKE_N)
[09:17:36] [PASSED] 0x46D3 (ALDERLAKE_N)
[09:17:36] [PASSED] 0x46D4 (ALDERLAKE_N)
[09:17:36] [PASSED] 0xA721 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7A1 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7A9 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7AC (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7AD (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA720 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7A0 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7A8 (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7AA (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA7AB (ALDERLAKE_P)
[09:17:36] [PASSED] 0xA780 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA781 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA782 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA783 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA788 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA789 (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA78A (ALDERLAKE_S)
[09:17:36] [PASSED] 0xA78B (ALDERLAKE_S)
[09:17:36] [PASSED] 0x4905 (DG1)
[09:17:36] [PASSED] 0x4906 (DG1)
[09:17:36] [PASSED] 0x4907 (DG1)
[09:17:36] [PASSED] 0x4908 (DG1)
[09:17:36] [PASSED] 0x4909 (DG1)
[09:17:36] [PASSED] 0x56C0 (DG2)
[09:17:36] [PASSED] 0x56C2 (DG2)
[09:17:36] [PASSED] 0x56C1 (DG2)
[09:17:36] [PASSED] 0x7D51 (METEORLAKE)
[09:17:36] [PASSED] 0x7DD1 (METEORLAKE)
[09:17:36] [PASSED] 0x7D41 (METEORLAKE)
[09:17:36] [PASSED] 0x7D67 (METEORLAKE)
[09:17:36] [PASSED] 0xB640 (METEORLAKE)
[09:17:36] [PASSED] 0x56A0 (DG2)
[09:17:36] [PASSED] 0x56A1 (DG2)
[09:17:36] [PASSED] 0x56A2 (DG2)
[09:17:36] [PASSED] 0x56BE (DG2)
[09:17:36] [PASSED] 0x56BF (DG2)
[09:17:36] [PASSED] 0x5690 (DG2)
[09:17:36] [PASSED] 0x5691 (DG2)
[09:17:36] [PASSED] 0x5692 (DG2)
[09:17:36] [PASSED] 0x56A5 (DG2)
[09:17:36] [PASSED] 0x56A6 (DG2)
[09:17:36] [PASSED] 0x56B0 (DG2)
[09:17:36] [PASSED] 0x56B1 (DG2)
[09:17:36] [PASSED] 0x56BA (DG2)
[09:17:36] [PASSED] 0x56BB (DG2)
[09:17:36] [PASSED] 0x56BC (DG2)
[09:17:36] [PASSED] 0x56BD (DG2)
[09:17:36] [PASSED] 0x5693 (DG2)
[09:17:36] [PASSED] 0x5694 (DG2)
[09:17:36] [PASSED] 0x5695 (DG2)
[09:17:36] [PASSED] 0x56A3 (DG2)
[09:17:36] [PASSED] 0x56A4 (DG2)
[09:17:36] [PASSED] 0x56B2 (DG2)
[09:17:36] [PASSED] 0x56B3 (DG2)
[09:17:36] [PASSED] 0x5696 (DG2)
[09:17:36] [PASSED] 0x5697 (DG2)
[09:17:36] [PASSED] 0xB69 (PVC)
[09:17:36] [PASSED] 0xB6E (PVC)
[09:17:36] [PASSED] 0xBD4 (PVC)
[09:17:36] [PASSED] 0xBD5 (PVC)
[09:17:36] [PASSED] 0xBD6 (PVC)
[09:17:36] [PASSED] 0xBD7 (PVC)
[09:17:36] [PASSED] 0xBD8 (PVC)
[09:17:36] [PASSED] 0xBD9 (PVC)
[09:17:36] [PASSED] 0xBDA (PVC)
[09:17:36] [PASSED] 0xBDB (PVC)
[09:17:36] [PASSED] 0xBE0 (PVC)
[09:17:36] [PASSED] 0xBE1 (PVC)
[09:17:36] [PASSED] 0xBE5 (PVC)
[09:17:36] [PASSED] 0x7D40 (METEORLAKE)
[09:17:36] [PASSED] 0x7D45 (METEORLAKE)
[09:17:36] [PASSED] 0x7D55 (METEORLAKE)
[09:17:36] [PASSED] 0x7D60 (METEORLAKE)
[09:17:36] [PASSED] 0x7DD5 (METEORLAKE)
[09:17:36] [PASSED] 0x6420 (LUNARLAKE)
[09:17:36] [PASSED] 0x64A0 (LUNARLAKE)
[09:17:36] [PASSED] 0x64B0 (LUNARLAKE)
[09:17:36] [PASSED] 0xE202 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE209 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE20B (BATTLEMAGE)
[09:17:36] [PASSED] 0xE20C (BATTLEMAGE)
[09:17:36] [PASSED] 0xE20D (BATTLEMAGE)
[09:17:36] [PASSED] 0xE210 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE211 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE212 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE216 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE220 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE221 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE222 (BATTLEMAGE)
[09:17:36] [PASSED] 0xE223 (BATTLEMAGE)
[09:17:36] [PASSED] 0xB080 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB081 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB082 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB083 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB084 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB085 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB086 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB087 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB08F (PANTHERLAKE)
[09:17:36] [PASSED] 0xB090 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB0A0 (PANTHERLAKE)
[09:17:36] [PASSED] 0xB0B0 (PANTHERLAKE)
[09:17:36] [PASSED] 0xFD80 (PANTHERLAKE)
[09:17:36] [PASSED] 0xFD81 (PANTHERLAKE)
[09:17:36] [PASSED] 0xD740 (NOVALAKE_S)
[09:17:36] [PASSED] 0xD741 (NOVALAKE_S)
[09:17:36] [PASSED] 0xD742 (NOVALAKE_S)
[09:17:36] [PASSED] 0xD743 (NOVALAKE_S)
[09:17:36] [PASSED] 0xD745 (NOVALAKE_S)
[09:17:36] [PASSED] 0xD74A (NOVALAKE_S)
[09:17:36] [PASSED] 0xD74B (NOVALAKE_S)
[09:17:36] [PASSED] 0x674C (CRESCENTISLAND)
[09:17:36] [PASSED] 0x674D (CRESCENTISLAND)
[09:17:36] [PASSED] 0x674E (CRESCENTISLAND)
[09:17:36] [PASSED] 0x674F (CRESCENTISLAND)
[09:17:36] [PASSED] 0x6750 (CRESCENTISLAND)
[09:17:36] [PASSED] 0xD750 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD751 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD752 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD753 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD754 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD755 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD756 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD757 (NOVALAKE_P)
[09:17:36] [PASSED] 0xD75F (NOVALAKE_P)
[09:17:36] =============== [PASSED] check_platform_desc ===============
[09:17:36] ===================== [PASSED] xe_pci ======================
[09:17:36] ============= xe_rtp_tables_test (5 subtests) ==============
[09:17:36] ================== xe_rtp_table_gt_test  ===================
[09:17:36] [PASSED] gt_was/14011060649
[09:17:36] [PASSED] gt_was/14011059788
[09:17:36] [PASSED] gt_was/14015795083
[09:17:36] [PASSED] gt_was/16021867713
[09:17:36] [PASSED] gt_was/14019449301
[09:17:36] [PASSED] gt_was/16028005424
[09:17:36] [PASSED] gt_was/14026578760
[09:17:36] [PASSED] gt_was/1409420604
[09:17:36] [PASSED] gt_was/1408615072
[09:17:36] [PASSED] gt_was/22010523718
[09:17:36] [PASSED] gt_was/14011006942
[09:17:36] [PASSED] gt_was/14014830051
[09:17:36] [PASSED] gt_was/18018781329
[09:17:36] [PASSED] gt_was/1509235366
[09:17:36] [PASSED] gt_was/18018781329
[09:17:36] [PASSED] gt_was/16016694945
[09:17:36] [PASSED] gt_was/14018575942
[09:17:36] [PASSED] gt_was/22016670082
[09:17:36] [PASSED] gt_was/22016670082
[09:17:36] [PASSED] gt_was/14017421178
[09:17:36] [PASSED] gt_was/16025250150
[09:17:36] [PASSED] gt_was/14021871409
[09:17:36] [PASSED] gt_was/16021865536
[09:17:36] [PASSED] gt_was/14021486841
[09:17:36] [PASSED] gt_was/14025160223
[09:17:36] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[09:17:36] [PASSED] gt_was/14025635424
[09:17:36] [PASSED] gt_was/16028005424
[09:17:36] ============== [PASSED] xe_rtp_table_gt_test ===============
[09:17:36] ================== xe_rtp_table_gt_test  ===================
[09:17:36] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[09:17:36] [PASSED] gt_tunings/Tuning: 32B Access Enable
[09:17:36] [PASSED] gt_tunings/Tuning: L3 cache
[09:17:36] [PASSED] gt_tunings/Tuning: L3 cache - media
[09:17:36] [PASSED] gt_tunings/Tuning: Compression Overfetch
[09:17:36] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[09:17:36] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[09:17:36] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[09:17:36] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[09:17:36] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[09:17:36] [PASSED] gt_tunings/Tuning: Stateless compression control
[09:17:36] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[09:17:36] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[09:17:36] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[09:17:36] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[09:17:36] ============== [PASSED] xe_rtp_table_gt_test ===============
[09:17:36] ================== xe_rtp_table_oob_test  ==================
[09:17:36] [PASSED] oob_was/1607983814
[09:17:36] [PASSED] oob_was/16010904313
[09:17:36] [PASSED] oob_was/18022495364
[09:17:36] [PASSED] oob_was/22012773006
[09:17:36] [PASSED] oob_was/14014475959
[09:17:36] [PASSED] oob_was/22011391025
[09:17:36] [PASSED] oob_was/22012727170
[09:17:36] [PASSED] oob_was/22012727685
[09:17:36] [PASSED] oob_was/22016596838
[09:17:36] [PASSED] oob_was/18020744125
[09:17:36] [PASSED] oob_was/1409600907
[09:17:36] [PASSED] oob_was/22014953428
[09:17:36] [PASSED] oob_was/16017236439
[09:17:36] [PASSED] oob_was/14019821291
[09:17:36] [PASSED] oob_was/14015076503
[09:17:36] [PASSED] oob_was/14018913170
[09:17:36] [PASSED] oob_was/14018094691
[09:17:36] [PASSED] oob_was/18024947630
[09:17:36] [PASSED] oob_was/16022287689
[09:17:36] [PASSED] oob_was/13011645652
[09:17:36] [PASSED] oob_was/14022293748
[09:17:36] [PASSED] oob_was/22019794406
[09:17:36] [PASSED] oob_was/22019338487
[09:17:36] [PASSED] oob_was/16023588340
[09:17:36] [PASSED] oob_was/14019789679
[09:17:36] [PASSED] oob_was/14022866841
[09:17:36] [PASSED] oob_was/16021333562
[09:17:36] [PASSED] oob_was/14016712196
[09:17:36] [PASSED] oob_was/14015568240
[09:17:36] [PASSED] oob_was/18013179988
[09:17:36] [PASSED] oob_was/1508761755
[09:17:36] [PASSED] oob_was/16023105232
[09:17:36] [PASSED] oob_was/16026508708
[09:17:36] [PASSED] oob_was/14020001231
[09:17:36] [PASSED] oob_was/16023683509
[09:17:36] [PASSED] oob_was/14025515070
[09:17:36] [PASSED] oob_was/15015404425_disable
[09:17:36] [PASSED] oob_was/16026007364
[09:17:36] [PASSED] oob_was/14020316580
[09:17:36] [PASSED] oob_was/14025883347
[09:17:36] [PASSED] oob_was/16029380221
[09:17:36] [PASSED] oob_was/22022079272
[09:17:36] [PASSED] oob_was/16029897822
[09:17:36] [PASSED] oob_was/14027054324
[09:17:36] ============== [PASSED] xe_rtp_table_oob_test ==============
[09:17:36] ================ xe_rtp_table_dev_oob_test  ================
[09:17:36] [PASSED] device_oob_was/22010954014
[09:17:36] [PASSED] device_oob_was/15015404425
[09:17:36] [PASSED] device_oob_was/22019338487_display
[09:17:36] [PASSED] device_oob_was/14022085890
[09:17:36] [PASSED] device_oob_was/14026539277
[09:17:36] [PASSED] device_oob_was/14026633728
[09:17:36] [PASSED] device_oob_was/14026746987
[09:17:36] [PASSED] device_oob_was/14026779378
[09:17:36] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[09:17:36] ========== xe_rtp_table_missing_upper_bound_test  ==========
[09:17:36] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[09:17:36] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[09:17:36] [PASSED] register_whitelist/1806527549
[09:17:36] [PASSED] register_whitelist/allow_read_ctx_timestamp
[09:17:36] [PASSED] register_whitelist/allow_read_queue_timestamp
[09:17:36] [PASSED] register_whitelist/16014440446
[09:17:36] [PASSED] register_whitelist/16017236439
[09:17:36] [PASSED] register_whitelist/16020183090
[09:17:36] [PASSED] register_whitelist/14024997852
[09:17:36] [PASSED] register_whitelist/14024997852
[09:17:36] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[09:17:36] =============== [PASSED] xe_rtp_tables_test ================
[09:17:36] =================== xe_rtp (3 subtests) ====================
[09:17:36] =================== xe_rtp_rules_tests  ====================
[09:17:36] [PASSED] no
[09:17:36] [PASSED] yes
[09:17:36] [PASSED] no-and-no
[09:17:36] [PASSED] no-and-yes
[09:17:36] [PASSED] yes-and-no
[09:17:36] [PASSED] yes-and-yes
[09:17:36] [PASSED] no-or-no
[09:17:36] [PASSED] no-or-yes
[09:17:36] [PASSED] yes-or-no
[09:17:36] [PASSED] yes-or-yes
[09:17:36] [PASSED] no-yes-or-yes-no
[09:17:36] [PASSED] no-yes-or-yes-yes
[09:17:36] [PASSED] yes-yes-or-no-yes
[09:17:36] [PASSED] yes-yes-or-yes-yes
[09:17:36] [PASSED] no-no-or-yes-or-no
[09:17:36] [PASSED] or
[09:17:36] [PASSED] or-yes
[09:17:36] [PASSED] or-no
[09:17:36] [PASSED] yes-or
[09:17:36] [PASSED] no-or
[09:17:36] [PASSED] no-or-or-yes
[09:17:36] [PASSED] yes-or-or-no
[09:17:36] [PASSED] no-or-or-no
[09:17:36] [PASSED] missing-context-engine-class
[09:17:36] [PASSED] missing-context-engine-class-or-yes
[09:17:36] [PASSED] missing-context-engine-class-or-or-yes
[09:17:36] =============== [PASSED] xe_rtp_rules_tests ================
[09:17:37] =============== xe_rtp_process_to_sr_tests  ================
[09:17:37] [PASSED] coalesce-same-reg
[09:17:37] [PASSED] coalesce-same-reg-literal-and-func
[09:17:37] [PASSED] no-match-no-add
[09:17:37] [PASSED] two-regs-two-entries
[09:17:37] [PASSED] clr-one-set-other
[09:17:37] [PASSED] set-field
[09:17:37] [PASSED] conflict-duplicate
[09:17:37] [PASSED] conflict-not-disjoint
[09:17:37] [PASSED] conflict-not-disjoint-literal-and-func
[09:17:37] [PASSED] conflict-reg-type
[09:17:37] [PASSED] bad-mcr-reg-forced-to-regular
[09:17:37] [PASSED] bad-regular-reg-forced-to-mcr
[09:17:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:17:37] ================== xe_rtp_process_tests  ===================
[09:17:37] [PASSED] active1
[09:17:37] [PASSED] active2
[09:17:37] [PASSED] active-inactive
[09:17:37] [PASSED] inactive-active
[09:17:37] [PASSED] inactive-active-inactive
[09:17:37] [PASSED] inactive-inactive-inactive
[09:17:37] ============== [PASSED] xe_rtp_process_tests ===============
[09:17:37] ===================== [PASSED] xe_rtp ======================
[09:17:37] ==================== xe_wa (1 subtest) =====================
[09:17:37] ======================== xe_wa_gt  =========================
[09:17:37] [PASSED] TIGERLAKE B0
[09:17:37] [PASSED] DG1 A0
[09:17:37] [PASSED] DG1 B0
[09:17:37] [PASSED] ALDERLAKE_S A0
[09:17:37] [PASSED] ALDERLAKE_S B0
[09:17:37] [PASSED] ALDERLAKE_S C0
[09:17:37] [PASSED] ALDERLAKE_S D0
[09:17:37] [PASSED] ALDERLAKE_P A0
[09:17:37] [PASSED] ALDERLAKE_P B0
[09:17:37] [PASSED] ALDERLAKE_P C0
[09:17:37] [PASSED] ALDERLAKE_S RPLS D0
[09:17:37] [PASSED] ALDERLAKE_P RPLU E0
[09:17:37] [PASSED] DG2 G10 C0
[09:17:37] [PASSED] DG2 G11 B1
[09:17:37] [PASSED] DG2 G12 A1
[09:17:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:17:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:17:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[09:17:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[09:17:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[09:17:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[09:17:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[09:17:37] ==================== [PASSED] xe_wa_gt =====================
[09:17:37] ====================== [PASSED] xe_wa ======================
[09:17:37] ============================================================
[09:17:37] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[09:17:37] Elapsed time: 36.297s total, 1.831s configuring, 33.700s building, 0.715s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:17:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:17:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:18:04] Starting KUnit Kernel (1/1)...
[09:18:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:18:04] ============= refcount_interrupt (4 subtests) ==============
[09:18:04] [PASSED] test_single_irq_change
[09:18:04] [PASSED] test_nested_irq_change
[09:18:04] [PASSED] test_multiple_irq_change
[09:18:04] [PASSED] test_irq_save
[09:18:04] =============== [PASSED] refcount_interrupt ================
[09:18:04] ============ drm_test_pick_cmdline (2 subtests) ============
[09:18:04] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[09:18:04] =============== drm_test_pick_cmdline_named  ===============
[09:18:04] [PASSED] NTSC
[09:18:04] [PASSED] NTSC-J
[09:18:04] [PASSED] PAL
[09:18:04] [PASSED] PAL-M
[09:18:04] =========== [PASSED] drm_test_pick_cmdline_named ===========
[09:18:04] ============== [PASSED] drm_test_pick_cmdline ==============
[09:18:04] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:18:04] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:18:04] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:18:04] =========== drm_validate_clone_mode (2 subtests) ===========
[09:18:04] ============== drm_test_check_in_clone_mode  ===============
[09:18:04] [PASSED] in_clone_mode
[09:18:04] [PASSED] not_in_clone_mode
[09:18:04] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:18:04] =============== drm_test_check_valid_clones  ===============
[09:18:04] [PASSED] not_in_clone_mode
[09:18:04] [PASSED] valid_clone
[09:18:04] [PASSED] invalid_clone
[09:18:04] =========== [PASSED] drm_test_check_valid_clones ===========
[09:18:04] ============= [PASSED] drm_validate_clone_mode =============
[09:18:04] ============= drm_validate_modeset (1 subtest) =============
[09:18:04] [PASSED] drm_test_check_connector_changed_modeset
[09:18:04] ============== [PASSED] drm_validate_modeset ===============
[09:18:04] ====== drm_test_bridge_get_current_state (1 subtest) =======
[09:18:04] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:18:04] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:18:04] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:18:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:18:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:18:04] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[09:18:04] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:18:04] ============== drm_bridge_alloc (2 subtests) ===============
[09:18:04] [PASSED] drm_test_drm_bridge_alloc_basic
[09:18:04] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:18:04] ================ [PASSED] drm_bridge_alloc =================
[09:18:04] ============= drm_bridge_bus_fmt (5 subtests) ==============
[09:18:04] [PASSED] drm_test_bridge_rgb_yuv_rgb
[09:18:04] [PASSED] drm_test_bridge_must_convert_to_yuv444
[09:18:04] [PASSED] drm_test_bridge_hdmi_auto_rgb
[09:18:04] [PASSED] drm_test_bridge_auto_first
[09:18:04] [PASSED] drm_test_bridge_rgb_yuv_no_path
[09:18:04] =============== [PASSED] drm_bridge_bus_fmt ================
[09:18:04] ============= drm_cmdline_parser (40 subtests) =============
[09:18:04] [PASSED] drm_test_cmdline_force_d_only
[09:18:04] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:18:04] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:18:04] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:18:04] [PASSED] drm_test_cmdline_force_e_only
[09:18:04] [PASSED] drm_test_cmdline_res
[09:18:04] [PASSED] drm_test_cmdline_res_vesa
[09:18:04] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:18:04] [PASSED] drm_test_cmdline_res_rblank
[09:18:04] [PASSED] drm_test_cmdline_res_bpp
[09:18:04] [PASSED] drm_test_cmdline_res_refresh
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:18:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:18:04] [PASSED] drm_test_cmdline_res_margins_force_on
[09:18:04] [PASSED] drm_test_cmdline_res_vesa_margins
[09:18:04] [PASSED] drm_test_cmdline_name
[09:18:04] [PASSED] drm_test_cmdline_name_bpp
[09:18:04] [PASSED] drm_test_cmdline_name_option
[09:18:04] [PASSED] drm_test_cmdline_name_bpp_option
[09:18:04] [PASSED] drm_test_cmdline_rotate_0
[09:18:04] [PASSED] drm_test_cmdline_rotate_90
[09:18:04] [PASSED] drm_test_cmdline_rotate_180
[09:18:04] [PASSED] drm_test_cmdline_rotate_270
[09:18:04] [PASSED] drm_test_cmdline_hmirror
[09:18:04] [PASSED] drm_test_cmdline_vmirror
[09:18:04] [PASSED] drm_test_cmdline_margin_options
[09:18:04] [PASSED] drm_test_cmdline_multiple_options
[09:18:04] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:18:04] [PASSED] drm_test_cmdline_extra_and_option
[09:18:04] [PASSED] drm_test_cmdline_freestanding_options
[09:18:04] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:18:04] [PASSED] drm_test_cmdline_panel_orientation
[09:18:04] ================ drm_test_cmdline_invalid  =================
[09:18:04] [PASSED] margin_only
[09:18:04] [PASSED] interlace_only
[09:18:04] [PASSED] res_missing_x
[09:18:04] [PASSED] res_missing_y
[09:18:04] [PASSED] res_bad_y
[09:18:04] [PASSED] res_missing_y_bpp
[09:18:04] [PASSED] res_bad_bpp
[09:18:04] [PASSED] res_bad_refresh
[09:18:04] [PASSED] res_bpp_refresh_force_on_off
[09:18:04] [PASSED] res_invalid_mode
[09:18:04] [PASSED] res_bpp_wrong_place_mode
[09:18:04] [PASSED] name_bpp_refresh
[09:18:04] [PASSED] name_refresh
[09:18:04] [PASSED] name_refresh_wrong_mode
[09:18:04] [PASSED] name_refresh_invalid_mode
[09:18:04] [PASSED] rotate_multiple
[09:18:04] [PASSED] rotate_invalid_val
[09:18:04] [PASSED] rotate_truncated
[09:18:04] [PASSED] invalid_option
[09:18:04] [PASSED] invalid_tv_option
[09:18:04] [PASSED] truncated_tv_option
[09:18:04] ============ [PASSED] drm_test_cmdline_invalid =============
[09:18:04] =============== drm_test_cmdline_tv_options  ===============
[09:18:04] [PASSED] NTSC
[09:18:04] [PASSED] NTSC_443
[09:18:04] [PASSED] NTSC_J
[09:18:04] [PASSED] PAL
[09:18:04] [PASSED] PAL_M
[09:18:04] [PASSED] PAL_N
[09:18:04] [PASSED] SECAM
[09:18:04] [PASSED] MONO_525
[09:18:04] [PASSED] MONO_625
[09:18:04] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:18:04] =============== [PASSED] drm_cmdline_parser ================
[09:18:04] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:18:04] [PASSED] drm_test_connector_hdmi_init_valid
[09:18:04] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:18:04] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:18:04] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:18:04] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:18:04] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:18:04] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:18:04] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:18:04] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[09:18:04] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:18:04] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:18:04] [PASSED] supported_formats=0x5 yuv420_allowed=1
[09:18:04] [PASSED] supported_formats=0x5 yuv420_allowed=0
[09:18:04] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:18:04] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:18:04] [PASSED] drm_test_connector_hdmi_init_null_product
[09:18:04] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:18:04] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:18:04] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:18:04] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:18:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:18:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:18:04] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:18:04] ========= drm_test_connector_hdmi_init_type_valid  =========
[09:18:04] [PASSED] HDMI-A
[09:18:04] [PASSED] HDMI-B
[09:18:04] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:18:04] ======== drm_test_connector_hdmi_init_type_invalid  ========
[09:18:04] [PASSED] Unknown
[09:18:04] [PASSED] VGA
[09:18:04] [PASSED] DVI-I
[09:18:04] [PASSED] DVI-D
[09:18:04] [PASSED] DVI-A
[09:18:04] [PASSED] Composite
[09:18:04] [PASSED] SVIDEO
[09:18:04] [PASSED] LVDS
[09:18:04] [PASSED] Component
[09:18:04] [PASSED] DIN
[09:18:04] [PASSED] DP
[09:18:04] [PASSED] TV
[09:18:04] [PASSED] eDP
[09:18:04] [PASSED] Virtual
[09:18:04] [PASSED] DSI
[09:18:04] [PASSED] DPI
[09:18:04] [PASSED] Writeback
[09:18:04] [PASSED] SPI
[09:18:04] [PASSED] USB
[09:18:04] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:18:04] ============ [PASSED] drmm_connector_hdmi_init =============
[09:18:04] ============= drmm_connector_init (3 subtests) =============
[09:18:04] [PASSED] drm_test_drmm_connector_init
[09:18:04] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:18:04] ========= drm_test_drmm_connector_init_type_valid  =========
[09:18:04] [PASSED] Unknown
[09:18:04] [PASSED] VGA
[09:18:04] [PASSED] DVI-I
[09:18:04] [PASSED] DVI-D
[09:18:04] [PASSED] DVI-A
[09:18:04] [PASSED] Composite
[09:18:04] [PASSED] SVIDEO
[09:18:04] [PASSED] LVDS
[09:18:04] [PASSED] Component
[09:18:04] [PASSED] DIN
[09:18:04] [PASSED] DP
[09:18:04] [PASSED] HDMI-A
[09:18:04] [PASSED] HDMI-B
[09:18:04] [PASSED] TV
[09:18:04] [PASSED] eDP
[09:18:04] [PASSED] Virtual
[09:18:04] [PASSED] DSI
[09:18:04] [PASSED] DPI
[09:18:04] [PASSED] Writeback
[09:18:04] [PASSED] SPI
[09:18:04] [PASSED] USB
[09:18:04] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:18:04] =============== [PASSED] drmm_connector_init ===============
[09:18:04] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_init
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:18:04] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[09:18:04] [PASSED] Unknown
[09:18:04] [PASSED] VGA
[09:18:04] [PASSED] DVI-I
[09:18:04] [PASSED] DVI-D
[09:18:04] [PASSED] DVI-A
[09:18:04] [PASSED] Composite
[09:18:04] [PASSED] SVIDEO
[09:18:04] [PASSED] LVDS
[09:18:04] [PASSED] Component
[09:18:04] [PASSED] DIN
[09:18:04] [PASSED] DP
[09:18:04] [PASSED] HDMI-A
[09:18:04] [PASSED] HDMI-B
[09:18:04] [PASSED] TV
[09:18:04] [PASSED] eDP
[09:18:04] [PASSED] Virtual
[09:18:04] [PASSED] DSI
[09:18:04] [PASSED] DPI
[09:18:04] [PASSED] Writeback
[09:18:04] [PASSED] SPI
[09:18:04] [PASSED] USB
[09:18:04] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:18:04] ======== drm_test_drm_connector_dynamic_init_name  =========
[09:18:04] [PASSED] Unknown
[09:18:04] [PASSED] VGA
[09:18:04] [PASSED] DVI-I
[09:18:04] [PASSED] DVI-D
[09:18:04] [PASSED] DVI-A
[09:18:04] [PASSED] Composite
[09:18:04] [PASSED] SVIDEO
[09:18:04] [PASSED] LVDS
[09:18:04] [PASSED] Component
[09:18:04] [PASSED] DIN
[09:18:04] [PASSED] DP
[09:18:04] [PASSED] HDMI-A
[09:18:04] [PASSED] HDMI-B
[09:18:04] [PASSED] TV
[09:18:04] [PASSED] eDP
[09:18:04] [PASSED] Virtual
[09:18:04] [PASSED] DSI
[09:18:04] [PASSED] DPI
[09:18:04] [PASSED] Writeback
[09:18:04] [PASSED] SPI
[09:18:04] [PASSED] USB
[09:18:04] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:18:04] =========== [PASSED] drm_connector_dynamic_init ============
[09:18:04] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:18:04] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:18:04] ======= drm_connector_dynamic_register (7 subtests) ========
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:18:04] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:18:04] ========= [PASSED] drm_connector_dynamic_register ==========
[09:18:04] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:18:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:18:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:18:04] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:18:04] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:18:04] ========== drm_test_get_tv_mode_from_name_valid  ===========
[09:18:04] [PASSED] NTSC
[09:18:04] [PASSED] NTSC-443
[09:18:04] [PASSED] NTSC-J
[09:18:04] [PASSED] PAL
[09:18:04] [PASSED] PAL-M
[09:18:04] [PASSED] PAL-N
[09:18:04] [PASSED] SECAM
[09:18:04] [PASSED] Mono
[09:18:04] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:18:04] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:18:04] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:18:04] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:18:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:18:04] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[09:18:04] [PASSED] VIC 96
[09:18:04] [PASSED] VIC 97
[09:18:04] [PASSED] VIC 101
[09:18:04] [PASSED] VIC 102
[09:18:04] [PASSED] VIC 106
[09:18:04] [PASSED] VIC 107
[09:18:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:18:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:18:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:18:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:18:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:18:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:18:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:18:04] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:18:04] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[09:18:04] [PASSED] Automatic
[09:18:04] [PASSED] Full
[09:18:04] [PASSED] Limited 16:235
[09:18:04] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:18:04] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:18:04] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:18:04] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:18:04] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[09:18:04] [PASSED] RGB
[09:18:04] [PASSED] YUV 4:2:0
[09:18:04] [PASSED] YUV 4:2:2
[09:18:04] [PASSED] YUV 4:4:4
[09:18:04] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:18:04] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:18:04] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:18:04] ============= drm_damage_helper (21 subtests) ==============
[09:18:04] [PASSED] drm_test_damage_iter_no_damage
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:18:04] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:18:04] [PASSED] drm_test_damage_iter_simple_damage
[09:18:04] [PASSED] drm_test_damage_iter_single_damage
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:18:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:18:04] [PASSED] drm_test_damage_iter_damage
[09:18:04] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:18:04] [PASSED] drm_test_damage_iter_damage_one_outside
[09:18:04] [PASSED] drm_test_damage_iter_damage_src_moved
[09:18:04] [PASSED] drm_test_damage_iter_damage_not_visible
[09:18:04] ================ [PASSED] drm_damage_helper ================
[09:18:04] ============== drm_dp_mst_helper (3 subtests) ==============
[09:18:04] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[09:18:04] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:18:04] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:18:04] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:18:04] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:18:04] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:18:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:18:04] ============== drm_test_dp_mst_calc_pbn_div  ===============
[09:18:04] [PASSED] Link rate 2000000 lane count 4
[09:18:04] [PASSED] Link rate 2000000 lane count 2
[09:18:04] [PASSED] Link rate 2000000 lane count 1
[09:18:04] [PASSED] Link rate 1350000 lane count 4
[09:18:04] [PASSED] Link rate 1350000 lane count 2
[09:18:04] [PASSED] Link rate 1350000 lane count 1
[09:18:04] [PASSED] Link rate 1000000 lane count 4
[09:18:04] [PASSED] Link rate 1000000 lane count 2
[09:18:04] [PASSED] Link rate 1000000 lane count 1
[09:18:04] [PASSED] Link rate 810000 lane count 4
[09:18:04] [PASSED] Link rate 810000 lane count 2
[09:18:04] [PASSED] Link rate 810000 lane count 1
[09:18:04] [PASSED] Link rate 540000 lane count 4
[09:18:04] [PASSED] Link rate 540000 lane count 2
[09:18:04] [PASSED] Link rate 540000 lane count 1
[09:18:04] [PASSED] Link rate 270000 lane count 4
[09:18:04] [PASSED] Link rate 270000 lane count 2
[09:18:04] [PASSED] Link rate 270000 lane count 1
[09:18:04] [PASSED] Link rate 162000 lane count 4
[09:18:04] [PASSED] Link rate 162000 lane count 2
[09:18:04] [PASSED] Link rate 162000 lane count 1
[09:18:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:18:04] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[09:18:04] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:18:04] [PASSED] DP_POWER_UP_PHY with port number
[09:18:04] [PASSED] DP_POWER_DOWN_PHY with port number
[09:18:04] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:18:04] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:18:04] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:18:04] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:18:04] [PASSED] DP_QUERY_PAYLOAD with port number
[09:18:04] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:18:04] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:18:04] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:18:04] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:18:04] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:18:04] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:18:04] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:18:04] [PASSED] DP_REMOTE_I2C_READ with port number
[09:18:04] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:18:04] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:18:04] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:18:04] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:18:04] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:18:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:18:04] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:18:04] ================ [PASSED] drm_dp_mst_helper ================
[09:18:04] ================== drm_exec (7 subtests) ===================
[09:18:04] [PASSED] sanitycheck
[09:18:04] [PASSED] test_lock
[09:18:04] [PASSED] test_lock_unlock
[09:18:04] [PASSED] test_duplicates
[09:18:04] [PASSED] test_prepare
[09:18:04] [PASSED] test_prepare_array
[09:18:04] [PASSED] test_multiple_loops
[09:18:04] ==================== [PASSED] drm_exec =====================
[09:18:04] =========== drm_format_helper_test (17 subtests) ===========
[09:18:04] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:18:04] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:18:04] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:18:04] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:18:04] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:18:04] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:18:04] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:18:04] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:18:04] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:18:04] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:18:04] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:18:04] ============== drm_test_fb_xrgb8888_to_mono  ===============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:18:04] ==================== drm_test_fb_swab  =====================
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ================ [PASSED] drm_test_fb_swab =================
[09:18:04] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:18:04] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[09:18:04] [PASSED] single_pixel_source_buffer
[09:18:04] [PASSED] single_pixel_clip_rectangle
[09:18:04] [PASSED] well_known_colors
[09:18:04] [PASSED] destination_pitch
[09:18:04] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:18:04] ================= drm_test_fb_clip_offset  =================
[09:18:04] [PASSED] pass through
[09:18:04] [PASSED] horizontal offset
[09:18:04] [PASSED] vertical offset
[09:18:04] [PASSED] horizontal and vertical offset
[09:18:04] [PASSED] horizontal offset (custom pitch)
[09:18:04] [PASSED] vertical offset (custom pitch)
[09:18:04] [PASSED] horizontal and vertical offset (custom pitch)
[09:18:04] ============= [PASSED] drm_test_fb_clip_offset =============
[09:18:04] =================== drm_test_fb_memcpy  ====================
[09:18:04] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:18:04] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:18:04] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:18:04] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:18:04] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:18:04] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:18:04] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:18:04] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:18:04] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:18:04] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:18:04] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:18:04] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:18:04] =============== [PASSED] drm_test_fb_memcpy ================
[09:18:04] ============= [PASSED] drm_format_helper_test ==============
[09:18:04] ================= drm_format (18 subtests) =================
[09:18:04] [PASSED] drm_test_format_block_width_invalid
[09:18:04] [PASSED] drm_test_format_block_width_one_plane
[09:18:04] [PASSED] drm_test_format_block_width_two_plane
[09:18:04] [PASSED] drm_test_format_block_width_three_plane
[09:18:04] [PASSED] drm_test_format_block_width_tiled
[09:18:04] [PASSED] drm_test_format_block_height_invalid
[09:18:04] [PASSED] drm_test_format_block_height_one_plane
[09:18:04] [PASSED] drm_test_format_block_height_two_plane
[09:18:04] [PASSED] drm_test_format_block_height_three_plane
[09:18:04] [PASSED] drm_test_format_block_height_tiled
[09:18:04] [PASSED] drm_test_format_min_pitch_invalid
[09:18:04] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:18:04] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:18:04] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:18:04] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:18:04] [PASSED] drm_test_format_min_pitch_two_plane
[09:18:04] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:18:04] [PASSED] drm_test_format_min_pitch_tiled
[09:18:04] =================== [PASSED] drm_format ====================
[09:18:04] ============== drm_framebuffer (10 subtests) ===============
[09:18:04] ========== drm_test_framebuffer_check_src_coords  ==========
[09:18:04] [PASSED] Success: source fits into fb
[09:18:04] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:18:04] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:18:04] [PASSED] Fail: overflowing fb with source width
[09:18:04] [PASSED] Fail: overflowing fb with source height
[09:18:04] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:18:04] [PASSED] drm_test_framebuffer_cleanup
[09:18:04] =============== drm_test_framebuffer_create  ===============
[09:18:04] [PASSED] ABGR8888 normal sizes
[09:18:04] [PASSED] ABGR8888 max sizes
[09:18:04] [PASSED] ABGR8888 pitch greater than min required
[09:18:04] [PASSED] ABGR8888 pitch less than min required
[09:18:04] [PASSED] ABGR8888 Invalid width
[09:18:04] [PASSED] ABGR8888 Invalid buffer handle
[09:18:04] [PASSED] No pixel format
[09:18:04] [PASSED] ABGR8888 Width 0
[09:18:04] [PASSED] ABGR8888 Height 0
[09:18:04] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:18:04] [PASSED] ABGR8888 Large buffer offset
[09:18:04] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:18:04] [PASSED] ABGR8888 Invalid flag
[09:18:04] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:18:04] [PASSED] ABGR8888 Valid buffer modifier
[09:18:04] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:18:04] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] NV12 Normal sizes
[09:18:04] [PASSED] NV12 Max sizes
[09:18:04] [PASSED] NV12 Invalid pitch
[09:18:04] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:18:04] [PASSED] NV12 different  modifier per-plane
[09:18:04] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:18:04] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] NV12 Modifier for inexistent plane
[09:18:04] [PASSED] NV12 Handle for inexistent plane
[09:18:04] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:18:04] [PASSED] YVU420 Normal sizes
[09:18:04] [PASSED] YVU420 Max sizes
[09:18:04] [PASSED] YVU420 Invalid pitch
[09:18:04] [PASSED] YVU420 Different pitches
[09:18:04] [PASSED] YVU420 Different buffer offsets/pitches
[09:18:04] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:18:04] [PASSED] YVU420 Valid modifier
[09:18:04] [PASSED] YVU420 Different modifiers per plane
[09:18:04] [PASSED] YVU420 Modifier for inexistent plane
[09:18:04] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:18:04] [PASSED] X0L2 Normal sizes
[09:18:04] [PASSED] X0L2 Max sizes
[09:18:04] [PASSED] X0L2 Invalid pitch
[09:18:04] [PASSED] X0L2 Pitch greater than minimum required
[09:18:04] [PASSED] X0L2 Handle for inexistent plane
[09:18:04] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:18:04] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:18:04] [PASSED] X0L2 Valid modifier
[09:18:04] [PASSED] X0L2 Modifier for inexistent plane
[09:18:04] =========== [PASSED] drm_test_framebuffer_create ===========
[09:18:04] [PASSED] drm_test_framebuffer_free
[09:18:04] [PASSED] drm_test_framebuffer_init
[09:18:04] [PASSED] drm_test_framebuffer_init_bad_format
[09:18:04] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:18:04] [PASSED] drm_test_framebuffer_lookup
[09:18:04] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:18:04] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:18:04] ================= [PASSED] drm_framebuffer =================
[09:18:04] ================ drm_gem_shmem (8 subtests) ================
[09:18:04] [PASSED] drm_gem_shmem_test_obj_create
[09:18:04] [PASSED] drm_gem_shmem_test_obj_create_private
[09:18:04] [PASSED] drm_gem_shmem_test_pin_pages
[09:18:04] [PASSED] drm_gem_shmem_test_vmap
[09:18:04] [PASSED] drm_gem_shmem_test_get_sg_table
[09:18:04] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:18:04] [PASSED] drm_gem_shmem_test_madvise
[09:18:04] [PASSED] drm_gem_shmem_test_purge
[09:18:04] ================== [PASSED] drm_gem_shmem ==================
[09:18:04] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:18:04] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[09:18:04] [PASSED] Automatic
[09:18:04] [PASSED] Full
[09:18:04] [PASSED] Limited 16:235
[09:18:04] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:18:04] [PASSED] drm_test_check_disable_connector
[09:18:04] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:18:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:18:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:18:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:18:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:18:04] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:18:04] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:18:04] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:18:04] [PASSED] drm_test_check_output_bpc_dvi
[09:18:04] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:18:04] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:18:04] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:18:04] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:18:04] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:18:04] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:18:04] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:18:04] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:18:04] ============ drm_test_check_hdmi_color_format  =============
[09:18:04] [PASSED] AUTO -> RGB
[09:18:04] [PASSED] YCBCR422 -> YUV422
[09:18:04] [PASSED] YCBCR420 -> YUV420
[09:18:04] [PASSED] YCBCR444 -> YUV444
[09:18:04] [PASSED] RGB -> RGB
[09:18:04] ======== [PASSED] drm_test_check_hdmi_color_format =========
[09:18:04] ======== drm_test_check_hdmi_color_format_420_only  ========
[09:18:04] [PASSED] RGB should fail
[09:18:04] [PASSED] YUV444 should fail
[09:18:04] [PASSED] YUV422 should fail
[09:18:04] [PASSED] YUV420 should work
[09:18:04] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[09:18:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:18:04] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:18:04] [PASSED] drm_test_check_broadcast_rgb_value
[09:18:04] [PASSED] drm_test_check_bpc_8_value
[09:18:04] [PASSED] drm_test_check_bpc_10_value
[09:18:04] [PASSED] drm_test_check_bpc_12_value
[09:18:04] [PASSED] drm_test_check_format_value
[09:18:04] [PASSED] drm_test_check_tmds_char_value
[09:18:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:18:04] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[09:18:04] [PASSED] drm_test_check_mode_valid
[09:18:04] [PASSED] drm_test_check_mode_valid_reject
[09:18:04] [PASSED] drm_test_check_mode_valid_reject_rate
[09:18:04] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:18:04] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[09:18:04] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[09:18:04] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[09:18:04] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:18:04] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[09:18:04] [PASSED] drm_test_check_infoframes
[09:18:04] [PASSED] drm_test_check_reject_avi_infoframe
[09:18:04] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[09:18:04] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[09:18:04] [PASSED] drm_test_check_reject_audio_infoframe
[09:18:04] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[09:18:04] ================= drm_managed (2 subtests) =================
[09:18:04] [PASSED] drm_test_managed_release_action
[09:18:04] [PASSED] drm_test_managed_run_action
[09:18:04] =================== [PASSED] drm_managed ===================
[09:18:04] =================== drm_mm (6 subtests) ====================
[09:18:04] [PASSED] drm_test_mm_init
[09:18:04] [PASSED] drm_test_mm_debug
[09:18:04] [PASSED] drm_test_mm_align32
[09:18:04] [PASSED] drm_test_mm_align64
[09:18:04] [PASSED] drm_test_mm_lowest
[09:18:04] [PASSED] drm_test_mm_highest
[09:18:04] ===================== [PASSED] drm_mm ======================
[09:18:04] ============= drm_modes_analog_tv (5 subtests) =============
[09:18:04] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:18:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:18:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:18:04] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:18:04] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:18:04] =============== [PASSED] drm_modes_analog_tv ===============
[09:18:04] ============== drm_plane_helper (2 subtests) ===============
[09:18:04] =============== drm_test_check_plane_state  ================
[09:18:04] [PASSED] clipping_simple
[09:18:04] [PASSED] clipping_rotate_reflect
[09:18:04] [PASSED] positioning_simple
[09:18:04] [PASSED] upscaling
[09:18:04] [PASSED] downscaling
[09:18:04] [PASSED] rounding1
[09:18:04] [PASSED] rounding2
[09:18:04] [PASSED] rounding3
[09:18:04] [PASSED] rounding4
[09:18:04] =========== [PASSED] drm_test_check_plane_state ============
[09:18:04] =========== drm_test_check_invalid_plane_state  ============
[09:18:04] [PASSED] positioning_invalid
[09:18:04] [PASSED] upscaling_invalid
[09:18:04] [PASSED] downscaling_invalid
[09:18:04] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:18:04] ================ [PASSED] drm_plane_helper =================
[09:18:04] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:18:04] ====== drm_test_connector_helper_tv_get_modes_check  =======
[09:18:04] [PASSED] None
[09:18:04] [PASSED] PAL
[09:18:04] [PASSED] NTSC
[09:18:04] [PASSED] Both, NTSC Default
[09:18:04] [PASSED] Both, PAL Default
[09:18:04] [PASSED] Both, NTSC Default, with PAL on command-line
[09:18:04] [PASSED] Both, PAL Default, with NTSC on command-line
[09:18:04] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:18:04] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:18:04] ================== drm_rect (9 subtests) ===================
[09:18:04] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:18:04] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:18:04] [PASSED] drm_test_rect_clip_scaled_clipped
[09:18:04] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:18:04] ================= drm_test_rect_intersect  =================
[09:18:04] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:18:04] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:18:04] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:18:04] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:18:04] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:18:04] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:18:04] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:18:04] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:18:04] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:18:04] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:18:04] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:18:04] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:18:04] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:18:04] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:18:04] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:18:04] ============= [PASSED] drm_test_rect_intersect =============
[09:18:04] ================ drm_test_rect_calc_hscale  ================
[09:18:04] [PASSED] normal use
[09:18:04] [PASSED] out of max range
[09:18:04] [PASSED] out of min range
[09:18:04] [PASSED] zero dst
[09:18:04] [PASSED] negative src
[09:18:04] [PASSED] negative dst
[09:18:04] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:18:04] ================ drm_test_rect_calc_vscale  ================
[09:18:04] [PASSED] normal use
[09:18:04] [PASSED] out of max range
[09:18:04] [PASSED] out of min range
[09:18:04] [PASSED] zero dst
[09:18:04] [PASSED] negative src
[09:18:04] [PASSED] negative dst
[09:18:04] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:18:04] ================== drm_test_rect_rotate  ===================
[09:18:04] [PASSED] reflect-x
[09:18:04] [PASSED] reflect-y
[09:18:04] [PASSED] rotate-0
[09:18:04] [PASSED] rotate-90
[09:18:04] [PASSED] rotate-180
[09:18:04] [PASSED] rotate-270
[09:18:04] ============== [PASSED] drm_test_rect_rotate ===============
[09:18:04] ================ drm_test_rect_rotate_inv  =================
[09:18:04] [PASSED] reflect-x
[09:18:04] [PASSED] reflect-y
[09:18:04] [PASSED] rotate-0
[09:18:04] [PASSED] rotate-90
[09:18:04] [PASSED] rotate-180
[09:18:04] [PASSED] rotate-270
[09:18:04] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:18:04] ==================== [PASSED] drm_rect =====================
[09:18:04] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:18:04] ============ drm_test_sysfb_build_fourcc_list  =============
[09:18:04] [PASSED] no native formats
[09:18:04] [PASSED] XRGB8888 as native format
[09:18:04] [PASSED] remove duplicates
[09:18:04] [PASSED] convert alpha formats
[09:18:04] [PASSED] random formats
[09:18:04] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:18:04] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:18:04] ================== drm_fixp (2 subtests) ===================
[09:18:04] [PASSED] drm_test_int2fixp
[09:18:04] [PASSED] drm_test_sm2fixp
[09:18:04] ==================== [PASSED] drm_fixp =====================
[09:18:04] ============================================================
[09:18:04] Testing complete. Ran 641 tests: passed: 641
[09:18:04] Elapsed time: 27.081s total, 1.829s configuring, 25.034s building, 0.187s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:18:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:18:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:18:16] Starting KUnit Kernel (1/1)...
[09:18:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:18:16] ============= refcount_interrupt (4 subtests) ==============
[09:18:16] [PASSED] test_single_irq_change
[09:18:16] [PASSED] test_nested_irq_change
[09:18:16] [PASSED] test_multiple_irq_change
[09:18:16] [PASSED] test_irq_save
[09:18:16] =============== [PASSED] refcount_interrupt ================
[09:18:16] ================= ttm_device (5 subtests) ==================
[09:18:16] [PASSED] ttm_device_init_basic
[09:18:16] [PASSED] ttm_device_init_multiple
[09:18:16] [PASSED] ttm_device_fini_basic
[09:18:16] [PASSED] ttm_device_init_no_vma_man
[09:18:16] ================== ttm_device_init_pools  ==================
[09:18:16] [PASSED] No DMA allocations, no DMA32 required
[09:18:16] [PASSED] DMA allocations, DMA32 required
[09:18:16] [PASSED] No DMA allocations, DMA32 required
[09:18:16] [PASSED] DMA allocations, no DMA32 required
[09:18:16] ============== [PASSED] ttm_device_init_pools ==============
[09:18:16] =================== [PASSED] ttm_device ====================
[09:18:16] ================== ttm_pool (8 subtests) ===================
[09:18:16] ================== ttm_pool_alloc_basic  ===================
[09:18:16] [PASSED] One page
[09:18:16] [PASSED] More than one page
[09:18:16] [PASSED] Above the allocation limit
[09:18:16] [PASSED] One page, with coherent DMA mappings enabled
[09:18:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:18:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:18:16] ============== ttm_pool_alloc_basic_dma_addr  ==============
[09:18:16] [PASSED] One page
[09:18:16] [PASSED] More than one page
[09:18:16] [PASSED] Above the allocation limit
[09:18:16] [PASSED] One page, with coherent DMA mappings enabled
[09:18:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:18:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:18:16] [PASSED] ttm_pool_alloc_order_caching_match
[09:18:16] [PASSED] ttm_pool_alloc_caching_mismatch
[09:18:16] [PASSED] ttm_pool_alloc_order_mismatch
[09:18:16] [PASSED] ttm_pool_free_dma_alloc
[09:18:16] [PASSED] ttm_pool_free_no_dma_alloc
[09:18:16] [PASSED] ttm_pool_fini_basic
[09:18:16] ==================== [PASSED] ttm_pool =====================
[09:18:16] ================ ttm_resource (8 subtests) =================
[09:18:16] ================= ttm_resource_init_basic  =================
[09:18:16] [PASSED] Init resource in TTM_PL_SYSTEM
[09:18:16] [PASSED] Init resource in TTM_PL_VRAM
[09:18:16] [PASSED] Init resource in a private placement
[09:18:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:18:16] ============= [PASSED] ttm_resource_init_basic =============
[09:18:16] [PASSED] ttm_resource_init_pinned
[09:18:16] [PASSED] ttm_resource_fini_basic
[09:18:16] [PASSED] ttm_resource_manager_init_basic
[09:18:16] [PASSED] ttm_resource_manager_usage_basic
[09:18:16] [PASSED] ttm_resource_manager_set_used_basic
[09:18:16] [PASSED] ttm_sys_man_alloc_basic
[09:18:16] [PASSED] ttm_sys_man_free_basic
[09:18:16] ================== [PASSED] ttm_resource ===================
[09:18:16] =================== ttm_tt (15 subtests) ===================
[09:18:16] ==================== ttm_tt_init_basic  ====================
[09:18:16] [PASSED] Page-aligned size
[09:18:16] [PASSED] Extra pages requested
[09:18:16] ================ [PASSED] ttm_tt_init_basic ================
[09:18:16] [PASSED] ttm_tt_init_misaligned
[09:18:16] [PASSED] ttm_tt_fini_basic
[09:18:16] [PASSED] ttm_tt_fini_sg
[09:18:16] [PASSED] ttm_tt_fini_shmem
[09:18:16] [PASSED] ttm_tt_create_basic
[09:18:16] [PASSED] ttm_tt_create_invalid_bo_type
[09:18:16] [PASSED] ttm_tt_create_ttm_exists
[09:18:16] [PASSED] ttm_tt_create_failed
[09:18:16] [PASSED] ttm_tt_destroy_basic
[09:18:16] [PASSED] ttm_tt_populate_null_ttm
[09:18:16] [PASSED] ttm_tt_populate_populated_ttm
[09:18:16] [PASSED] ttm_tt_unpopulate_basic
[09:18:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:18:16] [PASSED] ttm_tt_swapin_basic
[09:18:16] ===================== [PASSED] ttm_tt ======================
[09:18:16] =================== ttm_bo (14 subtests) ===================
[09:18:16] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[09:18:16] [PASSED] Cannot be interrupted and sleeps
[09:18:16] [PASSED] Cannot be interrupted, locks straight away
[09:18:16] [PASSED] Can be interrupted, sleeps
[09:18:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:18:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:18:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:18:16] [PASSED] ttm_bo_reserve_double_resv
[09:18:16] [PASSED] ttm_bo_reserve_interrupted
[09:18:16] [PASSED] ttm_bo_reserve_deadlock
[09:18:16] [PASSED] ttm_bo_unreserve_basic
[09:18:16] [PASSED] ttm_bo_unreserve_pinned
[09:18:16] [PASSED] ttm_bo_unreserve_bulk
[09:18:16] [PASSED] ttm_bo_fini_basic
[09:18:16] [PASSED] ttm_bo_fini_shared_resv
[09:18:16] [PASSED] ttm_bo_pin_basic
[09:18:16] [PASSED] ttm_bo_pin_unpin_resource
[09:18:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:18:16] ===================== [PASSED] ttm_bo ======================
[09:18:16] ============== ttm_bo_validate (22 subtests) ===============
[09:18:16] ============== ttm_bo_init_reserved_sys_man  ===============
[09:18:16] [PASSED] Buffer object for userspace
[09:18:16] [PASSED] Kernel buffer object
[09:18:16] [PASSED] Shared buffer object
[09:18:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:18:16] ============== ttm_bo_init_reserved_mock_man  ==============
[09:18:16] [PASSED] Buffer object for userspace
[09:18:16] [PASSED] Kernel buffer object
[09:18:16] [PASSED] Shared buffer object
[09:18:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:18:16] [PASSED] ttm_bo_init_reserved_resv
[09:18:16] ================== ttm_bo_validate_basic  ==================
[09:18:16] [PASSED] Buffer object for userspace
[09:18:16] [PASSED] Kernel buffer object
[09:18:16] [PASSED] Shared buffer object
[09:18:16] ============== [PASSED] ttm_bo_validate_basic ==============
[09:18:16] [PASSED] ttm_bo_validate_invalid_placement
[09:18:16] ============= ttm_bo_validate_same_placement  ==============
[09:18:16] [PASSED] System manager
[09:18:16] [PASSED] VRAM manager
[09:18:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:18:16] [PASSED] ttm_bo_validate_failed_alloc
[09:18:16] [PASSED] ttm_bo_validate_pinned
[09:18:16] [PASSED] ttm_bo_validate_busy_placement
[09:18:16] ================ ttm_bo_validate_multihop  =================
[09:18:16] [PASSED] Buffer object for userspace
[09:18:16] [PASSED] Kernel buffer object
[09:18:16] [PASSED] Shared buffer object
[09:18:16] ============ [PASSED] ttm_bo_validate_multihop =============
[09:18:16] ========== ttm_bo_validate_no_placement_signaled  ==========
[09:18:16] [PASSED] Buffer object in system domain, no page vector
[09:18:16] [PASSED] Buffer object in system domain with an existing page vector
[09:18:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:18:16] ======== ttm_bo_validate_no_placement_not_signaled  ========
[09:18:16] [PASSED] Buffer object for userspace
[09:18:16] [PASSED] Kernel buffer object
[09:18:16] [PASSED] Shared buffer object
[09:18:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:18:16] [PASSED] ttm_bo_validate_move_fence_signaled
[09:18:16] ========= ttm_bo_validate_move_fence_not_signaled  =========
[09:18:16] [PASSED] Waits for GPU
[09:18:16] [PASSED] Tries to lock straight away
[09:18:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:18:16] [PASSED] ttm_bo_validate_swapout
[09:18:16] [PASSED] ttm_bo_validate_happy_evict
[09:18:16] [PASSED] ttm_bo_validate_all_pinned_evict
[09:18:16] [PASSED] ttm_bo_validate_allowed_only_evict
[09:18:16] [PASSED] ttm_bo_validate_deleted_evict
[09:18:16] [PASSED] ttm_bo_validate_busy_domain_evict
[09:18:16] [PASSED] ttm_bo_validate_evict_gutting
[09:18:16] [PASSED] ttm_bo_validate_recrusive_evict
[09:18:16] ================= [PASSED] ttm_bo_validate =================
[09:18:16] ============================================================
[09:18:16] Testing complete. Ran 106 tests: passed: 106
[09:18:16] Elapsed time: 12.091s total, 1.828s configuring, 9.997s building, 0.225s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[09:18:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:18:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:18:27] Starting KUnit Kernel (1/1)...
[09:18:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:18:27] ============= refcount_interrupt (4 subtests) ==============
[09:18:27] [PASSED] test_single_irq_change
[09:18:27] [PASSED] test_nested_irq_change
[09:18:27] [PASSED] test_multiple_irq_change
[09:18:27] [PASSED] test_irq_save
[09:18:27] =============== [PASSED] refcount_interrupt ================
[09:18:27] =============== dma-buf-fence (12 subtests) ================
[09:18:27] [PASSED] test_sanitycheck
[09:18:27] [PASSED] test_signaling
[09:18:27] [PASSED] test_add_callback
[09:18:27] [PASSED] test_late_add_callback
[09:18:27] [PASSED] test_rm_callback
[09:18:27] [PASSED] test_late_rm_callback
[09:18:27] [PASSED] test_status
[09:18:27] [PASSED] test_error
[09:18:27] [PASSED] test_wait
[09:18:27] [PASSED] test_wait_timeout
[09:18:27] [PASSED] test_stub
[09:18:27] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[09:18:27] ================== [PASSED] dma-buf-fence ==================
[09:18:27] ============ dma-buf-fence-chain (11 subtests) =============
[09:18:27] [PASSED] test_sanitycheck
[09:18:27] [PASSED] test_find_seqno
[09:18:27] [PASSED] test_find_signaled
[09:18:27] [PASSED] test_find_out_of_order
[09:18:32] [PASSED] test_find_gap
[09:18:32] [PASSED] test_find_race
[09:18:32] [PASSED] test_signal_forward
[09:18:32] [PASSED] test_signal_backward
[09:18:32] [PASSED] test_wait_forward
[09:18:32] [PASSED] test_wait_backward
[09:18:32] [PASSED] test_wait_random
[09:18:32] =============== [PASSED] dma-buf-fence-chain ===============
[09:18:32] ============ dma-buf-fence-unwrap (10 subtests) ============
[09:18:32] [PASSED] test_sanitycheck
[09:18:32] [PASSED] test_unwrap_array
[09:18:32] [PASSED] test_unwrap_chain
[09:18:32] [PASSED] test_unwrap_chain_array
[09:18:32] [PASSED] test_unwrap_merge
[09:18:32] [PASSED] test_unwrap_merge_duplicate
[09:18:32] [PASSED] test_unwrap_merge_seqno
[09:18:32] [PASSED] test_unwrap_merge_order
[09:18:32] [PASSED] test_unwrap_merge_complex
[09:18:32] [PASSED] test_unwrap_merge_complex_seqno
[09:18:32] ============== [PASSED] dma-buf-fence-unwrap ===============
[09:18:32] ================ dma-buf-resv (5 subtests) =================
[09:18:32] [PASSED] test_sanitycheck
[09:18:32] ===================== test_signaling  ======================
[09:18:32] [PASSED] kernel
[09:18:32] [PASSED] write
[09:18:32] [PASSED] read
[09:18:32] [PASSED] bookkeep
[09:18:32] ================= [PASSED] test_signaling ==================
[09:18:32] ====================== test_for_each  ======================
[09:18:32] [PASSED] kernel
[09:18:32] [PASSED] write
[09:18:32] [PASSED] read
[09:18:32] [PASSED] bookkeep
[09:18:32] ================== [PASSED] test_for_each ==================
[09:18:32] ================= test_for_each_unlocked  ==================
[09:18:32] [PASSED] kernel
[09:18:32] [PASSED] write
[09:18:32] [PASSED] read
[09:18:32] [PASSED] bookkeep
[09:18:32] ============= [PASSED] test_for_each_unlocked ==============
[09:18:32] ===================== test_get_fences  =====================
[09:18:32] [PASSED] kernel
[09:18:32] [PASSED] write
[09:18:32] [PASSED] read
[09:18:32] [PASSED] bookkeep
[09:18:32] ================= [PASSED] test_get_fences =================
[09:18:32] ================== [PASSED] dma-buf-resv ===================
[09:18:32] ============================================================
[09:18:32] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[09:18:32] Elapsed time: 15.765s total, 1.793s configuring, 8.601s building, 5.339s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1459 bytes --]

== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev8)
URL   : https://patchwork.freedesktop.org/series/138256/
State : success

== Summary ==

CI Bug Log - changes from xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8_BAT -> xe-pw-138256v8_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-138256v8_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@engine:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9109])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/bat-ptl-2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/bat-ptl-2/igt@xe_waitfence@engine.html

  
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109


Build changes
-------------

  * IGT: IGT_9098 -> IGT_9099
  * Linux: xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 -> xe-pw-138256v8

  IGT_9098: 9098
  IGT_9099: 9099
  xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8
  xe-pw-138256v8: 138256v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/index.html

[-- Attachment #2: Type: text/html, Size: 2038 bytes --]

✗ Xe.CI.FULL: failure for Implement Wa_14021768792 to bypass m_n ratio limit (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 50017 bytes --]

== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev8)
URL   : https://patchwork.freedesktop.org/series/138256/
State : failure

== Summary ==

CI Bug Log - changes from xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8_FULL -> xe-pw-138256v8_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-138256v8_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-138256v8_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-138256v8_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-7/igt@kms_hdr@static-toggle-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html

  
Known issues
------------

  Here are the changes found in xe-pw-138256v8_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotunbind-rebind-with-load:
    - shard-bmg:          [PASS][3] -> [ABORT][4] ([Intel XE#8007])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-3/igt@core_hotunplug@hotunbind-rebind-with-load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-2/igt@core_hotunplug@hotunbind-rebind-with-load.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1466])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][6] -> [FAIL][7] ([Intel XE#3718] / [Intel XE#6078])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2:
    - shard-bmg:          [PASS][8] -> [FAIL][9] ([Intel XE#6078])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#3279]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1407]) +5 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#3658] / [Intel XE#7360]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#7059] / [Intel XE#7085])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#1124]) +9 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#607] / [Intel XE#7361])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#1124]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#1467] / [Intel XE#7367])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#7679]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-5/igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#7679])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-3/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#367]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#2887]) +16 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#3432]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2887]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#306] / [Intel XE#7358]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7358]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#373]) +8 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2252]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-b-plane-3:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#6969]) +7 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-b-plane-3.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#307] / [Intel XE#6974])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7642]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][31] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@kms_content_protection@suspend-resume@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#2321] / [Intel XE#7355])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1424]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#323] / [Intel XE#6035])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#4354] / [Intel XE#5882])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#8265])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#8265]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1137] / [Intel XE#2375])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1421]) +11 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [PASS][42] -> [FAIL][43] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-lnl-4/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-5/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][44] -> [FAIL][45] ([Intel XE#301])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#7179])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2311]) +7 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#6312] / [Intel XE#651]) +18 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#6312]) +15 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7905]) +60 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7865]) +30 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2313]) +11 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#7061]) +5 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#656] / [Intel XE#7905]) +46 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#7061])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-4/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1470])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1503])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#7173] / [Intel XE#7294])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7591])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#7283])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#7283]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#599])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#4596] / [Intel XE#5854]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#2763] / [Intel XE#6886]) +13 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#8396]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#4608] / [Intel XE#7304]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#4608]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#1489]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#1128] / [Intel XE#7413])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1406] / [Intel XE#7345])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1.html

  * igt@kms_psr@pr-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#1406]) +7 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2234] / [Intel XE#2850])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1127] / [Intel XE#5813])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2413])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#1499] / [Intel XE#9271])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-8/igt@kms_vrr@flip-basic.html

  * igt@xe_cw_post_sync@walker-post-sync:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#8608])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-8/igt@xe_cw_post_sync@walker-post-sync.html

  * igt@xe_evict@evict-beng-mixed-threads-large-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#6540] / [Intel XE#688]) +12 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html

  * igt@xe_evict@evict-small-multi-queue-priority:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#8370])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@xe_evict@evict-small-multi-queue-priority.html

  * igt@xe_exec_balancer@once-parallel-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#7482]) +21 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-5/igt@xe_exec_balancer@once-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#1392]) +8 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#8374]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#8374]) +10 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind.html

  * igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#9003])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#8364]) +6 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#8364]) +35 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr.html

  * igt@xe_exec_reset@close-execqueues-close-fd:
    - shard-lnl:          NOTRUN -> [ABORT][100] ([Intel XE#8007])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@xe_exec_reset@close-execqueues-close-fd.html

  * igt@xe_exec_reset@cm-multi-queue-close-execqueues:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#8369]) +2 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_exec_reset@cm-multi-queue-close-execqueues.html

  * igt@xe_exec_reset@cm-multi-queue-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#8369])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@xe_exec_reset@cm-multi-queue-close-fd.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][103] ([Intel XE#9130])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@xe_exec_reset@gt-reset-fault-injection.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#8378]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#8378]) +10 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_gpgpu_fill@offset-4x4:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#7954])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@xe_gpgpu_fill@offset-4x4.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#6964]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#6964])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-8/igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch.html

  * igt@xe_page_reclaim@basic-mixed:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#7793])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@xe_page_reclaim@basic-mixed.html

  * igt@xe_page_reclaim@binds-null-vma:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#7793]) +2 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@xe_page_reclaim@binds-null-vma.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#7590] / [Intel XE#7772])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-4/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_pm@d3cold-basic:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@s3-exec-after:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#584] / [Intel XE#7369])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@xe_pm@s3-exec-after.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-bmg:          [PASS][114] -> [INCOMPLETE][115] ([Intel XE#8175])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-4/igt@xe_pm@s3-vm-bind-unbind-all.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-6/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_prefetch_fault@prefetch-fault:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#7599])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_prefetch_fault@prefetch-fault.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#7599])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-4/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#944]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#944])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-4/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#7174]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled.html

  * igt@xe_sriov_auto_provisioning@fair-allocation:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#4130] / [Intel XE#7366])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-3/igt@xe_sriov_auto_provisioning@fair-allocation.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#4273])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-7/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-bmg:          [PASS][123] -> [FAIL][124] ([Intel XE#6569])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-4/igt@xe_sriov_flr@flr-vf1-clear.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-9/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets-low-priority:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#8339])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-6/igt@xe_sriov_scheduling@nonpreempt-engine-resets-low-priority.html

  * igt@xe_survivability@runtime-survivability:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#8415])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-8/igt@xe_survivability@runtime-survivability.html

  * igt@xe_vm@overcommit-fault-vram-lr-no-overcommit:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#7892])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-1/igt@xe_vm@overcommit-fault-vram-lr-no-overcommit.html

  * igt@xe_waitfence@engine:
    - shard-bmg:          [PASS][128] -> [FAIL][129] ([Intel XE#9109])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-9/igt@xe_waitfence@engine.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-1/igt@xe_waitfence@engine.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][130] ([Intel XE#8963])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][131] ([Intel XE#1503]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-10/igt@kms_hdr@invalid-hdr.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-lnl:          [FAIL][133] ([Intel XE#8399]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-lnl-4/igt@kms_pm_dc@dc5-psr-suspend-resume.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-lnl-2/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-bmg:          [FAIL][135] ([Intel XE#9096]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-6/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-5/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_pm@s3-basic-exec:
    - shard-bmg:          [INCOMPLETE][137] ([Intel XE#8175]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-6/igt@xe_pm@s3-basic-exec.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-5/igt@xe_pm@s3-basic-exec.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          [FAIL][139] ([Intel XE#6569]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-4/igt@xe_sriov_flr@flr-vfs-parallel.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-10/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][141] ([Intel XE#3544]) -> [SKIP][142] ([Intel XE#3374] / [Intel XE#3544])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][143] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][144] ([Intel XE#1729] / [Intel XE#7424])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-bmg:          [DMESG-WARN][145] ([Intel XE#9130]) -> [ABORT][146] ([Intel XE#9145])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8/shard-bmg-6/igt@xe_exec_reset@gt-reset-fault-injection.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/shard-bmg-7/igt@xe_exec_reset@gt-reset-fault-injection.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7173
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7294
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7954]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7954
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8175
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
  [Intel XE#8608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8608
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9003]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9003
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_9098 -> IGT_9099
  * Linux: xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 -> xe-pw-138256v8

  IGT_9098: 9098
  IGT_9099: 9099
  xe-5755-0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8
  xe-pw-138256v8: 138256v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v8/index.html

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