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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: "Iddamsetty, Aravind" <aravind.iddamsetty@intel.com>
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>,
	intel-xe@lists.freedesktop.org,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
Date: Mon, 24 Jul 2023 08:52:04 -0700	[thread overview]
Message-ID: <87351dqpcr.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <8fd9bc04-b737-0acd-a0c9-4f163c1a117c@intel.com>

On Mon, 24 Jul 2023 01:03:23 -0700, Iddamsetty, Aravind wrote:

Hi Aravind,

> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>> > On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>> +{
> >>>>> +	struct xe_pmu *pmu = &gt->tile->xe->pmu;
> >>>>> +	unsigned int gt_id = gt->info.id;
> >>>>> +	unsigned long flags;
> >>>>> +
> >>>>> +	spin_lock_irqsave(&pmu->lock, flags);
> >>>>> +
> >>>>> +	store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>> +		     __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>> +	store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>> +		     __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>> +	store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>> +		     __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>> +	store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>> +		     __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >
> > Here why should we store everything, we should store only those events
> > which are enabled?
>
> The events are enabled only when they are opened which can happen after
> the device is suspended hence we need to store all. As in the present
> case device is put to suspend immediately after probe and event is
> opened post driver load is done.

I don't think we can justify doing expensive PCIe reads and increasing the
time to go into runtime suspend, when PMU might not being used at all.

If we store only enabled samples and start storing them only after they are
enabled, what would be the consequence of this? The first non-zero sample
seen by the perf tool would be wrong and later samples will be fine?

If there is a consequence, we might have to go back to what I was saying
earlier about waking the device up and reading the enabled counter when
xe_pmu_event_start happens, to initialize the counter values. I am assuming
this will work?

Doing this IMO would be better than always doing these PCIe reads on
runtime suspend even when PMU is not being used.

Thanks.
--
Ashutosh

  parent reply	other threads:[~2023-07-24 15:52 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-27 12:21 [Intel-xe] [PATCH v2 0/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 1/2] drm/xe: Get GT clock to nanosecs Aravind Iddamsetty
2023-07-04  9:29   ` Upadhyay, Tejas
2023-07-04 10:14     ` Upadhyay, Tejas
2023-07-05  4:46       ` Iddamsetty, Aravind
2023-07-06  0:55   ` Dixit, Ashutosh
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-30 13:53   ` Upadhyay, Tejas
2023-07-03  5:11     ` Iddamsetty, Aravind
2023-07-04  3:34   ` Ghimiray, Himal Prasad
2023-07-05  4:52     ` Iddamsetty, Aravind
2023-07-04  9:10   ` Upadhyay, Tejas
2023-07-05  4:42     ` Iddamsetty, Aravind
2023-07-06  2:39   ` Dixit, Ashutosh
2023-07-06 13:42     ` Iddamsetty, Aravind
2023-07-07  2:18       ` Dixit, Ashutosh
2023-07-07  3:53         ` Iddamsetty, Aravind
2023-07-07  6:08           ` Dixit, Ashutosh
2023-07-07 10:42             ` Iddamsetty, Aravind
2023-07-07 21:25               ` Dixit, Ashutosh
2023-07-10  6:05                 ` Iddamsetty, Aravind
2023-07-10  8:12                   ` Ursulin, Tvrtko
2023-07-11 16:19                     ` Iddamsetty, Aravind
2023-07-11 23:10                       ` Dixit, Ashutosh
2023-07-12  3:11                         ` Iddamsetty, Aravind
2023-07-12  5:24                           ` Dixit, Ashutosh
2023-07-11 22:58                     ` Dixit, Ashutosh
2023-07-09  0:32           ` Dixit, Ashutosh
2023-07-10  4:13             ` Iddamsetty, Aravind
2023-07-10  5:57               ` Dixit, Ashutosh
2023-07-18  5:07           ` Dixit, Ashutosh
2023-07-19  6:59             ` Iddamsetty, Aravind
2023-07-06  2:40   ` Belgaumkar, Vinay
2023-07-06 13:06     ` Iddamsetty, Aravind
2023-07-21  1:02   ` Dixit, Ashutosh
2023-07-21 11:51     ` Iddamsetty, Aravind
2023-07-21 23:36       ` Dixit, Ashutosh
2023-07-22  6:04         ` Dixit, Ashutosh
2023-07-24  8:03           ` Iddamsetty, Aravind
2023-07-24  9:00             ` Ursulin, Tvrtko
2023-07-24 15:52               ` Dixit, Ashutosh
2023-07-24 15:52             ` Dixit, Ashutosh [this message]
2023-07-24 16:05               ` Iddamsetty, Aravind
2023-07-24 16:31                 ` Dixit, Ashutosh
2023-07-25 11:38                   ` Iddamsetty, Aravind
2023-08-07 21:16                     ` Dixit, Ashutosh
2023-08-07 22:22                       ` Dixit, Ashutosh
2023-08-08 13:45                         ` Iddamsetty, Aravind
2023-08-08 15:18                           ` Dixit, Ashutosh
2023-08-09  4:26                             ` Iddamsetty, Aravind
2023-08-09  5:02                               ` Dixit, Ashutosh
2023-07-24  9:38           ` Iddamsetty, Aravind
2023-07-22 14:39   ` Dixit, Ashutosh
2023-07-24  8:02     ` Iddamsetty, Aravind
2023-06-27 13:04 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe/pmu: Enable PMU interface (rev2) Patchwork
2023-06-27 13:05 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-06-27 13:06 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork

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