From: "Iddamsetty, Aravind" <aravind.iddamsetty@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>,
intel-xe@lists.freedesktop.org,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
Date: Mon, 24 Jul 2023 15:08:58 +0530 [thread overview]
Message-ID: <6a0ef5d5-c772-e04f-fb74-ca59e26b27c7@intel.com> (raw)
In-Reply-To: <875y6cqy6p.wl-ashutosh.dixit@intel.com>
On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>
>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>
>> Hi Aravind,
>>
>>> On 21-07-2023 06:32, Dixit, Ashutosh wrote:
>>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>>>>
>>>> More stuff to mull over. You can ignore comments starting with "OK", those
>>>> are just notes to myself.
>>>>
>>>> Also, maybe some time we can add a basic IGT which reads these exposed
>>>> counters and verifies that we can read them and they are monotonically
>>>> increasing?
>>>
>>> this is the IGT https://patchwork.freedesktop.org/series/119936/ series
>>> using these counters posted by Venkat.
>>>
>>>>
>>>>> There are a set of engine group busyness counters provided by HW which are
>>>>> perfect fit to be exposed via PMU perf events.
>>>>>
>>>>> BSPEC: 46559, 46560, 46722, 46729
>>>>
>>>> Also add these Bspec entries: 71028, 52071
>>>
>>> OK.
>>>
>>>>
>>>>>
>>>>> events can be listed using:
>>>>> perf list
>>>>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>>>>
>>>>> and can be read using:
>>>>>
>>>>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>>>>> time counts unit events
>>>>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>>
>>>>> The pmu base implementation is taken from i915.
>>>>>
>>>>> v2:
>>>>> Store last known value when device is awake return that while the GT is
>>>>> suspended and then update the driver copy when read during awake.
>>>>>
>>>>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/xe/Makefile | 2 +
>>>>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>>>>> drivers/gpu/drm/xe/xe_device.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>>>>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>>>>> drivers/gpu/drm/xe/xe_module.c | 5 +
>>>>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>>>>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>>>>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>>>>> include/uapi/drm/xe_drm.h | 16 +
>>>>> 11 files changed, 902 insertions(+)
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>>>>>
<snip>
>>>>> +
>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>> +{
>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>> + unsigned int gt_id = gt->info.id;
>>>>> + unsigned long flags;
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>
> Here why should we store everything, we should store only those events
> which are enabled?
>
> Also it would good if the above can be done in a loop somehow. 4 is fine
> but if we add events later, a loop will be nice, if possible.
i got your point. i could do something like this
for (i = __XE_SAMPLE_RENDER_GROUP_BUSY; i < __XE_NUM_PMU_SAMPLERS; i++) {
val = __engine_group_busyness_read(gt, i);
pmu->sample[gt_id][i] = val;
}
Thanks,
Aravind.
next prev parent reply other threads:[~2023-07-24 9:39 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 12:21 [Intel-xe] [PATCH v2 0/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 1/2] drm/xe: Get GT clock to nanosecs Aravind Iddamsetty
2023-07-04 9:29 ` Upadhyay, Tejas
2023-07-04 10:14 ` Upadhyay, Tejas
2023-07-05 4:46 ` Iddamsetty, Aravind
2023-07-06 0:55 ` Dixit, Ashutosh
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-30 13:53 ` Upadhyay, Tejas
2023-07-03 5:11 ` Iddamsetty, Aravind
2023-07-04 3:34 ` Ghimiray, Himal Prasad
2023-07-05 4:52 ` Iddamsetty, Aravind
2023-07-04 9:10 ` Upadhyay, Tejas
2023-07-05 4:42 ` Iddamsetty, Aravind
2023-07-06 2:39 ` Dixit, Ashutosh
2023-07-06 13:42 ` Iddamsetty, Aravind
2023-07-07 2:18 ` Dixit, Ashutosh
2023-07-07 3:53 ` Iddamsetty, Aravind
2023-07-07 6:08 ` Dixit, Ashutosh
2023-07-07 10:42 ` Iddamsetty, Aravind
2023-07-07 21:25 ` Dixit, Ashutosh
2023-07-10 6:05 ` Iddamsetty, Aravind
2023-07-10 8:12 ` Ursulin, Tvrtko
2023-07-11 16:19 ` Iddamsetty, Aravind
2023-07-11 23:10 ` Dixit, Ashutosh
2023-07-12 3:11 ` Iddamsetty, Aravind
2023-07-12 5:24 ` Dixit, Ashutosh
2023-07-11 22:58 ` Dixit, Ashutosh
2023-07-09 0:32 ` Dixit, Ashutosh
2023-07-10 4:13 ` Iddamsetty, Aravind
2023-07-10 5:57 ` Dixit, Ashutosh
2023-07-18 5:07 ` Dixit, Ashutosh
2023-07-19 6:59 ` Iddamsetty, Aravind
2023-07-06 2:40 ` Belgaumkar, Vinay
2023-07-06 13:06 ` Iddamsetty, Aravind
2023-07-21 1:02 ` Dixit, Ashutosh
2023-07-21 11:51 ` Iddamsetty, Aravind
2023-07-21 23:36 ` Dixit, Ashutosh
2023-07-22 6:04 ` Dixit, Ashutosh
2023-07-24 8:03 ` Iddamsetty, Aravind
2023-07-24 9:00 ` Ursulin, Tvrtko
2023-07-24 15:52 ` Dixit, Ashutosh
2023-07-24 15:52 ` Dixit, Ashutosh
2023-07-24 16:05 ` Iddamsetty, Aravind
2023-07-24 16:31 ` Dixit, Ashutosh
2023-07-25 11:38 ` Iddamsetty, Aravind
2023-08-07 21:16 ` Dixit, Ashutosh
2023-08-07 22:22 ` Dixit, Ashutosh
2023-08-08 13:45 ` Iddamsetty, Aravind
2023-08-08 15:18 ` Dixit, Ashutosh
2023-08-09 4:26 ` Iddamsetty, Aravind
2023-08-09 5:02 ` Dixit, Ashutosh
2023-07-24 9:38 ` Iddamsetty, Aravind [this message]
2023-07-22 14:39 ` Dixit, Ashutosh
2023-07-24 8:02 ` Iddamsetty, Aravind
2023-06-27 13:04 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe/pmu: Enable PMU interface (rev2) Patchwork
2023-06-27 13:05 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-06-27 13:06 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
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