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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: "Iddamsetty, Aravind" <aravind.iddamsetty@intel.com>
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>,
	intel-xe@lists.freedesktop.org,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
Date: Thu, 06 Jul 2023 23:08:04 -0700	[thread overview]
Message-ID: <878rbsckzf.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <04ae6811-9bc1-c66d-6cb8-640bfd8a9c7b@intel.com>

On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>

Hi Aravind,

I will look at the timing stuff later but one further question about the
requirement:

> > Also, could you please explain where the requirement to expose these OAG
> > group busy/free registers via the PMU is coming from? Since these are OA
> > registers presumably they can be collected using the OA subsystem.
>
> L0 sysman needs this
> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> and xpumanager uses this
> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp

So fine these are UMD requirements, but why do these quantities (everything
in this patch) have to exposed via PMU? I could just create sysfs or an
ioctl to provide these to userland, right?

I had this same question about i915 PMU which was never answered. i915 PMU
IMO does truly strange things like sample freq's every 5 ms and provides
software averages which I thought userspace can easily do.

I don't think it's the timestamps, maybe there is some convention related
to the cpu pmu (which I am not familiar with).

Let's see, maybe Tvrtko can also answer why these things were exposed via
i915 PMU.

Thanks.
--
Ashutosh


> >
> > The i915 PMU I believe deduces busyness by sampling the RING_CTL register
> > using a timer. So these registers look better since you can get these
> > busyness values directly. On the other hand you can only get busyness for
> > an engine group and things like compute seem to be missing?
>
> The per engine busyness is a different thing we still need that and it
> has different implementation with GuC enabled, I believe Umesh is
> looking into that.
>
> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
> also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
> >
> > Also, would you know about plans to expose other kinds of busyness-es? I
> > think we may be exposing per-VF and also per-client busyness via PMU. Not
> > sure what else GuC can expose. Knowing all this we can better understand
> > how these particular busyness values will be used.
>
> ya, that shall be coming next probably from Umesh but per client
> busyness is through fdinfo.

  reply	other threads:[~2023-07-07  6:18 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-27 12:21 [Intel-xe] [PATCH v2 0/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 1/2] drm/xe: Get GT clock to nanosecs Aravind Iddamsetty
2023-07-04  9:29   ` Upadhyay, Tejas
2023-07-04 10:14     ` Upadhyay, Tejas
2023-07-05  4:46       ` Iddamsetty, Aravind
2023-07-06  0:55   ` Dixit, Ashutosh
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-30 13:53   ` Upadhyay, Tejas
2023-07-03  5:11     ` Iddamsetty, Aravind
2023-07-04  3:34   ` Ghimiray, Himal Prasad
2023-07-05  4:52     ` Iddamsetty, Aravind
2023-07-04  9:10   ` Upadhyay, Tejas
2023-07-05  4:42     ` Iddamsetty, Aravind
2023-07-06  2:39   ` Dixit, Ashutosh
2023-07-06 13:42     ` Iddamsetty, Aravind
2023-07-07  2:18       ` Dixit, Ashutosh
2023-07-07  3:53         ` Iddamsetty, Aravind
2023-07-07  6:08           ` Dixit, Ashutosh [this message]
2023-07-07 10:42             ` Iddamsetty, Aravind
2023-07-07 21:25               ` Dixit, Ashutosh
2023-07-10  6:05                 ` Iddamsetty, Aravind
2023-07-10  8:12                   ` Ursulin, Tvrtko
2023-07-11 16:19                     ` Iddamsetty, Aravind
2023-07-11 23:10                       ` Dixit, Ashutosh
2023-07-12  3:11                         ` Iddamsetty, Aravind
2023-07-12  5:24                           ` Dixit, Ashutosh
2023-07-11 22:58                     ` Dixit, Ashutosh
2023-07-09  0:32           ` Dixit, Ashutosh
2023-07-10  4:13             ` Iddamsetty, Aravind
2023-07-10  5:57               ` Dixit, Ashutosh
2023-07-18  5:07           ` Dixit, Ashutosh
2023-07-19  6:59             ` Iddamsetty, Aravind
2023-07-06  2:40   ` Belgaumkar, Vinay
2023-07-06 13:06     ` Iddamsetty, Aravind
2023-07-21  1:02   ` Dixit, Ashutosh
2023-07-21 11:51     ` Iddamsetty, Aravind
2023-07-21 23:36       ` Dixit, Ashutosh
2023-07-22  6:04         ` Dixit, Ashutosh
2023-07-24  8:03           ` Iddamsetty, Aravind
2023-07-24  9:00             ` Ursulin, Tvrtko
2023-07-24 15:52               ` Dixit, Ashutosh
2023-07-24 15:52             ` Dixit, Ashutosh
2023-07-24 16:05               ` Iddamsetty, Aravind
2023-07-24 16:31                 ` Dixit, Ashutosh
2023-07-25 11:38                   ` Iddamsetty, Aravind
2023-08-07 21:16                     ` Dixit, Ashutosh
2023-08-07 22:22                       ` Dixit, Ashutosh
2023-08-08 13:45                         ` Iddamsetty, Aravind
2023-08-08 15:18                           ` Dixit, Ashutosh
2023-08-09  4:26                             ` Iddamsetty, Aravind
2023-08-09  5:02                               ` Dixit, Ashutosh
2023-07-24  9:38           ` Iddamsetty, Aravind
2023-07-22 14:39   ` Dixit, Ashutosh
2023-07-24  8:02     ` Iddamsetty, Aravind
2023-06-27 13:04 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe/pmu: Enable PMU interface (rev2) Patchwork
2023-06-27 13:05 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-06-27 13:06 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-06-27 13:10 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork

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