Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>

Hi Aravind,

> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> +	u64 val = 0;
> +
> +	switch (config) {
> +	case XE_PMU_RENDER_GROUP_BUSY(0):
> +		val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> +		break;
> +	case XE_PMU_COPY_GROUP_BUSY(0):
> +		val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> +		break;
> +	case XE_PMU_MEDIA_GROUP_BUSY(0):
> +		val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> +		break;
> +	case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> +		val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> +		break;
> +	default:
> +		drm_warn(&gt->tile->xe->drm, "unknown pmu event\n");
> +	}
> +
> +	return xe_gt_clock_interval_to_ns(gt, val * 16);
> +}

A few questions on just the above function first:

1. OK so these registers won't be available to VF's, but any idea what
   these counts are when VF's are active?

2. When would these 32 bit registers overflow? Let us say a group is
   continuously busy and we are running at 1 GHz, the registers would
   overflow in 4 seconds (max value 4G)?

3. What is the multiplication by 16 (not factored above in 2.)? I don't see
   that in Bspec.

Thanks.
--
Ashutosh