* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
@ 2023-06-30 13:53 ` Upadhyay, Tejas
2023-07-03 5:11 ` Iddamsetty, Aravind
2023-07-04 3:34 ` Ghimiray, Himal Prasad
` (5 subsequent siblings)
6 siblings, 1 reply; 59+ messages in thread
From: Upadhyay, Tejas @ 2023-06-30 13:53 UTC (permalink / raw)
To: Iddamsetty, Aravind, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
Review in progress, as it is large patch , its taking time. Some initial comments as follows:
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Aravind Iddamsetty
> Sent: Tuesday, June 27, 2023 5:51 PM
> To: intel-xe@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
> <tvrtko.ursulin@intel.com>
> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>
> There are a set of engine group busyness counters provided by HW which
> are perfect fit to be exposed via PMU perf events.
>
> BSPEC: 46559, 46560, 46722, 46729
>
> events can be listed using:
> perf list
> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>
> and can be read using:
>
> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> time counts unit events
> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>
> The pmu base implementation is taken from i915.
>
> v2:
> Store last known value when device is awake return that while the GT is
> suspended and then update the driver copy when read during awake.
>
> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> drivers/gpu/drm/xe/xe_device.c | 2 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt.c | 2 +
> drivers/gpu/drm/xe/xe_irq.c | 22 +
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> include/uapi/drm/xe_drm.h | 16 +
> 11 files changed, 902 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
> drivers/gpu/drm/xe/xe_pmu_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 081c57fd8632..e52ab795c566 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/skl_universal_plane.o \
> i915-display/skl_watermark.o
>
> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> +
> ifeq ($(CONFIG_ACPI),y)
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_acpi.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..c7d9e4634745 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -285,6 +285,11 @@
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
> XE_REG(0xdb80)
> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> +
> #define SAMPLER_MODE XE_REG_MCR(0xe18c,
> XE_REG_OPTION_MASKED)
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
> 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_debugfs_register(xe);
>
> + xe_pmu_register(&xe->pmu);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 0226d44a6af2..3ba99aae92b9 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
> #include "xe_devcoredump_types.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> +#include "xe_pmu.h"
> #include "xe_step_types.h"
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> @@ -332,6 +333,9 @@ struct xe_device {
> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> bool d3cold_allowed;
>
> + /* @pmu: performance monitoring unit */
> + struct xe_pmu pmu;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
> 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index b4ed1e4a3388..cb943fb94ec7 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,6 +27,24 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> + irqreturn_t res)
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
> +
> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
> u32 val = xe_mmio_read32(mmio, reg);
> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> dg1_intr_enable(xe, false);
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_module.c
> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
> 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -12,6 +12,7 @@
> #include "xe_hw_fence.h"
> #include "xe_module.h"
> #include "xe_pci.h"
> +#include "xe_pmu.h"
> #include "xe_sched_job.h"
>
> bool enable_guc = true;
> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> .init = xe_sched_job_module_init,
> .exit = xe_sched_job_module_exit,
> },
> + {
> + .init = xe_pmu_init,
> + .exit = xe_pmu_exit,
> + },
> {
> .init = xe_register_pci_driver,
> .exit = xe_unregister_pci_driver,
> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> new file mode 100644 index 000000000000..bef1895be9f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> @@ -0,0 +1,739 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <drm/drm_drv.h>
> +#include <drm/drm_managed.h>
> +#include <drm/xe_drm.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt_clock.h"
> +#include "xe_mmio.h"
> +
> +static cpumask_t xe_pmu_cpumask;
> +static unsigned int xe_pmu_target_cpu = -1;
> +
> +static unsigned int config_gt_id(const u64 config) {
> + return config >> __XE_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config) {
> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
> +
> +static unsigned int
> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> +
> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
> +
> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
> +sample) {
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
> +
> +static void
> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
> +val) {
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
> +
> +static int engine_busyness_sample_type(u64 config) {
> + int type = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> + break;
> + }
> +
> + return type;
> +}
> +
> +static void xe_pmu_event_destroy(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> +
> + drm_WARN_ON(&xe->drm, event->parent);
> +
> + drm_dev_put(&xe->drm);
> +}
> +
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
> +
> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + int sample_type = engine_busyness_sample_type(config);
> + struct xe_device *xe = gt->tile->xe;
> + const unsigned int gt_id = gt->info.id;
> + struct xe_pmu *pmu = &xe->pmu;
> + bool device_awake;
> + unsigned long flags;
> + u64 val;
> +
> + /*
> + * found no better way to check if device is awake or not. Before
> + * we suspend we set the submission_state.enabled to false.
> + */
> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> + if (device_awake)
> + val = __engine_group_busyness_read(gt, config);
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + if (device_awake)
> + store_sample(pmu, gt_id, sample_type, val);
> + else
> + val = read_sample(pmu, gt_id, sample_type);
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +
> + return val;
> +}
> +
> +void engine_group_busyness_store(struct xe_gt *gt) {
> + struct xe_pmu *pmu = >->tile->xe->pmu;
> + unsigned int gt_id = gt->info.id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_RENDER_GROUP_BUSY(0)));
Should not you pass gt_id here?, like XE_PMU_RENDER_GROUP_BUSY(gt_id), I know it will not make difference right now as we have max 0 or 1 id of GT, but in future this might be still compatible if we pass gt_id.
> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_COPY_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_MEDIA_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id,
> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> +
> + spin_unlock_irqrestore(&pmu->lock, flags); }
> +
> +static int
> +config_status(struct xe_device *xe, u64 config) {
> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> + unsigned int gt_id = config_gt_id(config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> +
> + if (gt_id > max_gt_id)
> + return -ENOENT;
> +
> + switch (config_counter(config)) {
> + case XE_PMU_INTERRUPTS(0):
> + if (gt_id)
> + return -ENOENT;
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + if (GRAPHICS_VER(xe) < 12)
> + return -ENOENT;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
> XE_GT_TYPE_MEDIA)
> + return -ENOENT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_pmu_event_init(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> + int ret;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* unsupported modes and filters */
> + if (event->attr.sample_period) /* no sampling */
> + return -EINVAL;
> +
> + if (has_branch_stack(event))
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /* only allow running on one cpu at a time */
> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> + return -EINVAL;
> +
> + ret = config_status(xe, event->attr.config);
> + if (ret)
> + return ret;
> +
> + if (!event->parent) {
> + drm_dev_get(&xe->drm);
> + event->destroy = xe_pmu_event_destroy;
> + }
> +
> + return 0;
> +}
> +
> +static u64 __xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + const unsigned int gt_id = config_gt_id(event->attr.config);
> + const u64 config = config_counter(event->attr.config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_INTERRUPTS(0):
> + val = READ_ONCE(pmu->irq_count);
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = engine_group_busyness_read(gt, config);
> + }
> +
> + return val;
> +}
> +
> +static void xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct hw_perf_event *hwc = &event->hw;
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 prev, new;
> +
> + if (pmu->closed) {
> + event->hw.state = PERF_HES_STOPPED;
> + return;
> + }
> +again:
> + prev = local64_read(&hwc->prev_count);
> + new = __xe_pmu_event_read(event);
> +
> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> + goto again;
> +
> + local64_add(new - prev, &event->count); }
> +
> +static void xe_pmu_enable(struct perf_event *event) {
> + /*
> + * Store the current counter value so we can report the correct delta
> + * for all listeners. Even when the event was already enabled and has
> + * an existing non-zero value.
> + */
> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> }
> +
> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return;
> +
> + xe_pmu_enable(event);
> + event->hw.state = 0;
> +}
> +
> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
> + if (flags & PERF_EF_UPDATE)
> + xe_pmu_event_read(event);
> +
> + event->hw.state = PERF_HES_STOPPED;
> +}
> +
> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (flags & PERF_EF_START)
> + xe_pmu_event_start(event, flags);
> +
> + return 0;
> +}
> +
> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
> +
> +static int xe_pmu_event_event_idx(struct perf_event *event) {
> + return 0;
> +}
> +
> +struct xe_str_attribute {
> + struct device_attribute attr;
> + const char *str;
> +};
> +
> +static ssize_t xe_pmu_format_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_str_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_str_attribute, attr);
> + return sprintf(buf, "%s\n", eattr->str); }
> +
> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> + (&((struct xe_str_attribute[]) { \
> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL),
> \
> + .str = _config, } \
> + })[0].attr.attr)
> +
> +static struct attribute *xe_pmu_format_attrs[] = {
> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_format_attr_group = {
> + .name = "format",
> + .attrs = xe_pmu_format_attrs,
> +};
> +
> +struct xe_ext_attribute {
> + struct device_attribute attr;
> + unsigned long val;
> +};
> +
> +static ssize_t xe_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
> +
> +static ssize_t cpumask_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
> +
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *xe_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> + .attrs = xe_cpumask_attrs,
> +};
> +
> +#define __event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = false, \
> +}
> +
> +#define __global_event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = true, \
> +}
> +
> +static struct xe_ext_attribute *
> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
> +config) {
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = xe_pmu_event_show;
> + attr->val = config;
> +
> + return ++attr;
> +}
> +
> +static struct perf_pmu_events_attr *
> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> + const char *str)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = perf_event_sysfs_show;
> + attr->event_str = str;
> +
> + return ++attr;
> +}
> +
> +static struct attribute **
> +create_event_attributes(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + static const struct {
> + unsigned int counter;
> + const char *name;
> + const char *unit;
> + bool global;
> + } events[] = {
> + __global_event(0, "interrupts", NULL),
> + __event(1, "render-group-busy", "ns"),
> + __event(2, "copy-group-busy", "ns"),
> + __event(3, "media-group-busy", "ns"),
> + __event(4, "any-engine-group-busy", "ns"),
> + };
> +
> + unsigned int count = 0;
> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> + struct attribute **attr = NULL, **attr_iter;
> + struct xe_gt *gt;
> + unsigned int i, j;
> +
> + /* Count how many counters we will be exposing. */
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> +
> + if (!config_status(xe, config))
> + count++;
> + }
> + }
> +
> + /* Allocate attribute objects and table. */
> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> + if (!xe_attr)
> + goto err_alloc;
> +
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> + if (!pmu_attr)
> + goto err_alloc;
> +
> + /* Max one pointer of each attribute type plus a termination entry.
> */
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + goto err_alloc;
> +
> + xe_iter = xe_attr;
> + pmu_iter = pmu_attr;
> + attr_iter = attr;
> +
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> + char *str;
> +
> + if (config_status(xe, config))
> + continue;
> +
> + if (events[i].global)
> + str = kstrdup(events[i].name, GFP_KERNEL);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &xe_iter->attr.attr;
> + xe_iter = add_xe_attr(xe_iter, str, config);
> +
> + if (events[i].unit) {
> + if (events[i].global)
> + str = kasprintf(GFP_KERNEL,
> "%s.unit",
> + events[i].name);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-
> gt%u.unit",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &pmu_iter->attr.attr;
> + pmu_iter = add_pmu_attr(pmu_iter, str,
> + events[i].unit);
> + }
> + }
> + }
> +
> + pmu->xe_attr = xe_attr;
> + pmu->pmu_attr = pmu_attr;
> +
> + return attr;
> +
> +err:
> + for (attr_iter = attr; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> +err_alloc:
> + kfree(attr);
> + kfree(xe_attr);
> + kfree(pmu_attr);
> +
> + return NULL;
> +}
> +
> +static void free_event_attributes(struct xe_pmu *pmu) {
> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> +
> + for (; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> + kfree(pmu->events_attr_group.attrs);
> + kfree(pmu->xe_attr);
> + kfree(pmu->pmu_attr);
> +
> + pmu->events_attr_group.attrs = NULL;
> + pmu->xe_attr = NULL;
> + pmu->pmu_attr = NULL;
> +}
> +
> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /* Select the first online CPU as a designated reader. */
> + if (cpumask_empty(&xe_pmu_cpumask))
> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> +
> + return 0;
> +}
> +
> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
> +*node) {
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> + unsigned int target = xe_pmu_target_cpu;
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /*
> + * Unregistering an instance generates a CPU offline event which we
> must
> + * ignore to avoid incorrectly modifying the shared
> xe_pmu_cpumask.
> + */
> + if (pmu->closed)
> + return 0;
> +
> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
> cpu);
> +
> + /* Migrate events if there is a valid target */
> + if (target < nr_cpu_ids) {
> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> + xe_pmu_target_cpu = target;
> + }
> + }
> +
> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> + pmu->cpuhp.cpu = target;
> + }
> +
> + return 0;
> +}
> +
> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> +
> +int xe_pmu_init(void)
> +{
> + int ret;
> +
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "perf/x86/intel/xe:online",
> + xe_pmu_cpu_online,
> + xe_pmu_cpu_offline);
> + if (ret < 0)
> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> + ret);
> + else
> + cpuhp_slot = ret;
> +
> + return 0;
> +}
> +
> +void xe_pmu_exit(void)
> +{
> + if (cpuhp_slot != CPUHP_INVALID)
> + cpuhp_remove_multi_state(cpuhp_slot);
> +}
> +
> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
> + if (cpuhp_slot == CPUHP_INVALID)
> + return -EINVAL;
> +
> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> }
> +
> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
> +
> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
> + struct xe_pmu *pmu = arg;
> +
> + if (!pmu->base.event_init)
> + return;
> +
> + /*
> + * "Disconnect" the PMU callbacks - since all are atomic
> synchronize_rcu
> + * ensures all currently executing ones will have exited before we
> + * proceed with unregistration.
> + */
> + pmu->closed = true;
> + synchronize_rcu();
> +
> + xe_pmu_unregister_cpuhp_state(pmu);
> +
> + perf_pmu_unregister(&pmu->base);
> + pmu->base.event_init = NULL;
> + kfree(pmu->base.attr_groups);
> + kfree(pmu->name);
> + free_event_attributes(pmu);
> +}
> +
> +static void init_samples(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + struct xe_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, xe, i)
> + engine_group_busyness_store(gt);
> +}
> +
> +void xe_pmu_register(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + const struct attribute_group *attr_groups[] = {
> + &xe_pmu_format_attr_group,
> + &pmu->events_attr_group,
> + &xe_pmu_cpumask_attr_group,
> + NULL
> + };
> +
No newline needed here I think.
> + int ret = -ENOMEM;
> +
> + spin_lock_init(&pmu->lock);
> + pmu->cpuhp.cpu = -1;
> + init_samples(pmu);
> +
> + pmu->name = kasprintf(GFP_KERNEL,
> + "xe_%s",
> + dev_name(xe->drm.dev));
> + if (pmu->name)
> + /* tools/perf reserves colons as special. */
> + strreplace((char *)pmu->name, ':', '_');
> +
We can skip checking pmu->name again here.
Thanks,
Tejas
> + if (!pmu->name)
> + goto err;
> +
> + pmu->events_attr_group.name = "events";
> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> + if (!pmu->events_attr_group.attrs)
> + goto err_name;
> +
> + pmu->base.attr_groups = kmemdup(attr_groups,
> sizeof(attr_groups),
> + GFP_KERNEL);
> + if (!pmu->base.attr_groups)
> + goto err_attr;
> +
> + pmu->base.module = THIS_MODULE;
> + pmu->base.task_ctx_nr = perf_invalid_context;
> + pmu->base.event_init = xe_pmu_event_init;
> + pmu->base.add = xe_pmu_event_add;
> + pmu->base.del = xe_pmu_event_del;
> + pmu->base.start = xe_pmu_event_start;
> + pmu->base.stop = xe_pmu_event_stop;
> + pmu->base.read = xe_pmu_event_read;
> + pmu->base.event_idx = xe_pmu_event_event_idx;
> +
> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> + if (ret)
> + goto err_groups;
> +
> + ret = xe_pmu_register_cpuhp_state(pmu);
> + if (ret)
> + goto err_unreg;
> +
> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
> pmu);
> + XE_WARN_ON(ret);
> +
> + return;
> +
> +err_unreg:
> + perf_pmu_unregister(&pmu->base);
> +err_groups:
> + kfree(pmu->base.attr_groups);
> +err_attr:
> + pmu->base.event_init = NULL;
> + free_event_attributes(pmu);
> +err_name:
> + kfree(pmu->name);
> +err:
> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> new file mode 100644 index 000000000000..d3f47f4ab343
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_H_
> +#define _XE_PMU_H_
> +
> +#include "xe_gt_types.h"
> +#include "xe_pmu_types.h"
> +
> +#ifdef CONFIG_PERF_EVENTS
> +int xe_pmu_init(void);
> +void xe_pmu_exit(void);
> +void xe_pmu_register(struct xe_pmu *pmu); void
> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
> b/drivers/gpu/drm/xe/xe_pmu_types.h
> new file mode 100644
> index 000000000000..e87edd4d6a87
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_TYPES_H_
> +#define _XE_PMU_TYPES_H_
> +
> +#include <linux/perf_event.h>
> +#include <linux/spinlock_types.h>
> +#include <uapi/drm/xe_drm.h>
> +
> +enum {
> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __XE_SAMPLE_COPY_GROUP_BUSY,
> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __XE_NUM_PMU_SAMPLERS
> +};
> +
> +struct xe_pmu_sample {
> + u64 cur;
> +};
> +
> +#define XE_MAX_GT_PER_TILE 2
> +
> +struct xe_pmu {
> + /**
> + * @cpuhp: Struct used for CPU hotplug handling.
> + */
> + struct {
> + struct hlist_node node;
> + unsigned int cpu;
> + } cpuhp;
> + /**
> + * @base: PMU base.
> + */
> + struct pmu base;
> + /**
> + * @closed: xe is unregistering.
> + */
> + bool closed;
> + /**
> + * @name: Name as registered with perf core.
> + */
> + const char *name;
> + /**
> + * @lock: Lock protecting enable mask and ref count handling.
> + */
> + spinlock_t lock;
> + /**
> + * @sample: Current and previous (raw) counters.
> + *
> + * These counters are updated when the device is awake.
> + *
> + */
> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
> __XE_NUM_PMU_SAMPLERS];
> + /**
> + * @irq_count: Number of interrupts
> + *
> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> + * occasional wraparound easily. It's 32bit after all.
> + */
> + unsigned long irq_count;
> + /**
> + * @events_attr_group: Device events attribute group.
> + */
> + struct attribute_group events_attr_group;
> + /**
> + * @xe_attr: Memory block holding device attributes.
> + */
> + void *xe_attr;
> + /**
> + * @pmu_attr: Memory block holding device attributes.
> + */
> + void *pmu_attr;
> +};
> +
> +#endif
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> 965cd9527ff1..ed097056f944 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> __u64 reserved[2];
> };
>
> +/* PMU event config IDs */
> +
> +/*
> + * Top 4 bits of every counter are GT id.
> + */
> +#define __XE_PMU_GT_SHIFT (60)
> +
> +#define ___XE_PMU_OTHER(gt, x) \
> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> +
> +#define XE_PMU_INTERRUPTS(gt)
> ___XE_PMU_OTHER(gt, 0)
> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 1)
> +#define XE_PMU_COPY_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 2)
> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 3)
> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 4)
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.25.1
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-30 13:53 ` Upadhyay, Tejas
@ 2023-07-03 5:11 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-03 5:11 UTC (permalink / raw)
To: Upadhyay, Tejas, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
On 30-06-2023 19:23, Upadhyay, Tejas wrote:
> Review in progress, as it is large patch , its taking time. Some initial comments as follows:
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> Aravind Iddamsetty
>> Sent: Tuesday, June 27, 2023 5:51 PM
>> To: intel-xe@lists.freedesktop.org
>> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
>> <tvrtko.ursulin@intel.com>
>> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>>
>> There are a set of engine group busyness counters provided by HW which
>> are perfect fit to be exposed via PMU perf events.
>>
>> BSPEC: 46559, 46560, 46722, 46729
>>
>> events can be listed using:
>> perf list
>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>
>> and can be read using:
>>
>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>> time counts unit events
>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>
>> The pmu base implementation is taken from i915.
>>
>> v2:
>> Store last known value when device is awake return that while the GT is
>> suspended and then update the driver copy when read during awake.
>>
>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>> drivers/gpu/drm/xe/xe_device.c | 2 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>> drivers/gpu/drm/xe/xe_module.c | 5 +
>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>> include/uapi/drm/xe_drm.h | 16 +
>> 11 files changed, 902 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
>> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
>> drivers/gpu/drm/xe/xe_pmu_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 081c57fd8632..e52ab795c566 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/skl_universal_plane.o \
>> i915-display/skl_watermark.o
>>
>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>> +
>> ifeq ($(CONFIG_ACPI),y)
>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_acpi.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3f664011eaea..c7d9e4634745 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -285,6 +285,11 @@
>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>
>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
>> XE_REG(0xdb80)
>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>> +
>> #define SAMPLER_MODE XE_REG_MCR(0xe18c,
>> XE_REG_OPTION_MASKED)
>> #define ENABLE_SMALLPL REG_BIT(15)
>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_debugfs_register(xe);
>>
>> + xe_pmu_register(&xe->pmu);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>> b/drivers/gpu/drm/xe/xe_device_types.h
>> index 0226d44a6af2..3ba99aae92b9 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -15,6 +15,7 @@
>> #include "xe_devcoredump_types.h"
>> #include "xe_gt_types.h"
>> #include "xe_platform_types.h"
>> +#include "xe_pmu.h"
>> #include "xe_step_types.h"
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> @@ -332,6 +333,9 @@ struct xe_device {
>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>> bool d3cold_allowed;
>>
>> + /* @pmu: performance monitoring unit */
>> + struct xe_pmu pmu;
>> +
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
>> 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>>
>> + engine_group_busyness_store(gt);
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index b4ed1e4a3388..cb943fb94ec7 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,6 +27,24 @@
>> #define IIR(offset) XE_REG(offset + 0x8)
>> #define IER(offset) XE_REG(offset + 0xc)
>>
>> +/*
>> + * Interrupt statistic for PMU. Increments the counter only if the
>> + * interrupt originated from the GPU so interrupts from a device which
>> + * shares the interrupt line are not accounted.
>> + */
>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>> + irqreturn_t res)
>> +{
>> + if (unlikely(res != IRQ_HANDLED))
>> + return;
>> +
>> + /*
>> + * A clever compiler translates that into INC. A not so clever one
>> + * should at least prevent store tearing.
>> + */
>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
>> +
>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
>> u32 val = xe_mmio_read32(mmio, reg);
>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>>
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> dg1_intr_enable(xe, false);
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_module.c
>> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_fence.h"
>> #include "xe_module.h"
>> #include "xe_pci.h"
>> +#include "xe_pmu.h"
>> #include "xe_sched_job.h"
>>
>> bool enable_guc = true;
>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>> .init = xe_sched_job_module_init,
>> .exit = xe_sched_job_module_exit,
>> },
>> + {
>> + .init = xe_pmu_init,
>> + .exit = xe_pmu_exit,
>> + },
>> {
>> .init = xe_register_pci_driver,
>> .exit = xe_unregister_pci_driver,
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> new file mode 100644 index 000000000000..bef1895be9f7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -0,0 +1,739 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_drv.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "regs/xe_gt_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt_clock.h"
>> +#include "xe_mmio.h"
>> +
>> +static cpumask_t xe_pmu_cpumask;
>> +static unsigned int xe_pmu_target_cpu = -1;
>> +
>> +static unsigned int config_gt_id(const u64 config) {
>> + return config >> __XE_PMU_GT_SHIFT;
>> +}
>> +
>> +static u64 config_counter(const u64 config) {
>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
>> +
>> +static unsigned int
>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>> +
>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>> +
>> + return idx;
>> +}
>> +
>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
>> +sample) {
>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
>> +
>> +static void
>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
>> +val) {
>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
>> +
>> +static int engine_busyness_sample_type(u64 config) {
>> + int type = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>> + break;
>> + }
>> +
>> + return type;
>> +}
>> +
>> +static void xe_pmu_event_destroy(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> +
>> + drm_WARN_ON(&xe->drm, event->parent);
>> +
>> + drm_dev_put(&xe->drm);
>> +}
>> +
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
>> +
>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + int sample_type = engine_busyness_sample_type(config);
>> + struct xe_device *xe = gt->tile->xe;
>> + const unsigned int gt_id = gt->info.id;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + bool device_awake;
>> + unsigned long flags;
>> + u64 val;
>> +
>> + /*
>> + * found no better way to check if device is awake or not. Before
>> + * we suspend we set the submission_state.enabled to false.
>> + */
>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>> + if (device_awake)
>> + val = __engine_group_busyness_read(gt, config);
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + if (device_awake)
>> + store_sample(pmu, gt_id, sample_type, val);
>> + else
>> + val = read_sample(pmu, gt_id, sample_type);
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +
>> + return val;
>> +}
>> +
>> +void engine_group_busyness_store(struct xe_gt *gt) {
>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>> + unsigned int gt_id = gt->info.id;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_RENDER_GROUP_BUSY(0)));
>
> Should not you pass gt_id here?, like XE_PMU_RENDER_GROUP_BUSY(gt_id), I know it will not make difference right now as we have max 0 or 1 id of GT, but in future this might be still compatible if we pass gt_id.
__engine_group_busyness_read is already having a gt reference hence no
need to pass again in config.
>
>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_COPY_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_MEDIA_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id,
>> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags); }
>> +
>> +static int
>> +config_status(struct xe_device *xe, u64 config) {
>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>> + unsigned int gt_id = config_gt_id(config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> +
>> + if (gt_id > max_gt_id)
>> + return -ENOENT;
>> +
>> + switch (config_counter(config)) {
>> + case XE_PMU_INTERRUPTS(0):
>> + if (gt_id)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + if (GRAPHICS_VER(xe) < 12)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
>> XE_GT_TYPE_MEDIA)
>> + return -ENOENT;
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_event_init(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + int ret;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* unsupported modes and filters */
>> + if (event->attr.sample_period) /* no sampling */
>> + return -EINVAL;
>> +
>> + if (has_branch_stack(event))
>> + return -EOPNOTSUPP;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /* only allow running on one cpu at a time */
>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>> + return -EINVAL;
>> +
>> + ret = config_status(xe, event->attr.config);
>> + if (ret)
>> + return ret;
>> +
>> + if (!event->parent) {
>> + drm_dev_get(&xe->drm);
>> + event->destroy = xe_pmu_event_destroy;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static u64 __xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>> + const u64 config = config_counter(event->attr.config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_INTERRUPTS(0):
>> + val = READ_ONCE(pmu->irq_count);
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = engine_group_busyness_read(gt, config);
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static void xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 prev, new;
>> +
>> + if (pmu->closed) {
>> + event->hw.state = PERF_HES_STOPPED;
>> + return;
>> + }
>> +again:
>> + prev = local64_read(&hwc->prev_count);
>> + new = __xe_pmu_event_read(event);
>> +
>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>> + goto again;
>> +
>> + local64_add(new - prev, &event->count); }
>> +
>> +static void xe_pmu_enable(struct perf_event *event) {
>> + /*
>> + * Store the current counter value so we can report the correct delta
>> + * for all listeners. Even when the event was already enabled and has
>> + * an existing non-zero value.
>> + */
>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>> }
>> +
>> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return;
>> +
>> + xe_pmu_enable(event);
>> + event->hw.state = 0;
>> +}
>> +
>> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
>> + if (flags & PERF_EF_UPDATE)
>> + xe_pmu_event_read(event);
>> +
>> + event->hw.state = PERF_HES_STOPPED;
>> +}
>> +
>> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (flags & PERF_EF_START)
>> + xe_pmu_event_start(event, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
>> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
>> +
>> +static int xe_pmu_event_event_idx(struct perf_event *event) {
>> + return 0;
>> +}
>> +
>> +struct xe_str_attribute {
>> + struct device_attribute attr;
>> + const char *str;
>> +};
>> +
>> +static ssize_t xe_pmu_format_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_str_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>> + return sprintf(buf, "%s\n", eattr->str); }
>> +
>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>> + (&((struct xe_str_attribute[]) { \
>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL),
>> \
>> + .str = _config, } \
>> + })[0].attr.attr)
>> +
>> +static struct attribute *xe_pmu_format_attrs[] = {
>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_format_attr_group = {
>> + .name = "format",
>> + .attrs = xe_pmu_format_attrs,
>> +};
>> +
>> +struct xe_ext_attribute {
>> + struct device_attribute attr;
>> + unsigned long val;
>> +};
>> +
>> +static ssize_t xe_pmu_event_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_ext_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
>> +
>> +static ssize_t cpumask_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
>> +
>> +static DEVICE_ATTR_RO(cpumask);
>> +
>> +static struct attribute *xe_cpumask_attrs[] = {
>> + &dev_attr_cpumask.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>> + .attrs = xe_cpumask_attrs,
>> +};
>> +
>> +#define __event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = false, \
>> +}
>> +
>> +#define __global_event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = true, \
>> +}
>> +
>> +static struct xe_ext_attribute *
>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
>> +config) {
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = xe_pmu_event_show;
>> + attr->val = config;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct perf_pmu_events_attr *
>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>> + const char *str)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = perf_event_sysfs_show;
>> + attr->event_str = str;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct attribute **
>> +create_event_attributes(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + static const struct {
>> + unsigned int counter;
>> + const char *name;
>> + const char *unit;
>> + bool global;
>> + } events[] = {
>> + __global_event(0, "interrupts", NULL),
>> + __event(1, "render-group-busy", "ns"),
>> + __event(2, "copy-group-busy", "ns"),
>> + __event(3, "media-group-busy", "ns"),
>> + __event(4, "any-engine-group-busy", "ns"),
>> + };
>> +
>> + unsigned int count = 0;
>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>> + struct attribute **attr = NULL, **attr_iter;
>> + struct xe_gt *gt;
>> + unsigned int i, j;
>> +
>> + /* Count how many counters we will be exposing. */
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> +
>> + if (!config_status(xe, config))
>> + count++;
>> + }
>> + }
>> +
>> + /* Allocate attribute objects and table. */
>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>> + if (!xe_attr)
>> + goto err_alloc;
>> +
>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>> + if (!pmu_attr)
>> + goto err_alloc;
>> +
>> + /* Max one pointer of each attribute type plus a termination entry.
>> */
>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + goto err_alloc;
>> +
>> + xe_iter = xe_attr;
>> + pmu_iter = pmu_attr;
>> + attr_iter = attr;
>> +
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> + char *str;
>> +
>> + if (config_status(xe, config))
>> + continue;
>> +
>> + if (events[i].global)
>> + str = kstrdup(events[i].name, GFP_KERNEL);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &xe_iter->attr.attr;
>> + xe_iter = add_xe_attr(xe_iter, str, config);
>> +
>> + if (events[i].unit) {
>> + if (events[i].global)
>> + str = kasprintf(GFP_KERNEL,
>> "%s.unit",
>> + events[i].name);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-
>> gt%u.unit",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &pmu_iter->attr.attr;
>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>> + events[i].unit);
>> + }
>> + }
>> + }
>> +
>> + pmu->xe_attr = xe_attr;
>> + pmu->pmu_attr = pmu_attr;
>> +
>> + return attr;
>> +
>> +err:
>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> +err_alloc:
>> + kfree(attr);
>> + kfree(xe_attr);
>> + kfree(pmu_attr);
>> +
>> + return NULL;
>> +}
>> +
>> +static void free_event_attributes(struct xe_pmu *pmu) {
>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>> +
>> + for (; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> + kfree(pmu->events_attr_group.attrs);
>> + kfree(pmu->xe_attr);
>> + kfree(pmu->pmu_attr);
>> +
>> + pmu->events_attr_group.attrs = NULL;
>> + pmu->xe_attr = NULL;
>> + pmu->pmu_attr = NULL;
>> +}
>> +
>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /* Select the first online CPU as a designated reader. */
>> + if (cpumask_empty(&xe_pmu_cpumask))
>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
>> +*node) {
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> + unsigned int target = xe_pmu_target_cpu;
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /*
>> + * Unregistering an instance generates a CPU offline event which we
>> must
>> + * ignore to avoid incorrectly modifying the shared
>> xe_pmu_cpumask.
>> + */
>> + if (pmu->closed)
>> + return 0;
>> +
>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
>> cpu);
>> +
>> + /* Migrate events if there is a valid target */
>> + if (target < nr_cpu_ids) {
>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>> + xe_pmu_target_cpu = target;
>> + }
>> + }
>> +
>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>> + pmu->cpuhp.cpu = target;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>> +
>> +int xe_pmu_init(void)
>> +{
>> + int ret;
>> +
>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> + "perf/x86/intel/xe:online",
>> + xe_pmu_cpu_online,
>> + xe_pmu_cpu_offline);
>> + if (ret < 0)
>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>> + ret);
>> + else
>> + cpuhp_slot = ret;
>> +
>> + return 0;
>> +}
>> +
>> +void xe_pmu_exit(void)
>> +{
>> + if (cpuhp_slot != CPUHP_INVALID)
>> + cpuhp_remove_multi_state(cpuhp_slot);
>> +}
>> +
>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
>> + if (cpuhp_slot == CPUHP_INVALID)
>> + return -EINVAL;
>> +
>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
>> }
>> +
>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
>> +
>> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
>> + struct xe_pmu *pmu = arg;
>> +
>> + if (!pmu->base.event_init)
>> + return;
>> +
>> + /*
>> + * "Disconnect" the PMU callbacks - since all are atomic
>> synchronize_rcu
>> + * ensures all currently executing ones will have exited before we
>> + * proceed with unregistration.
>> + */
>> + pmu->closed = true;
>> + synchronize_rcu();
>> +
>> + xe_pmu_unregister_cpuhp_state(pmu);
>> +
>> + perf_pmu_unregister(&pmu->base);
>> + pmu->base.event_init = NULL;
>> + kfree(pmu->base.attr_groups);
>> + kfree(pmu->name);
>> + free_event_attributes(pmu);
>> +}
>> +
>> +static void init_samples(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + struct xe_gt *gt;
>> + unsigned int i;
>> +
>> + for_each_gt(gt, xe, i)
>> + engine_group_busyness_store(gt);
>> +}
>> +
>> +void xe_pmu_register(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + const struct attribute_group *attr_groups[] = {
>> + &xe_pmu_format_attr_group,
>> + &pmu->events_attr_group,
>> + &xe_pmu_cpumask_attr_group,
>> + NULL
>> + };
>> +
>
> No newline needed here I think.
>
>> + int ret = -ENOMEM;
>> +
>> + spin_lock_init(&pmu->lock);
>> + pmu->cpuhp.cpu = -1;
>> + init_samples(pmu);
>> +
>> + pmu->name = kasprintf(GFP_KERNEL,
>> + "xe_%s",
>> + dev_name(xe->drm.dev));
>> + if (pmu->name)
>> + /* tools/perf reserves colons as special. */
>> + strreplace((char *)pmu->name, ':', '_');
>> +
>
> We can skip checking pmu->name again here.
skipping the below will not catch the error. i can combine them to an if
else.
Thanks,
Aravind.
>
> Thanks,
> Tejas
>> + if (!pmu->name)
>> + goto err;
>> +
>> + pmu->events_attr_group.name = "events";
>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>> + if (!pmu->events_attr_group.attrs)
>> + goto err_name;
>> +
>> + pmu->base.attr_groups = kmemdup(attr_groups,
>> sizeof(attr_groups),
>> + GFP_KERNEL);
>> + if (!pmu->base.attr_groups)
>> + goto err_attr;
>> +
>> + pmu->base.module = THIS_MODULE;
>> + pmu->base.task_ctx_nr = perf_invalid_context;
>> + pmu->base.event_init = xe_pmu_event_init;
>> + pmu->base.add = xe_pmu_event_add;
>> + pmu->base.del = xe_pmu_event_del;
>> + pmu->base.start = xe_pmu_event_start;
>> + pmu->base.stop = xe_pmu_event_stop;
>> + pmu->base.read = xe_pmu_event_read;
>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>> +
>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>> + if (ret)
>> + goto err_groups;
>> +
>> + ret = xe_pmu_register_cpuhp_state(pmu);
>> + if (ret)
>> + goto err_unreg;
>> +
>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
>> pmu);
>> + XE_WARN_ON(ret);
>> +
>> + return;
>> +
>> +err_unreg:
>> + perf_pmu_unregister(&pmu->base);
>> +err_groups:
>> + kfree(pmu->base.attr_groups);
>> +err_attr:
>> + pmu->base.event_init = NULL;
>> + free_event_attributes(pmu);
>> +err_name:
>> + kfree(pmu->name);
>> +err:
>> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>> new file mode 100644 index 000000000000..d3f47f4ab343
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_H_
>> +#define _XE_PMU_H_
>> +
>> +#include "xe_gt_types.h"
>> +#include "xe_pmu_types.h"
>> +
>> +#ifdef CONFIG_PERF_EVENTS
>> +int xe_pmu_init(void);
>> +void xe_pmu_exit(void);
>> +void xe_pmu_register(struct xe_pmu *pmu); void
>> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
>> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
>> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
>> +
>> +#endif
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
>> b/drivers/gpu/drm/xe/xe_pmu_types.h
>> new file mode 100644
>> index 000000000000..e87edd4d6a87
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_TYPES_H_
>> +#define _XE_PMU_TYPES_H_
>> +
>> +#include <linux/perf_event.h>
>> +#include <linux/spinlock_types.h>
>> +#include <uapi/drm/xe_drm.h>
>> +
>> +enum {
>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __XE_NUM_PMU_SAMPLERS
>> +};
>> +
>> +struct xe_pmu_sample {
>> + u64 cur;
>> +};
>> +
>> +#define XE_MAX_GT_PER_TILE 2
>> +
>> +struct xe_pmu {
>> + /**
>> + * @cpuhp: Struct used for CPU hotplug handling.
>> + */
>> + struct {
>> + struct hlist_node node;
>> + unsigned int cpu;
>> + } cpuhp;
>> + /**
>> + * @base: PMU base.
>> + */
>> + struct pmu base;
>> + /**
>> + * @closed: xe is unregistering.
>> + */
>> + bool closed;
>> + /**
>> + * @name: Name as registered with perf core.
>> + */
>> + const char *name;
>> + /**
>> + * @lock: Lock protecting enable mask and ref count handling.
>> + */
>> + spinlock_t lock;
>> + /**
>> + * @sample: Current and previous (raw) counters.
>> + *
>> + * These counters are updated when the device is awake.
>> + *
>> + */
>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
>> __XE_NUM_PMU_SAMPLERS];
>> + /**
>> + * @irq_count: Number of interrupts
>> + *
>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>> + * occasional wraparound easily. It's 32bit after all.
>> + */
>> + unsigned long irq_count;
>> + /**
>> + * @events_attr_group: Device events attribute group.
>> + */
>> + struct attribute_group events_attr_group;
>> + /**
>> + * @xe_attr: Memory block holding device attributes.
>> + */
>> + void *xe_attr;
>> + /**
>> + * @pmu_attr: Memory block holding device attributes.
>> + */
>> + void *pmu_attr;
>> +};
>> +
>> +#endif
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
>> 965cd9527ff1..ed097056f944 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>> __u64 reserved[2];
>> };
>>
>> +/* PMU event config IDs */
>> +
>> +/*
>> + * Top 4 bits of every counter are GT id.
>> + */
>> +#define __XE_PMU_GT_SHIFT (60)
>> +
>> +#define ___XE_PMU_OTHER(gt, x) \
>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>> +
>> +#define XE_PMU_INTERRUPTS(gt)
>> ___XE_PMU_OTHER(gt, 0)
>> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 1)
>> +#define XE_PMU_COPY_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 2)
>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 3)
>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 4)
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> --
>> 2.25.1
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-30 13:53 ` Upadhyay, Tejas
@ 2023-07-04 3:34 ` Ghimiray, Himal Prasad
2023-07-05 4:52 ` Iddamsetty, Aravind
2023-07-04 9:10 ` Upadhyay, Tejas
` (4 subsequent siblings)
6 siblings, 1 reply; 59+ messages in thread
From: Ghimiray, Himal Prasad @ 2023-07-04 3:34 UTC (permalink / raw)
To: Iddamsetty, Aravind, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
Hi Aravind,
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Aravind Iddamsetty
> Sent: 27 June 2023 17:51
> To: intel-xe@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
> <tvrtko.ursulin@intel.com>
> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>
> There are a set of engine group busyness counters provided by HW which
> are perfect fit to be exposed via PMU perf events.
>
> BSPEC: 46559, 46560, 46722, 46729
>
> events can be listed using:
> perf list
> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>
> and can be read using:
>
> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> time counts unit events
> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>
> The pmu base implementation is taken from i915.
>
> v2:
> Store last known value when device is awake return that while the GT is
> suspended and then update the driver copy when read during awake.
>
> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> drivers/gpu/drm/xe/xe_device.c | 2 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt.c | 2 +
> drivers/gpu/drm/xe/xe_irq.c | 22 +
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_pmu.c | 739
> +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> include/uapi/drm/xe_drm.h | 16 +
> 11 files changed, 902 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
> drivers/gpu/drm/xe/xe_pmu_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 081c57fd8632..e52ab795c566 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/skl_universal_plane.o \
> i915-display/skl_watermark.o
>
> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> +
> ifeq ($(CONFIG_ACPI),y)
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_acpi.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..c7d9e4634745 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -285,6 +285,11 @@
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
> XE_REG(0xdb80)
> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE
> XE_REG(0xdba0)
> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> +#define XE_OAG_RENDER_BUSY_FREE
> XE_REG(0xdbdc)
> +
> #define SAMPLER_MODE
> XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
> 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_debugfs_register(xe);
>
> + xe_pmu_register(&xe->pmu);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize,
> xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 0226d44a6af2..3ba99aae92b9 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
> #include "xe_devcoredump_types.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> +#include "xe_pmu.h"
> #include "xe_step_types.h"
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> @@ -332,6 +333,9 @@ struct xe_device {
> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> bool d3cold_allowed;
>
> + /* @pmu: performance monitoring unit */
> + struct xe_pmu pmu;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
> 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index b4ed1e4a3388..cb943fb94ec7 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,6 +27,24 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> + irqreturn_t res)
The res parameter seems redundant, the caller should call xe_pmu_irq_stats
only in case of IRQ_HANDLED. Do we see need to pass this as an argument from caller and
check in this function ?
BR
Himal
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
> +
> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
> u32 val = xe_mmio_read32(mmio, reg);
> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> dg1_intr_enable(xe, false);
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_module.c
> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
> 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -12,6 +12,7 @@
> #include "xe_hw_fence.h"
> #include "xe_module.h"
> #include "xe_pci.h"
> +#include "xe_pmu.h"
> #include "xe_sched_job.h"
>
> bool enable_guc = true;
> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> .init = xe_sched_job_module_init,
> .exit = xe_sched_job_module_exit,
> },
> + {
> + .init = xe_pmu_init,
> + .exit = xe_pmu_exit,
> + },
> {
> .init = xe_register_pci_driver,
> .exit = xe_unregister_pci_driver,
> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> new file mode 100644 index 000000000000..bef1895be9f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> @@ -0,0 +1,739 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <drm/drm_drv.h>
> +#include <drm/drm_managed.h>
> +#include <drm/xe_drm.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt_clock.h"
> +#include "xe_mmio.h"
> +
> +static cpumask_t xe_pmu_cpumask;
> +static unsigned int xe_pmu_target_cpu = -1;
> +
> +static unsigned int config_gt_id(const u64 config) {
> + return config >> __XE_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config) {
> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
> +
> +static unsigned int
> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> +
> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
> +
> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
> +sample) {
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
> +
> +static void
> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
> +val) {
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
> +
> +static int engine_busyness_sample_type(u64 config) {
> + int type = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> + break;
> + }
> +
> + return type;
> +}
> +
> +static void xe_pmu_event_destroy(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> +
> + drm_WARN_ON(&xe->drm, event->parent);
> +
> + drm_dev_put(&xe->drm);
> +}
> +
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
> +
> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + int sample_type = engine_busyness_sample_type(config);
> + struct xe_device *xe = gt->tile->xe;
> + const unsigned int gt_id = gt->info.id;
> + struct xe_pmu *pmu = &xe->pmu;
> + bool device_awake;
> + unsigned long flags;
> + u64 val;
> +
> + /*
> + * found no better way to check if device is awake or not. Before
> + * we suspend we set the submission_state.enabled to false.
> + */
> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> + if (device_awake)
> + val = __engine_group_busyness_read(gt, config);
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + if (device_awake)
> + store_sample(pmu, gt_id, sample_type, val);
> + else
> + val = read_sample(pmu, gt_id, sample_type);
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +
> + return val;
> +}
> +
> +void engine_group_busyness_store(struct xe_gt *gt) {
> + struct xe_pmu *pmu = >->tile->xe->pmu;
> + unsigned int gt_id = gt->info.id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_RENDER_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_COPY_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_MEDIA_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id,
> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> +
> + spin_unlock_irqrestore(&pmu->lock, flags); }
> +
> +static int
> +config_status(struct xe_device *xe, u64 config) {
> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> + unsigned int gt_id = config_gt_id(config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> +
> + if (gt_id > max_gt_id)
> + return -ENOENT;
> +
> + switch (config_counter(config)) {
> + case XE_PMU_INTERRUPTS(0):
> + if (gt_id)
> + return -ENOENT;
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + if (GRAPHICS_VER(xe) < 12)
> + return -ENOENT;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
> XE_GT_TYPE_MEDIA)
> + return -ENOENT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_pmu_event_init(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> + int ret;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* unsupported modes and filters */
> + if (event->attr.sample_period) /* no sampling */
> + return -EINVAL;
> +
> + if (has_branch_stack(event))
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /* only allow running on one cpu at a time */
> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> + return -EINVAL;
> +
> + ret = config_status(xe, event->attr.config);
> + if (ret)
> + return ret;
> +
> + if (!event->parent) {
> + drm_dev_get(&xe->drm);
> + event->destroy = xe_pmu_event_destroy;
> + }
> +
> + return 0;
> +}
> +
> +static u64 __xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + const unsigned int gt_id = config_gt_id(event->attr.config);
> + const u64 config = config_counter(event->attr.config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_INTERRUPTS(0):
> + val = READ_ONCE(pmu->irq_count);
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = engine_group_busyness_read(gt, config);
> + }
> +
> + return val;
> +}
> +
> +static void xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct hw_perf_event *hwc = &event->hw;
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 prev, new;
> +
> + if (pmu->closed) {
> + event->hw.state = PERF_HES_STOPPED;
> + return;
> + }
> +again:
> + prev = local64_read(&hwc->prev_count);
> + new = __xe_pmu_event_read(event);
> +
> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> + goto again;
> +
> + local64_add(new - prev, &event->count); }
> +
> +static void xe_pmu_enable(struct perf_event *event) {
> + /*
> + * Store the current counter value so we can report the correct delta
> + * for all listeners. Even when the event was already enabled and has
> + * an existing non-zero value.
> + */
> + local64_set(&event->hw.prev_count,
> __xe_pmu_event_read(event)); }
> +
> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return;
> +
> + xe_pmu_enable(event);
> + event->hw.state = 0;
> +}
> +
> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
> + if (flags & PERF_EF_UPDATE)
> + xe_pmu_event_read(event);
> +
> + event->hw.state = PERF_HES_STOPPED;
> +}
> +
> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (flags & PERF_EF_START)
> + xe_pmu_event_start(event, flags);
> +
> + return 0;
> +}
> +
> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
> +
> +static int xe_pmu_event_event_idx(struct perf_event *event) {
> + return 0;
> +}
> +
> +struct xe_str_attribute {
> + struct device_attribute attr;
> + const char *str;
> +};
> +
> +static ssize_t xe_pmu_format_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_str_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_str_attribute, attr);
> + return sprintf(buf, "%s\n", eattr->str); }
> +
> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> + (&((struct xe_str_attribute[]) { \
> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show,
> NULL), \
> + .str = _config, } \
> + })[0].attr.attr)
> +
> +static struct attribute *xe_pmu_format_attrs[] = {
> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_format_attr_group = {
> + .name = "format",
> + .attrs = xe_pmu_format_attrs,
> +};
> +
> +struct xe_ext_attribute {
> + struct device_attribute attr;
> + unsigned long val;
> +};
> +
> +static ssize_t xe_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
> +
> +static ssize_t cpumask_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
> +
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *xe_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> + .attrs = xe_cpumask_attrs,
> +};
> +
> +#define __event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = false, \
> +}
> +
> +#define __global_event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = true, \
> +}
> +
> +static struct xe_ext_attribute *
> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
> +config) {
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = xe_pmu_event_show;
> + attr->val = config;
> +
> + return ++attr;
> +}
> +
> +static struct perf_pmu_events_attr *
> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> + const char *str)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = perf_event_sysfs_show;
> + attr->event_str = str;
> +
> + return ++attr;
> +}
> +
> +static struct attribute **
> +create_event_attributes(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + static const struct {
> + unsigned int counter;
> + const char *name;
> + const char *unit;
> + bool global;
> + } events[] = {
> + __global_event(0, "interrupts", NULL),
> + __event(1, "render-group-busy", "ns"),
> + __event(2, "copy-group-busy", "ns"),
> + __event(3, "media-group-busy", "ns"),
> + __event(4, "any-engine-group-busy", "ns"),
> + };
> +
> + unsigned int count = 0;
> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> + struct attribute **attr = NULL, **attr_iter;
> + struct xe_gt *gt;
> + unsigned int i, j;
> +
> + /* Count how many counters we will be exposing. */
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> +
> + if (!config_status(xe, config))
> + count++;
> + }
> + }
> +
> + /* Allocate attribute objects and table. */
> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> + if (!xe_attr)
> + goto err_alloc;
> +
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> + if (!pmu_attr)
> + goto err_alloc;
> +
> + /* Max one pointer of each attribute type plus a termination entry.
> */
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + goto err_alloc;
> +
> + xe_iter = xe_attr;
> + pmu_iter = pmu_attr;
> + attr_iter = attr;
> +
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> + char *str;
> +
> + if (config_status(xe, config))
> + continue;
> +
> + if (events[i].global)
> + str = kstrdup(events[i].name, GFP_KERNEL);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &xe_iter->attr.attr;
> + xe_iter = add_xe_attr(xe_iter, str, config);
> +
> + if (events[i].unit) {
> + if (events[i].global)
> + str = kasprintf(GFP_KERNEL,
> "%s.unit",
> + events[i].name);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-
> gt%u.unit",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &pmu_iter->attr.attr;
> + pmu_iter = add_pmu_attr(pmu_iter, str,
> + events[i].unit);
> + }
> + }
> + }
> +
> + pmu->xe_attr = xe_attr;
> + pmu->pmu_attr = pmu_attr;
> +
> + return attr;
> +
> +err:
> + for (attr_iter = attr; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> +err_alloc:
> + kfree(attr);
> + kfree(xe_attr);
> + kfree(pmu_attr);
> +
> + return NULL;
> +}
> +
> +static void free_event_attributes(struct xe_pmu *pmu) {
> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> +
> + for (; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> + kfree(pmu->events_attr_group.attrs);
> + kfree(pmu->xe_attr);
> + kfree(pmu->pmu_attr);
> +
> + pmu->events_attr_group.attrs = NULL;
> + pmu->xe_attr = NULL;
> + pmu->pmu_attr = NULL;
> +}
> +
> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /* Select the first online CPU as a designated reader. */
> + if (cpumask_empty(&xe_pmu_cpumask))
> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> +
> + return 0;
> +}
> +
> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
> +*node) {
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> + unsigned int target = xe_pmu_target_cpu;
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /*
> + * Unregistering an instance generates a CPU offline event which we
> must
> + * ignore to avoid incorrectly modifying the shared
> xe_pmu_cpumask.
> + */
> + if (pmu->closed)
> + return 0;
> +
> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
> cpu);
> +
> + /* Migrate events if there is a valid target */
> + if (target < nr_cpu_ids) {
> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> + xe_pmu_target_cpu = target;
> + }
> + }
> +
> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> + pmu->cpuhp.cpu = target;
> + }
> +
> + return 0;
> +}
> +
> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> +
> +int xe_pmu_init(void)
> +{
> + int ret;
> +
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "perf/x86/intel/xe:online",
> + xe_pmu_cpu_online,
> + xe_pmu_cpu_offline);
> + if (ret < 0)
> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> + ret);
> + else
> + cpuhp_slot = ret;
> +
> + return 0;
> +}
> +
> +void xe_pmu_exit(void)
> +{
> + if (cpuhp_slot != CPUHP_INVALID)
> + cpuhp_remove_multi_state(cpuhp_slot);
> +}
> +
> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
> + if (cpuhp_slot == CPUHP_INVALID)
> + return -EINVAL;
> +
> + return cpuhp_state_add_instance(cpuhp_slot, &pmu-
> >cpuhp.node); }
> +
> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
> +
> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
> + struct xe_pmu *pmu = arg;
> +
> + if (!pmu->base.event_init)
> + return;
> +
> + /*
> + * "Disconnect" the PMU callbacks - since all are atomic
> synchronize_rcu
> + * ensures all currently executing ones will have exited before we
> + * proceed with unregistration.
> + */
> + pmu->closed = true;
> + synchronize_rcu();
> +
> + xe_pmu_unregister_cpuhp_state(pmu);
> +
> + perf_pmu_unregister(&pmu->base);
> + pmu->base.event_init = NULL;
> + kfree(pmu->base.attr_groups);
> + kfree(pmu->name);
> + free_event_attributes(pmu);
> +}
> +
> +static void init_samples(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + struct xe_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, xe, i)
> + engine_group_busyness_store(gt);
> +}
> +
> +void xe_pmu_register(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + const struct attribute_group *attr_groups[] = {
> + &xe_pmu_format_attr_group,
> + &pmu->events_attr_group,
> + &xe_pmu_cpumask_attr_group,
> + NULL
> + };
> +
> + int ret = -ENOMEM;
> +
> + spin_lock_init(&pmu->lock);
> + pmu->cpuhp.cpu = -1;
> + init_samples(pmu);
> +
> + pmu->name = kasprintf(GFP_KERNEL,
> + "xe_%s",
> + dev_name(xe->drm.dev));
> + if (pmu->name)
> + /* tools/perf reserves colons as special. */
> + strreplace((char *)pmu->name, ':', '_');
> +
> + if (!pmu->name)
> + goto err;
> +
> + pmu->events_attr_group.name = "events";
> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> + if (!pmu->events_attr_group.attrs)
> + goto err_name;
> +
> + pmu->base.attr_groups = kmemdup(attr_groups,
> sizeof(attr_groups),
> + GFP_KERNEL);
> + if (!pmu->base.attr_groups)
> + goto err_attr;
> +
> + pmu->base.module = THIS_MODULE;
> + pmu->base.task_ctx_nr = perf_invalid_context;
> + pmu->base.event_init = xe_pmu_event_init;
> + pmu->base.add = xe_pmu_event_add;
> + pmu->base.del = xe_pmu_event_del;
> + pmu->base.start = xe_pmu_event_start;
> + pmu->base.stop = xe_pmu_event_stop;
> + pmu->base.read = xe_pmu_event_read;
> + pmu->base.event_idx = xe_pmu_event_event_idx;
> +
> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> + if (ret)
> + goto err_groups;
> +
> + ret = xe_pmu_register_cpuhp_state(pmu);
> + if (ret)
> + goto err_unreg;
> +
> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
> pmu);
> + XE_WARN_ON(ret);
> +
> + return;
> +
> +err_unreg:
> + perf_pmu_unregister(&pmu->base);
> +err_groups:
> + kfree(pmu->base.attr_groups);
> +err_attr:
> + pmu->base.event_init = NULL;
> + free_event_attributes(pmu);
> +err_name:
> + kfree(pmu->name);
> +err:
> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> new file mode 100644 index 000000000000..d3f47f4ab343
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_H_
> +#define _XE_PMU_H_
> +
> +#include "xe_gt_types.h"
> +#include "xe_pmu_types.h"
> +
> +#ifdef CONFIG_PERF_EVENTS
> +int xe_pmu_init(void);
> +void xe_pmu_exit(void);
> +void xe_pmu_register(struct xe_pmu *pmu); void
> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
> b/drivers/gpu/drm/xe/xe_pmu_types.h
> new file mode 100644
> index 000000000000..e87edd4d6a87
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_TYPES_H_
> +#define _XE_PMU_TYPES_H_
> +
> +#include <linux/perf_event.h>
> +#include <linux/spinlock_types.h>
> +#include <uapi/drm/xe_drm.h>
> +
> +enum {
> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __XE_SAMPLE_COPY_GROUP_BUSY,
> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __XE_NUM_PMU_SAMPLERS
> +};
> +
> +struct xe_pmu_sample {
> + u64 cur;
> +};
> +
> +#define XE_MAX_GT_PER_TILE 2
> +
> +struct xe_pmu {
> + /**
> + * @cpuhp: Struct used for CPU hotplug handling.
> + */
> + struct {
> + struct hlist_node node;
> + unsigned int cpu;
> + } cpuhp;
> + /**
> + * @base: PMU base.
> + */
> + struct pmu base;
> + /**
> + * @closed: xe is unregistering.
> + */
> + bool closed;
> + /**
> + * @name: Name as registered with perf core.
> + */
> + const char *name;
> + /**
> + * @lock: Lock protecting enable mask and ref count handling.
> + */
> + spinlock_t lock;
> + /**
> + * @sample: Current and previous (raw) counters.
> + *
> + * These counters are updated when the device is awake.
> + *
> + */
> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
> __XE_NUM_PMU_SAMPLERS];
> + /**
> + * @irq_count: Number of interrupts
> + *
> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> + * occasional wraparound easily. It's 32bit after all.
> + */
> + unsigned long irq_count;
> + /**
> + * @events_attr_group: Device events attribute group.
> + */
> + struct attribute_group events_attr_group;
> + /**
> + * @xe_attr: Memory block holding device attributes.
> + */
> + void *xe_attr;
> + /**
> + * @pmu_attr: Memory block holding device attributes.
> + */
> + void *pmu_attr;
> +};
> +
> +#endif
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> 965cd9527ff1..ed097056f944 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> __u64 reserved[2];
> };
>
> +/* PMU event config IDs */
> +
> +/*
> + * Top 4 bits of every counter are GT id.
> + */
> +#define __XE_PMU_GT_SHIFT (60)
> +
> +#define ___XE_PMU_OTHER(gt, x) \
> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> +
> +#define XE_PMU_INTERRUPTS(gt)
> ___XE_PMU_OTHER(gt, 0)
> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 1)
> +#define XE_PMU_COPY_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 2)
> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 3)
> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 4)
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.25.1
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-04 3:34 ` Ghimiray, Himal Prasad
@ 2023-07-05 4:52 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-05 4:52 UTC (permalink / raw)
To: Ghimiray, Himal Prasad, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
On 04-07-2023 09:04, Ghimiray, Himal Prasad wrote:
> Hi Aravind,
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> Aravind Iddamsetty
>> Sent: 27 June 2023 17:51
>> To: intel-xe@lists.freedesktop.org
>> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
>> <tvrtko.ursulin@intel.com>
>> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>>
>> There are a set of engine group busyness counters provided by HW which
>> are perfect fit to be exposed via PMU perf events.
>>
>> BSPEC: 46559, 46560, 46722, 46729
>>
>> events can be listed using:
>> perf list
>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>
>> and can be read using:
>>
>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>> time counts unit events
>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>
>> The pmu base implementation is taken from i915.
>>
>> v2:
>> Store last known value when device is awake return that while the GT is
>> suspended and then update the driver copy when read during awake.
>>
>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>> drivers/gpu/drm/xe/xe_device.c | 2 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>> drivers/gpu/drm/xe/xe_module.c | 5 +
>> drivers/gpu/drm/xe/xe_pmu.c | 739
>> +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>> include/uapi/drm/xe_drm.h | 16 +
>> 11 files changed, 902 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
>> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
>> drivers/gpu/drm/xe/xe_pmu_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 081c57fd8632..e52ab795c566 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/skl_universal_plane.o \
>> i915-display/skl_watermark.o
>>
>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>> +
>> ifeq ($(CONFIG_ACPI),y)
>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_acpi.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3f664011eaea..c7d9e4634745 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -285,6 +285,11 @@
>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>
>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
>> XE_REG(0xdb80)
>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE
>> XE_REG(0xdba0)
>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>> +#define XE_OAG_RENDER_BUSY_FREE
>> XE_REG(0xdbdc)
>> +
>> #define SAMPLER_MODE
>> XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
>> #define ENABLE_SMALLPL REG_BIT(15)
>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_debugfs_register(xe);
>>
>> + xe_pmu_register(&xe->pmu);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize,
>> xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>> b/drivers/gpu/drm/xe/xe_device_types.h
>> index 0226d44a6af2..3ba99aae92b9 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -15,6 +15,7 @@
>> #include "xe_devcoredump_types.h"
>> #include "xe_gt_types.h"
>> #include "xe_platform_types.h"
>> +#include "xe_pmu.h"
>> #include "xe_step_types.h"
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> @@ -332,6 +333,9 @@ struct xe_device {
>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>> bool d3cold_allowed;
>>
>> + /* @pmu: performance monitoring unit */
>> + struct xe_pmu pmu;
>> +
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
>> 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>>
>> + engine_group_busyness_store(gt);
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index b4ed1e4a3388..cb943fb94ec7 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,6 +27,24 @@
>> #define IIR(offset) XE_REG(offset + 0x8)
>> #define IER(offset) XE_REG(offset + 0xc)
>>
>> +/*
>> + * Interrupt statistic for PMU. Increments the counter only if the
>> + * interrupt originated from the GPU so interrupts from a device which
>> + * shares the interrupt line are not accounted.
>> + */
>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>> + irqreturn_t res)
> The res parameter seems redundant, the caller should call xe_pmu_irq_stats
> only in case of IRQ_HANDLED. Do we see need to pass this as an argument from caller and
> check in this function ?
ya makes sense, as it is being invoked just before IRQ_HANDLED.
Thanks,
Aravind.
>
> BR
> Himal
>> +{
>> + if (unlikely(res != IRQ_HANDLED))
>> + return;
>> +
>> + /*
>> + * A clever compiler translates that into INC. A not so clever one
>> + * should at least prevent store tearing.
>> + */
>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
>> +
>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
>> u32 val = xe_mmio_read32(mmio, reg);
>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>>
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> dg1_intr_enable(xe, false);
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_module.c
>> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_fence.h"
>> #include "xe_module.h"
>> #include "xe_pci.h"
>> +#include "xe_pmu.h"
>> #include "xe_sched_job.h"
>>
>> bool enable_guc = true;
>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>> .init = xe_sched_job_module_init,
>> .exit = xe_sched_job_module_exit,
>> },
>> + {
>> + .init = xe_pmu_init,
>> + .exit = xe_pmu_exit,
>> + },
>> {
>> .init = xe_register_pci_driver,
>> .exit = xe_unregister_pci_driver,
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> new file mode 100644 index 000000000000..bef1895be9f7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -0,0 +1,739 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_drv.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "regs/xe_gt_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt_clock.h"
>> +#include "xe_mmio.h"
>> +
>> +static cpumask_t xe_pmu_cpumask;
>> +static unsigned int xe_pmu_target_cpu = -1;
>> +
>> +static unsigned int config_gt_id(const u64 config) {
>> + return config >> __XE_PMU_GT_SHIFT;
>> +}
>> +
>> +static u64 config_counter(const u64 config) {
>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
>> +
>> +static unsigned int
>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>> +
>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>> +
>> + return idx;
>> +}
>> +
>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
>> +sample) {
>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
>> +
>> +static void
>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
>> +val) {
>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
>> +
>> +static int engine_busyness_sample_type(u64 config) {
>> + int type = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>> + break;
>> + }
>> +
>> + return type;
>> +}
>> +
>> +static void xe_pmu_event_destroy(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> +
>> + drm_WARN_ON(&xe->drm, event->parent);
>> +
>> + drm_dev_put(&xe->drm);
>> +}
>> +
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
>> +
>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + int sample_type = engine_busyness_sample_type(config);
>> + struct xe_device *xe = gt->tile->xe;
>> + const unsigned int gt_id = gt->info.id;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + bool device_awake;
>> + unsigned long flags;
>> + u64 val;
>> +
>> + /*
>> + * found no better way to check if device is awake or not. Before
>> + * we suspend we set the submission_state.enabled to false.
>> + */
>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>> + if (device_awake)
>> + val = __engine_group_busyness_read(gt, config);
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + if (device_awake)
>> + store_sample(pmu, gt_id, sample_type, val);
>> + else
>> + val = read_sample(pmu, gt_id, sample_type);
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +
>> + return val;
>> +}
>> +
>> +void engine_group_busyness_store(struct xe_gt *gt) {
>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>> + unsigned int gt_id = gt->info.id;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_RENDER_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_COPY_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_MEDIA_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id,
>> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags); }
>> +
>> +static int
>> +config_status(struct xe_device *xe, u64 config) {
>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>> + unsigned int gt_id = config_gt_id(config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> +
>> + if (gt_id > max_gt_id)
>> + return -ENOENT;
>> +
>> + switch (config_counter(config)) {
>> + case XE_PMU_INTERRUPTS(0):
>> + if (gt_id)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + if (GRAPHICS_VER(xe) < 12)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
>> XE_GT_TYPE_MEDIA)
>> + return -ENOENT;
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_event_init(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + int ret;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* unsupported modes and filters */
>> + if (event->attr.sample_period) /* no sampling */
>> + return -EINVAL;
>> +
>> + if (has_branch_stack(event))
>> + return -EOPNOTSUPP;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /* only allow running on one cpu at a time */
>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>> + return -EINVAL;
>> +
>> + ret = config_status(xe, event->attr.config);
>> + if (ret)
>> + return ret;
>> +
>> + if (!event->parent) {
>> + drm_dev_get(&xe->drm);
>> + event->destroy = xe_pmu_event_destroy;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static u64 __xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>> + const u64 config = config_counter(event->attr.config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_INTERRUPTS(0):
>> + val = READ_ONCE(pmu->irq_count);
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = engine_group_busyness_read(gt, config);
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static void xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 prev, new;
>> +
>> + if (pmu->closed) {
>> + event->hw.state = PERF_HES_STOPPED;
>> + return;
>> + }
>> +again:
>> + prev = local64_read(&hwc->prev_count);
>> + new = __xe_pmu_event_read(event);
>> +
>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>> + goto again;
>> +
>> + local64_add(new - prev, &event->count); }
>> +
>> +static void xe_pmu_enable(struct perf_event *event) {
>> + /*
>> + * Store the current counter value so we can report the correct delta
>> + * for all listeners. Even when the event was already enabled and has
>> + * an existing non-zero value.
>> + */
>> + local64_set(&event->hw.prev_count,
>> __xe_pmu_event_read(event)); }
>> +
>> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return;
>> +
>> + xe_pmu_enable(event);
>> + event->hw.state = 0;
>> +}
>> +
>> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
>> + if (flags & PERF_EF_UPDATE)
>> + xe_pmu_event_read(event);
>> +
>> + event->hw.state = PERF_HES_STOPPED;
>> +}
>> +
>> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (flags & PERF_EF_START)
>> + xe_pmu_event_start(event, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
>> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
>> +
>> +static int xe_pmu_event_event_idx(struct perf_event *event) {
>> + return 0;
>> +}
>> +
>> +struct xe_str_attribute {
>> + struct device_attribute attr;
>> + const char *str;
>> +};
>> +
>> +static ssize_t xe_pmu_format_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_str_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>> + return sprintf(buf, "%s\n", eattr->str); }
>> +
>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>> + (&((struct xe_str_attribute[]) { \
>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show,
>> NULL), \
>> + .str = _config, } \
>> + })[0].attr.attr)
>> +
>> +static struct attribute *xe_pmu_format_attrs[] = {
>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_format_attr_group = {
>> + .name = "format",
>> + .attrs = xe_pmu_format_attrs,
>> +};
>> +
>> +struct xe_ext_attribute {
>> + struct device_attribute attr;
>> + unsigned long val;
>> +};
>> +
>> +static ssize_t xe_pmu_event_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_ext_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
>> +
>> +static ssize_t cpumask_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
>> +
>> +static DEVICE_ATTR_RO(cpumask);
>> +
>> +static struct attribute *xe_cpumask_attrs[] = {
>> + &dev_attr_cpumask.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>> + .attrs = xe_cpumask_attrs,
>> +};
>> +
>> +#define __event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = false, \
>> +}
>> +
>> +#define __global_event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = true, \
>> +}
>> +
>> +static struct xe_ext_attribute *
>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
>> +config) {
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = xe_pmu_event_show;
>> + attr->val = config;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct perf_pmu_events_attr *
>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>> + const char *str)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = perf_event_sysfs_show;
>> + attr->event_str = str;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct attribute **
>> +create_event_attributes(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + static const struct {
>> + unsigned int counter;
>> + const char *name;
>> + const char *unit;
>> + bool global;
>> + } events[] = {
>> + __global_event(0, "interrupts", NULL),
>> + __event(1, "render-group-busy", "ns"),
>> + __event(2, "copy-group-busy", "ns"),
>> + __event(3, "media-group-busy", "ns"),
>> + __event(4, "any-engine-group-busy", "ns"),
>> + };
>> +
>> + unsigned int count = 0;
>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>> + struct attribute **attr = NULL, **attr_iter;
>> + struct xe_gt *gt;
>> + unsigned int i, j;
>> +
>> + /* Count how many counters we will be exposing. */
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> +
>> + if (!config_status(xe, config))
>> + count++;
>> + }
>> + }
>> +
>> + /* Allocate attribute objects and table. */
>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>> + if (!xe_attr)
>> + goto err_alloc;
>> +
>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>> + if (!pmu_attr)
>> + goto err_alloc;
>> +
>> + /* Max one pointer of each attribute type plus a termination entry.
>> */
>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + goto err_alloc;
>> +
>> + xe_iter = xe_attr;
>> + pmu_iter = pmu_attr;
>> + attr_iter = attr;
>> +
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> + char *str;
>> +
>> + if (config_status(xe, config))
>> + continue;
>> +
>> + if (events[i].global)
>> + str = kstrdup(events[i].name, GFP_KERNEL);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &xe_iter->attr.attr;
>> + xe_iter = add_xe_attr(xe_iter, str, config);
>> +
>> + if (events[i].unit) {
>> + if (events[i].global)
>> + str = kasprintf(GFP_KERNEL,
>> "%s.unit",
>> + events[i].name);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-
>> gt%u.unit",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &pmu_iter->attr.attr;
>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>> + events[i].unit);
>> + }
>> + }
>> + }
>> +
>> + pmu->xe_attr = xe_attr;
>> + pmu->pmu_attr = pmu_attr;
>> +
>> + return attr;
>> +
>> +err:
>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> +err_alloc:
>> + kfree(attr);
>> + kfree(xe_attr);
>> + kfree(pmu_attr);
>> +
>> + return NULL;
>> +}
>> +
>> +static void free_event_attributes(struct xe_pmu *pmu) {
>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>> +
>> + for (; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> + kfree(pmu->events_attr_group.attrs);
>> + kfree(pmu->xe_attr);
>> + kfree(pmu->pmu_attr);
>> +
>> + pmu->events_attr_group.attrs = NULL;
>> + pmu->xe_attr = NULL;
>> + pmu->pmu_attr = NULL;
>> +}
>> +
>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /* Select the first online CPU as a designated reader. */
>> + if (cpumask_empty(&xe_pmu_cpumask))
>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
>> +*node) {
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> + unsigned int target = xe_pmu_target_cpu;
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /*
>> + * Unregistering an instance generates a CPU offline event which we
>> must
>> + * ignore to avoid incorrectly modifying the shared
>> xe_pmu_cpumask.
>> + */
>> + if (pmu->closed)
>> + return 0;
>> +
>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
>> cpu);
>> +
>> + /* Migrate events if there is a valid target */
>> + if (target < nr_cpu_ids) {
>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>> + xe_pmu_target_cpu = target;
>> + }
>> + }
>> +
>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>> + pmu->cpuhp.cpu = target;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>> +
>> +int xe_pmu_init(void)
>> +{
>> + int ret;
>> +
>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> + "perf/x86/intel/xe:online",
>> + xe_pmu_cpu_online,
>> + xe_pmu_cpu_offline);
>> + if (ret < 0)
>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>> + ret);
>> + else
>> + cpuhp_slot = ret;
>> +
>> + return 0;
>> +}
>> +
>> +void xe_pmu_exit(void)
>> +{
>> + if (cpuhp_slot != CPUHP_INVALID)
>> + cpuhp_remove_multi_state(cpuhp_slot);
>> +}
>> +
>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
>> + if (cpuhp_slot == CPUHP_INVALID)
>> + return -EINVAL;
>> +
>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu-
>>> cpuhp.node); }
>> +
>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
>> +
>> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
>> + struct xe_pmu *pmu = arg;
>> +
>> + if (!pmu->base.event_init)
>> + return;
>> +
>> + /*
>> + * "Disconnect" the PMU callbacks - since all are atomic
>> synchronize_rcu
>> + * ensures all currently executing ones will have exited before we
>> + * proceed with unregistration.
>> + */
>> + pmu->closed = true;
>> + synchronize_rcu();
>> +
>> + xe_pmu_unregister_cpuhp_state(pmu);
>> +
>> + perf_pmu_unregister(&pmu->base);
>> + pmu->base.event_init = NULL;
>> + kfree(pmu->base.attr_groups);
>> + kfree(pmu->name);
>> + free_event_attributes(pmu);
>> +}
>> +
>> +static void init_samples(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + struct xe_gt *gt;
>> + unsigned int i;
>> +
>> + for_each_gt(gt, xe, i)
>> + engine_group_busyness_store(gt);
>> +}
>> +
>> +void xe_pmu_register(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + const struct attribute_group *attr_groups[] = {
>> + &xe_pmu_format_attr_group,
>> + &pmu->events_attr_group,
>> + &xe_pmu_cpumask_attr_group,
>> + NULL
>> + };
>> +
>> + int ret = -ENOMEM;
>> +
>> + spin_lock_init(&pmu->lock);
>> + pmu->cpuhp.cpu = -1;
>> + init_samples(pmu);
>> +
>> + pmu->name = kasprintf(GFP_KERNEL,
>> + "xe_%s",
>> + dev_name(xe->drm.dev));
>> + if (pmu->name)
>> + /* tools/perf reserves colons as special. */
>> + strreplace((char *)pmu->name, ':', '_');
>> +
>> + if (!pmu->name)
>> + goto err;
>> +
>> + pmu->events_attr_group.name = "events";
>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>> + if (!pmu->events_attr_group.attrs)
>> + goto err_name;
>> +
>> + pmu->base.attr_groups = kmemdup(attr_groups,
>> sizeof(attr_groups),
>> + GFP_KERNEL);
>> + if (!pmu->base.attr_groups)
>> + goto err_attr;
>> +
>> + pmu->base.module = THIS_MODULE;
>> + pmu->base.task_ctx_nr = perf_invalid_context;
>> + pmu->base.event_init = xe_pmu_event_init;
>> + pmu->base.add = xe_pmu_event_add;
>> + pmu->base.del = xe_pmu_event_del;
>> + pmu->base.start = xe_pmu_event_start;
>> + pmu->base.stop = xe_pmu_event_stop;
>> + pmu->base.read = xe_pmu_event_read;
>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>> +
>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>> + if (ret)
>> + goto err_groups;
>> +
>> + ret = xe_pmu_register_cpuhp_state(pmu);
>> + if (ret)
>> + goto err_unreg;
>> +
>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
>> pmu);
>> + XE_WARN_ON(ret);
>> +
>> + return;
>> +
>> +err_unreg:
>> + perf_pmu_unregister(&pmu->base);
>> +err_groups:
>> + kfree(pmu->base.attr_groups);
>> +err_attr:
>> + pmu->base.event_init = NULL;
>> + free_event_attributes(pmu);
>> +err_name:
>> + kfree(pmu->name);
>> +err:
>> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>> new file mode 100644 index 000000000000..d3f47f4ab343
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_H_
>> +#define _XE_PMU_H_
>> +
>> +#include "xe_gt_types.h"
>> +#include "xe_pmu_types.h"
>> +
>> +#ifdef CONFIG_PERF_EVENTS
>> +int xe_pmu_init(void);
>> +void xe_pmu_exit(void);
>> +void xe_pmu_register(struct xe_pmu *pmu); void
>> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
>> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
>> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
>> +
>> +#endif
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
>> b/drivers/gpu/drm/xe/xe_pmu_types.h
>> new file mode 100644
>> index 000000000000..e87edd4d6a87
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_TYPES_H_
>> +#define _XE_PMU_TYPES_H_
>> +
>> +#include <linux/perf_event.h>
>> +#include <linux/spinlock_types.h>
>> +#include <uapi/drm/xe_drm.h>
>> +
>> +enum {
>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __XE_NUM_PMU_SAMPLERS
>> +};
>> +
>> +struct xe_pmu_sample {
>> + u64 cur;
>> +};
>> +
>> +#define XE_MAX_GT_PER_TILE 2
>> +
>> +struct xe_pmu {
>> + /**
>> + * @cpuhp: Struct used for CPU hotplug handling.
>> + */
>> + struct {
>> + struct hlist_node node;
>> + unsigned int cpu;
>> + } cpuhp;
>> + /**
>> + * @base: PMU base.
>> + */
>> + struct pmu base;
>> + /**
>> + * @closed: xe is unregistering.
>> + */
>> + bool closed;
>> + /**
>> + * @name: Name as registered with perf core.
>> + */
>> + const char *name;
>> + /**
>> + * @lock: Lock protecting enable mask and ref count handling.
>> + */
>> + spinlock_t lock;
>> + /**
>> + * @sample: Current and previous (raw) counters.
>> + *
>> + * These counters are updated when the device is awake.
>> + *
>> + */
>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
>> __XE_NUM_PMU_SAMPLERS];
>> + /**
>> + * @irq_count: Number of interrupts
>> + *
>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>> + * occasional wraparound easily. It's 32bit after all.
>> + */
>> + unsigned long irq_count;
>> + /**
>> + * @events_attr_group: Device events attribute group.
>> + */
>> + struct attribute_group events_attr_group;
>> + /**
>> + * @xe_attr: Memory block holding device attributes.
>> + */
>> + void *xe_attr;
>> + /**
>> + * @pmu_attr: Memory block holding device attributes.
>> + */
>> + void *pmu_attr;
>> +};
>> +
>> +#endif
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
>> 965cd9527ff1..ed097056f944 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>> __u64 reserved[2];
>> };
>>
>> +/* PMU event config IDs */
>> +
>> +/*
>> + * Top 4 bits of every counter are GT id.
>> + */
>> +#define __XE_PMU_GT_SHIFT (60)
>> +
>> +#define ___XE_PMU_OTHER(gt, x) \
>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>> +
>> +#define XE_PMU_INTERRUPTS(gt)
>> ___XE_PMU_OTHER(gt, 0)
>> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 1)
>> +#define XE_PMU_COPY_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 2)
>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 3)
>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 4)
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> --
>> 2.25.1
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
2023-06-30 13:53 ` Upadhyay, Tejas
2023-07-04 3:34 ` Ghimiray, Himal Prasad
@ 2023-07-04 9:10 ` Upadhyay, Tejas
2023-07-05 4:42 ` Iddamsetty, Aravind
2023-07-06 2:39 ` Dixit, Ashutosh
` (3 subsequent siblings)
6 siblings, 1 reply; 59+ messages in thread
From: Upadhyay, Tejas @ 2023-07-04 9:10 UTC (permalink / raw)
To: Iddamsetty, Aravind, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Aravind Iddamsetty
> Sent: Tuesday, June 27, 2023 5:51 PM
> To: intel-xe@lists.freedesktop.org
> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
> <tvrtko.ursulin@intel.com>
> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>
> There are a set of engine group busyness counters provided by HW which
> are perfect fit to be exposed via PMU perf events.
>
> BSPEC: 46559, 46560, 46722, 46729
>
> events can be listed using:
> perf list
> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>
> and can be read using:
>
> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> time counts unit events
> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>
> The pmu base implementation is taken from i915.
>
> v2:
> Store last known value when device is awake return that while the GT is
> suspended and then update the driver copy when read during awake.
>
> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> drivers/gpu/drm/xe/xe_device.c | 2 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt.c | 2 +
> drivers/gpu/drm/xe/xe_irq.c | 22 +
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> include/uapi/drm/xe_drm.h | 16 +
> 11 files changed, 902 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
> drivers/gpu/drm/xe/xe_pmu_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 081c57fd8632..e52ab795c566 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/skl_universal_plane.o \
> i915-display/skl_watermark.o
>
> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> +
> ifeq ($(CONFIG_ACPI),y)
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_acpi.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..c7d9e4634745 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -285,6 +285,11 @@
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
> XE_REG(0xdb80)
> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> +
> #define SAMPLER_MODE XE_REG_MCR(0xe18c,
> XE_REG_OPTION_MASKED)
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
> 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_debugfs_register(xe);
>
> + xe_pmu_register(&xe->pmu);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 0226d44a6af2..3ba99aae92b9 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
> #include "xe_devcoredump_types.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> +#include "xe_pmu.h"
> #include "xe_step_types.h"
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> @@ -332,6 +333,9 @@ struct xe_device {
> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> bool d3cold_allowed;
>
> + /* @pmu: performance monitoring unit */
/** @pmu: performance monitoring unit */
> + struct xe_pmu pmu;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
> 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index b4ed1e4a3388..cb943fb94ec7 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,6 +27,24 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> + irqreturn_t res)
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
> +
> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
> u32 val = xe_mmio_read32(mmio, reg);
> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> dg1_intr_enable(xe, false);
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_module.c
> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
> 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -12,6 +12,7 @@
> #include "xe_hw_fence.h"
> #include "xe_module.h"
> #include "xe_pci.h"
> +#include "xe_pmu.h"
> #include "xe_sched_job.h"
>
> bool enable_guc = true;
> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> .init = xe_sched_job_module_init,
> .exit = xe_sched_job_module_exit,
> },
> + {
> + .init = xe_pmu_init,
> + .exit = xe_pmu_exit,
> + },
> {
> .init = xe_register_pci_driver,
> .exit = xe_unregister_pci_driver,
> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> new file mode 100644 index 000000000000..bef1895be9f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> @@ -0,0 +1,739 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <drm/drm_drv.h>
> +#include <drm/drm_managed.h>
> +#include <drm/xe_drm.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt_clock.h"
> +#include "xe_mmio.h"
> +
> +static cpumask_t xe_pmu_cpumask;
> +static unsigned int xe_pmu_target_cpu = -1;
> +
> +static unsigned int config_gt_id(const u64 config) {
> + return config >> __XE_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config) {
> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
> +
> +static unsigned int
> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> +
> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
> +
> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
> +sample) {
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
> +
> +static void
> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
> +val) {
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
> +
> +static int engine_busyness_sample_type(u64 config) {
> + int type = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> + break;
> + }
> +
> + return type;
> +}
> +
> +static void xe_pmu_event_destroy(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> +
> + drm_WARN_ON(&xe->drm, event->parent);
> +
> + drm_dev_put(&xe->drm);
> +}
> +
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt,
> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
> +
> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
> + int sample_type = engine_busyness_sample_type(config);
> + struct xe_device *xe = gt->tile->xe;
> + const unsigned int gt_id = gt->info.id;
> + struct xe_pmu *pmu = &xe->pmu;
> + bool device_awake;
> + unsigned long flags;
> + u64 val;
Many places Christmas tree order for variable declaration group not followed. Please apply wherever applicable.
> +
> + /*
> + * found no better way to check if device is awake or not. Before
> + * we suspend we set the submission_state.enabled to false.
> + */
> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> + if (device_awake)
> + val = __engine_group_busyness_read(gt, config);
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + if (device_awake)
> + store_sample(pmu, gt_id, sample_type, val);
> + else
> + val = read_sample(pmu, gt_id, sample_type);
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +
> + return val;
> +}
> +
> +void engine_group_busyness_store(struct xe_gt *gt) {
> + struct xe_pmu *pmu = >->tile->xe->pmu;
> + unsigned int gt_id = gt->info.id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_RENDER_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_COPY_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> XE_PMU_MEDIA_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id,
> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __engine_group_busyness_read(gt,
> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> +
> + spin_unlock_irqrestore(&pmu->lock, flags); }
> +
> +static int
> +config_status(struct xe_device *xe, u64 config) {
> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> + unsigned int gt_id = config_gt_id(config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> +
> + if (gt_id > max_gt_id)
> + return -ENOENT;
> +
> + switch (config_counter(config)) {
> + case XE_PMU_INTERRUPTS(0):
> + if (gt_id)
> + return -ENOENT;
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + if (GRAPHICS_VER(xe) < 12)
> + return -ENOENT;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
> XE_GT_TYPE_MEDIA)
> + return -ENOENT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_pmu_event_init(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> + int ret;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* unsupported modes and filters */
> + if (event->attr.sample_period) /* no sampling */
> + return -EINVAL;
> +
> + if (has_branch_stack(event))
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /* only allow running on one cpu at a time */
> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> + return -EINVAL;
> +
> + ret = config_status(xe, event->attr.config);
> + if (ret)
> + return ret;
> +
> + if (!event->parent) {
> + drm_dev_get(&xe->drm);
> + event->destroy = xe_pmu_event_destroy;
> + }
> +
> + return 0;
> +}
> +
> +static u64 __xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + const unsigned int gt_id = config_gt_id(event->attr.config);
> + const u64 config = config_counter(event->attr.config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_INTERRUPTS(0):
> + val = READ_ONCE(pmu->irq_count);
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = engine_group_busyness_read(gt, config);
> + }
Do you need to handle default case here?
Also, if possible can you please think of breaking up this into small patches. Its huge patch to review. Split it only if it makes sense.
Thanks,
Tejas
> +
> + return val;
> +}
> +
> +static void xe_pmu_event_read(struct perf_event *event) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct hw_perf_event *hwc = &event->hw;
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 prev, new;
> +
> + if (pmu->closed) {
> + event->hw.state = PERF_HES_STOPPED;
> + return;
> + }
> +again:
> + prev = local64_read(&hwc->prev_count);
> + new = __xe_pmu_event_read(event);
> +
> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> + goto again;
> +
> + local64_add(new - prev, &event->count); }
> +
> +static void xe_pmu_enable(struct perf_event *event) {
> + /*
> + * Store the current counter value so we can report the correct delta
> + * for all listeners. Even when the event was already enabled and has
> + * an existing non-zero value.
> + */
> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> }
> +
> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return;
> +
> + xe_pmu_enable(event);
> + event->hw.state = 0;
> +}
> +
> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
> + if (flags & PERF_EF_UPDATE)
> + xe_pmu_event_read(event);
> +
> + event->hw.state = PERF_HES_STOPPED;
> +}
> +
> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (flags & PERF_EF_START)
> + xe_pmu_event_start(event, flags);
> +
> + return 0;
> +}
> +
> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
> +
> +static int xe_pmu_event_event_idx(struct perf_event *event) {
> + return 0;
> +}
> +
> +struct xe_str_attribute {
> + struct device_attribute attr;
> + const char *str;
> +};
> +
> +static ssize_t xe_pmu_format_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_str_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_str_attribute, attr);
> + return sprintf(buf, "%s\n", eattr->str); }
> +
> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> + (&((struct xe_str_attribute[]) { \
> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL),
> \
> + .str = _config, } \
> + })[0].attr.attr)
> +
> +static struct attribute *xe_pmu_format_attrs[] = {
> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_format_attr_group = {
> + .name = "format",
> + .attrs = xe_pmu_format_attrs,
> +};
> +
> +struct xe_ext_attribute {
> + struct device_attribute attr;
> + unsigned long val;
> +};
> +
> +static ssize_t xe_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct xe_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
> +
> +static ssize_t cpumask_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
> +
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *xe_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> + .attrs = xe_cpumask_attrs,
> +};
> +
> +#define __event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = false, \
> +}
> +
> +#define __global_event(__counter, __name, __unit) \ { \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = true, \
> +}
> +
> +static struct xe_ext_attribute *
> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
> +config) {
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = xe_pmu_event_show;
> + attr->val = config;
> +
> + return ++attr;
> +}
> +
> +static struct perf_pmu_events_attr *
> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> + const char *str)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = perf_event_sysfs_show;
> + attr->event_str = str;
> +
> + return ++attr;
> +}
> +
> +static struct attribute **
> +create_event_attributes(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + static const struct {
> + unsigned int counter;
> + const char *name;
> + const char *unit;
> + bool global;
> + } events[] = {
> + __global_event(0, "interrupts", NULL),
> + __event(1, "render-group-busy", "ns"),
> + __event(2, "copy-group-busy", "ns"),
> + __event(3, "media-group-busy", "ns"),
> + __event(4, "any-engine-group-busy", "ns"),
> + };
> +
> + unsigned int count = 0;
> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> + struct attribute **attr = NULL, **attr_iter;
> + struct xe_gt *gt;
> + unsigned int i, j;
> +
> + /* Count how many counters we will be exposing. */
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> +
> + if (!config_status(xe, config))
> + count++;
> + }
> + }
> +
> + /* Allocate attribute objects and table. */
> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> + if (!xe_attr)
> + goto err_alloc;
> +
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> + if (!pmu_attr)
> + goto err_alloc;
> +
> + /* Max one pointer of each attribute type plus a termination entry.
> */
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + goto err_alloc;
> +
> + xe_iter = xe_attr;
> + pmu_iter = pmu_attr;
> + attr_iter = attr;
> +
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j,
> events[i].counter);
> + char *str;
> +
> + if (config_status(xe, config))
> + continue;
> +
> + if (events[i].global)
> + str = kstrdup(events[i].name, GFP_KERNEL);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &xe_iter->attr.attr;
> + xe_iter = add_xe_attr(xe_iter, str, config);
> +
> + if (events[i].unit) {
> + if (events[i].global)
> + str = kasprintf(GFP_KERNEL,
> "%s.unit",
> + events[i].name);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-
> gt%u.unit",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &pmu_iter->attr.attr;
> + pmu_iter = add_pmu_attr(pmu_iter, str,
> + events[i].unit);
> + }
> + }
> + }
> +
> + pmu->xe_attr = xe_attr;
> + pmu->pmu_attr = pmu_attr;
> +
> + return attr;
> +
> +err:
> + for (attr_iter = attr; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> +err_alloc:
> + kfree(attr);
> + kfree(xe_attr);
> + kfree(pmu_attr);
> +
> + return NULL;
> +}
> +
> +static void free_event_attributes(struct xe_pmu *pmu) {
> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> +
> + for (; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> + kfree(pmu->events_attr_group.attrs);
> + kfree(pmu->xe_attr);
> + kfree(pmu->pmu_attr);
> +
> + pmu->events_attr_group.attrs = NULL;
> + pmu->xe_attr = NULL;
> + pmu->pmu_attr = NULL;
> +}
> +
> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /* Select the first online CPU as a designated reader. */
> + if (cpumask_empty(&xe_pmu_cpumask))
> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> +
> + return 0;
> +}
> +
> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
> +*node) {
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
> cpuhp.node);
> + unsigned int target = xe_pmu_target_cpu;
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /*
> + * Unregistering an instance generates a CPU offline event which we
> must
> + * ignore to avoid incorrectly modifying the shared
> xe_pmu_cpumask.
> + */
> + if (pmu->closed)
> + return 0;
> +
> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
> cpu);
> +
> + /* Migrate events if there is a valid target */
> + if (target < nr_cpu_ids) {
> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> + xe_pmu_target_cpu = target;
> + }
> + }
> +
> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> + pmu->cpuhp.cpu = target;
> + }
> +
> + return 0;
> +}
> +
> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> +
> +int xe_pmu_init(void)
> +{
> + int ret;
> +
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "perf/x86/intel/xe:online",
> + xe_pmu_cpu_online,
> + xe_pmu_cpu_offline);
> + if (ret < 0)
> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> + ret);
> + else
> + cpuhp_slot = ret;
> +
> + return 0;
> +}
> +
> +void xe_pmu_exit(void)
> +{
> + if (cpuhp_slot != CPUHP_INVALID)
> + cpuhp_remove_multi_state(cpuhp_slot);
> +}
> +
> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
> + if (cpuhp_slot == CPUHP_INVALID)
> + return -EINVAL;
> +
> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> }
> +
> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
> +
> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
> + struct xe_pmu *pmu = arg;
> +
> + if (!pmu->base.event_init)
> + return;
> +
> + /*
> + * "Disconnect" the PMU callbacks - since all are atomic
> synchronize_rcu
> + * ensures all currently executing ones will have exited before we
> + * proceed with unregistration.
> + */
> + pmu->closed = true;
> + synchronize_rcu();
> +
> + xe_pmu_unregister_cpuhp_state(pmu);
> +
> + perf_pmu_unregister(&pmu->base);
> + pmu->base.event_init = NULL;
> + kfree(pmu->base.attr_groups);
> + kfree(pmu->name);
> + free_event_attributes(pmu);
> +}
> +
> +static void init_samples(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + struct xe_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, xe, i)
> + engine_group_busyness_store(gt);
> +}
> +
> +void xe_pmu_register(struct xe_pmu *pmu) {
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + const struct attribute_group *attr_groups[] = {
> + &xe_pmu_format_attr_group,
> + &pmu->events_attr_group,
> + &xe_pmu_cpumask_attr_group,
> + NULL
> + };
> +
> + int ret = -ENOMEM;
> +
> + spin_lock_init(&pmu->lock);
> + pmu->cpuhp.cpu = -1;
> + init_samples(pmu);
> +
> + pmu->name = kasprintf(GFP_KERNEL,
> + "xe_%s",
> + dev_name(xe->drm.dev));
> + if (pmu->name)
> + /* tools/perf reserves colons as special. */
> + strreplace((char *)pmu->name, ':', '_');
> +
> + if (!pmu->name)
> + goto err;
> +
> + pmu->events_attr_group.name = "events";
> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> + if (!pmu->events_attr_group.attrs)
> + goto err_name;
> +
> + pmu->base.attr_groups = kmemdup(attr_groups,
> sizeof(attr_groups),
> + GFP_KERNEL);
> + if (!pmu->base.attr_groups)
> + goto err_attr;
> +
> + pmu->base.module = THIS_MODULE;
> + pmu->base.task_ctx_nr = perf_invalid_context;
> + pmu->base.event_init = xe_pmu_event_init;
> + pmu->base.add = xe_pmu_event_add;
> + pmu->base.del = xe_pmu_event_del;
> + pmu->base.start = xe_pmu_event_start;
> + pmu->base.stop = xe_pmu_event_stop;
> + pmu->base.read = xe_pmu_event_read;
> + pmu->base.event_idx = xe_pmu_event_event_idx;
> +
> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> + if (ret)
> + goto err_groups;
> +
> + ret = xe_pmu_register_cpuhp_state(pmu);
> + if (ret)
> + goto err_unreg;
> +
> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
> pmu);
> + XE_WARN_ON(ret);
> +
> + return;
> +
> +err_unreg:
> + perf_pmu_unregister(&pmu->base);
> +err_groups:
> + kfree(pmu->base.attr_groups);
> +err_attr:
> + pmu->base.event_init = NULL;
> + free_event_attributes(pmu);
> +err_name:
> + kfree(pmu->name);
> +err:
> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> new file mode 100644 index 000000000000..d3f47f4ab343
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_H_
> +#define _XE_PMU_H_
> +
> +#include "xe_gt_types.h"
> +#include "xe_pmu_types.h"
> +
> +#ifdef CONFIG_PERF_EVENTS
> +int xe_pmu_init(void);
> +void xe_pmu_exit(void);
> +void xe_pmu_register(struct xe_pmu *pmu); void
> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
> b/drivers/gpu/drm/xe/xe_pmu_types.h
> new file mode 100644
> index 000000000000..e87edd4d6a87
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_TYPES_H_
> +#define _XE_PMU_TYPES_H_
> +
> +#include <linux/perf_event.h>
> +#include <linux/spinlock_types.h>
> +#include <uapi/drm/xe_drm.h>
> +
> +enum {
> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __XE_SAMPLE_COPY_GROUP_BUSY,
> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __XE_NUM_PMU_SAMPLERS
> +};
> +
> +struct xe_pmu_sample {
> + u64 cur;
> +};
> +
> +#define XE_MAX_GT_PER_TILE 2
> +
> +struct xe_pmu {
> + /**
> + * @cpuhp: Struct used for CPU hotplug handling.
> + */
> + struct {
> + struct hlist_node node;
> + unsigned int cpu;
> + } cpuhp;
> + /**
> + * @base: PMU base.
> + */
> + struct pmu base;
> + /**
> + * @closed: xe is unregistering.
> + */
> + bool closed;
> + /**
> + * @name: Name as registered with perf core.
> + */
> + const char *name;
> + /**
> + * @lock: Lock protecting enable mask and ref count handling.
> + */
> + spinlock_t lock;
> + /**
> + * @sample: Current and previous (raw) counters.
> + *
> + * These counters are updated when the device is awake.
> + *
> + */
> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
> __XE_NUM_PMU_SAMPLERS];
> + /**
> + * @irq_count: Number of interrupts
> + *
> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> + * occasional wraparound easily. It's 32bit after all.
> + */
> + unsigned long irq_count;
> + /**
> + * @events_attr_group: Device events attribute group.
> + */
> + struct attribute_group events_attr_group;
> + /**
> + * @xe_attr: Memory block holding device attributes.
> + */
> + void *xe_attr;
> + /**
> + * @pmu_attr: Memory block holding device attributes.
> + */
> + void *pmu_attr;
> +};
> +
> +#endif
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> 965cd9527ff1..ed097056f944 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> __u64 reserved[2];
> };
>
> +/* PMU event config IDs */
> +
> +/*
> + * Top 4 bits of every counter are GT id.
> + */
> +#define __XE_PMU_GT_SHIFT (60)
> +
> +#define ___XE_PMU_OTHER(gt, x) \
> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> +
> +#define XE_PMU_INTERRUPTS(gt)
> ___XE_PMU_OTHER(gt, 0)
> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 1)
> +#define XE_PMU_COPY_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 2)
> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 3)
> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
> ___XE_PMU_OTHER(gt, 4)
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.25.1
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-04 9:10 ` Upadhyay, Tejas
@ 2023-07-05 4:42 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-05 4:42 UTC (permalink / raw)
To: Upadhyay, Tejas, intel-xe@lists.freedesktop.org
Cc: Bommu, Krishnaiah, Ursulin, Tvrtko
On 04-07-2023 14:40, Upadhyay, Tejas wrote:
>
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> Aravind Iddamsetty
>> Sent: Tuesday, June 27, 2023 5:51 PM
>> To: intel-xe@lists.freedesktop.org
>> Cc: Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko
>> <tvrtko.ursulin@intel.com>
>> Subject: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>>
>> There are a set of engine group busyness counters provided by HW which
>> are perfect fit to be exposed via PMU perf events.
>>
>> BSPEC: 46559, 46560, 46722, 46729
>>
>> events can be listed using:
>> perf list
>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>
>> and can be read using:
>>
>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>> time counts unit events
>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>
>> The pmu base implementation is taken from i915.
>>
>> v2:
>> Store last known value when device is awake return that while the GT is
>> suspended and then update the driver copy when read during awake.
>>
>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>> drivers/gpu/drm/xe/xe_device.c | 2 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>> drivers/gpu/drm/xe/xe_module.c | 5 +
>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>> include/uapi/drm/xe_drm.h | 16 +
>> 11 files changed, 902 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c create mode 100644
>> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
>> drivers/gpu/drm/xe/xe_pmu_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 081c57fd8632..e52ab795c566 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/skl_universal_plane.o \
>> i915-display/skl_watermark.o
>>
>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>> +
>> ifeq ($(CONFIG_ACPI),y)
>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_acpi.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3f664011eaea..c7d9e4634745 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -285,6 +285,11 @@
>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>
>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE
>> XE_REG(0xdb80)
>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>> +
>> #define SAMPLER_MODE XE_REG_MCR(0xe18c,
>> XE_REG_OPTION_MASKED)
>> #define ENABLE_SMALLPL REG_BIT(15)
>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_debugfs_register(xe);
>>
>> + xe_pmu_register(&xe->pmu);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>> b/drivers/gpu/drm/xe/xe_device_types.h
>> index 0226d44a6af2..3ba99aae92b9 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -15,6 +15,7 @@
>> #include "xe_devcoredump_types.h"
>> #include "xe_gt_types.h"
>> #include "xe_platform_types.h"
>> +#include "xe_pmu.h"
>> #include "xe_step_types.h"
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> @@ -332,6 +333,9 @@ struct xe_device {
>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>> bool d3cold_allowed;
>>
>> + /* @pmu: performance monitoring unit */
>
> /** @pmu: performance monitoring unit */
right I noticed this in CI it complained.
>
>> + struct xe_pmu pmu;
>> +
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
>> 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>>
>> + engine_group_busyness_store(gt);
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index b4ed1e4a3388..cb943fb94ec7 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,6 +27,24 @@
>> #define IIR(offset) XE_REG(offset + 0x8)
>> #define IER(offset) XE_REG(offset + 0xc)
>>
>> +/*
>> + * Interrupt statistic for PMU. Increments the counter only if the
>> + * interrupt originated from the GPU so interrupts from a device which
>> + * shares the interrupt line are not accounted.
>> + */
>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>> + irqreturn_t res)
>> +{
>> + if (unlikely(res != IRQ_HANDLED))
>> + return;
>> +
>> + /*
>> + * A clever compiler translates that into INC. A not so clever one
>> + * should at least prevent store tearing.
>> + */
>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
>> +
>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) {
>> u32 val = xe_mmio_read32(mmio, reg);
>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>>
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> dg1_intr_enable(xe, false);
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_module.c
>> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_fence.h"
>> #include "xe_module.h"
>> #include "xe_pci.h"
>> +#include "xe_pmu.h"
>> #include "xe_sched_job.h"
>>
>> bool enable_guc = true;
>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>> .init = xe_sched_job_module_init,
>> .exit = xe_sched_job_module_exit,
>> },
>> + {
>> + .init = xe_pmu_init,
>> + .exit = xe_pmu_exit,
>> + },
>> {
>> .init = xe_register_pci_driver,
>> .exit = xe_unregister_pci_driver,
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> new file mode 100644 index 000000000000..bef1895be9f7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -0,0 +1,739 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_drv.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "regs/xe_gt_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt_clock.h"
>> +#include "xe_mmio.h"
>> +
>> +static cpumask_t xe_pmu_cpumask;
>> +static unsigned int xe_pmu_target_cpu = -1;
>> +
>> +static unsigned int config_gt_id(const u64 config) {
>> + return config >> __XE_PMU_GT_SHIFT;
>> +}
>> +
>> +static u64 config_counter(const u64 config) {
>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
>> +
>> +static unsigned int
>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample) {
>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>> +
>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>> +
>> + return idx;
>> +}
>> +
>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
>> +sample) {
>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
>> +
>> +static void
>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
>> +val) {
>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
>> +
>> +static int engine_busyness_sample_type(u64 config) {
>> + int type = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>> + break;
>> + }
>> +
>> + return type;
>> +}
>> +
>> +static void xe_pmu_event_destroy(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> +
>> + drm_WARN_ON(&xe->drm, event->parent);
>> +
>> + drm_dev_put(&xe->drm);
>> +}
>> +
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt,
>> XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
>> +
>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config) {
>> + int sample_type = engine_busyness_sample_type(config);
>> + struct xe_device *xe = gt->tile->xe;
>> + const unsigned int gt_id = gt->info.id;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + bool device_awake;
>> + unsigned long flags;
>> + u64 val;
>
> Many places Christmas tree order for variable declaration group not followed. Please apply wherever applicable.
sure will take care.
>
>> +
>> + /*
>> + * found no better way to check if device is awake or not. Before
>> + * we suspend we set the submission_state.enabled to false.
>> + */
>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>> + if (device_awake)
>> + val = __engine_group_busyness_read(gt, config);
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + if (device_awake)
>> + store_sample(pmu, gt_id, sample_type, val);
>> + else
>> + val = read_sample(pmu, gt_id, sample_type);
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +
>> + return val;
>> +}
>> +
>> +void engine_group_busyness_store(struct xe_gt *gt) {
>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>> + unsigned int gt_id = gt->info.id;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_RENDER_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_COPY_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_MEDIA_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id,
>> __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags); }
>> +
>> +static int
>> +config_status(struct xe_device *xe, u64 config) {
>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>> + unsigned int gt_id = config_gt_id(config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> +
>> + if (gt_id > max_gt_id)
>> + return -ENOENT;
>> +
>> + switch (config_counter(config)) {
>> + case XE_PMU_INTERRUPTS(0):
>> + if (gt_id)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + if (GRAPHICS_VER(xe) < 12)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + if (MEDIA_VER(xe) >= 13 && gt->info.type !=
>> XE_GT_TYPE_MEDIA)
>> + return -ENOENT;
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_event_init(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + int ret;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* unsupported modes and filters */
>> + if (event->attr.sample_period) /* no sampling */
>> + return -EINVAL;
>> +
>> + if (has_branch_stack(event))
>> + return -EOPNOTSUPP;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /* only allow running on one cpu at a time */
>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>> + return -EINVAL;
>> +
>> + ret = config_status(xe, event->attr.config);
>> + if (ret)
>> + return ret;
>> +
>> + if (!event->parent) {
>> + drm_dev_get(&xe->drm);
>> + event->destroy = xe_pmu_event_destroy;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static u64 __xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>> + const u64 config = config_counter(event->attr.config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_INTERRUPTS(0):
>> + val = READ_ONCE(pmu->irq_count);
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = engine_group_busyness_read(gt, config);
>> + }
>
> Do you need to handle default case here?
ideally i could but an unknown config will not even reach this far, but
to satisfy the symantics of switch i'll put default.
>
> Also, if possible can you please think of breaking up this into small patches. Its huge patch to review. Split it only if it makes sense.
well if i break most of the routines will be dummy in one of the
patches. But let me see what I can do when i spin the next version.
Thanks,
Aravind.
>
> Thanks,
> Tejas
>> +
>> + return val;
>> +}
>> +
>> +static void xe_pmu_event_read(struct perf_event *event) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 prev, new;
>> +
>> + if (pmu->closed) {
>> + event->hw.state = PERF_HES_STOPPED;
>> + return;
>> + }
>> +again:
>> + prev = local64_read(&hwc->prev_count);
>> + new = __xe_pmu_event_read(event);
>> +
>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>> + goto again;
>> +
>> + local64_add(new - prev, &event->count); }
>> +
>> +static void xe_pmu_enable(struct perf_event *event) {
>> + /*
>> + * Store the current counter value so we can report the correct delta
>> + * for all listeners. Even when the event was already enabled and has
>> + * an existing non-zero value.
>> + */
>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>> }
>> +
>> +static void xe_pmu_event_start(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return;
>> +
>> + xe_pmu_enable(event);
>> + event->hw.state = 0;
>> +}
>> +
>> +static void xe_pmu_event_stop(struct perf_event *event, int flags) {
>> + if (flags & PERF_EF_UPDATE)
>> + xe_pmu_event_read(event);
>> +
>> + event->hw.state = PERF_HES_STOPPED;
>> +}
>> +
>> +static int xe_pmu_event_add(struct perf_event *event, int flags) {
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (flags & PERF_EF_START)
>> + xe_pmu_event_start(event, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_pmu_event_del(struct perf_event *event, int flags) {
>> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
>> +
>> +static int xe_pmu_event_event_idx(struct perf_event *event) {
>> + return 0;
>> +}
>> +
>> +struct xe_str_attribute {
>> + struct device_attribute attr;
>> + const char *str;
>> +};
>> +
>> +static ssize_t xe_pmu_format_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_str_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>> + return sprintf(buf, "%s\n", eattr->str); }
>> +
>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>> + (&((struct xe_str_attribute[]) { \
>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL),
>> \
>> + .str = _config, } \
>> + })[0].attr.attr)
>> +
>> +static struct attribute *xe_pmu_format_attrs[] = {
>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_format_attr_group = {
>> + .name = "format",
>> + .attrs = xe_pmu_format_attrs,
>> +};
>> +
>> +struct xe_ext_attribute {
>> + struct device_attribute attr;
>> + unsigned long val;
>> +};
>> +
>> +static ssize_t xe_pmu_event_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + struct xe_ext_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
>> +
>> +static ssize_t cpumask_show(struct device *dev,
>> + struct device_attribute *attr, char *buf) {
>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
>> +
>> +static DEVICE_ATTR_RO(cpumask);
>> +
>> +static struct attribute *xe_cpumask_attrs[] = {
>> + &dev_attr_cpumask.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>> + .attrs = xe_cpumask_attrs,
>> +};
>> +
>> +#define __event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = false, \
>> +}
>> +
>> +#define __global_event(__counter, __name, __unit) \ { \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = true, \
>> +}
>> +
>> +static struct xe_ext_attribute *
>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
>> +config) {
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = xe_pmu_event_show;
>> + attr->val = config;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct perf_pmu_events_attr *
>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>> + const char *str)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = perf_event_sysfs_show;
>> + attr->event_str = str;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct attribute **
>> +create_event_attributes(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + static const struct {
>> + unsigned int counter;
>> + const char *name;
>> + const char *unit;
>> + bool global;
>> + } events[] = {
>> + __global_event(0, "interrupts", NULL),
>> + __event(1, "render-group-busy", "ns"),
>> + __event(2, "copy-group-busy", "ns"),
>> + __event(3, "media-group-busy", "ns"),
>> + __event(4, "any-engine-group-busy", "ns"),
>> + };
>> +
>> + unsigned int count = 0;
>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>> + struct attribute **attr = NULL, **attr_iter;
>> + struct xe_gt *gt;
>> + unsigned int i, j;
>> +
>> + /* Count how many counters we will be exposing. */
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> +
>> + if (!config_status(xe, config))
>> + count++;
>> + }
>> + }
>> +
>> + /* Allocate attribute objects and table. */
>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>> + if (!xe_attr)
>> + goto err_alloc;
>> +
>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>> + if (!pmu_attr)
>> + goto err_alloc;
>> +
>> + /* Max one pointer of each attribute type plus a termination entry.
>> */
>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + goto err_alloc;
>> +
>> + xe_iter = xe_attr;
>> + pmu_iter = pmu_attr;
>> + attr_iter = attr;
>> +
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j,
>> events[i].counter);
>> + char *str;
>> +
>> + if (config_status(xe, config))
>> + continue;
>> +
>> + if (events[i].global)
>> + str = kstrdup(events[i].name, GFP_KERNEL);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &xe_iter->attr.attr;
>> + xe_iter = add_xe_attr(xe_iter, str, config);
>> +
>> + if (events[i].unit) {
>> + if (events[i].global)
>> + str = kasprintf(GFP_KERNEL,
>> "%s.unit",
>> + events[i].name);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-
>> gt%u.unit",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &pmu_iter->attr.attr;
>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>> + events[i].unit);
>> + }
>> + }
>> + }
>> +
>> + pmu->xe_attr = xe_attr;
>> + pmu->pmu_attr = pmu_attr;
>> +
>> + return attr;
>> +
>> +err:
>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> +err_alloc:
>> + kfree(attr);
>> + kfree(xe_attr);
>> + kfree(pmu_attr);
>> +
>> + return NULL;
>> +}
>> +
>> +static void free_event_attributes(struct xe_pmu *pmu) {
>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>> +
>> + for (; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> + kfree(pmu->events_attr_group.attrs);
>> + kfree(pmu->xe_attr);
>> + kfree(pmu->pmu_attr);
>> +
>> + pmu->events_attr_group.attrs = NULL;
>> + pmu->xe_attr = NULL;
>> + pmu->pmu_attr = NULL;
>> +}
>> +
>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /* Select the first online CPU as a designated reader. */
>> + if (cpumask_empty(&xe_pmu_cpumask))
>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
>> +*node) {
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> + unsigned int target = xe_pmu_target_cpu;
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /*
>> + * Unregistering an instance generates a CPU offline event which we
>> must
>> + * ignore to avoid incorrectly modifying the shared
>> xe_pmu_cpumask.
>> + */
>> + if (pmu->closed)
>> + return 0;
>> +
>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>> + target = cpumask_any_but(topology_sibling_cpumask(cpu),
>> cpu);
>> +
>> + /* Migrate events if there is a valid target */
>> + if (target < nr_cpu_ids) {
>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>> + xe_pmu_target_cpu = target;
>> + }
>> + }
>> +
>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>> + pmu->cpuhp.cpu = target;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>> +
>> +int xe_pmu_init(void)
>> +{
>> + int ret;
>> +
>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> + "perf/x86/intel/xe:online",
>> + xe_pmu_cpu_online,
>> + xe_pmu_cpu_offline);
>> + if (ret < 0)
>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>> + ret);
>> + else
>> + cpuhp_slot = ret;
>> +
>> + return 0;
>> +}
>> +
>> +void xe_pmu_exit(void)
>> +{
>> + if (cpuhp_slot != CPUHP_INVALID)
>> + cpuhp_remove_multi_state(cpuhp_slot);
>> +}
>> +
>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
>> + if (cpuhp_slot == CPUHP_INVALID)
>> + return -EINVAL;
>> +
>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
>> }
>> +
>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
>> +
>> +static void xe_pmu_unregister(struct drm_device *device, void *arg) {
>> + struct xe_pmu *pmu = arg;
>> +
>> + if (!pmu->base.event_init)
>> + return;
>> +
>> + /*
>> + * "Disconnect" the PMU callbacks - since all are atomic
>> synchronize_rcu
>> + * ensures all currently executing ones will have exited before we
>> + * proceed with unregistration.
>> + */
>> + pmu->closed = true;
>> + synchronize_rcu();
>> +
>> + xe_pmu_unregister_cpuhp_state(pmu);
>> +
>> + perf_pmu_unregister(&pmu->base);
>> + pmu->base.event_init = NULL;
>> + kfree(pmu->base.attr_groups);
>> + kfree(pmu->name);
>> + free_event_attributes(pmu);
>> +}
>> +
>> +static void init_samples(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + struct xe_gt *gt;
>> + unsigned int i;
>> +
>> + for_each_gt(gt, xe, i)
>> + engine_group_busyness_store(gt);
>> +}
>> +
>> +void xe_pmu_register(struct xe_pmu *pmu) {
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + const struct attribute_group *attr_groups[] = {
>> + &xe_pmu_format_attr_group,
>> + &pmu->events_attr_group,
>> + &xe_pmu_cpumask_attr_group,
>> + NULL
>> + };
>> +
>> + int ret = -ENOMEM;
>> +
>> + spin_lock_init(&pmu->lock);
>> + pmu->cpuhp.cpu = -1;
>> + init_samples(pmu);
>> +
>> + pmu->name = kasprintf(GFP_KERNEL,
>> + "xe_%s",
>> + dev_name(xe->drm.dev));
>> + if (pmu->name)
>> + /* tools/perf reserves colons as special. */
>> + strreplace((char *)pmu->name, ':', '_');
>> +
>> + if (!pmu->name)
>> + goto err;
>> +
>> + pmu->events_attr_group.name = "events";
>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>> + if (!pmu->events_attr_group.attrs)
>> + goto err_name;
>> +
>> + pmu->base.attr_groups = kmemdup(attr_groups,
>> sizeof(attr_groups),
>> + GFP_KERNEL);
>> + if (!pmu->base.attr_groups)
>> + goto err_attr;
>> +
>> + pmu->base.module = THIS_MODULE;
>> + pmu->base.task_ctx_nr = perf_invalid_context;
>> + pmu->base.event_init = xe_pmu_event_init;
>> + pmu->base.add = xe_pmu_event_add;
>> + pmu->base.del = xe_pmu_event_del;
>> + pmu->base.start = xe_pmu_event_start;
>> + pmu->base.stop = xe_pmu_event_stop;
>> + pmu->base.read = xe_pmu_event_read;
>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>> +
>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>> + if (ret)
>> + goto err_groups;
>> +
>> + ret = xe_pmu_register_cpuhp_state(pmu);
>> + if (ret)
>> + goto err_unreg;
>> +
>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister,
>> pmu);
>> + XE_WARN_ON(ret);
>> +
>> + return;
>> +
>> +err_unreg:
>> + perf_pmu_unregister(&pmu->base);
>> +err_groups:
>> + kfree(pmu->base.attr_groups);
>> +err_attr:
>> + pmu->base.event_init = NULL;
>> + free_event_attributes(pmu);
>> +err_name:
>> + kfree(pmu->name);
>> +err:
>> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>> new file mode 100644 index 000000000000..d3f47f4ab343
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_H_
>> +#define _XE_PMU_H_
>> +
>> +#include "xe_gt_types.h"
>> +#include "xe_pmu_types.h"
>> +
>> +#ifdef CONFIG_PERF_EVENTS
>> +int xe_pmu_init(void);
>> +void xe_pmu_exit(void);
>> +void xe_pmu_register(struct xe_pmu *pmu); void
>> +engine_group_busyness_store(struct xe_gt *gt); #else static inline int
>> +xe_pmu_init(void) { return 0; } static inline void xe_pmu_exit(void) {}
>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {} static inline
>> +void engine_group_busyness_store(struct xe_gt *gt) {} #endif
>> +
>> +#endif
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
>> b/drivers/gpu/drm/xe/xe_pmu_types.h
>> new file mode 100644
>> index 000000000000..e87edd4d6a87
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_TYPES_H_
>> +#define _XE_PMU_TYPES_H_
>> +
>> +#include <linux/perf_event.h>
>> +#include <linux/spinlock_types.h>
>> +#include <uapi/drm/xe_drm.h>
>> +
>> +enum {
>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __XE_NUM_PMU_SAMPLERS
>> +};
>> +
>> +struct xe_pmu_sample {
>> + u64 cur;
>> +};
>> +
>> +#define XE_MAX_GT_PER_TILE 2
>> +
>> +struct xe_pmu {
>> + /**
>> + * @cpuhp: Struct used for CPU hotplug handling.
>> + */
>> + struct {
>> + struct hlist_node node;
>> + unsigned int cpu;
>> + } cpuhp;
>> + /**
>> + * @base: PMU base.
>> + */
>> + struct pmu base;
>> + /**
>> + * @closed: xe is unregistering.
>> + */
>> + bool closed;
>> + /**
>> + * @name: Name as registered with perf core.
>> + */
>> + const char *name;
>> + /**
>> + * @lock: Lock protecting enable mask and ref count handling.
>> + */
>> + spinlock_t lock;
>> + /**
>> + * @sample: Current and previous (raw) counters.
>> + *
>> + * These counters are updated when the device is awake.
>> + *
>> + */
>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
>> __XE_NUM_PMU_SAMPLERS];
>> + /**
>> + * @irq_count: Number of interrupts
>> + *
>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>> + * occasional wraparound easily. It's 32bit after all.
>> + */
>> + unsigned long irq_count;
>> + /**
>> + * @events_attr_group: Device events attribute group.
>> + */
>> + struct attribute_group events_attr_group;
>> + /**
>> + * @xe_attr: Memory block holding device attributes.
>> + */
>> + void *xe_attr;
>> + /**
>> + * @pmu_attr: Memory block holding device attributes.
>> + */
>> + void *pmu_attr;
>> +};
>> +
>> +#endif
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
>> 965cd9527ff1..ed097056f944 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>> __u64 reserved[2];
>> };
>>
>> +/* PMU event config IDs */
>> +
>> +/*
>> + * Top 4 bits of every counter are GT id.
>> + */
>> +#define __XE_PMU_GT_SHIFT (60)
>> +
>> +#define ___XE_PMU_OTHER(gt, x) \
>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>> +
>> +#define XE_PMU_INTERRUPTS(gt)
>> ___XE_PMU_OTHER(gt, 0)
>> +#define XE_PMU_RENDER_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 1)
>> +#define XE_PMU_COPY_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 2)
>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 3)
>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt)
>> ___XE_PMU_OTHER(gt, 4)
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> --
>> 2.25.1
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
` (2 preceding siblings ...)
2023-07-04 9:10 ` Upadhyay, Tejas
@ 2023-07-06 2:39 ` Dixit, Ashutosh
2023-07-06 13:42 ` Iddamsetty, Aravind
2023-07-06 2:40 ` Belgaumkar, Vinay
` (2 subsequent siblings)
6 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-06 2:39 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>
Hi Aravind,
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> +}
A few questions on just the above function first:
1. OK so these registers won't be available to VF's, but any idea what
these counts are when VF's are active?
2. When would these 32 bit registers overflow? Let us say a group is
continuously busy and we are running at 1 GHz, the registers would
overflow in 4 seconds (max value 4G)?
3. What is the multiplication by 16 (not factored above in 2.)? I don't see
that in Bspec.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-06 2:39 ` Dixit, Ashutosh
@ 2023-07-06 13:42 ` Iddamsetty, Aravind
2023-07-07 2:18 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-06 13:42 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 06-07-2023 08:09, Dixit, Ashutosh wrote:
> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>
>
> Hi Aravind,
>
Hi Ashutosh,
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>> +{
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>> +}
>
> A few questions on just the above function first:
>
> 1. OK so these registers won't be available to VF's, but any idea what
> these counts are when VF's are active?
VF's cannot access the registers but the counters will be incrementing
if respective engines are busy and can be monitored from PF and that
will be across all VFs.
>
> 2. When would these 32 bit registers overflow? Let us say a group is
> continuously busy and we are running at 1 GHz, the registers would
> overflow in 4 seconds (max value 4G)?
Based on BSPEC:52071 they use MHZ clock assuming the default 24MHz, it
would take around 5726 secs to overflow.
>
> 3. What is the multiplication by 16 (not factored above in 2.)? I don't see
> that in Bspec.
These counters are incremented based on crystal clock frequency and we
need to convert to CS time base hence a 16x mul. BSPEC:52071
Thanks,
Aravind.
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-06 13:42 ` Iddamsetty, Aravind
@ 2023-07-07 2:18 ` Dixit, Ashutosh
2023-07-07 3:53 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-07 2:18 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> On 06-07-2023 08:09, Dixit, Ashutosh wrote:
> > On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>
> >> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> >> +{
> >> + u64 val = 0;
> >> +
> >> + switch (config) {
> >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_COPY_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> >> + break;
> >> + default:
> >> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> >> + }
> >> +
> >> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> >> +}
> >
> > A few questions on just the above function first:
> >
> > 1. OK so these registers won't be available to VF's, but any idea what
> > these counts are when VF's are active?
>
> VF's cannot access the registers but the counters will be incrementing
> if respective engines are busy and can be monitored from PF and that
> will be across all VFs.
Ok, good.
>
> >
> > 2. When would these 32 bit registers overflow? Let us say a group is
> > continuously busy and we are running at 1 GHz, the registers would
> > overflow in 4 seconds (max value 4G)?
>
> Based on BSPEC:52071 they use MHZ clock assuming the default 24MHz, it
> would take around 5726 secs to overflow.
OK, overflow should not be an issue then. Though I have seen 19.2 and 38.4
MHz in OA. Also, if these are OAG registers, OA timestamp freq can be
different from CS timestamp freq, so not sure if that needs to be
handled. See i915_perf_oa_timestamp_frequency() in i915.
>
> >
> > 3. What is the multiplication by 16 (not factored above in 2.)? I don't see
> > that in Bspec.
>
> These counters are incremented based on crystal clock frequency and we
> need to convert to CS time base hence a 16x mul. BSPEC:52071
Hmm still don't see the 16x mul in BSPEC:52071. Anyway.
Also, could you please explain where the requirement to expose these OAG
group busy/free registers via the PMU is coming from? Since these are OA
registers presumably they can be collected using the OA subsystem.
The i915 PMU I believe deduces busyness by sampling the RING_CTL register
using a timer. So these registers look better since you can get these
busyness values directly. On the other hand you can only get busyness for
an engine group and things like compute seem to be missing?
Also, would you know about plans to expose other kinds of busyness-es? I
think we may be exposing per-VF and also per-client busyness via PMU. Not
sure what else GuC can expose. Knowing all this we can better understand
how these particular busyness values will be used.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 2:18 ` Dixit, Ashutosh
@ 2023-07-07 3:53 ` Iddamsetty, Aravind
2023-07-07 6:08 ` Dixit, Ashutosh
` (2 more replies)
0 siblings, 3 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-07 3:53 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 07-07-2023 07:48, Dixit, Ashutosh wrote:
> On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
Hi Ashutosh,
>
>> On 06-07-2023 08:09, Dixit, Ashutosh wrote:
>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>
>>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>>>> +{
>>>> + u64 val = 0;
>>>> +
>>>> + switch (config) {
>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>>>> + break;
>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>>>> + break;
>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>>>> + break;
>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>>>> + break;
>>>> + default:
>>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>>>> + }
>>>> +
>>>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>>>> +}
>>>
>>> A few questions on just the above function first:
>>>
>>> 1. OK so these registers won't be available to VF's, but any idea what
>>> these counts are when VF's are active?
>>
>> VF's cannot access the registers but the counters will be incrementing
>> if respective engines are busy and can be monitored from PF and that
>> will be across all VFs.
>
> Ok, good.
>
>>
>>>
>>> 2. When would these 32 bit registers overflow? Let us say a group is
>>> continuously busy and we are running at 1 GHz, the registers would
>>> overflow in 4 seconds (max value 4G)?
>>
>> Based on BSPEC:52071 they use MHZ clock assuming the default 24MHz, it
>> would take around 5726 secs to overflow.
>
> OK, overflow should not be an issue then. Though I have seen 19.2 and 38.4
> MHz in OA. Also, if these are OAG registers, OA timestamp freq can be
> different from CS timestamp freq, so not sure if that needs to be
> handled. See i915_perf_oa_timestamp_frequency() in i915.
so that is handled by below calculation
>
>>
>>>
>>> 3. What is the multiplication by 16 (not factored above in 2.)? I don't see
>>> that in Bspec.
>>
>> These counters are incremented based on crystal clock frequency and we
>> need to convert to CS time base hence a 16x mul. BSPEC:52071
>
> Hmm still don't see the 16x mul in BSPEC:52071. Anyway.
lets say the frequency is 24MHz so the counter increments every
1333.333ns(granularity) and corresponding cs timestamp base for this
frequency is 83.333ns, 1333.333/83.333 = 16 and this true for rest of
the frequency selections as well. hence we multiply the counter x 16.
>
> Also, could you please explain where the requirement to expose these OAG
> group busy/free registers via the PMU is coming from? Since these are OA
> registers presumably they can be collected using the OA subsystem.
L0 sysman needs this
https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
and xpumanager uses this
https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
>
> The i915 PMU I believe deduces busyness by sampling the RING_CTL register
> using a timer. So these registers look better since you can get these
> busyness values directly. On the other hand you can only get busyness for
> an engine group and things like compute seem to be missing?
The per engine busyness is a different thing we still need that and it
has different implementation with GuC enabled, I believe Umesh is
looking into that.
compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
>
> Also, would you know about plans to expose other kinds of busyness-es? I
> think we may be exposing per-VF and also per-client busyness via PMU. Not
> sure what else GuC can expose. Knowing all this we can better understand
> how these particular busyness values will be used.
ya, that shall be coming next probably from Umesh but per client
busyness is through fdinfo.
Thanks,
Aravind.
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 3:53 ` Iddamsetty, Aravind
@ 2023-07-07 6:08 ` Dixit, Ashutosh
2023-07-07 10:42 ` Iddamsetty, Aravind
2023-07-09 0:32 ` Dixit, Ashutosh
2023-07-18 5:07 ` Dixit, Ashutosh
2 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-07 6:08 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
I will look at the timing stuff later but one further question about the
requirement:
> > Also, could you please explain where the requirement to expose these OAG
> > group busy/free registers via the PMU is coming from? Since these are OA
> > registers presumably they can be collected using the OA subsystem.
>
> L0 sysman needs this
> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> and xpumanager uses this
> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
So fine these are UMD requirements, but why do these quantities (everything
in this patch) have to exposed via PMU? I could just create sysfs or an
ioctl to provide these to userland, right?
I had this same question about i915 PMU which was never answered. i915 PMU
IMO does truly strange things like sample freq's every 5 ms and provides
software averages which I thought userspace can easily do.
I don't think it's the timestamps, maybe there is some convention related
to the cpu pmu (which I am not familiar with).
Let's see, maybe Tvrtko can also answer why these things were exposed via
i915 PMU.
Thanks.
--
Ashutosh
> >
> > The i915 PMU I believe deduces busyness by sampling the RING_CTL register
> > using a timer. So these registers look better since you can get these
> > busyness values directly. On the other hand you can only get busyness for
> > an engine group and things like compute seem to be missing?
>
> The per engine busyness is a different thing we still need that and it
> has different implementation with GuC enabled, I believe Umesh is
> looking into that.
>
> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
> also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
> >
> > Also, would you know about plans to expose other kinds of busyness-es? I
> > think we may be exposing per-VF and also per-client busyness via PMU. Not
> > sure what else GuC can expose. Knowing all this we can better understand
> > how these particular busyness values will be used.
>
> ya, that shall be coming next probably from Umesh but per client
> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 6:08 ` Dixit, Ashutosh
@ 2023-07-07 10:42 ` Iddamsetty, Aravind
2023-07-07 21:25 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-07 10:42 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 07-07-2023 11:38, Dixit, Ashutosh wrote:
> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
Hi Ashutosh,
> I will look at the timing stuff later but one further question about the
> requirement:
>
>>> Also, could you please explain where the requirement to expose these OAG
>>> group busy/free registers via the PMU is coming from? Since these are OA
>>> registers presumably they can be collected using the OA subsystem.
>>
>> L0 sysman needs this
>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
>> and xpumanager uses this
>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
>
> So fine these are UMD requirements, but why do these quantities (everything
> in this patch) have to exposed via PMU? I could just create sysfs or an
> ioctl to provide these to userland, right?
PMU is enhanced interface to present the metrics, it provides low
latency reads compared to sysfs and one can read multiple events in a
single shot and it will give timestamps as well which sysfs cannot
provide and which is one of the requirements of UMD. Also UMDs/
observability tools do not want to have any open handles to get these
info so ioctl is dropped out.
the other motivation to use PMU in xe is the existing tools like
intel_gpu_top will work with just a minor change.
>
> I had this same question about i915 PMU which was never answered. i915 PMU
> IMO does truly strange things like sample freq's every 5 ms and provides
> software averages which I thought userspace can easily do.
that is a different thing nothing to do with PMU interface
Thanks,
Aravind.
>
> I don't think it's the timestamps, maybe there is some convention related
> to the cpu pmu (which I am not familiar with).
>
> Let's see, maybe Tvrtko can also answer why these things were exposed via
> i915 PMU.
>
> Thanks.
> --
> Ashutosh
>
>
>>>
>>> The i915 PMU I believe deduces busyness by sampling the RING_CTL register
>>> using a timer. So these registers look better since you can get these
>>> busyness values directly. On the other hand you can only get busyness for
>>> an engine group and things like compute seem to be missing?
>>
>> The per engine busyness is a different thing we still need that and it
>> has different implementation with GuC enabled, I believe Umesh is
>> looking into that.
>>
>> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
>> also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
>>>
>>> Also, would you know about plans to expose other kinds of busyness-es? I
>>> think we may be exposing per-VF and also per-client busyness via PMU. Not
>>> sure what else GuC can expose. Knowing all this we can better understand
>>> how these particular busyness values will be used.
>>
>> ya, that shall be coming next probably from Umesh but per client
>> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 10:42 ` Iddamsetty, Aravind
@ 2023-07-07 21:25 ` Dixit, Ashutosh
2023-07-10 6:05 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-07 21:25 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Fri, 07 Jul 2023 03:42:36 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> On 07-07-2023 11:38, Dixit, Ashutosh wrote:
> > On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
> > I will look at the timing stuff later but one further question about the
> > requirement:
> >
> >>> Also, could you please explain where the requirement to expose these OAG
> >>> group busy/free registers via the PMU is coming from? Since these are OA
> >>> registers presumably they can be collected using the OA subsystem.
> >>
> >> L0 sysman needs this
> >> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> >> and xpumanager uses this
> >> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
> >
> > So fine these are UMD requirements, but why do these quantities (everything
> > in this patch) have to exposed via PMU? I could just create sysfs or an
> > ioctl to provide these to userland, right?
>
> PMU is enhanced interface to present the metrics, it provides low
> latency reads compared to sysfs
Why lower latency compared to sysfs? In both cases we have user to kernel
transitions and then register reads etc.
> and one can read multiple events in a single shot
Yes, this PMU can do and sysfs can't, though ioctl's can do this.
> and it will give timestamps as well which sysfs cannot provide and which
> is one of the requirements of UMD.
Ioctl's can do this if implement (counter, timestamp) pairs, but I agree
this may look strange so PMU does seem to have an advantage here.
But are these timestamps needed? The spec talks about different timestamp
bases but in this case we have already converted to ns and I am wondering
if the UMD can use it's own timestamps (maybe average of the ioctl call and
return from ioctl) if UMD needs timestamps.
> Also UMDs/ observability tools do not want to have any open handles to
> get these info so ioctl is dropped out.
Why? This also I don't follow. And UMD has an perf pmu fd open. See
igt@perf_pmu@module-unload e.g. which tests that module unload should fail
if the perf pmu fd is open (which takes a ref count on the module).
> the other motivation to use PMU in xe is the existing tools like
> intel_gpu_top will work with just a minor change.
Not too concerned about userspace tools. They can be changed to use a
different interface.
So I am still not convinced xe needs to expose a PMU interface with these
sort of "software events/counters". So my question is why can't we just
have an ioctl to expose these things, why PMU?
Incidentally if you look at amdgpu_pmu.c, they seem to exposing some
hardware sort of events through the PMU, not our kind of software stuff.
Another interesting thing is if we have ftrace statements they seem to
automatically be exposed by PMU
(https://perf.wiki.kernel.org/index.php/Tutorial), e.g.:
i915:i915_request_add [Tracepoint event]
i915:i915_request_queue [Tracepoint event]
i915:i915_request_retire [Tracepoint event]
i915:i915_request_wait_begin [Tracepoint event]
i915:i915_request_wait_end [Tracepoint event]
So I am wondering if this might be an option?
So anyway let's try to understand the need for the PMU interface a bit more
before deciding on this. Once we introduce the interface (a) people will
willy nilly start exposing random stuff through that inteface (b) same
stuff will get exposed via multiple interfaces (e.g. frequency and rc6
residency in i915) etc. I am speaking on the basis of what I saw in i915.
Let's see if Tvrtko responds, otherwise I will try to get him on irc or
something. It will be good to have some input from maybe one of the
architects too about this.
Thanks.
--
Ashutosh
> > I had this same question about i915 PMU which was never answered. i915 PMU
> > IMO does truly strange things like sample freq's every 5 ms and provides
> > software averages which I thought userspace can easily do.
>
> that is a different thing nothing to do with PMU interface
>
> Thanks,
> Aravind.
> >
> > I don't think it's the timestamps, maybe there is some convention related
> > to the cpu pmu (which I am not familiar with).
> >
> > Let's see, maybe Tvrtko can also answer why these things were exposed via
> > i915 PMU.
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >
> >>>
> >>> The i915 PMU I believe deduces busyness by sampling the RING_CTL register
> >>> using a timer. So these registers look better since you can get these
> >>> busyness values directly. On the other hand you can only get busyness for
> >>> an engine group and things like compute seem to be missing?
> >>
> >> The per engine busyness is a different thing we still need that and it
> >> has different implementation with GuC enabled, I believe Umesh is
> >> looking into that.
> >>
> >> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
> >> also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
> >>>
> >>> Also, would you know about plans to expose other kinds of busyness-es? I
> >>> think we may be exposing per-VF and also per-client busyness via PMU. Not
> >>> sure what else GuC can expose. Knowing all this we can better understand
> >>> how these particular busyness values will be used.
> >>
> >> ya, that shall be coming next probably from Umesh but per client
> >> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 21:25 ` Dixit, Ashutosh
@ 2023-07-10 6:05 ` Iddamsetty, Aravind
2023-07-10 8:12 ` Ursulin, Tvrtko
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-10 6:05 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 08-07-2023 02:55, Dixit, Ashutosh wrote:
> On Fri, 07 Jul 2023 03:42:36 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
>> On 07-07-2023 11:38, Dixit, Ashutosh wrote:
>>> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>>> I will look at the timing stuff later but one further question about the
>>> requirement:
>>>
>>>>> Also, could you please explain where the requirement to expose these OAG
>>>>> group busy/free registers via the PMU is coming from? Since these are OA
>>>>> registers presumably they can be collected using the OA subsystem.
>>>>
>>>> L0 sysman needs this
>>>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
>>>> and xpumanager uses this
>>>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
>>>
>>> So fine these are UMD requirements, but why do these quantities (everything
>>> in this patch) have to exposed via PMU? I could just create sysfs or an
>>> ioctl to provide these to userland, right?
>>
>> PMU is enhanced interface to present the metrics, it provides low
>> latency reads compared to sysfs
>
> Why lower latency compared to sysfs? In both cases we have user to kernel
> transitions and then register reads etc.
The sysfs will have to go through filesystem which adds latency but here
i think the most important aspect is requirement of read timestamps.
>
>> and one can read multiple events in a single shot
>
> Yes, this PMU can do and sysfs can't, though ioctl's can do this.
>
>> and it will give timestamps as well which sysfs cannot provide and which
>> is one of the requirements of UMD.
>
> Ioctl's can do this if implement (counter, timestamp) pairs, but I agree
> this may look strange so PMU does seem to have an advantage here.
>
> But are these timestamps needed? The spec talks about different timestamp
> bases but in this case we have already converted to ns and I am wondering
> if the UMD can use it's own timestamps (maybe average of the ioctl call and
> return from ioctl) if UMD needs timestamps.
here i'm talking about read timestamps not the counter itself and when
we already have an interface(PMU) which can give these details why to do
duplicate effort in ioctl
>
>> Also UMDs/ observability tools do not want to have any open handles to
>> get these info so ioctl is dropped out.
>
> Why? This also I don't follow. And UMD has an perf pmu fd open. See
> igt@perf_pmu@module-unload e.g. which tests that module unload should fail
> if the perf pmu fd is open (which takes a ref count on the module).
here I'm referring to drm fd, one need not open drm fd to read via pmu,
and typically UMDs do not want to open drm fd as it takes device
reference and might toggle the device state(eg: wake device) when we are
trying to read some stats which is not needed.
>
>> the other motivation to use PMU in xe is the existing tools like
>> intel_gpu_top will work with just a minor change.
>
> Not too concerned about userspace tools. They can be changed to use a
> different interface.
>
> So I am still not convinced xe needs to expose a PMU interface with these
> sort of "software events/counters". So my question is why can't we just
> have an ioctl to expose these things, why PMU?
firstly, PMU satisfies all requirements of UMD, requiring read
timestamps, multiple event read. So as we already have a time tested
interface is kernel why should we try to duplicate. secondly, using
ioctl one has to open drm fd which umds do not want.
>
> Incidentally if you look at amdgpu_pmu.c, they seem to exposing some
> hardware sort of events through the PMU, not our kind of software stuff.
the counters that I'm exposing in this series are hardware counters itself.
>
> Another interesting thing is if we have ftrace statements they seem to
> automatically be exposed by PMU
> (https://perf.wiki.kernel.org/index.php/Tutorial), e.g.:
>
> i915:i915_request_add [Tracepoint event]
> i915:i915_request_queue [Tracepoint event]
> i915:i915_request_retire [Tracepoint event]
> i915:i915_request_wait_begin [Tracepoint event]
> i915:i915_request_wait_end [Tracepoint event]
>
> So I am wondering if this might be an option?
i'm little confused here how ftrace will expose any counters as it is
mostly for profiling?
Thanks,
Aravind.
>
> So anyway let's try to understand the need for the PMU interface a bit more
> before deciding on this. Once we introduce the interface (a) people will
> willy nilly start exposing random stuff through that inteface (b) same
> stuff will get exposed via multiple interfaces (e.g. frequency and rc6
> residency in i915) etc. I am speaking on the basis of what I saw in i915.
>
> Let's see if Tvrtko responds, otherwise I will try to get him on irc or
> something. It will be good to have some input from maybe one of the
> architects too about this.
>
> Thanks.
> --
> Ashutosh
>
>>> I had this same question about i915 PMU which was never answered. i915 PMU
>>> IMO does truly strange things like sample freq's every 5 ms and provides
>>> software averages which I thought userspace can easily do.
>>
>> that is a different thing nothing to do with PMU interface
>>
>> Thanks,
>> Aravind.
>>>
>>> I don't think it's the timestamps, maybe there is some convention related
>>> to the cpu pmu (which I am not familiar with).
>>>
>>> Let's see, maybe Tvrtko can also answer why these things were exposed via
>>> i915 PMU.
>>>
>>> Thanks.
>>> --
>>> Ashutosh
>>>
>>>
>>>>>
>>>>> The i915 PMU I believe deduces busyness by sampling the RING_CTL register
>>>>> using a timer. So these registers look better since you can get these
>>>>> busyness values directly. On the other hand you can only get busyness for
>>>>> an engine group and things like compute seem to be missing?
>>>>
>>>> The per engine busyness is a different thing we still need that and it
>>>> has different implementation with GuC enabled, I believe Umesh is
>>>> looking into that.
>>>>
>>>> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE and
>>>> also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
>>>>>
>>>>> Also, would you know about plans to expose other kinds of busyness-es? I
>>>>> think we may be exposing per-VF and also per-client busyness via PMU. Not
>>>>> sure what else GuC can expose. Knowing all this we can better understand
>>>>> how these particular busyness values will be used.
>>>>
>>>> ya, that shall be coming next probably from Umesh but per client
>>>> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-10 6:05 ` Iddamsetty, Aravind
@ 2023-07-10 8:12 ` Ursulin, Tvrtko
2023-07-11 16:19 ` Iddamsetty, Aravind
2023-07-11 22:58 ` Dixit, Ashutosh
0 siblings, 2 replies; 59+ messages in thread
From: Ursulin, Tvrtko @ 2023-07-10 8:12 UTC (permalink / raw)
To: Iddamsetty, Aravind, Dixit, Ashutosh
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org
Hi,
A few random comments:
* For question about why OA is not i915_perf.c and not Perf/PMU read comment on top of i915_perf.c.
* In terms of efficiency - don't forget the fact sysfs is one value per file and in text format - so multiple counters to be read is multiple system calls (two per value at least - unless that new ioctl which opens and reads in one is used) and binary->text->binary conversion. While PMU is one ioctl to read as many counters as wanted straight in machine usable format.
* In terms of why not ioctl - my memory is hazy but I am pretty sure people requesting this interface at the time had a strong requirement to not have it. Could be what Aravind listed, or maybe even more to it.
* For sysfs there definitely was something about sysfs not being wanted with containers but I can't remember the details. Possibly people were saying they wouldn't want to mount sysfs inside them for some reason.
* The fact tracepoint names are shown with perf list does not make them PMU. 😊
* I also wouldn't discount so easily aligning with the same interface in terms of tools like intel_gpu_top. The tool has it's users and it would be non-trivial cost to refactor into wholly different backends. Most importantly someone would need to commit to that which looking at the past record of involvements I estimate is not very likely to happen.
* Also in terms of software counters, the story is not that simple as i915 invented them. There was an option to actually use OA registers to implement engine busyness stats but unfortunately the capability wasn't consistent across hw generations we needed to support. Not all engines had corresponding OA counters and there was also one other problem with OA which currently escapes me. Needing to keep the device awake maybe? But anyway, that is one reason for sw counters, including sampling on ringbuffer platforms, and accurate sw stats on execlists.
Sampled frequency (more granular than 1 HZ snapshots) was also AFAIR a customer requirement and i915 can do it much more cheaply than userspace hammering on sysfs can.
Of course the user/customer requirements might have changed so I am not saying that all past decisions still apply. Just providing context.
Regards,
Tvrtko
-----Original Message-----
From: Iddamsetty, Aravind <aravind.iddamsetty@intel.com>
Sent: Monday, July 10, 2023 7:05 AM
To: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Cc: intel-xe@lists.freedesktop.org; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
On 08-07-2023 02:55, Dixit, Ashutosh wrote:
> On Fri, 07 Jul 2023 03:42:36 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
>> On 07-07-2023 11:38, Dixit, Ashutosh wrote:
>>> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>>> I will look at the timing stuff later but one further question about
>>> the
>>> requirement:
>>>
>>>>> Also, could you please explain where the requirement to expose
>>>>> these OAG group busy/free registers via the PMU is coming from?
>>>>> Since these are OA registers presumably they can be collected using the OA subsystem.
>>>>
>>>> L0 sysman needs this
>>>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine
>>>> -properties-t
>>>> and xpumanager uses this
>>>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu
>>>> /gpu_device.cpp
>>>
>>> So fine these are UMD requirements, but why do these quantities
>>> (everything in this patch) have to exposed via PMU? I could just
>>> create sysfs or an ioctl to provide these to userland, right?
>>
>> PMU is enhanced interface to present the metrics, it provides low
>> latency reads compared to sysfs
>
> Why lower latency compared to sysfs? In both cases we have user to
> kernel transitions and then register reads etc.
The sysfs will have to go through filesystem which adds latency but here i think the most important aspect is requirement of read timestamps.
>
>> and one can read multiple events in a single shot
>
> Yes, this PMU can do and sysfs can't, though ioctl's can do this.
>
>> and it will give timestamps as well which sysfs cannot provide and
>> which is one of the requirements of UMD.
>
> Ioctl's can do this if implement (counter, timestamp) pairs, but I
> agree this may look strange so PMU does seem to have an advantage here.
>
> But are these timestamps needed? The spec talks about different
> timestamp bases but in this case we have already converted to ns and I
> am wondering if the UMD can use it's own timestamps (maybe average of
> the ioctl call and return from ioctl) if UMD needs timestamps.
here i'm talking about read timestamps not the counter itself and when we already have an interface(PMU) which can give these details why to do duplicate effort in ioctl
>
>> Also UMDs/ observability tools do not want to have any open handles
>> to get these info so ioctl is dropped out.
>
> Why? This also I don't follow. And UMD has an perf pmu fd open. See
> igt@perf_pmu@module-unload e.g. which tests that module unload should
> fail if the perf pmu fd is open (which takes a ref count on the module).
here I'm referring to drm fd, one need not open drm fd to read via pmu, and typically UMDs do not want to open drm fd as it takes device reference and might toggle the device state(eg: wake device) when we are trying to read some stats which is not needed.
>
>> the other motivation to use PMU in xe is the existing tools like
>> intel_gpu_top will work with just a minor change.
>
> Not too concerned about userspace tools. They can be changed to use a
> different interface.
>
> So I am still not convinced xe needs to expose a PMU interface with
> these sort of "software events/counters". So my question is why can't
> we just have an ioctl to expose these things, why PMU?
firstly, PMU satisfies all requirements of UMD, requiring read timestamps, multiple event read. So as we already have a time tested interface is kernel why should we try to duplicate. secondly, using ioctl one has to open drm fd which umds do not want.
>
> Incidentally if you look at amdgpu_pmu.c, they seem to exposing some
> hardware sort of events through the PMU, not our kind of software stuff.
the counters that I'm exposing in this series are hardware counters itself.
>
> Another interesting thing is if we have ftrace statements they seem to
> automatically be exposed by PMU
> (https://perf.wiki.kernel.org/index.php/Tutorial), e.g.:
>
> i915:i915_request_add [Tracepoint event]
> i915:i915_request_queue [Tracepoint event]
> i915:i915_request_retire [Tracepoint event]
> i915:i915_request_wait_begin [Tracepoint event]
> i915:i915_request_wait_end [Tracepoint event]
>
> So I am wondering if this might be an option?
i'm little confused here how ftrace will expose any counters as it is mostly for profiling?
Thanks,
Aravind.
>
> So anyway let's try to understand the need for the PMU interface a bit
> more before deciding on this. Once we introduce the interface (a)
> people will willy nilly start exposing random stuff through that
> inteface (b) same stuff will get exposed via multiple interfaces (e.g.
> frequency and rc6 residency in i915) etc. I am speaking on the basis of what I saw in i915.
>
> Let's see if Tvrtko responds, otherwise I will try to get him on irc
> or something. It will be good to have some input from maybe one of the
> architects too about this.
>
> Thanks.
> --
> Ashutosh
>
>>> I had this same question about i915 PMU which was never answered.
>>> i915 PMU IMO does truly strange things like sample freq's every 5 ms
>>> and provides software averages which I thought userspace can easily do.
>>
>> that is a different thing nothing to do with PMU interface
>>
>> Thanks,
>> Aravind.
>>>
>>> I don't think it's the timestamps, maybe there is some convention
>>> related to the cpu pmu (which I am not familiar with).
>>>
>>> Let's see, maybe Tvrtko can also answer why these things were
>>> exposed via
>>> i915 PMU.
>>>
>>> Thanks.
>>> --
>>> Ashutosh
>>>
>>>
>>>>>
>>>>> The i915 PMU I believe deduces busyness by sampling the RING_CTL
>>>>> register using a timer. So these registers look better since you
>>>>> can get these busyness values directly. On the other hand you can
>>>>> only get busyness for an engine group and things like compute seem to be missing?
>>>>
>>>> The per engine busyness is a different thing we still need that and
>>>> it has different implementation with GuC enabled, I believe Umesh
>>>> is looking into that.
>>>>
>>>> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE
>>>> and also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
>>>>>
>>>>> Also, would you know about plans to expose other kinds of
>>>>> busyness-es? I think we may be exposing per-VF and also per-client
>>>>> busyness via PMU. Not sure what else GuC can expose. Knowing all
>>>>> this we can better understand how these particular busyness values will be used.
>>>>
>>>> ya, that shall be coming next probably from Umesh but per client
>>>> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-10 8:12 ` Ursulin, Tvrtko
@ 2023-07-11 16:19 ` Iddamsetty, Aravind
2023-07-11 23:10 ` Dixit, Ashutosh
2023-07-11 22:58 ` Dixit, Ashutosh
1 sibling, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-11 16:19 UTC (permalink / raw)
To: Ursulin, Tvrtko, Dixit, Ashutosh
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org
Hi Ashutosh,
Please let me know if you have any more questions around this.
Thanks,
Aravind.
On 10-07-2023 13:42, Ursulin, Tvrtko wrote:
>
> Hi,
>
> A few random comments:
>
> * For question about why OA is not i915_perf.c and not Perf/PMU read comment on top of i915_perf.c.
>
> * In terms of efficiency - don't forget the fact sysfs is one value per file and in text format - so multiple counters to be read is multiple system calls (two per value at least - unless that new ioctl which opens and reads in one is used) and binary->text->binary conversion. While PMU is one ioctl to read as many counters as wanted straight in machine usable format.
>
> * In terms of why not ioctl - my memory is hazy but I am pretty sure people requesting this interface at the time had a strong requirement to not have it. Could be what Aravind listed, or maybe even more to it.
>
> * For sysfs there definitely was something about sysfs not being wanted with containers but I can't remember the details. Possibly people were saying they wouldn't want to mount sysfs inside them for some reason.
>
> * The fact tracepoint names are shown with perf list does not make them PMU. 😊
>
> * I also wouldn't discount so easily aligning with the same interface in terms of tools like intel_gpu_top. The tool has it's users and it would be non-trivial cost to refactor into wholly different backends. Most importantly someone would need to commit to that which looking at the past record of involvements I estimate is not very likely to happen.
>
> * Also in terms of software counters, the story is not that simple as i915 invented them. There was an option to actually use OA registers to implement engine busyness stats but unfortunately the capability wasn't consistent across hw generations we needed to support. Not all engines had corresponding OA counters and there was also one other problem with OA which currently escapes me. Needing to keep the device awake maybe? But anyway, that is one reason for sw counters, including sampling on ringbuffer platforms, and accurate sw stats on execlists.
>
> Sampled frequency (more granular than 1 HZ snapshots) was also AFAIR a customer requirement and i915 can do it much more cheaply than userspace hammering on sysfs can.
>
> Of course the user/customer requirements might have changed so I am not saying that all past decisions still apply. Just providing context.
>
> Regards,
>
> Tvrtko
>
> -----Original Message-----
> From: Iddamsetty, Aravind <aravind.iddamsetty@intel.com>
> Sent: Monday, July 10, 2023 7:05 AM
> To: Dixit, Ashutosh <ashutosh.dixit@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>
>
>
> On 08-07-2023 02:55, Dixit, Ashutosh wrote:
>> On Fri, 07 Jul 2023 03:42:36 -0700, Iddamsetty, Aravind wrote:
>>>
>>
>> Hi Aravind,
>>
>>> On 07-07-2023 11:38, Dixit, Ashutosh wrote:
>>>> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>>>> I will look at the timing stuff later but one further question about
>>>> the
>>>> requirement:
>>>>
>>>>>> Also, could you please explain where the requirement to expose
>>>>>> these OAG group busy/free registers via the PMU is coming from?
>>>>>> Since these are OA registers presumably they can be collected using the OA subsystem.
>>>>>
>>>>> L0 sysman needs this
>>>>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine
>>>>> -properties-t
>>>>> and xpumanager uses this
>>>>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu
>>>>> /gpu_device.cpp
>>>>
>>>> So fine these are UMD requirements, but why do these quantities
>>>> (everything in this patch) have to exposed via PMU? I could just
>>>> create sysfs or an ioctl to provide these to userland, right?
>>>
>>> PMU is enhanced interface to present the metrics, it provides low
>>> latency reads compared to sysfs
>>
>> Why lower latency compared to sysfs? In both cases we have user to
>> kernel transitions and then register reads etc.
>
> The sysfs will have to go through filesystem which adds latency but here i think the most important aspect is requirement of read timestamps.
>
>>
>>> and one can read multiple events in a single shot
>>
>> Yes, this PMU can do and sysfs can't, though ioctl's can do this.
>>
>>> and it will give timestamps as well which sysfs cannot provide and
>>> which is one of the requirements of UMD.
>>
>> Ioctl's can do this if implement (counter, timestamp) pairs, but I
>> agree this may look strange so PMU does seem to have an advantage here.
>>
>> But are these timestamps needed? The spec talks about different
>> timestamp bases but in this case we have already converted to ns and I
>> am wondering if the UMD can use it's own timestamps (maybe average of
>> the ioctl call and return from ioctl) if UMD needs timestamps.
>
> here i'm talking about read timestamps not the counter itself and when we already have an interface(PMU) which can give these details why to do duplicate effort in ioctl
>>
>>> Also UMDs/ observability tools do not want to have any open handles
>>> to get these info so ioctl is dropped out.
>>
>> Why? This also I don't follow. And UMD has an perf pmu fd open. See
>> igt@perf_pmu@module-unload e.g. which tests that module unload should
>> fail if the perf pmu fd is open (which takes a ref count on the module).
>
> here I'm referring to drm fd, one need not open drm fd to read via pmu, and typically UMDs do not want to open drm fd as it takes device reference and might toggle the device state(eg: wake device) when we are trying to read some stats which is not needed.
>
>>
>>> the other motivation to use PMU in xe is the existing tools like
>>> intel_gpu_top will work with just a minor change.
>>
>> Not too concerned about userspace tools. They can be changed to use a
>> different interface.
>>
>> So I am still not convinced xe needs to expose a PMU interface with
>> these sort of "software events/counters". So my question is why can't
>> we just have an ioctl to expose these things, why PMU?
>
> firstly, PMU satisfies all requirements of UMD, requiring read timestamps, multiple event read. So as we already have a time tested interface is kernel why should we try to duplicate. secondly, using ioctl one has to open drm fd which umds do not want.
>>
>> Incidentally if you look at amdgpu_pmu.c, they seem to exposing some
>> hardware sort of events through the PMU, not our kind of software stuff.
>
> the counters that I'm exposing in this series are hardware counters itself.
>
>>
>> Another interesting thing is if we have ftrace statements they seem to
>> automatically be exposed by PMU
>> (https://perf.wiki.kernel.org/index.php/Tutorial), e.g.:
>>
>> i915:i915_request_add [Tracepoint event]
>> i915:i915_request_queue [Tracepoint event]
>> i915:i915_request_retire [Tracepoint event]
>> i915:i915_request_wait_begin [Tracepoint event]
>> i915:i915_request_wait_end [Tracepoint event]
>>
>> So I am wondering if this might be an option?
>
> i'm little confused here how ftrace will expose any counters as it is mostly for profiling?
>
> Thanks,
> Aravind.
>>
>> So anyway let's try to understand the need for the PMU interface a bit
>> more before deciding on this. Once we introduce the interface (a)
>> people will willy nilly start exposing random stuff through that
>> inteface (b) same stuff will get exposed via multiple interfaces (e.g.
>> frequency and rc6 residency in i915) etc. I am speaking on the basis of what I saw in i915.
>>
>> Let's see if Tvrtko responds, otherwise I will try to get him on irc
>> or something. It will be good to have some input from maybe one of the
>> architects too about this.
>>
>> Thanks.
>> --
>> Ashutosh
>>
>>>> I had this same question about i915 PMU which was never answered.
>>>> i915 PMU IMO does truly strange things like sample freq's every 5 ms
>>>> and provides software averages which I thought userspace can easily do.
>>>
>>> that is a different thing nothing to do with PMU interface
>>>
>>> Thanks,
>>> Aravind.
>>>>
>>>> I don't think it's the timestamps, maybe there is some convention
>>>> related to the cpu pmu (which I am not familiar with).
>>>>
>>>> Let's see, maybe Tvrtko can also answer why these things were
>>>> exposed via
>>>> i915 PMU.
>>>>
>>>> Thanks.
>>>> --
>>>> Ashutosh
>>>>
>>>>
>>>>>>
>>>>>> The i915 PMU I believe deduces busyness by sampling the RING_CTL
>>>>>> register using a timer. So these registers look better since you
>>>>>> can get these busyness values directly. On the other hand you can
>>>>>> only get busyness for an engine group and things like compute seem to be missing?
>>>>>
>>>>> The per engine busyness is a different thing we still need that and
>>>>> it has different implementation with GuC enabled, I believe Umesh
>>>>> is looking into that.
>>>>>
>>>>> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE
>>>>> and also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
>>>>>>
>>>>>> Also, would you know about plans to expose other kinds of
>>>>>> busyness-es? I think we may be exposing per-VF and also per-client
>>>>>> busyness via PMU. Not sure what else GuC can expose. Knowing all
>>>>>> this we can better understand how these particular busyness values will be used.
>>>>>
>>>>> ya, that shall be coming next probably from Umesh but per client
>>>>> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-11 16:19 ` Iddamsetty, Aravind
@ 2023-07-11 23:10 ` Dixit, Ashutosh
2023-07-12 3:11 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-11 23:10 UTC (permalink / raw)
To: Iddamsetty, Aravind
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org,
Ursulin, Tvrtko
On Tue, 11 Jul 2023 09:19:24 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> Please let me know if you have any more questions around this.
I've asked. But you probably know that since this is uapi, to merge this we
would need a fully reviewed UMD (non IGT) merge request which consumes what
we are exposing. So while we are reviewing this maybe let's ask L0 etc. for
the merge request. I looked at xpumanager but didn't see it consuming what
we are exposing via PMU here.
Maybe we'll need an ack from someone like Joonas too.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-11 23:10 ` Dixit, Ashutosh
@ 2023-07-12 3:11 ` Iddamsetty, Aravind
2023-07-12 5:24 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-12 3:11 UTC (permalink / raw)
To: Dixit, Ashutosh
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org,
Ursulin, Tvrtko
On 12-07-2023 04:40, Dixit, Ashutosh wrote:
> On Tue, 11 Jul 2023 09:19:24 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
>> Please let me know if you have any more questions around this.
>
> I've asked. But you probably know that since this is uapi, to merge this we
> would need a fully reviewed UMD (non IGT) merge request which consumes what
> we are exposing. So while we are reviewing this maybe let's ask L0 etc. for
> the merge request. I looked at xpumanager but didn't see it consuming what
> we are exposing via PMU here.
Hi Ashutosh,
For the UAPI consumption we can use the linux generic perf tool, won't
it be agreeable.
Thanks,
Aravind.
>
> Maybe we'll need an ack from someone like Joonas too.
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-12 3:11 ` Iddamsetty, Aravind
@ 2023-07-12 5:24 ` Dixit, Ashutosh
0 siblings, 0 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-12 5:24 UTC (permalink / raw)
To: Iddamsetty, Aravind
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org,
Ursulin, Tvrtko
On Tue, 11 Jul 2023 20:11:12 -0700, Iddamsetty, Aravind wrote:
>
> On 12-07-2023 04:40, Dixit, Ashutosh wrote:
> > On Tue, 11 Jul 2023 09:19:24 -0700, Iddamsetty, Aravind wrote:
> >>
> >
> >> Please let me know if you have any more questions around this.
> >
> > I've asked. But you probably know that since this is uapi, to merge this we
> > would need a fully reviewed UMD (non IGT) merge request which consumes what
> > we are exposing. So while we are reviewing this maybe let's ask L0 etc. for
> > the merge request. I looked at xpumanager but didn't see it consuming what
> > we are exposing via PMU here.
> Hi Ashutosh,
>
> For the UAPI consumption we can use the linux generic perf tool, won't
> it be agreeable.
We can check with Joonas or Matt Roper, but afaiu because the linux generic
perf tool has nothing specific about what we are exposing it will not be
enough, we will need a L0 or another "approved" UMD merge request (I
believe L0 is approved).
> >
> > Maybe we'll need an ack from someone like Joonas too.
> >
> > Thanks.
> > --
> > Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-10 8:12 ` Ursulin, Tvrtko
2023-07-11 16:19 ` Iddamsetty, Aravind
@ 2023-07-11 22:58 ` Dixit, Ashutosh
1 sibling, 0 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-11 22:58 UTC (permalink / raw)
To: Ursulin, Tvrtko; +Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org
On Mon, 10 Jul 2023 01:12:03 -0700, Ursulin, Tvrtko wrote:
>
>
Hi Tvrtko,
Thanks for providing the context. I have a couple of further questions:
* For client busyness it seems we mananged to invent a drm wide fdinfo
based method (non PMU). Are any such efforts on for the kinds of things
we are exposing via the i915 PMU or do you see a possibility for this?
For it would appear that all drm drivers would want to expose such perf
info and a common method across drm is desirable?
* Would you or anyone else have an idea of what other drm drivers (say AMD)
are exposing with Perf/PMU? And why they didn't see the need to do what
was done in i915 (it seems they are not exposing the same sort of stuff
which i915 is exposing)?
And a few comments below.
> A few random comments:
>
> * For question about why OA is not i915_perf.c and not Perf/PMU read
> * comment on top of i915_perf.c.
... why OA is i915_perf.c and not Perf/PMU ... The question Aravind asked
earlier.
> * In terms of efficiency - don't forget the fact sysfs is one value per
> * file and in text format - so multiple counters to be read is multiple
> * system calls (two per value at least - unless that new ioctl which
> * opens and reads in one is used) and binary->text->binary
> * conversion. While PMU is one ioctl to read as many counters as wanted
> * straight in machine usable format.
>
> * In terms of why not ioctl - my memory is hazy but I am pretty sure
> * people requesting this interface at the time had a strong requirement
> * to not have it. Could be what Aravind listed, or maybe even more to it.
Another advantage PMU has over ioctl is "discoverability", at run time your
can discover what is available. Maybe can be done via ioctl extensions or
versioning such as is used in OA.
So overall I have also come round to thinking to expose perf stats, PMU
seems to be a better interface than ioctl or sysfs.
> * For sysfs there definitely was something about sysfs not being wanted
> * with containers but I can't remember the details. Possibly people were
> * saying they wouldn't want to mount sysfs inside them for some reason.
Heard the other day that using sysfs with containers needs some kernel
changes.
> * The fact tracepoint names are shown with perf list does not make them
> * PMU. 😊
Yup I tried this out and there was no real information there.
> * I also wouldn't discount so easily aligning with the same interface in
> * terms of tools like intel_gpu_top. The tool has it's users and it would
> * be non-trivial cost to refactor into wholly different backends. Most
> * importantly someone would need to commit to that which looking at the
> * past record of involvements I estimate is not very likely to happen.
Agreed, doing it say via OA would be more complicated too. I think tools
around OA exist but likely doing it in IGT is probably not going to happen.
And even if we did do something with OA, we would need a way to expose
busyness data which GuC emits (as opposed to what HW emits).
> * Also in terms of software counters, the story is not that simple as
> * i915 invented them. There was an option to actually use OA registers to
> * implement engine busyness stats but unfortunately the capability wasn't
> * consistent across hw generations we needed to support. Not all engines
> * had corresponding OA counters and there was also one other problem with
> * OA which currently escapes me. Needing to keep the device awake maybe?
> * But anyway, that is one reason for sw counters, including sampling on
> * ringbuffer platforms, and accurate sw stats on execlists.
>
> Sampled frequency (more granular than 1 HZ snapshots) was also AFAIR a
> customer requirement and i915 can do it much more cheaply than userspace
> hammering on sysfs can.
Agreed kernel can do it more cheaply, but maybe doing it at 20 Hz in
usersapce (rather than 200 Hz in the kernel) is sufficient? And userspace
won't have to deal with the i915 quirks such as freq is only measured when
GPU is unparked.
> Of course the user/customer requirements might have changed so I am not
> saying that all past decisions still apply. Just providing context.
Yes thanks for that, much appreciated.
Ashutosh
>
> Regards,
>
> Tvrtko
>
> -----Original Message-----
> From: Iddamsetty, Aravind <aravind.iddamsetty@intel.com>
> Sent: Monday, July 10, 2023 7:05 AM
> To: Dixit, Ashutosh <ashutosh.dixit@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>
> Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
>
>
>
> On 08-07-2023 02:55, Dixit, Ashutosh wrote:
> > On Fri, 07 Jul 2023 03:42:36 -0700, Iddamsetty, Aravind wrote:
> >>
> >
> > Hi Aravind,
> >
> >> On 07-07-2023 11:38, Dixit, Ashutosh wrote:
> >>> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
> >>> I will look at the timing stuff later but one further question about
> >>> the
> >>> requirement:
> >>>
> >>>>> Also, could you please explain where the requirement to expose
> >>>>> these OAG group busy/free registers via the PMU is coming from?
> >>>>> Since these are OA registers presumably they can be collected using the OA subsystem.
> >>>>
> >>>> L0 sysman needs this
> >>>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine
> >>>> -properties-t
> >>>> and xpumanager uses this
> >>>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu
> >>>> /gpu_device.cpp
> >>>
> >>> So fine these are UMD requirements, but why do these quantities
> >>> (everything in this patch) have to exposed via PMU? I could just
> >>> create sysfs or an ioctl to provide these to userland, right?
> >>
> >> PMU is enhanced interface to present the metrics, it provides low
> >> latency reads compared to sysfs
> >
> > Why lower latency compared to sysfs? In both cases we have user to
> > kernel transitions and then register reads etc.
>
> The sysfs will have to go through filesystem which adds latency but here i think the most important aspect is requirement of read timestamps.
>
> >
> >> and one can read multiple events in a single shot
> >
> > Yes, this PMU can do and sysfs can't, though ioctl's can do this.
> >
> >> and it will give timestamps as well which sysfs cannot provide and
> >> which is one of the requirements of UMD.
> >
> > Ioctl's can do this if implement (counter, timestamp) pairs, but I
> > agree this may look strange so PMU does seem to have an advantage here.
> >
> > But are these timestamps needed? The spec talks about different
> > timestamp bases but in this case we have already converted to ns and I
> > am wondering if the UMD can use it's own timestamps (maybe average of
> > the ioctl call and return from ioctl) if UMD needs timestamps.
>
> here i'm talking about read timestamps not the counter itself and when we already have an interface(PMU) which can give these details why to do duplicate effort in ioctl
> >
> >> Also UMDs/ observability tools do not want to have any open handles
> >> to get these info so ioctl is dropped out.
> >
> > Why? This also I don't follow. And UMD has an perf pmu fd open. See
> > igt@perf_pmu@module-unload e.g. which tests that module unload should
> > fail if the perf pmu fd is open (which takes a ref count on the module).
>
> here I'm referring to drm fd, one need not open drm fd to read via pmu, and typically UMDs do not want to open drm fd as it takes device reference and might toggle the device state(eg: wake device) when we are trying to read some stats which is not needed.
>
> >
> >> the other motivation to use PMU in xe is the existing tools like
> >> intel_gpu_top will work with just a minor change.
> >
> > Not too concerned about userspace tools. They can be changed to use a
> > different interface.
> >
> > So I am still not convinced xe needs to expose a PMU interface with
> > these sort of "software events/counters". So my question is why can't
> > we just have an ioctl to expose these things, why PMU?
>
> firstly, PMU satisfies all requirements of UMD, requiring read timestamps, multiple event read. So as we already have a time tested interface is kernel why should we try to duplicate. secondly, using ioctl one has to open drm fd which umds do not want.
> >
> > Incidentally if you look at amdgpu_pmu.c, they seem to exposing some
> > hardware sort of events through the PMU, not our kind of software stuff.
>
> the counters that I'm exposing in this series are hardware counters itself.
>
> >
> > Another interesting thing is if we have ftrace statements they seem to
> > automatically be exposed by PMU
> > (https://perf.wiki.kernel.org/index.php/Tutorial), e.g.:
> >
> > i915:i915_request_add [Tracepoint event]
> > i915:i915_request_queue [Tracepoint event]
> > i915:i915_request_retire [Tracepoint event]
> > i915:i915_request_wait_begin [Tracepoint event]
> > i915:i915_request_wait_end [Tracepoint event]
> >
> > So I am wondering if this might be an option?
>
> i'm little confused here how ftrace will expose any counters as it is mostly for profiling?
>
> Thanks,
> Aravind.
> >
> > So anyway let's try to understand the need for the PMU interface a bit
> > more before deciding on this. Once we introduce the interface (a)
> > people will willy nilly start exposing random stuff through that
> > inteface (b) same stuff will get exposed via multiple interfaces (e.g.
> > frequency and rc6 residency in i915) etc. I am speaking on the basis of what I saw in i915.
> >
> > Let's see if Tvrtko responds, otherwise I will try to get him on irc
> > or something. It will be good to have some input from maybe one of the
> > architects too about this.
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >>> I had this same question about i915 PMU which was never answered.
> >>> i915 PMU IMO does truly strange things like sample freq's every 5 ms
> >>> and provides software averages which I thought userspace can easily do.
> >>
> >> that is a different thing nothing to do with PMU interface
> >>
> >> Thanks,
> >> Aravind.
> >>>
> >>> I don't think it's the timestamps, maybe there is some convention
> >>> related to the cpu pmu (which I am not familiar with).
> >>>
> >>> Let's see, maybe Tvrtko can also answer why these things were
> >>> exposed via
> >>> i915 PMU.
> >>>
> >>> Thanks.
> >>> --
> >>> Ashutosh
> >>>
> >>>
> >>>>>
> >>>>> The i915 PMU I believe deduces busyness by sampling the RING_CTL
> >>>>> register using a timer. So these registers look better since you
> >>>>> can get these busyness values directly. On the other hand you can
> >>>>> only get busyness for an engine group and things like compute seem to be missing?
> >>>>
> >>>> The per engine busyness is a different thing we still need that and
> >>>> it has different implementation with GuC enabled, I believe Umesh
> >>>> is looking into that.
> >>>>
> >>>> compute group will still be accounted in XE_OAG_RENDER_BUSY_FREE
> >>>> and also under XE_OAG_RC0_ANY_ENGINE_BUSY_FREE.
> >>>>>
> >>>>> Also, would you know about plans to expose other kinds of
> >>>>> busyness-es? I think we may be exposing per-VF and also per-client
> >>>>> busyness via PMU. Not sure what else GuC can expose. Knowing all
> >>>>> this we can better understand how these particular busyness values will be used.
> >>>>
> >>>> ya, that shall be coming next probably from Umesh but per client
> >>>> busyness is through fdinfo.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 3:53 ` Iddamsetty, Aravind
2023-07-07 6:08 ` Dixit, Ashutosh
@ 2023-07-09 0:32 ` Dixit, Ashutosh
2023-07-10 4:13 ` Iddamsetty, Aravind
2023-07-18 5:07 ` Dixit, Ashutosh
2 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-09 0:32 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
> On 07-07-2023 07:48, Dixit, Ashutosh wrote:
> > On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
> > Also, could you please explain where the requirement to expose these OAG
> > group busy/free registers via the PMU is coming from? Since these are OA
> > registers presumably they can be collected using the OA subsystem.
>
> L0 sysman needs this
> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> and xpumanager uses this
> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
Also there is the above mentioned open regarding this: "Since these are OA
registers presumably they can be collected using the OA subsystem". L0 now
seems to be supporting OA and we are going to provide an OA subsystem for
xe. This probably also needs arch input.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-09 0:32 ` Dixit, Ashutosh
@ 2023-07-10 4:13 ` Iddamsetty, Aravind
2023-07-10 5:57 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-10 4:13 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 09-07-2023 06:02, Dixit, Ashutosh wrote:
> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>> On 07-07-2023 07:48, Dixit, Ashutosh wrote:
>>> On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
>>> Also, could you please explain where the requirement to expose these OAG
>>> group busy/free registers via the PMU is coming from? Since these are OA
>>> registers presumably they can be collected using the OA subsystem.
>>
>> L0 sysman needs this
>> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
>> and xpumanager uses this
>> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
>
> Also there is the above mentioned open regarding this: "Since these are OA
> registers presumably they can be collected using the OA subsystem". L0 now
> seems to be supporting OA and we are going to provide an OA subsystem for
> xe. This probably also needs arch input.
While I try to check on this, by any chance do you know why we have to
go with custom OA subsystem implementation and cannot use PMU for
reporting OA.
Thanks,
Aravind.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-10 4:13 ` Iddamsetty, Aravind
@ 2023-07-10 5:57 ` Dixit, Ashutosh
0 siblings, 0 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-10 5:57 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Sun, 09 Jul 2023 21:13:59 -0700, Iddamsetty, Aravind wrote:
>
> On 09-07-2023 06:02, Dixit, Ashutosh wrote:
> > On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
> >> On 07-07-2023 07:48, Dixit, Ashutosh wrote:
> >>> On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
> >>> Also, could you please explain where the requirement to expose these OAG
> >>> group busy/free registers via the PMU is coming from? Since these are OA
> >>> registers presumably they can be collected using the OA subsystem.
> >>
> >> L0 sysman needs this
> >> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> >> and xpumanager uses this
> >> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp
> >
> > Also there is the above mentioned open regarding this: "Since these are OA
> > registers presumably they can be collected using the OA subsystem". L0 now
> > seems to be supporting OA and we are going to provide an OA subsystem for
> > xe. This probably also needs arch input.
>
> While I try to check on this, by any chance do you know why we have to
> go with custom OA subsystem implementation and cannot use PMU for
> reporting OA.
Because we already had a big OA subsystem in i915 (i915_perf.c) which we
are bringing over to xe. And OA has many more metrics than just the few we
are exposing (or had exposed via the PMU). You can see these metrics in
build/lib directory of the IGT build (after you compile IGT). Grep for
busyness. Some of metrics which come from GuC will not be available from OA
(since OA data is HW generated) so we will have to expose these separately.
Separately, I think it would be good to understand how other drm drivers
expose such performance data (such as what we were doing in i915 with OA
and PMU) for userland to digest.
Let's see. I am not against PMU per se, just asking questions so we can get
some opinion about these things before we commit to supporting the PMU
interface.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-07 3:53 ` Iddamsetty, Aravind
2023-07-07 6:08 ` Dixit, Ashutosh
2023-07-09 0:32 ` Dixit, Ashutosh
@ 2023-07-18 5:07 ` Dixit, Ashutosh
2023-07-19 6:59 ` Iddamsetty, Aravind
2 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-18 5:07 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
Back to this review.
> >> On 06-07-2023 08:09, Dixit, Ashutosh wrote:
> >>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
> >>
> >>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> >>>> +{
> >>>> + u64 val = 0;
> >>>> +
> >>>> + switch (config) {
> >>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> >>>> + break;
> >>>> + case XE_PMU_COPY_GROUP_BUSY(0):
> >>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> >>>> + break;
> >>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> >>>> + break;
> >>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> >>>> + break;
> >>>> + default:
> >>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> >>>> + }
> >>>> +
> >>>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> >>>> +}
> >>>
> >>> A few questions on just the above function first:
> >>>
> >>> 1. OK so these registers won't be available to VF's, but any idea what
> >>> these counts are when VF's are active?
> >>
> >> VF's cannot access the registers but the counters will be incrementing
> >> if respective engines are busy and can be monitored from PF and that
> >> will be across all VFs.
> >
> > Ok, good.
> >
> >>
> >>>
> >>> 2. When would these 32 bit registers overflow? Let us say a group is
> >>> continuously busy and we are running at 1 GHz, the registers would
> >>> overflow in 4 seconds (max value 4G)?
> >>
> >> Based on BSPEC:52071 they use MHZ clock assuming the default 24MHz, it
> >> would take around 5726 secs to overflow.
> >
> > OK, overflow should not be an issue then. Though I have seen 19.2 and 38.4
> > MHz in OA. Also, if these are OAG registers, OA timestamp freq can be
> > different from CS timestamp freq, so not sure if that needs to be
> > handled. See i915_perf_oa_timestamp_frequency() in i915.
>
> so that is handled by below calculation
> >>
> >>>
> >>> 3. What is the multiplication by 16 (not factored above in 2.)? I don't see
> >>> that in Bspec.
> >>
> >> These counters are incremented based on crystal clock frequency and we
> >> need to convert to CS time base hence a 16x mul. BSPEC:52071
> >
> > Hmm still don't see the 16x mul in BSPEC:52071. Anyway.
>
> lets say the frequency is 24MHz so the counter increments every
> 1333.333ns(granularity) and corresponding cs timestamp base for this
> frequency is 83.333ns, 1333.333/83.333 = 16 and this true for rest of
> the frequency selections as well. hence we multiply the counter x 16.
OK, I finally see in Bspec:71028: "Unit in GPMusec. Refer to Timestamp
Bases for details" which is a pointer to Bspec: 52071. So the 16x multiply
looks correct (and these registers are not running at OA freq otherwise
we'd have to use i915_perf_oa_timestamp_frequency()). Hopefully it's
correct. Thanks.
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-18 5:07 ` Dixit, Ashutosh
@ 2023-07-19 6:59 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-19 6:59 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 18-07-2023 10:37, Dixit, Ashutosh wrote:
> On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
> Back to this review.
>
>>>> On 06-07-2023 08:09, Dixit, Ashutosh wrote:
>>>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>>>
>>>>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>>>>>> +{
>>>>>> + u64 val = 0;
>>>>>> +
>>>>>> + switch (config) {
>>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>>>>>> + break;
>>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>>>>>> + break;
>>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>>>>>> + break;
>>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>>>>>> + break;
>>>>>> + default:
>>>>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>>>>>> + }
>>>>>> +
>>>>>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>>>>>> +}
>>>>>
>>>>> A few questions on just the above function first:
>>>>>
>>>>> 1. OK so these registers won't be available to VF's, but any idea what
>>>>> these counts are when VF's are active?
>>>>
>>>> VF's cannot access the registers but the counters will be incrementing
>>>> if respective engines are busy and can be monitored from PF and that
>>>> will be across all VFs.
>>>
>>> Ok, good.
>>>
>>>>
>>>>>
>>>>> 2. When would these 32 bit registers overflow? Let us say a group is
>>>>> continuously busy and we are running at 1 GHz, the registers would
>>>>> overflow in 4 seconds (max value 4G)?
>>>>
>>>> Based on BSPEC:52071 they use MHZ clock assuming the default 24MHz, it
>>>> would take around 5726 secs to overflow.
>>>
>>> OK, overflow should not be an issue then. Though I have seen 19.2 and 38.4
>>> MHz in OA. Also, if these are OAG registers, OA timestamp freq can be
>>> different from CS timestamp freq, so not sure if that needs to be
>>> handled. See i915_perf_oa_timestamp_frequency() in i915.
>>
>> so that is handled by below calculation
>
>>>>
>>>>>
>>>>> 3. What is the multiplication by 16 (not factored above in 2.)? I don't see
>>>>> that in Bspec.
>>>>
>>>> These counters are incremented based on crystal clock frequency and we
>>>> need to convert to CS time base hence a 16x mul. BSPEC:52071
>>>
>>> Hmm still don't see the 16x mul in BSPEC:52071. Anyway.
>>
>> lets say the frequency is 24MHz so the counter increments every
>> 1333.333ns(granularity) and corresponding cs timestamp base for this
>> frequency is 83.333ns, 1333.333/83.333 = 16 and this true for rest of
>> the frequency selections as well. hence we multiply the counter x 16.
>
> OK, I finally see in Bspec:71028: "Unit in GPMusec. Refer to Timestamp
> Bases for details" which is a pointer to Bspec: 52071. So the 16x multiply
> looks correct (and these registers are not running at OA freq otherwise
> we'd have to use i915_perf_oa_timestamp_frequency()). Hopefully it's
> correct. Thanks.
Thanks,
Aravind.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
` (3 preceding siblings ...)
2023-07-06 2:39 ` Dixit, Ashutosh
@ 2023-07-06 2:40 ` Belgaumkar, Vinay
2023-07-06 13:06 ` Iddamsetty, Aravind
2023-07-21 1:02 ` Dixit, Ashutosh
2023-07-22 14:39 ` Dixit, Ashutosh
6 siblings, 1 reply; 59+ messages in thread
From: Belgaumkar, Vinay @ 2023-07-06 2:40 UTC (permalink / raw)
To: intel-xe
On 6/27/2023 5:21 AM, aravind.iddamsetty at intel.com (Aravind
Iddamsetty) wrote:
> There are a set of engine group busyness counters provided by HW which are
> perfect fit to be exposed via PMU perf events.
>
> BSPEC: 46559, 46560, 46722, 46729
>
> events can be listed using:
> perf list
> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>
> and can be read using:
>
> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> time counts unit events
> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>
> The pmu base implementation is taken from i915.
>
> v2:
> Store last known value when device is awake return that while the GT is
> suspended and then update the driver copy when read during awake.
>
> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu at intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> drivers/gpu/drm/xe/xe_device.c | 2 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt.c | 2 +
> drivers/gpu/drm/xe/xe_irq.c | 22 +
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> include/uapi/drm/xe_drm.h | 16 +
> 11 files changed, 902 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 081c57fd8632..e52ab795c566 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/skl_universal_plane.o \
> i915-display/skl_watermark.o
>
> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> +
> ifeq ($(CONFIG_ACPI),y)
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_acpi.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..c7d9e4634745 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -285,6 +285,11 @@
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> +
> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index c7985af85a53..b2c7bd4a97d9 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_debugfs_register(xe);
>
> + xe_pmu_register(&xe->pmu);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 0226d44a6af2..3ba99aae92b9 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
> #include "xe_devcoredump_types.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> +#include "xe_pmu.h"
> #include "xe_step_types.h"
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> @@ -332,6 +333,9 @@ struct xe_device {
> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> bool d3cold_allowed;
>
> + /* @pmu: performance monitoring unit */
> + struct xe_pmu pmu;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index b4ed1e4a3388..cb943fb94ec7 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,6 +27,24 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> + irqreturn_t res)
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
> +}
> +
> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> {
> u32 val = xe_mmio_read32(mmio, reg);
> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> dg1_intr_enable(xe, false);
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> index 75e5be939f53..f6fe89748525 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -12,6 +12,7 @@
> #include "xe_hw_fence.h"
> #include "xe_module.h"
> #include "xe_pci.h"
> +#include "xe_pmu.h"
> #include "xe_sched_job.h"
>
> bool enable_guc = true;
> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> .init = xe_sched_job_module_init,
> .exit = xe_sched_job_module_exit,
> },
> + {
> + .init = xe_pmu_init,
> + .exit = xe_pmu_exit,
> + },
> {
> .init = xe_register_pci_driver,
> .exit = xe_unregister_pci_driver,
> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> new file mode 100644
> index 000000000000..bef1895be9f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> @@ -0,0 +1,739 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright ? 2023 Intel Corporation
> + */
> +
> +#include <drm/drm_drv.h>
> +#include <drm/drm_managed.h>
> +#include <drm/xe_drm.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt_clock.h"
> +#include "xe_mmio.h"
> +
> +static cpumask_t xe_pmu_cpumask;
> +static unsigned int xe_pmu_target_cpu = -1;
> +
> +static unsigned int config_gt_id(const u64 config)
> +{
> + return config >> __XE_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config)
> +{
> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
> +}
> +
> +static unsigned int
> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> +
> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
> +
> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
> +}
> +
> +static void
> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
> +{
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
> +}
> +
> +static int engine_busyness_sample_type(u64 config)
> +{
> + int type = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> + break;
> + }
> +
> + return type;
> +}
> +
> +static void xe_pmu_event_destroy(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> +
> + drm_WARN_ON(&xe->drm, event->parent);
> +
> + drm_dev_put(&xe->drm);
> +}
> +
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> +}
> +
> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> + int sample_type = engine_busyness_sample_type(config);
> + struct xe_device *xe = gt->tile->xe;
> + const unsigned int gt_id = gt->info.id;
> + struct xe_pmu *pmu = &xe->pmu;
> + bool device_awake;
> + unsigned long flags;
> + u64 val;
> +
> + /*
> + * found no better way to check if device is awake or not. Before
> + * we suspend we set the submission_state.enabled to false.
> + */
> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> + if (device_awake)
> + val = __engine_group_busyness_read(gt, config);
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + if (device_awake)
> + store_sample(pmu, gt_id, sample_type, val);
> + else
> + val = read_sample(pmu, gt_id, sample_type);
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +
> + return val;
> +}
> +
> +void engine_group_busyness_store(struct xe_gt *gt)
> +{
> + struct xe_pmu *pmu = >->tile->xe->pmu;
> + unsigned int gt_id = gt->info.id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +}
> +
> +static int
> +config_status(struct xe_device *xe, u64 config)
> +{
> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> + unsigned int gt_id = config_gt_id(config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> +
> + if (gt_id > max_gt_id)
> + return -ENOENT;
> +
> + switch (config_counter(config)) {
> + case XE_PMU_INTERRUPTS(0):
> + if (gt_id)
> + return -ENOENT;
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + if (GRAPHICS_VER(xe) < 12)
> + return -ENOENT;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
> + return -ENOENT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_pmu_event_init(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> + int ret;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* unsupported modes and filters */
> + if (event->attr.sample_period) /* no sampling */
> + return -EINVAL;
> +
> + if (has_branch_stack(event))
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /* only allow running on one cpu at a time */
> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> + return -EINVAL;
> +
> + ret = config_status(xe, event->attr.config);
> + if (ret)
> + return ret;
> +
> + if (!event->parent) {
> + drm_dev_get(&xe->drm);
> + event->destroy = xe_pmu_event_destroy;
> + }
> +
> + return 0;
> +}
> +
> +static u64 __xe_pmu_event_read(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + const unsigned int gt_id = config_gt_id(event->attr.config);
> + const u64 config = config_counter(event->attr.config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_INTERRUPTS(0):
> + val = READ_ONCE(pmu->irq_count);
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = engine_group_busyness_read(gt, config);
> + }
> +
> + return val;
> +}
> +
> +static void xe_pmu_event_read(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct hw_perf_event *hwc = &event->hw;
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 prev, new;
> +
> + if (pmu->closed) {
> + event->hw.state = PERF_HES_STOPPED;
> + return;
> + }
> +again:
> + prev = local64_read(&hwc->prev_count);
> + new = __xe_pmu_event_read(event);
> +
> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> + goto again;
> +
> + local64_add(new - prev, &event->count);
> +}
> +
> +static void xe_pmu_enable(struct perf_event *event)
> +{
> + /*
> + * Store the current counter value so we can report the correct delta
> + * for all listeners. Even when the event was already enabled and has
> + * an existing non-zero value.
> + */
> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> +}
> +
> +static void xe_pmu_event_start(struct perf_event *event, int flags)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return;
> +
> + xe_pmu_enable(event);
> + event->hw.state = 0;
> +}
> +
> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
> +{
> + if (flags & PERF_EF_UPDATE)
> + xe_pmu_event_read(event);
> +
> + event->hw.state = PERF_HES_STOPPED;
> +}
> +
> +static int xe_pmu_event_add(struct perf_event *event, int flags)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (flags & PERF_EF_START)
> + xe_pmu_event_start(event, flags);
> +
> + return 0;
> +}
> +
> +static void xe_pmu_event_del(struct perf_event *event, int flags)
> +{
> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
> +}
> +
> +static int xe_pmu_event_event_idx(struct perf_event *event)
> +{
> + return 0;
> +}
> +
> +struct xe_str_attribute {
> + struct device_attribute attr;
> + const char *str;
> +};
> +
> +static ssize_t xe_pmu_format_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct xe_str_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_str_attribute, attr);
> + return sprintf(buf, "%s\n", eattr->str);
> +}
> +
> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> + (&((struct xe_str_attribute[]) { \
> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
> + .str = _config, } \
> + })[0].attr.attr)
> +
> +static struct attribute *xe_pmu_format_attrs[] = {
> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_format_attr_group = {
> + .name = "format",
> + .attrs = xe_pmu_format_attrs,
> +};
> +
> +struct xe_ext_attribute {
> + struct device_attribute attr;
> + unsigned long val;
> +};
> +
> +static ssize_t xe_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct xe_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> + return sprintf(buf, "config=0x%lx\n", eattr->val);
> +}
> +
> +static ssize_t cpumask_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
> +}
> +
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *xe_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> + .attrs = xe_cpumask_attrs,
> +};
> +
> +#define __event(__counter, __name, __unit) \
> +{ \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = false, \
> +}
> +
> +#define __global_event(__counter, __name, __unit) \
> +{ \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = true, \
> +}
> +
> +static struct xe_ext_attribute *
> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = xe_pmu_event_show;
> + attr->val = config;
> +
> + return ++attr;
> +}
> +
> +static struct perf_pmu_events_attr *
> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> + const char *str)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = perf_event_sysfs_show;
> + attr->event_str = str;
> +
> + return ++attr;
> +}
> +
> +static struct attribute **
> +create_event_attributes(struct xe_pmu *pmu)
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + static const struct {
> + unsigned int counter;
> + const char *name;
> + const char *unit;
> + bool global;
> + } events[] = {
> + __global_event(0, "interrupts", NULL),
> + __event(1, "render-group-busy", "ns"),
> + __event(2, "copy-group-busy", "ns"),
> + __event(3, "media-group-busy", "ns"),
> + __event(4, "any-engine-group-busy", "ns"),
> + };
> +
> + unsigned int count = 0;
> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> + struct attribute **attr = NULL, **attr_iter;
> + struct xe_gt *gt;
> + unsigned int i, j;
> +
> + /* Count how many counters we will be exposing. */
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> +
> + if (!config_status(xe, config))
> + count++;
> + }
> + }
> +
> + /* Allocate attribute objects and table. */
> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> + if (!xe_attr)
> + goto err_alloc;
> +
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> + if (!pmu_attr)
> + goto err_alloc;
> +
> + /* Max one pointer of each attribute type plus a termination entry. */
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + goto err_alloc;
> +
> + xe_iter = xe_attr;
> + pmu_iter = pmu_attr;
> + attr_iter = attr;
> +
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> + char *str;
> +
> + if (config_status(xe, config))
> + continue;
> +
> + if (events[i].global)
> + str = kstrdup(events[i].name, GFP_KERNEL);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &xe_iter->attr.attr;
> + xe_iter = add_xe_attr(xe_iter, str, config);
> +
> + if (events[i].unit) {
> + if (events[i].global)
> + str = kasprintf(GFP_KERNEL, "%s.unit",
> + events[i].name);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &pmu_iter->attr.attr;
> + pmu_iter = add_pmu_attr(pmu_iter, str,
> + events[i].unit);
> + }
> + }
> + }
> +
> + pmu->xe_attr = xe_attr;
> + pmu->pmu_attr = pmu_attr;
> +
> + return attr;
> +
> +err:
> + for (attr_iter = attr; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> +err_alloc:
> + kfree(attr);
> + kfree(xe_attr);
> + kfree(pmu_attr);
> +
> + return NULL;
> +}
> +
> +static void free_event_attributes(struct xe_pmu *pmu)
> +{
> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> +
> + for (; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> + kfree(pmu->events_attr_group.attrs);
> + kfree(pmu->xe_attr);
> + kfree(pmu->pmu_attr);
> +
> + pmu->events_attr_group.attrs = NULL;
> + pmu->xe_attr = NULL;
> + pmu->pmu_attr = NULL;
> +}
> +
> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /* Select the first online CPU as a designated reader. */
> + if (cpumask_empty(&xe_pmu_cpumask))
> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> +
> + return 0;
> +}
> +
> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> + unsigned int target = xe_pmu_target_cpu;
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /*
> + * Unregistering an instance generates a CPU offline event which we must
> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
> + */
> + if (pmu->closed)
> + return 0;
> +
> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
> +
> + /* Migrate events if there is a valid target */
> + if (target < nr_cpu_ids) {
> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> + xe_pmu_target_cpu = target;
> + }
> + }
> +
> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> + pmu->cpuhp.cpu = target;
> + }
> +
> + return 0;
> +}
> +
> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> +
> +int xe_pmu_init(void)
> +{
> + int ret;
> +
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "perf/x86/intel/xe:online",
> + xe_pmu_cpu_online,
> + xe_pmu_cpu_offline);
> + if (ret < 0)
> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> + ret);
> + else
> + cpuhp_slot = ret;
> +
> + return 0;
> +}
> +
> +void xe_pmu_exit(void)
> +{
> + if (cpuhp_slot != CPUHP_INVALID)
> + cpuhp_remove_multi_state(cpuhp_slot);
> +}
> +
> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
> +{
> + if (cpuhp_slot == CPUHP_INVALID)
> + return -EINVAL;
> +
> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> +}
> +
> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
> +{
> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
> +}
> +
> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
> +{
> + struct xe_pmu *pmu = arg;
> +
> + if (!pmu->base.event_init)
> + return;
> +
> + /*
> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
> + * ensures all currently executing ones will have exited before we
> + * proceed with unregistration.
> + */
> + pmu->closed = true;
> + synchronize_rcu();
> +
> + xe_pmu_unregister_cpuhp_state(pmu);
> +
> + perf_pmu_unregister(&pmu->base);
> + pmu->base.event_init = NULL;
> + kfree(pmu->base.attr_groups);
> + kfree(pmu->name);
> + free_event_attributes(pmu);
> +}
> +
> +static void init_samples(struct xe_pmu *pmu)
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + struct xe_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, xe, i)
> + engine_group_busyness_store(gt);
> +}
> +
> +void xe_pmu_register(struct xe_pmu *pmu)
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + const struct attribute_group *attr_groups[] = {
> + &xe_pmu_format_attr_group,
> + &pmu->events_attr_group,
> + &xe_pmu_cpumask_attr_group,
> + NULL
> + };
> +
> + int ret = -ENOMEM;
> +
> + spin_lock_init(&pmu->lock);
> + pmu->cpuhp.cpu = -1;
> + init_samples(pmu);
> +
> + pmu->name = kasprintf(GFP_KERNEL,
> + "xe_%s",
> + dev_name(xe->drm.dev));
> + if (pmu->name)
> + /* tools/perf reserves colons as special. */
> + strreplace((char *)pmu->name, ':', '_');
> +
> + if (!pmu->name)
> + goto err;
> +
> + pmu->events_attr_group.name = "events";
> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> + if (!pmu->events_attr_group.attrs)
> + goto err_name;
> +
> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
> + GFP_KERNEL);
> + if (!pmu->base.attr_groups)
> + goto err_attr;
> +
> + pmu->base.module = THIS_MODULE;
> + pmu->base.task_ctx_nr = perf_invalid_context;
> + pmu->base.event_init = xe_pmu_event_init;
> + pmu->base.add = xe_pmu_event_add;
> + pmu->base.del = xe_pmu_event_del;
> + pmu->base.start = xe_pmu_event_start;
> + pmu->base.stop = xe_pmu_event_stop;
> + pmu->base.read = xe_pmu_event_read;
> + pmu->base.event_idx = xe_pmu_event_event_idx;
> +
> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> + if (ret)
> + goto err_groups;
> +
> + ret = xe_pmu_register_cpuhp_state(pmu);
> + if (ret)
> + goto err_unreg;
> +
> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
> + XE_WARN_ON(ret);
> +
> + return;
> +
> +err_unreg:
> + perf_pmu_unregister(&pmu->base);
> +err_groups:
> + kfree(pmu->base.attr_groups);
> +err_attr:
> + pmu->base.event_init = NULL;
> + free_event_attributes(pmu);
> +err_name:
> + kfree(pmu->name);
> +err:
> + drm_notice(&xe->drm, "Failed to register PMU!\n");
> +}
> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> new file mode 100644
> index 000000000000..d3f47f4ab343
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright ? 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_H_
> +#define _XE_PMU_H_
> +
> +#include "xe_gt_types.h"
> +#include "xe_pmu_types.h"
> +
> +#ifdef CONFIG_PERF_EVENTS
> +int xe_pmu_init(void);
> +void xe_pmu_exit(void);
> +void xe_pmu_register(struct xe_pmu *pmu);
> +void engine_group_busyness_store(struct xe_gt *gt);
> +#else
> +static inline int xe_pmu_init(void) { return 0; }
> +static inline void xe_pmu_exit(void) {}
> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
> +#endif
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
> new file mode 100644
> index 000000000000..e87edd4d6a87
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright ? 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_TYPES_H_
> +#define _XE_PMU_TYPES_H_
> +
> +#include <linux/perf_event.h>
> +#include <linux/spinlock_types.h>
> +#include <uapi/drm/xe_drm.h>
> +
> +enum {
> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __XE_SAMPLE_COPY_GROUP_BUSY,
> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __XE_NUM_PMU_SAMPLERS
> +};
> +
> +struct xe_pmu_sample {
> + u64 cur;
> +};
> +
> +#define XE_MAX_GT_PER_TILE 2
> +
> +struct xe_pmu {
> + /**
> + * @cpuhp: Struct used for CPU hotplug handling.
> + */
> + struct {
> + struct hlist_node node;
> + unsigned int cpu;
> + } cpuhp;
> + /**
> + * @base: PMU base.
> + */
> + struct pmu base;
Are we not adding this timer for xe (it exists in i915)?
/**
* @timer: Timer for internal i915 PMU sampling.
*/
struct hrtimer timer;
Thanks,
Vinay.
> + /**
> + * @closed: xe is unregistering.
> + */
> + bool closed;
> + /**
> + * @name: Name as registered with perf core.
> + */
> + const char *name;
> + /**
> + * @lock: Lock protecting enable mask and ref count handling.
> + */
> + spinlock_t lock;
> + /**
> + * @sample: Current and previous (raw) counters.
> + *
> + * These counters are updated when the device is awake.
> + *
> + */
> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
> + /**
> + * @irq_count: Number of interrupts
> + *
> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> + * occasional wraparound easily. It's 32bit after all.
> + */
> + unsigned long irq_count;
> + /**
> + * @events_attr_group: Device events attribute group.
> + */
> + struct attribute_group events_attr_group;
> + /**
> + * @xe_attr: Memory block holding device attributes.
> + */
> + void *xe_attr;
> + /**
> + * @pmu_attr: Memory block holding device attributes.
> + */
> + void *pmu_attr;
> +};
> +
> +#endif
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 965cd9527ff1..ed097056f944 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> __u64 reserved[2];
> };
>
> +/* PMU event config IDs */
> +
> +/*
> + * Top 4 bits of every counter are GT id.
> + */
> +#define __XE_PMU_GT_SHIFT (60)
> +
> +#define ___XE_PMU_OTHER(gt, x) \
> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> +
> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
> +
> #if defined(__cplusplus)
> }
> #endif
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-06 2:40 ` Belgaumkar, Vinay
@ 2023-07-06 13:06 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-06 13:06 UTC (permalink / raw)
To: Belgaumkar, Vinay, intel-xe
On 06-07-2023 08:10, Belgaumkar, Vinay wrote:
>
> On 6/27/2023 5:21 AM, aravind.iddamsetty at intel.com (Aravind
> Iddamsetty) wrote:
>> There are a set of engine group busyness counters provided by HW which
>> are
>> perfect fit to be exposed via PMU perf events.
>>
>> BSPEC: 46559, 46560, 46722, 46729
>>
>> events can be listed using:
>> perf list
>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>
>> and can be read using:
>>
>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>> time counts unit events
>> 1.001139062 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 2.003294678 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 3.005199582 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 4.007076497 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 5.008553068 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 6.010531563 43520 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 7.012468029 44800 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 8.013463515 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 9.015300183 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.017233010 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.971934120 0 ns
>> xe_0000_8c_00.0/render-group-busy-gt0/
>>
>> The pmu base implementation is taken from i915.
>>
>> v2:
>> Store last known value when device is awake return that while the GT is
>> suspended and then update the driver copy when read during awake.
>>
>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu at intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>> drivers/gpu/drm/xe/xe_device.c | 2 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>> drivers/gpu/drm/xe/xe_module.c | 5 +
>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>> include/uapi/drm/xe_drm.h | 16 +
>> 11 files changed, 902 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 081c57fd8632..e52ab795c566 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/skl_universal_plane.o \
>> i915-display/skl_watermark.o
>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>> +
>> ifeq ($(CONFIG_ACPI),y)
>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_acpi.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3f664011eaea..c7d9e4634745 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -285,6 +285,11 @@
>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>> +
>> #define SAMPLER_MODE XE_REG_MCR(0xe18c,
>> XE_REG_OPTION_MASKED)
>> #define ENABLE_SMALLPL REG_BIT(15)
>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c
>> index c7985af85a53..b2c7bd4a97d9 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>> xe_debugfs_register(xe);
>> + xe_pmu_register(&xe->pmu);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>> b/drivers/gpu/drm/xe/xe_device_types.h
>> index 0226d44a6af2..3ba99aae92b9 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -15,6 +15,7 @@
>> #include "xe_devcoredump_types.h"
>> #include "xe_gt_types.h"
>> #include "xe_platform_types.h"
>> +#include "xe_pmu.h"
>> #include "xe_step_types.h"
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> @@ -332,6 +333,9 @@ struct xe_device {
>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>> bool d3cold_allowed;
>> + /* @pmu: performance monitoring unit */
>> + struct xe_pmu pmu;
>> +
>> /* private: */
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>> index 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>> + engine_group_busyness_store(gt);
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index b4ed1e4a3388..cb943fb94ec7 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,6 +27,24 @@
>> #define IIR(offset) XE_REG(offset + 0x8)
>> #define IER(offset) XE_REG(offset + 0xc)
>> +/*
>> + * Interrupt statistic for PMU. Increments the counter only if the
>> + * interrupt originated from the GPU so interrupts from a device which
>> + * shares the interrupt line are not accounted.
>> + */
>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>> + irqreturn_t res)
>> +{
>> + if (unlikely(res != IRQ_HANDLED))
>> + return;
>> +
>> + /*
>> + * A clever compiler translates that into INC. A not so clever one
>> + * should at least prevent store tearing.
>> + */
>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
>> +}
>> +
>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
>> {
>> u32 val = xe_mmio_read32(mmio, reg);
>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void
>> *arg)
>> xe_display_irq_enable(xe, gu_misc_iir);
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void
>> *arg)
>> dg1_intr_enable(xe, false);
>> xe_display_irq_enable(xe, gu_misc_iir);
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_module.c
>> b/drivers/gpu/drm/xe/xe_module.c
>> index 75e5be939f53..f6fe89748525 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_fence.h"
>> #include "xe_module.h"
>> #include "xe_pci.h"
>> +#include "xe_pmu.h"
>> #include "xe_sched_job.h"
>> bool enable_guc = true;
>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>> .init = xe_sched_job_module_init,
>> .exit = xe_sched_job_module_exit,
>> },
>> + {
>> + .init = xe_pmu_init,
>> + .exit = xe_pmu_exit,
>> + },
>> {
>> .init = xe_register_pci_driver,
>> .exit = xe_unregister_pci_driver,
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> new file mode 100644
>> index 000000000000..bef1895be9f7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -0,0 +1,739 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright ? 2023 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_drv.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "regs/xe_gt_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt_clock.h"
>> +#include "xe_mmio.h"
>> +
>> +static cpumask_t xe_pmu_cpumask;
>> +static unsigned int xe_pmu_target_cpu = -1;
>> +
>> +static unsigned int config_gt_id(const u64 config)
>> +{
>> + return config >> __XE_PMU_GT_SHIFT;
>> +}
>> +
>> +static u64 config_counter(const u64 config)
>> +{
>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
>> +}
>> +
>> +static unsigned int
>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>> +{
>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>> +
>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>> +
>> + return idx;
>> +}
>> +
>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int
>> sample)
>> +{
>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
>> +}
>> +
>> +static void
>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64
>> val)
>> +{
>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
>> +}
>> +
>> +static int engine_busyness_sample_type(u64 config)
>> +{
>> + int type = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>> + break;
>> + }
>> +
>> + return type;
>> +}
>> +
>> +static void xe_pmu_event_destroy(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> +
>> + drm_WARN_ON(&xe->drm, event->parent);
>> +
>> + drm_dev_put(&xe->drm);
>> +}
>> +
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>> +{
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>> +}
>> +
>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
>> +{
>> + int sample_type = engine_busyness_sample_type(config);
>> + struct xe_device *xe = gt->tile->xe;
>> + const unsigned int gt_id = gt->info.id;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + bool device_awake;
>> + unsigned long flags;
>> + u64 val;
>> +
>> + /*
>> + * found no better way to check if device is awake or not. Before
>> + * we suspend we set the submission_state.enabled to false.
>> + */
>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>> + if (device_awake)
>> + val = __engine_group_busyness_read(gt, config);
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + if (device_awake)
>> + store_sample(pmu, gt_id, sample_type, val);
>> + else
>> + val = read_sample(pmu, gt_id, sample_type);
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +
>> + return val;
>> +}
>> +
>> +void engine_group_busyness_store(struct xe_gt *gt)
>> +{
>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>> + unsigned int gt_id = gt->info.id;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_RENDER_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_COPY_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_MEDIA_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __engine_group_busyness_read(gt,
>> XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +}
>> +
>> +static int
>> +config_status(struct xe_device *xe, u64 config)
>> +{
>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>> + unsigned int gt_id = config_gt_id(config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> +
>> + if (gt_id > max_gt_id)
>> + return -ENOENT;
>> +
>> + switch (config_counter(config)) {
>> + case XE_PMU_INTERRUPTS(0):
>> + if (gt_id)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + if (GRAPHICS_VER(xe) < 12)
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
>> + return -ENOENT;
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_event_init(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + int ret;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* unsupported modes and filters */
>> + if (event->attr.sample_period) /* no sampling */
>> + return -EINVAL;
>> +
>> + if (has_branch_stack(event))
>> + return -EOPNOTSUPP;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /* only allow running on one cpu at a time */
>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>> + return -EINVAL;
>> +
>> + ret = config_status(xe, event->attr.config);
>> + if (ret)
>> + return ret;
>> +
>> + if (!event->parent) {
>> + drm_dev_get(&xe->drm);
>> + event->destroy = xe_pmu_event_destroy;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static u64 __xe_pmu_event_read(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>> + const u64 config = config_counter(event->attr.config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_INTERRUPTS(0):
>> + val = READ_ONCE(pmu->irq_count);
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = engine_group_busyness_read(gt, config);
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static void xe_pmu_event_read(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 prev, new;
>> +
>> + if (pmu->closed) {
>> + event->hw.state = PERF_HES_STOPPED;
>> + return;
>> + }
>> +again:
>> + prev = local64_read(&hwc->prev_count);
>> + new = __xe_pmu_event_read(event);
>> +
>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>> + goto again;
>> +
>> + local64_add(new - prev, &event->count);
>> +}
>> +
>> +static void xe_pmu_enable(struct perf_event *event)
>> +{
>> + /*
>> + * Store the current counter value so we can report the correct
>> delta
>> + * for all listeners. Even when the event was already enabled and
>> has
>> + * an existing non-zero value.
>> + */
>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>> +}
>> +
>> +static void xe_pmu_event_start(struct perf_event *event, int flags)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return;
>> +
>> + xe_pmu_enable(event);
>> + event->hw.state = 0;
>> +}
>> +
>> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
>> +{
>> + if (flags & PERF_EF_UPDATE)
>> + xe_pmu_event_read(event);
>> +
>> + event->hw.state = PERF_HES_STOPPED;
>> +}
>> +
>> +static int xe_pmu_event_add(struct perf_event *event, int flags)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (flags & PERF_EF_START)
>> + xe_pmu_event_start(event, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_pmu_event_del(struct perf_event *event, int flags)
>> +{
>> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
>> +}
>> +
>> +static int xe_pmu_event_event_idx(struct perf_event *event)
>> +{
>> + return 0;
>> +}
>> +
>> +struct xe_str_attribute {
>> + struct device_attribute attr;
>> + const char *str;
>> +};
>> +
>> +static ssize_t xe_pmu_format_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct xe_str_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>> + return sprintf(buf, "%s\n", eattr->str);
>> +}
>> +
>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>> + (&((struct xe_str_attribute[]) { \
>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
>> + .str = _config, } \
>> + })[0].attr.attr)
>> +
>> +static struct attribute *xe_pmu_format_attrs[] = {
>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_format_attr_group = {
>> + .name = "format",
>> + .attrs = xe_pmu_format_attrs,
>> +};
>> +
>> +struct xe_ext_attribute {
>> + struct device_attribute attr;
>> + unsigned long val;
>> +};
>> +
>> +static ssize_t xe_pmu_event_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct xe_ext_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>> + return sprintf(buf, "config=0x%lx\n", eattr->val);
>> +}
>> +
>> +static ssize_t cpumask_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
>> +}
>> +
>> +static DEVICE_ATTR_RO(cpumask);
>> +
>> +static struct attribute *xe_cpumask_attrs[] = {
>> + &dev_attr_cpumask.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>> + .attrs = xe_cpumask_attrs,
>> +};
>> +
>> +#define __event(__counter, __name, __unit) \
>> +{ \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = false, \
>> +}
>> +
>> +#define __global_event(__counter, __name, __unit) \
>> +{ \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = true, \
>> +}
>> +
>> +static struct xe_ext_attribute *
>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = xe_pmu_event_show;
>> + attr->val = config;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct perf_pmu_events_attr *
>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>> + const char *str)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = perf_event_sysfs_show;
>> + attr->event_str = str;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct attribute **
>> +create_event_attributes(struct xe_pmu *pmu)
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + static const struct {
>> + unsigned int counter;
>> + const char *name;
>> + const char *unit;
>> + bool global;
>> + } events[] = {
>> + __global_event(0, "interrupts", NULL),
>> + __event(1, "render-group-busy", "ns"),
>> + __event(2, "copy-group-busy", "ns"),
>> + __event(3, "media-group-busy", "ns"),
>> + __event(4, "any-engine-group-busy", "ns"),
>> + };
>> +
>> + unsigned int count = 0;
>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>> + struct attribute **attr = NULL, **attr_iter;
>> + struct xe_gt *gt;
>> + unsigned int i, j;
>> +
>> + /* Count how many counters we will be exposing. */
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>> +
>> + if (!config_status(xe, config))
>> + count++;
>> + }
>> + }
>> +
>> + /* Allocate attribute objects and table. */
>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>> + if (!xe_attr)
>> + goto err_alloc;
>> +
>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>> + if (!pmu_attr)
>> + goto err_alloc;
>> +
>> + /* Max one pointer of each attribute type plus a termination
>> entry. */
>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + goto err_alloc;
>> +
>> + xe_iter = xe_attr;
>> + pmu_iter = pmu_attr;
>> + attr_iter = attr;
>> +
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>> + char *str;
>> +
>> + if (config_status(xe, config))
>> + continue;
>> +
>> + if (events[i].global)
>> + str = kstrdup(events[i].name, GFP_KERNEL);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &xe_iter->attr.attr;
>> + xe_iter = add_xe_attr(xe_iter, str, config);
>> +
>> + if (events[i].unit) {
>> + if (events[i].global)
>> + str = kasprintf(GFP_KERNEL, "%s.unit",
>> + events[i].name);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &pmu_iter->attr.attr;
>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>> + events[i].unit);
>> + }
>> + }
>> + }
>> +
>> + pmu->xe_attr = xe_attr;
>> + pmu->pmu_attr = pmu_attr;
>> +
>> + return attr;
>> +
>> +err:
>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> +err_alloc:
>> + kfree(attr);
>> + kfree(xe_attr);
>> + kfree(pmu_attr);
>> +
>> + return NULL;
>> +}
>> +
>> +static void free_event_attributes(struct xe_pmu *pmu)
>> +{
>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>> +
>> + for (; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> + kfree(pmu->events_attr_group.attrs);
>> + kfree(pmu->xe_attr);
>> + kfree(pmu->pmu_attr);
>> +
>> + pmu->events_attr_group.attrs = NULL;
>> + pmu->xe_attr = NULL;
>> + pmu->pmu_attr = NULL;
>> +}
>> +
>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /* Select the first online CPU as a designated reader. */
>> + if (cpumask_empty(&xe_pmu_cpumask))
>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>> cpuhp.node);
>> + unsigned int target = xe_pmu_target_cpu;
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /*
>> + * Unregistering an instance generates a CPU offline event which
>> we must
>> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
>> + */
>> + if (pmu->closed)
>> + return 0;
>> +
>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
>> +
>> + /* Migrate events if there is a valid target */
>> + if (target < nr_cpu_ids) {
>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>> + xe_pmu_target_cpu = target;
>> + }
>> + }
>> +
>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>> + pmu->cpuhp.cpu = target;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>> +
>> +int xe_pmu_init(void)
>> +{
>> + int ret;
>> +
>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> + "perf/x86/intel/xe:online",
>> + xe_pmu_cpu_online,
>> + xe_pmu_cpu_offline);
>> + if (ret < 0)
>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>> + ret);
>> + else
>> + cpuhp_slot = ret;
>> +
>> + return 0;
>> +}
>> +
>> +void xe_pmu_exit(void)
>> +{
>> + if (cpuhp_slot != CPUHP_INVALID)
>> + cpuhp_remove_multi_state(cpuhp_slot);
>> +}
>> +
>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
>> +{
>> + if (cpuhp_slot == CPUHP_INVALID)
>> + return -EINVAL;
>> +
>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
>> +}
>> +
>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
>> +{
>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
>> +}
>> +
>> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
>> +{
>> + struct xe_pmu *pmu = arg;
>> +
>> + if (!pmu->base.event_init)
>> + return;
>> +
>> + /*
>> + * "Disconnect" the PMU callbacks - since all are atomic
>> synchronize_rcu
>> + * ensures all currently executing ones will have exited before we
>> + * proceed with unregistration.
>> + */
>> + pmu->closed = true;
>> + synchronize_rcu();
>> +
>> + xe_pmu_unregister_cpuhp_state(pmu);
>> +
>> + perf_pmu_unregister(&pmu->base);
>> + pmu->base.event_init = NULL;
>> + kfree(pmu->base.attr_groups);
>> + kfree(pmu->name);
>> + free_event_attributes(pmu);
>> +}
>> +
>> +static void init_samples(struct xe_pmu *pmu)
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + struct xe_gt *gt;
>> + unsigned int i;
>> +
>> + for_each_gt(gt, xe, i)
>> + engine_group_busyness_store(gt);
>> +}
>> +
>> +void xe_pmu_register(struct xe_pmu *pmu)
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + const struct attribute_group *attr_groups[] = {
>> + &xe_pmu_format_attr_group,
>> + &pmu->events_attr_group,
>> + &xe_pmu_cpumask_attr_group,
>> + NULL
>> + };
>> +
>> + int ret = -ENOMEM;
>> +
>> + spin_lock_init(&pmu->lock);
>> + pmu->cpuhp.cpu = -1;
>> + init_samples(pmu);
>> +
>> + pmu->name = kasprintf(GFP_KERNEL,
>> + "xe_%s",
>> + dev_name(xe->drm.dev));
>> + if (pmu->name)
>> + /* tools/perf reserves colons as special. */
>> + strreplace((char *)pmu->name, ':', '_');
>> +
>> + if (!pmu->name)
>> + goto err;
>> +
>> + pmu->events_attr_group.name = "events";
>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>> + if (!pmu->events_attr_group.attrs)
>> + goto err_name;
>> +
>> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
>> + GFP_KERNEL);
>> + if (!pmu->base.attr_groups)
>> + goto err_attr;
>> +
>> + pmu->base.module = THIS_MODULE;
>> + pmu->base.task_ctx_nr = perf_invalid_context;
>> + pmu->base.event_init = xe_pmu_event_init;
>> + pmu->base.add = xe_pmu_event_add;
>> + pmu->base.del = xe_pmu_event_del;
>> + pmu->base.start = xe_pmu_event_start;
>> + pmu->base.stop = xe_pmu_event_stop;
>> + pmu->base.read = xe_pmu_event_read;
>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>> +
>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>> + if (ret)
>> + goto err_groups;
>> +
>> + ret = xe_pmu_register_cpuhp_state(pmu);
>> + if (ret)
>> + goto err_unreg;
>> +
>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
>> + XE_WARN_ON(ret);
>> +
>> + return;
>> +
>> +err_unreg:
>> + perf_pmu_unregister(&pmu->base);
>> +err_groups:
>> + kfree(pmu->base.attr_groups);
>> +err_attr:
>> + pmu->base.event_init = NULL;
>> + free_event_attributes(pmu);
>> +err_name:
>> + kfree(pmu->name);
>> +err:
>> + drm_notice(&xe->drm, "Failed to register PMU!\n");
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>> new file mode 100644
>> index 000000000000..d3f47f4ab343
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright ? 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_H_
>> +#define _XE_PMU_H_
>> +
>> +#include "xe_gt_types.h"
>> +#include "xe_pmu_types.h"
>> +
>> +#ifdef CONFIG_PERF_EVENTS
>> +int xe_pmu_init(void);
>> +void xe_pmu_exit(void);
>> +void xe_pmu_register(struct xe_pmu *pmu);
>> +void engine_group_busyness_store(struct xe_gt *gt);
>> +#else
>> +static inline int xe_pmu_init(void) { return 0; }
>> +static inline void xe_pmu_exit(void) {}
>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
>> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
>> +#endif
>> +
>> +#endif
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
>> b/drivers/gpu/drm/xe/xe_pmu_types.h
>> new file mode 100644
>> index 000000000000..e87edd4d6a87
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright ? 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_TYPES_H_
>> +#define _XE_PMU_TYPES_H_
>> +
>> +#include <linux/perf_event.h>
>> +#include <linux/spinlock_types.h>
>> +#include <uapi/drm/xe_drm.h>
>> +
>> +enum {
>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __XE_NUM_PMU_SAMPLERS
>> +};
>> +
>> +struct xe_pmu_sample {
>> + u64 cur;
>> +};
>> +
>> +#define XE_MAX_GT_PER_TILE 2
>> +
>> +struct xe_pmu {
>> + /**
>> + * @cpuhp: Struct used for CPU hotplug handling.
>> + */
>> + struct {
>> + struct hlist_node node;
>> + unsigned int cpu;
>> + } cpuhp;
>> + /**
>> + * @base: PMU base.
>> + */
>> + struct pmu base;
>
> Are we not adding this timer for xe (it exists in i915)?
>
> /**
> * @timer: Timer for internal i915 PMU sampling.
> */
> struct hrtimer timer;
In my current implementation i have limited to expose only OA engine
counters which doesn't need an internal sampling timer as we directly
read from OA HW registers.
Thanks,
Aravind.
>
> Thanks,
>
> Vinay.
>
>> + /**
>> + * @closed: xe is unregistering.
>> + */
>> + bool closed;
>> + /**
>> + * @name: Name as registered with perf core.
>> + */
>> + const char *name;
>> + /**
>> + * @lock: Lock protecting enable mask and ref count handling.
>> + */
>> + spinlock_t lock;
>> + /**
>> + * @sample: Current and previous (raw) counters.
>> + *
>> + * These counters are updated when the device is awake.
>> + *
>> + */
>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
>> __XE_NUM_PMU_SAMPLERS];
>> + /**
>> + * @irq_count: Number of interrupts
>> + *
>> + * Intentionally unsigned long to avoid atomics or heuristics on
>> 32bit.
>> + * 4e9 interrupts are a lot and postprocessing can really deal
>> with an
>> + * occasional wraparound easily. It's 32bit after all.
>> + */
>> + unsigned long irq_count;
>> + /**
>> + * @events_attr_group: Device events attribute group.
>> + */
>> + struct attribute_group events_attr_group;
>> + /**
>> + * @xe_attr: Memory block holding device attributes.
>> + */
>> + void *xe_attr;
>> + /**
>> + * @pmu_attr: Memory block holding device attributes.
>> + */
>> + void *pmu_attr;
>> +};
>> +
>> +#endif
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 965cd9527ff1..ed097056f944 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>> __u64 reserved[2];
>> };
>> +/* PMU event config IDs */
>> +
>> +/*
>> + * Top 4 bits of every counter are GT id.
>> + */
>> +#define __XE_PMU_GT_SHIFT (60)
>> +
>> +#define ___XE_PMU_OTHER(gt, x) \
>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>> +
>> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
>> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
>> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
` (4 preceding siblings ...)
2023-07-06 2:40 ` Belgaumkar, Vinay
@ 2023-07-21 1:02 ` Dixit, Ashutosh
2023-07-21 11:51 ` Iddamsetty, Aravind
2023-07-22 14:39 ` Dixit, Ashutosh
6 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-21 1:02 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>
Hi Aravind,
More stuff to mull over. You can ignore comments starting with "OK", those
are just notes to myself.
Also, maybe some time we can add a basic IGT which reads these exposed
counters and verifies that we can read them and they are monotonically
increasing?
> There are a set of engine group busyness counters provided by HW which are
> perfect fit to be exposed via PMU perf events.
>
> BSPEC: 46559, 46560, 46722, 46729
Also add these Bspec entries: 71028, 52071
>
> events can be listed using:
> perf list
> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>
> and can be read using:
>
> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> time counts unit events
> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>
> The pmu base implementation is taken from i915.
>
> v2:
> Store last known value when device is awake return that while the GT is
> suspended and then update the driver copy when read during awake.
>
> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> drivers/gpu/drm/xe/xe_device.c | 2 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt.c | 2 +
> drivers/gpu/drm/xe/xe_irq.c | 22 +
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> include/uapi/drm/xe_drm.h | 16 +
> 11 files changed, 902 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 081c57fd8632..e52ab795c566 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/skl_universal_plane.o \
> i915-display/skl_watermark.o
>
> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> +
> ifeq ($(CONFIG_ACPI),y)
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_acpi.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..c7d9e4634745 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -285,6 +285,11 @@
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> +
> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index c7985af85a53..b2c7bd4a97d9 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_debugfs_register(xe);
>
> + xe_pmu_register(&xe->pmu);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 0226d44a6af2..3ba99aae92b9 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
> #include "xe_devcoredump_types.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> +#include "xe_pmu.h"
> #include "xe_step_types.h"
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> @@ -332,6 +333,9 @@ struct xe_device {
> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> bool d3cold_allowed;
>
> + /* @pmu: performance monitoring unit */
> + struct xe_pmu pmu;
> +
Now I am wondering why we don't make the PMU per-gt (or per-tile)? Per-gt
would work for these busyness registers and I am not sure how the
interrupts are hooked up.
In i915 the PMU being device level helped in having a single timer (rather
than a per gt timer).
Anyway probably not much practical benefit by make it per-gt/per-tile, so
maybe leave as is. Just thinking out loud.
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
Not sure I follow the reason for doing this at suspend time? If PMU was
active there should be a previous value. Why must we take a new sample
explicitly here?
To me looks like engine_group_busyness_store should not be needed, see
comment below for init_samples too.
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index b4ed1e4a3388..cb943fb94ec7 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,6 +27,24 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
No inline, compiler will do it, but looks like we may want to always_inline
this. Also this function should really be in xe_pmu.h? Anyway probably
leave as is.
> + irqreturn_t res)
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
> +}
> +
> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> {
> u32 val = xe_mmio_read32(mmio, reg);
> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> dg1_intr_enable(xe, false);
> xe_display_irq_enable(xe, gu_misc_iir);
>
> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> index 75e5be939f53..f6fe89748525 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -12,6 +12,7 @@
> #include "xe_hw_fence.h"
> #include "xe_module.h"
> #include "xe_pci.h"
> +#include "xe_pmu.h"
> #include "xe_sched_job.h"
>
> bool enable_guc = true;
> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> .init = xe_sched_job_module_init,
> .exit = xe_sched_job_module_exit,
> },
> + {
> + .init = xe_pmu_init,
> + .exit = xe_pmu_exit,
> + },
> {
> .init = xe_register_pci_driver,
> .exit = xe_unregister_pci_driver,
> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> new file mode 100644
> index 000000000000..bef1895be9f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> @@ -0,0 +1,739 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2023 Intel Corporation
> + */
This SPDX header is for .h files not .c files. Actually, it is for neither :/
> +
> +#include <drm/drm_drv.h>
> +#include <drm/drm_managed.h>
> +#include <drm/xe_drm.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt_clock.h"
> +#include "xe_mmio.h"
> +
> +static cpumask_t xe_pmu_cpumask;
> +static unsigned int xe_pmu_target_cpu = -1;
> +
> +static unsigned int config_gt_id(const u64 config)
> +{
> + return config >> __XE_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config)
> +{
> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
> +}
> +
> +static unsigned int
> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> +
> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
The compiler does this for us if we make sample array 2-d.
> +
> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
> +}
> +
> +static void
> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
> +{
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
> +}
The three functions above are not needed if we make the sample array
2-d. See here:
https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
Only a part of the patch above was merged (see 8ed0753b527dc) to keep the
patch size small, but since for xe we are starting from scratch we can
implement the whole approach above (get rid of the read/store helpers
entirely, direct assignment without the helpers works).
> +
> +static int engine_busyness_sample_type(u64 config)
> +{
> + int type = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> + break;
> + }
> +
> + return type;
> +}
> +
> +static void xe_pmu_event_destroy(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> +
> + drm_WARN_ON(&xe->drm, event->parent);
> +
> + drm_dev_put(&xe->drm);
> +}
> +
> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> + break;
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> + break;
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> + break;
> + default:
> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> + }
We need xe_device_mem_access_get, also xe_force_wake_get if applicable,
somewhere before reading these registers.
> +
> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> +}
> +
> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
> +{
> + int sample_type = engine_busyness_sample_type(config);
> + struct xe_device *xe = gt->tile->xe;
> + const unsigned int gt_id = gt->info.id;
> + struct xe_pmu *pmu = &xe->pmu;
> + bool device_awake;
> + unsigned long flags;
> + u64 val;
> +
> + /*
> + * found no better way to check if device is awake or not. Before
xe_device_mem_access_get_if_ongoing (hard to find name).
> + * we suspend we set the submission_state.enabled to false.
> + */
> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> + if (device_awake)
> + val = __engine_group_busyness_read(gt, config);
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + if (device_awake)
> + store_sample(pmu, gt_id, sample_type, val);
> + else
> + val = read_sample(pmu, gt_id, sample_type);
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +
> + return val;
> +}
> +
> +void engine_group_busyness_store(struct xe_gt *gt)
> +{
> + struct xe_pmu *pmu = >->tile->xe->pmu;
> + unsigned int gt_id = gt->info.id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pmu->lock, flags);
> +
> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> +
> + spin_unlock_irqrestore(&pmu->lock, flags);
> +}
> +
> +static int
> +config_status(struct xe_device *xe, u64 config)
> +{
> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> + unsigned int gt_id = config_gt_id(config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> +
> + if (gt_id > max_gt_id)
> + return -ENOENT;
> +
> + switch (config_counter(config)) {
> + case XE_PMU_INTERRUPTS(0):
> + if (gt_id)
> + return -ENOENT;
OK: this is a global event so we say this is enabled only for gt0.
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + if (GRAPHICS_VER(xe) < 12)
Any point checking? xe only supports Gen12+.
> + return -ENOENT;
> + break;
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
> + return -ENOENT;
OK: this makes sense, so we will expose this event only for media gt's.
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_pmu_event_init(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> + int ret;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* unsupported modes and filters */
> + if (event->attr.sample_period) /* no sampling */
> + return -EINVAL;
> +
> + if (has_branch_stack(event))
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /* only allow running on one cpu at a time */
> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> + return -EINVAL;
> +
> + ret = config_status(xe, event->attr.config);
> + if (ret)
> + return ret;
> +
> + if (!event->parent) {
> + drm_dev_get(&xe->drm);
> + event->destroy = xe_pmu_event_destroy;
> + }
> +
> + return 0;
> +}
> +
> +static u64 __xe_pmu_event_read(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + const unsigned int gt_id = config_gt_id(event->attr.config);
> + const u64 config = config_counter(event->attr.config);
> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 val = 0;
> +
> + switch (config) {
> + case XE_PMU_INTERRUPTS(0):
> + val = READ_ONCE(pmu->irq_count);
OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff would
be to take pmu->lock (both while reading and writing irq_count) but that
would be expensive in the interrupt handler (as the .h hints). So all we
can do is what is done here.
> + break;
> + case XE_PMU_RENDER_GROUP_BUSY(0):
> + case XE_PMU_COPY_GROUP_BUSY(0):
> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> + val = engine_group_busyness_read(gt, config);
> + }
> +
> + return val;
> +}
> +
> +static void xe_pmu_event_read(struct perf_event *event)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct hw_perf_event *hwc = &event->hw;
> + struct xe_pmu *pmu = &xe->pmu;
> + u64 prev, new;
> +
> + if (pmu->closed) {
> + event->hw.state = PERF_HES_STOPPED;
> + return;
> + }
> +again:
> + prev = local64_read(&hwc->prev_count);
> + new = __xe_pmu_event_read(event);
> +
> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> + goto again;
> +
> + local64_add(new - prev, &event->count);
> +}
> +
> +static void xe_pmu_enable(struct perf_event *event)
> +{
> + /*
> + * Store the current counter value so we can report the correct delta
> + * for all listeners. Even when the event was already enabled and has
> + * an existing non-zero value.
> + */
> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> +}
> +
> +static void xe_pmu_event_start(struct perf_event *event, int flags)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return;
> +
> + xe_pmu_enable(event);
> + event->hw.state = 0;
> +}
> +
> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
> +{
> + if (flags & PERF_EF_UPDATE)
> + xe_pmu_event_read(event);
> +
> + event->hw.state = PERF_HES_STOPPED;
> +}
> +
> +static int xe_pmu_event_add(struct perf_event *event, int flags)
> +{
> + struct xe_device *xe =
> + container_of(event->pmu, typeof(*xe), pmu.base);
> + struct xe_pmu *pmu = &xe->pmu;
> +
> + if (pmu->closed)
> + return -ENODEV;
> +
> + if (flags & PERF_EF_START)
> + xe_pmu_event_start(event, flags);
> +
> + return 0;
> +}
> +
> +static void xe_pmu_event_del(struct perf_event *event, int flags)
> +{
> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
> +}
> +
> +static int xe_pmu_event_event_idx(struct perf_event *event)
> +{
> + return 0;
> +}
> +
> +struct xe_str_attribute {
> + struct device_attribute attr;
> + const char *str;
> +};
> +
> +static ssize_t xe_pmu_format_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct xe_str_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_str_attribute, attr);
> + return sprintf(buf, "%s\n", eattr->str);
> +}
> +
> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> + (&((struct xe_str_attribute[]) { \
> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
> + .str = _config, } \
> + })[0].attr.attr)
> +
> +static struct attribute *xe_pmu_format_attrs[] = {
> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
0-20 means 0-20 bits? Though here we probably have different number of
config bits? Probably doesn't matter?
The string will show up with:
cat /sys/devices/xe/format/xe_eventid
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_format_attr_group = {
> + .name = "format",
> + .attrs = xe_pmu_format_attrs,
> +};
> +
> +struct xe_ext_attribute {
> + struct device_attribute attr;
> + unsigned long val;
> +};
> +
> +static ssize_t xe_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct xe_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> + return sprintf(buf, "config=0x%lx\n", eattr->val);
> +}
> +
> +static ssize_t cpumask_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
> +}
> +
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *xe_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> + .attrs = xe_cpumask_attrs,
> +};
> +
> +#define __event(__counter, __name, __unit) \
> +{ \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = false, \
> +}
> +
> +#define __global_event(__counter, __name, __unit) \
> +{ \
> + .counter = (__counter), \
> + .name = (__name), \
> + .unit = (__unit), \
> + .global = true, \
> +}
> +
> +static struct xe_ext_attribute *
> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = xe_pmu_event_show;
> + attr->val = config;
> +
> + return ++attr;
> +}
> +
> +static struct perf_pmu_events_attr *
> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> + const char *str)
> +{
> + sysfs_attr_init(&attr->attr.attr);
> + attr->attr.attr.name = name;
> + attr->attr.attr.mode = 0444;
> + attr->attr.show = perf_event_sysfs_show;
> + attr->event_str = str;
> +
> + return ++attr;
> +}
> +
> +static struct attribute **
> +create_event_attributes(struct xe_pmu *pmu)
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + static const struct {
> + unsigned int counter;
> + const char *name;
> + const char *unit;
> + bool global;
> + } events[] = {
> + __global_event(0, "interrupts", NULL),
> + __event(1, "render-group-busy", "ns"),
> + __event(2, "copy-group-busy", "ns"),
> + __event(3, "media-group-busy", "ns"),
> + __event(4, "any-engine-group-busy", "ns"),
> + };
OK: this function is some black magic to expose stuff through
PMU. Identical to i915 and seems to be working from the commit message so
should be fine.
> +
> + unsigned int count = 0;
> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> + struct attribute **attr = NULL, **attr_iter;
> + struct xe_gt *gt;
> + unsigned int i, j;
> +
> + /* Count how many counters we will be exposing. */
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> +
> + if (!config_status(xe, config))
> + count++;
> + }
> + }
> +
> + /* Allocate attribute objects and table. */
> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> + if (!xe_attr)
> + goto err_alloc;
> +
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> + if (!pmu_attr)
> + goto err_alloc;
> +
> + /* Max one pointer of each attribute type plus a termination entry. */
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + goto err_alloc;
> +
> + xe_iter = xe_attr;
> + pmu_iter = pmu_attr;
> + attr_iter = attr;
> +
> + for_each_gt(gt, xe, j) {
> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> + char *str;
> +
> + if (config_status(xe, config))
> + continue;
> +
> + if (events[i].global)
> + str = kstrdup(events[i].name, GFP_KERNEL);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &xe_iter->attr.attr;
> + xe_iter = add_xe_attr(xe_iter, str, config);
> +
> + if (events[i].unit) {
> + if (events[i].global)
> + str = kasprintf(GFP_KERNEL, "%s.unit",
> + events[i].name);
> + else
> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
> + events[i].name, j);
> + if (!str)
> + goto err;
> +
> + *attr_iter++ = &pmu_iter->attr.attr;
> + pmu_iter = add_pmu_attr(pmu_iter, str,
> + events[i].unit);
> + }
> + }
> + }
> +
> + pmu->xe_attr = xe_attr;
> + pmu->pmu_attr = pmu_attr;
> +
> + return attr;
> +
> +err:
> + for (attr_iter = attr; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> +err_alloc:
> + kfree(attr);
> + kfree(xe_attr);
> + kfree(pmu_attr);
> +
> + return NULL;
> +}
> +
> +static void free_event_attributes(struct xe_pmu *pmu)
> +{
> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> +
> + for (; *attr_iter; attr_iter++)
> + kfree((*attr_iter)->name);
> +
> + kfree(pmu->events_attr_group.attrs);
> + kfree(pmu->xe_attr);
> + kfree(pmu->pmu_attr);
> +
> + pmu->events_attr_group.attrs = NULL;
> + pmu->xe_attr = NULL;
> + pmu->pmu_attr = NULL;
> +}
> +
> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /* Select the first online CPU as a designated reader. */
> + if (cpumask_empty(&xe_pmu_cpumask))
> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> +
> + return 0;
> +}
> +
> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
> +{
> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> + unsigned int target = xe_pmu_target_cpu;
> +
> + XE_BUG_ON(!pmu->base.event_init);
> +
> + /*
> + * Unregistering an instance generates a CPU offline event which we must
> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
> + */
> + if (pmu->closed)
> + return 0;
> +
> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
> +
> + /* Migrate events if there is a valid target */
> + if (target < nr_cpu_ids) {
> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> + xe_pmu_target_cpu = target;
> + }
> + }
> +
> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> + pmu->cpuhp.cpu = target;
> + }
> +
> + return 0;
> +}
> +
> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> +
> +int xe_pmu_init(void)
> +{
> + int ret;
> +
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "perf/x86/intel/xe:online",
> + xe_pmu_cpu_online,
> + xe_pmu_cpu_offline);
> + if (ret < 0)
> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> + ret);
> + else
> + cpuhp_slot = ret;
> +
> + return 0;
> +}
> +
> +void xe_pmu_exit(void)
> +{
> + if (cpuhp_slot != CPUHP_INVALID)
> + cpuhp_remove_multi_state(cpuhp_slot);
> +}
> +
> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
> +{
> + if (cpuhp_slot == CPUHP_INVALID)
> + return -EINVAL;
> +
> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> +}
> +
> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
> +{
> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
> +}
> +
> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
> +{
> + struct xe_pmu *pmu = arg;
> +
> + if (!pmu->base.event_init)
> + return;
> +
> + /*
> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
> + * ensures all currently executing ones will have exited before we
> + * proceed with unregistration.
> + */
> + pmu->closed = true;
> + synchronize_rcu();
> +
> + xe_pmu_unregister_cpuhp_state(pmu);
> +
> + perf_pmu_unregister(&pmu->base);
> + pmu->base.event_init = NULL;
> + kfree(pmu->base.attr_groups);
> + kfree(pmu->name);
> + free_event_attributes(pmu);
> +}
> +
> +static void init_samples(struct xe_pmu *pmu)
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + struct xe_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, xe, i)
> + engine_group_busyness_store(gt);
> +}
> +
> +void xe_pmu_register(struct xe_pmu *pmu)
Why void, why not int? PMU failure is non fatal error?
> +{
> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> + const struct attribute_group *attr_groups[] = {
> + &xe_pmu_format_attr_group,
> + &pmu->events_attr_group,
> + &xe_pmu_cpumask_attr_group,
Can someone please explain what this cpumask/cpuhotplug stuff does and
whether it needs to be in this patch? There's something here:
b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
I'd rather just have the basic PMU infra and the events in this patch and
punt this cpumask/cpuhotplug stuff to a later patch, unless someone can say
what it does.
Though perf_pmu_register seems to be doing some per cpu stuff so likely
this is needed. But amdgpu_pmu only has event and format attributes.
Mostly leave as is I guess.
> + NULL
> + };
> +
> + int ret = -ENOMEM;
> +
> + spin_lock_init(&pmu->lock);
> + pmu->cpuhp.cpu = -1;
> + init_samples(pmu);
Why init_samples here? Can't we init the particular sample in
xe_pmu_event_init or even xe_pmu_event_start?
Init'ing here may be too soon since the event might not be enabled for a
long time. So really this needs to move to xe_pmu_event_init or
xe_pmu_event_start.
Actually this is already happening in xe_pmu_enable. We just need to decide
when we want to wake the device up and when we don't. So maybe wake the
device up at start (use xe_device_mem_access_get) and not wake up during
read (xe_device_mem_access_get_if_ongoing etc.)?
> +
> + pmu->name = kasprintf(GFP_KERNEL,
> + "xe_%s",
> + dev_name(xe->drm.dev));
> + if (pmu->name)
> + /* tools/perf reserves colons as special. */
> + strreplace((char *)pmu->name, ':', '_');
> +
> + if (!pmu->name)
> + goto err;
> +
> + pmu->events_attr_group.name = "events";
> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> + if (!pmu->events_attr_group.attrs)
> + goto err_name;
> +
> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
> + GFP_KERNEL);
> + if (!pmu->base.attr_groups)
> + goto err_attr;
> +
> + pmu->base.module = THIS_MODULE;
> + pmu->base.task_ctx_nr = perf_invalid_context;
> + pmu->base.event_init = xe_pmu_event_init;
> + pmu->base.add = xe_pmu_event_add;
> + pmu->base.del = xe_pmu_event_del;
> + pmu->base.start = xe_pmu_event_start;
> + pmu->base.stop = xe_pmu_event_stop;
> + pmu->base.read = xe_pmu_event_read;
> + pmu->base.event_idx = xe_pmu_event_event_idx;
> +
> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> + if (ret)
> + goto err_groups;
> +
> + ret = xe_pmu_register_cpuhp_state(pmu);
> + if (ret)
> + goto err_unreg;
> +
> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
> + XE_WARN_ON(ret);
We should just follow the regular error rewind here too and let
drm_notice() at the end print the error. This is what other drivers calling
drmm_add_action_or_reset seem to be doing.
> +
> + return;
> +
> +err_unreg:
> + perf_pmu_unregister(&pmu->base);
> +err_groups:
> + kfree(pmu->base.attr_groups);
> +err_attr:
> + pmu->base.event_init = NULL;
> + free_event_attributes(pmu);
> +err_name:
> + kfree(pmu->name);
> +err:
> + drm_notice(&xe->drm, "Failed to register PMU!\n");
> +}
> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> new file mode 100644
> index 000000000000..d3f47f4ab343
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_H_
> +#define _XE_PMU_H_
> +
> +#include "xe_gt_types.h"
> +#include "xe_pmu_types.h"
> +
> +#ifdef CONFIG_PERF_EVENTS
nit but maybe this should be:
#if IS_ENABLED(CONFIG_PERF_EVENTS)
or,
#if IS_BUILTIN(CONFIG_PERF_EVENTS)
Note CONFIG_PERF_EVENTS is a boolean kconfig option.
See similar macro IS_REACHABLE() in i915_hwmon.h.
> +int xe_pmu_init(void);
> +void xe_pmu_exit(void);
> +void xe_pmu_register(struct xe_pmu *pmu);
> +void engine_group_busyness_store(struct xe_gt *gt);
Add xe_pmu_ prefix if function is needed (hopefully not).
> +#else
> +static inline int xe_pmu_init(void) { return 0; }
> +static inline void xe_pmu_exit(void) {}
> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
> +#endif
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
> new file mode 100644
> index 000000000000..e87edd4d6a87
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_PMU_TYPES_H_
> +#define _XE_PMU_TYPES_H_
> +
> +#include <linux/perf_event.h>
> +#include <linux/spinlock_types.h>
> +#include <uapi/drm/xe_drm.h>
> +
> +enum {
> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> + __XE_SAMPLE_COPY_GROUP_BUSY,
> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> + __XE_NUM_PMU_SAMPLERS
OK: irq_count is missing here since these are read from device...
> +};
> +
> +struct xe_pmu_sample {
> + u64 cur;
> +};
This was also discussed for i915 PMU, no point having a struct with a
single u64 member. Might as well just use u64 wherever we are using
struct xe_pmu_sample.
> +
> +#define XE_MAX_GT_PER_TILE 2
Why per tile? The array size should be max_gt_per_device. Just call it
XE_MAX_GT?
> +
> +struct xe_pmu {
> + /**
> + * @cpuhp: Struct used for CPU hotplug handling.
> + */
> + struct {
> + struct hlist_node node;
> + unsigned int cpu;
> + } cpuhp;
> + /**
> + * @base: PMU base.
> + */
> + struct pmu base;
> + /**
> + * @closed: xe is unregistering.
> + */
> + bool closed;
> + /**
> + * @name: Name as registered with perf core.
> + */
> + const char *name;
> + /**
> + * @lock: Lock protecting enable mask and ref count handling.
> + */
> + spinlock_t lock;
> + /**
> + * @sample: Current and previous (raw) counters.
> + *
> + * These counters are updated when the device is awake.
> + *
> + */
> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
Change to 2-d array. See above.
> + /**
> + * @irq_count: Number of interrupts
> + *
> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> + * occasional wraparound easily. It's 32bit after all.
> + */
> + unsigned long irq_count;
> + /**
> + * @events_attr_group: Device events attribute group.
> + */
> + struct attribute_group events_attr_group;
> + /**
> + * @xe_attr: Memory block holding device attributes.
> + */
> + void *xe_attr;
> + /**
> + * @pmu_attr: Memory block holding device attributes.
> + */
> + void *pmu_attr;
> +};
> +
> +#endif
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 965cd9527ff1..ed097056f944 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> __u64 reserved[2];
> };
>
> +/* PMU event config IDs */
> +
> +/*
> + * Top 4 bits of every counter are GT id.
> + */
> +#define __XE_PMU_GT_SHIFT (60)
To future-proof this, and also because we seem to have plenty of bits
available, I think we should change this to 56 (instead of 60).
> +
> +#define ___XE_PMU_OTHER(gt, x) \
> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> +
> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.25.1
>
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-21 1:02 ` Dixit, Ashutosh
@ 2023-07-21 11:51 ` Iddamsetty, Aravind
2023-07-21 23:36 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-21 11:51 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 21-07-2023 06:32, Dixit, Ashutosh wrote:
> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>
>
> Hi Aravind,
Hi Ashutosh,
>
> More stuff to mull over. You can ignore comments starting with "OK", those
> are just notes to myself.
>
> Also, maybe some time we can add a basic IGT which reads these exposed
> counters and verifies that we can read them and they are monotonically
> increasing?
this is the IGT https://patchwork.freedesktop.org/series/119936/ series
using these counters posted by Venkat.
>
>> There are a set of engine group busyness counters provided by HW which are
>> perfect fit to be exposed via PMU perf events.
>>
>> BSPEC: 46559, 46560, 46722, 46729
>
> Also add these Bspec entries: 71028, 52071
OK.
>
>>
>> events can be listed using:
>> perf list
>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>
>> and can be read using:
>>
>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>> time counts unit events
>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>
>> The pmu base implementation is taken from i915.
>>
>> v2:
>> Store last known value when device is awake return that while the GT is
>> suspended and then update the driver copy when read during awake.
>>
>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>> drivers/gpu/drm/xe/xe_device.c | 2 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>> drivers/gpu/drm/xe/xe_module.c | 5 +
>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>> include/uapi/drm/xe_drm.h | 16 +
>> 11 files changed, 902 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
>> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 081c57fd8632..e52ab795c566 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/skl_universal_plane.o \
>> i915-display/skl_watermark.o
>>
>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>> +
>> ifeq ($(CONFIG_ACPI),y)
>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_acpi.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3f664011eaea..c7d9e4634745 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -285,6 +285,11 @@
>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>
>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>> +
>> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
>> #define ENABLE_SMALLPL REG_BIT(15)
>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index c7985af85a53..b2c7bd4a97d9 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_debugfs_register(xe);
>>
>> + xe_pmu_register(&xe->pmu);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 0226d44a6af2..3ba99aae92b9 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -15,6 +15,7 @@
>> #include "xe_devcoredump_types.h"
>> #include "xe_gt_types.h"
>> #include "xe_platform_types.h"
>> +#include "xe_pmu.h"
>> #include "xe_step_types.h"
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> @@ -332,6 +333,9 @@ struct xe_device {
>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>> bool d3cold_allowed;
>>
>> + /* @pmu: performance monitoring unit */
>> + struct xe_pmu pmu;
>> +
>
> Now I am wondering why we don't make the PMU per-gt (or per-tile)? Per-gt
> would work for these busyness registers and I am not sure how the
> interrupts are hooked up.
>
> In i915 the PMU being device level helped in having a single timer (rather
> than a per gt timer).
>
> Anyway probably not much practical benefit by make it per-gt/per-tile, so
> maybe leave as is. Just thinking out loud.
we are able to expose per-gt counters so do not see any benefit in
making pmu per-gt, also i believe struct pmu is per device it will have
a type associated which is unique for a device.
>
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>> index 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>>
>> + engine_group_busyness_store(gt);
>
> Not sure I follow the reason for doing this at suspend time? If PMU was
> active there should be a previous value. Why must we take a new sample
> explicitly here?
the PMU interface can be read even when device is suspend and in such
cases we should not wake up the device, and if we try to read the
register when device is suspended it gives spurious counter you can
check in version#1 of this series we were getting huge values. as we put
the device to suspend immediately after probe. So storing the last known
good value before suspend.
>
> To me looks like engine_group_busyness_store should not be needed, see
> comment below for init_samples too.
>
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index b4ed1e4a3388..cb943fb94ec7 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,6 +27,24 @@
>> #define IIR(offset) XE_REG(offset + 0x8)
>> #define IER(offset) XE_REG(offset + 0xc)
>>
>> +/*
>> + * Interrupt statistic for PMU. Increments the counter only if the
>> + * interrupt originated from the GPU so interrupts from a device which
>> + * shares the interrupt line are not accounted.
>> + */
>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>
> No inline, compiler will do it, but looks like we may want to always_inline
> this. Also this function should really be in xe_pmu.h? Anyway probably
> leave as is.
>
>> + irqreturn_t res)
>> +{
>> + if (unlikely(res != IRQ_HANDLED))
>> + return;
>> +
>> + /*
>> + * A clever compiler translates that into INC. A not so clever one
>> + * should at least prevent store tearing.
>> + */
>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
>> +}
>> +
>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
>> {
>> u32 val = xe_mmio_read32(mmio, reg);
>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>>
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> dg1_intr_enable(xe, false);
>> xe_display_irq_enable(xe, gu_misc_iir);
>>
>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>> +
>> return IRQ_HANDLED;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>> index 75e5be939f53..f6fe89748525 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_fence.h"
>> #include "xe_module.h"
>> #include "xe_pci.h"
>> +#include "xe_pmu.h"
>> #include "xe_sched_job.h"
>>
>> bool enable_guc = true;
>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>> .init = xe_sched_job_module_init,
>> .exit = xe_sched_job_module_exit,
>> },
>> + {
>> + .init = xe_pmu_init,
>> + .exit = xe_pmu_exit,
>> + },
>> {
>> .init = xe_register_pci_driver,
>> .exit = xe_unregister_pci_driver,
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> new file mode 100644
>> index 000000000000..bef1895be9f7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -0,0 +1,739 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2023 Intel Corporation
>> + */
>
> This SPDX header is for .h files not .c files. Actually, it is for neither :/
But i see this in almost all the files in xe.
>
>> +
>> +#include <drm/drm_drv.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "regs/xe_gt_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt_clock.h"
>> +#include "xe_mmio.h"
>> +
>> +static cpumask_t xe_pmu_cpumask;
>> +static unsigned int xe_pmu_target_cpu = -1;
>> +
>> +static unsigned int config_gt_id(const u64 config)
>> +{
>> + return config >> __XE_PMU_GT_SHIFT;
>> +}
>> +
>> +static u64 config_counter(const u64 config)
>> +{
>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
>> +}
>> +
>> +static unsigned int
>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>> +{
>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>> +
>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>> +
>> + return idx;
>> +}
>
> The compiler does this for us if we make sample array 2-d.
>
>> +
>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>> +{
>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
>> +}
>> +
>> +static void
>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
>> +{
>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
>> +}
>
> The three functions above are not needed if we make the sample array
> 2-d. See here:
>
> https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
>
> Only a part of the patch above was merged (see 8ed0753b527dc) to keep the
> patch size small, but since for xe we are starting from scratch we can
> implement the whole approach above (get rid of the read/store helpers
> entirely, direct assignment without the helpers works).
Ok I'll go over it.
>
>> +
>> +static int engine_busyness_sample_type(u64 config)
>> +{
>> + int type = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>> + break;
>> + }
>> +
>> + return type;
>> +}
>> +
>> +static void xe_pmu_event_destroy(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> +
>> + drm_WARN_ON(&xe->drm, event->parent);
>> +
>> + drm_dev_put(&xe->drm);
>> +}
>> +
>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>> +{
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>> + break;
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>> + break;
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>> + break;
>> + default:
>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>> + }
>
> We need xe_device_mem_access_get, also xe_force_wake_get if applicable,
> somewhere before reading these registers.
>
>> +
>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>> +}
>> +
>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
>> +{
>> + int sample_type = engine_busyness_sample_type(config);
>> + struct xe_device *xe = gt->tile->xe;
>> + const unsigned int gt_id = gt->info.id;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + bool device_awake;
>> + unsigned long flags;
>> + u64 val;
>> +
>> + /*
>> + * found no better way to check if device is awake or not. Before
>
> xe_device_mem_access_get_if_ongoing (hard to find name).
thanks for sharing looks to be added recently. If we use this we needn't
use xe_device_mem_access_get.
>
>> + * we suspend we set the submission_state.enabled to false.
>> + */
>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>> + if (device_awake)
>> + val = __engine_group_busyness_read(gt, config);
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + if (device_awake)
>> + store_sample(pmu, gt_id, sample_type, val);
>> + else
>> + val = read_sample(pmu, gt_id, sample_type);
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +
>> + return val;
>> +}
>> +
>> +void engine_group_busyness_store(struct xe_gt *gt)
>> +{
>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>> + unsigned int gt_id = gt->info.id;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&pmu->lock, flags);
>> +
>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>> +
>> + spin_unlock_irqrestore(&pmu->lock, flags);
>> +}
>> +
>> +static int
>> +config_status(struct xe_device *xe, u64 config)
>> +{
>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>> + unsigned int gt_id = config_gt_id(config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> +
>> + if (gt_id > max_gt_id)
>> + return -ENOENT;
>> +
>> + switch (config_counter(config)) {
>> + case XE_PMU_INTERRUPTS(0):
>> + if (gt_id)
>> + return -ENOENT;
>
> OK: this is a global event so we say this is enabled only for gt0.
>
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + if (GRAPHICS_VER(xe) < 12)
>
> Any point checking? xe only supports Gen12+.
hmmm ya good point will remove this.
>
>> + return -ENOENT;
>> + break;
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
>> + return -ENOENT;
>
> OK: this makes sense, so we will expose this event only for media gt's.
>
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_event_init(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + int ret;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* unsupported modes and filters */
>> + if (event->attr.sample_period) /* no sampling */
>> + return -EINVAL;
>> +
>> + if (has_branch_stack(event))
>> + return -EOPNOTSUPP;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /* only allow running on one cpu at a time */
>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>> + return -EINVAL;
>> +
>> + ret = config_status(xe, event->attr.config);
>> + if (ret)
>> + return ret;
>> +
>> + if (!event->parent) {
>> + drm_dev_get(&xe->drm);
>> + event->destroy = xe_pmu_event_destroy;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static u64 __xe_pmu_event_read(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>> + const u64 config = config_counter(event->attr.config);
>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 val = 0;
>> +
>> + switch (config) {
>> + case XE_PMU_INTERRUPTS(0):
>> + val = READ_ONCE(pmu->irq_count);
>
> OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff would
> be to take pmu->lock (both while reading and writing irq_count) but that
> would be expensive in the interrupt handler (as the .h hints). So all we
> can do is what is done here.
>
>> + break;
>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>> + case XE_PMU_COPY_GROUP_BUSY(0):
>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>> + val = engine_group_busyness_read(gt, config);
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static void xe_pmu_event_read(struct perf_event *event)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct xe_pmu *pmu = &xe->pmu;
>> + u64 prev, new;
>> +
>> + if (pmu->closed) {
>> + event->hw.state = PERF_HES_STOPPED;
>> + return;
>> + }
>> +again:
>> + prev = local64_read(&hwc->prev_count);
>> + new = __xe_pmu_event_read(event);
>> +
>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>> + goto again;
>> +
>> + local64_add(new - prev, &event->count);
>> +}
>> +
>> +static void xe_pmu_enable(struct perf_event *event)
>> +{
>> + /*
>> + * Store the current counter value so we can report the correct delta
>> + * for all listeners. Even when the event was already enabled and has
>> + * an existing non-zero value.
>> + */
>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>> +}
>> +
>> +static void xe_pmu_event_start(struct perf_event *event, int flags)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return;
>> +
>> + xe_pmu_enable(event);
>> + event->hw.state = 0;
>> +}
>> +
>> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
>> +{
>> + if (flags & PERF_EF_UPDATE)
>> + xe_pmu_event_read(event);
>> +
>> + event->hw.state = PERF_HES_STOPPED;
>> +}
>> +
>> +static int xe_pmu_event_add(struct perf_event *event, int flags)
>> +{
>> + struct xe_device *xe =
>> + container_of(event->pmu, typeof(*xe), pmu.base);
>> + struct xe_pmu *pmu = &xe->pmu;
>> +
>> + if (pmu->closed)
>> + return -ENODEV;
>> +
>> + if (flags & PERF_EF_START)
>> + xe_pmu_event_start(event, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_pmu_event_del(struct perf_event *event, int flags)
>> +{
>> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
>> +}
>> +
>> +static int xe_pmu_event_event_idx(struct perf_event *event)
>> +{
>> + return 0;
>> +}
>> +
>> +struct xe_str_attribute {
>> + struct device_attribute attr;
>> + const char *str;
>> +};
>> +
>> +static ssize_t xe_pmu_format_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct xe_str_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>> + return sprintf(buf, "%s\n", eattr->str);
>> +}
>> +
>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>> + (&((struct xe_str_attribute[]) { \
>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
>> + .str = _config, } \
>> + })[0].attr.attr)
>> +
>> +static struct attribute *xe_pmu_format_attrs[] = {
>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>
> 0-20 means 0-20 bits? Though here we probably have different number of
> config bits? Probably doesn't matter?
as i understand this is not used anymore so will remove it.
>
> The string will show up with:
>
> cat /sys/devices/xe/format/xe_eventid
>
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_format_attr_group = {
>> + .name = "format",
>> + .attrs = xe_pmu_format_attrs,
>> +};
>> +
>> +struct xe_ext_attribute {
>> + struct device_attribute attr;
>> + unsigned long val;
>> +};
>> +
>> +static ssize_t xe_pmu_event_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct xe_ext_attribute *eattr;
>> +
>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>> + return sprintf(buf, "config=0x%lx\n", eattr->val);
>> +}
>> +
>> +static ssize_t cpumask_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
>> +}
>> +
>> +static DEVICE_ATTR_RO(cpumask);
>> +
>> +static struct attribute *xe_cpumask_attrs[] = {
>> + &dev_attr_cpumask.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>> + .attrs = xe_cpumask_attrs,
>> +};
>> +
>> +#define __event(__counter, __name, __unit) \
>> +{ \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = false, \
>> +}
>> +
>> +#define __global_event(__counter, __name, __unit) \
>> +{ \
>> + .counter = (__counter), \
>> + .name = (__name), \
>> + .unit = (__unit), \
>> + .global = true, \
>> +}
>> +
>> +static struct xe_ext_attribute *
>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = xe_pmu_event_show;
>> + attr->val = config;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct perf_pmu_events_attr *
>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>> + const char *str)
>> +{
>> + sysfs_attr_init(&attr->attr.attr);
>> + attr->attr.attr.name = name;
>> + attr->attr.attr.mode = 0444;
>> + attr->attr.show = perf_event_sysfs_show;
>> + attr->event_str = str;
>> +
>> + return ++attr;
>> +}
>> +
>> +static struct attribute **
>> +create_event_attributes(struct xe_pmu *pmu)
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + static const struct {
>> + unsigned int counter;
>> + const char *name;
>> + const char *unit;
>> + bool global;
>> + } events[] = {
>> + __global_event(0, "interrupts", NULL),
>> + __event(1, "render-group-busy", "ns"),
>> + __event(2, "copy-group-busy", "ns"),
>> + __event(3, "media-group-busy", "ns"),
>> + __event(4, "any-engine-group-busy", "ns"),
>> + };
>
> OK: this function is some black magic to expose stuff through
> PMU. Identical to i915 and seems to be working from the commit message so
> should be fine.
>
>> +
>> + unsigned int count = 0;
>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>> + struct attribute **attr = NULL, **attr_iter;
>> + struct xe_gt *gt;
>> + unsigned int i, j;
>> +
>> + /* Count how many counters we will be exposing. */
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>> +
>> + if (!config_status(xe, config))
>> + count++;
>> + }
>> + }
>> +
>> + /* Allocate attribute objects and table. */
>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>> + if (!xe_attr)
>> + goto err_alloc;
>> +
>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>> + if (!pmu_attr)
>> + goto err_alloc;
>> +
>> + /* Max one pointer of each attribute type plus a termination entry. */
>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + goto err_alloc;
>> +
>> + xe_iter = xe_attr;
>> + pmu_iter = pmu_attr;
>> + attr_iter = attr;
>> +
>> + for_each_gt(gt, xe, j) {
>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>> + char *str;
>> +
>> + if (config_status(xe, config))
>> + continue;
>> +
>> + if (events[i].global)
>> + str = kstrdup(events[i].name, GFP_KERNEL);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &xe_iter->attr.attr;
>> + xe_iter = add_xe_attr(xe_iter, str, config);
>> +
>> + if (events[i].unit) {
>> + if (events[i].global)
>> + str = kasprintf(GFP_KERNEL, "%s.unit",
>> + events[i].name);
>> + else
>> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
>> + events[i].name, j);
>> + if (!str)
>> + goto err;
>> +
>> + *attr_iter++ = &pmu_iter->attr.attr;
>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>> + events[i].unit);
>> + }
>> + }
>> + }
>> +
>> + pmu->xe_attr = xe_attr;
>> + pmu->pmu_attr = pmu_attr;
>> +
>> + return attr;
>> +
>> +err:
>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> +err_alloc:
>> + kfree(attr);
>> + kfree(xe_attr);
>> + kfree(pmu_attr);
>> +
>> + return NULL;
>> +}
>> +
>> +static void free_event_attributes(struct xe_pmu *pmu)
>> +{
>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>> +
>> + for (; *attr_iter; attr_iter++)
>> + kfree((*attr_iter)->name);
>> +
>> + kfree(pmu->events_attr_group.attrs);
>> + kfree(pmu->xe_attr);
>> + kfree(pmu->pmu_attr);
>> +
>> + pmu->events_attr_group.attrs = NULL;
>> + pmu->xe_attr = NULL;
>> + pmu->pmu_attr = NULL;
>> +}
>> +
>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /* Select the first online CPU as a designated reader. */
>> + if (cpumask_empty(&xe_pmu_cpumask))
>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
>> + unsigned int target = xe_pmu_target_cpu;
>> +
>> + XE_BUG_ON(!pmu->base.event_init);
>> +
>> + /*
>> + * Unregistering an instance generates a CPU offline event which we must
>> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
>> + */
>> + if (pmu->closed)
>> + return 0;
>> +
>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
>> +
>> + /* Migrate events if there is a valid target */
>> + if (target < nr_cpu_ids) {
>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>> + xe_pmu_target_cpu = target;
>> + }
>> + }
>> +
>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>> + pmu->cpuhp.cpu = target;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>> +
>> +int xe_pmu_init(void)
>> +{
>> + int ret;
>> +
>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> + "perf/x86/intel/xe:online",
>> + xe_pmu_cpu_online,
>> + xe_pmu_cpu_offline);
>> + if (ret < 0)
>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>> + ret);
>> + else
>> + cpuhp_slot = ret;
>> +
>> + return 0;
>> +}
>> +
>> +void xe_pmu_exit(void)
>> +{
>> + if (cpuhp_slot != CPUHP_INVALID)
>> + cpuhp_remove_multi_state(cpuhp_slot);
>> +}
>> +
>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
>> +{
>> + if (cpuhp_slot == CPUHP_INVALID)
>> + return -EINVAL;
>> +
>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
>> +}
>> +
>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
>> +{
>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
>> +}
>> +
>> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
>> +{
>> + struct xe_pmu *pmu = arg;
>> +
>> + if (!pmu->base.event_init)
>> + return;
>> +
>> + /*
>> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
>> + * ensures all currently executing ones will have exited before we
>> + * proceed with unregistration.
>> + */
>> + pmu->closed = true;
>> + synchronize_rcu();
>> +
>> + xe_pmu_unregister_cpuhp_state(pmu);
>> +
>> + perf_pmu_unregister(&pmu->base);
>> + pmu->base.event_init = NULL;
>> + kfree(pmu->base.attr_groups);
>> + kfree(pmu->name);
>> + free_event_attributes(pmu);
>> +}
>> +
>> +static void init_samples(struct xe_pmu *pmu)
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + struct xe_gt *gt;
>> + unsigned int i;
>> +
>> + for_each_gt(gt, xe, i)
>> + engine_group_busyness_store(gt);
>> +}
>> +
>> +void xe_pmu_register(struct xe_pmu *pmu)
>
> Why void, why not int? PMU failure is non fatal error?
Ya device is functional , it is only that these counters are not
available. Hence didn't want to fail the driver load.
>
>> +{
>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>> + const struct attribute_group *attr_groups[] = {
>> + &xe_pmu_format_attr_group,
>> + &pmu->events_attr_group,
>> + &xe_pmu_cpumask_attr_group,
>
> Can someone please explain what this cpumask/cpuhotplug stuff does and
> whether it needs to be in this patch? There's something here:
comments from original patch series in
i915:https://patchwork.kernel.org/project/intel-gfx/patch/20170802123249.14194-5-tvrtko.ursulin@linux.intel.com/
"IIRC an uncore PMU should expose a cpumask through sysfs, and then perf
tools will read that mask and auto-magically limit the number of CPUs it
instantiates the counter on."
and ours are global counters not per cpu so we limit to just to single cpu.
And as i understand we use the cpuhotplug support to migrate too new cpu
incase the earlier one goes offline.
>
> b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
>
> I'd rather just have the basic PMU infra and the events in this patch and
> punt this cpumask/cpuhotplug stuff to a later patch, unless someone can say
> what it does.
>
> Though perf_pmu_register seems to be doing some per cpu stuff so likely
> this is needed. But amdgpu_pmu only has event and format attributes.
>
> Mostly leave as is I guess.
>
>> + NULL
>> + };
>> +
>> + int ret = -ENOMEM;
>> +
>> + spin_lock_init(&pmu->lock);
>> + pmu->cpuhp.cpu = -1;
>> + init_samples(pmu);
>
> Why init_samples here? Can't we init the particular sample in
> xe_pmu_event_init or even xe_pmu_event_start?
>
> Init'ing here may be too soon since the event might not be enabled for a
> long time. So really this needs to move to xe_pmu_event_init or
> xe_pmu_event_start.
The device is put to suspend immediately after driver probe, typically
pmu is opened even before any workload is run so essentially device is
still in suspend state hence we cannot access registers so storing the
last known value in init_samples. otherwise we see the bug in v#1 of series.
>
> Actually this is already happening in xe_pmu_enable. We just need to decide
> when we want to wake the device up and when we don't. So maybe wake the
> device up at start (use xe_device_mem_access_get) and not wake up during
> read (xe_device_mem_access_get_if_ongoing etc.)?
>
>> +
>> + pmu->name = kasprintf(GFP_KERNEL,
>> + "xe_%s",
>> + dev_name(xe->drm.dev));
>> + if (pmu->name)
>> + /* tools/perf reserves colons as special. */
>> + strreplace((char *)pmu->name, ':', '_');
>> +
>> + if (!pmu->name)
>> + goto err;
>> +
>> + pmu->events_attr_group.name = "events";
>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>> + if (!pmu->events_attr_group.attrs)
>> + goto err_name;
>> +
>> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
>> + GFP_KERNEL);
>> + if (!pmu->base.attr_groups)
>> + goto err_attr;
>> +
>> + pmu->base.module = THIS_MODULE;
>> + pmu->base.task_ctx_nr = perf_invalid_context;
>> + pmu->base.event_init = xe_pmu_event_init;
>> + pmu->base.add = xe_pmu_event_add;
>> + pmu->base.del = xe_pmu_event_del;
>> + pmu->base.start = xe_pmu_event_start;
>> + pmu->base.stop = xe_pmu_event_stop;
>> + pmu->base.read = xe_pmu_event_read;
>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>> +
>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>> + if (ret)
>> + goto err_groups;
>> +
>> + ret = xe_pmu_register_cpuhp_state(pmu);
>> + if (ret)
>> + goto err_unreg;
>> +
>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
>> + XE_WARN_ON(ret);
>
> We should just follow the regular error rewind here too and let
> drm_notice() at the end print the error. This is what other drivers calling
> drmm_add_action_or_reset seem to be doing.
Ok ok.
>
>> +
>> + return;
>> +
>> +err_unreg:
>> + perf_pmu_unregister(&pmu->base);
>> +err_groups:
>> + kfree(pmu->base.attr_groups);
>> +err_attr:
>> + pmu->base.event_init = NULL;
>> + free_event_attributes(pmu);
>> +err_name:
>> + kfree(pmu->name);
>> +err:
>> + drm_notice(&xe->drm, "Failed to register PMU!\n");
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>> new file mode 100644
>> index 000000000000..d3f47f4ab343
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_H_
>> +#define _XE_PMU_H_
>> +
>> +#include "xe_gt_types.h"
>> +#include "xe_pmu_types.h"
>> +
>> +#ifdef CONFIG_PERF_EVENTS
>
> nit but maybe this should be:
>
> #if IS_ENABLED(CONFIG_PERF_EVENTS)
>
> or,
>
> #if IS_BUILTIN(CONFIG_PERF_EVENTS)
>
> Note CONFIG_PERF_EVENTS is a boolean kconfig option.
>
> See similar macro IS_REACHABLE() in i915_hwmon.h.
>
>> +int xe_pmu_init(void);
>> +void xe_pmu_exit(void);
>> +void xe_pmu_register(struct xe_pmu *pmu);
>> +void engine_group_busyness_store(struct xe_gt *gt);
>
> Add xe_pmu_ prefix if function is needed (hopefully not).
OK
>
>> +#else
>> +static inline int xe_pmu_init(void) { return 0; }
>> +static inline void xe_pmu_exit(void) {}
>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
>> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
>> +#endif
>> +
>> +#endif
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
>> new file mode 100644
>> index 000000000000..e87edd4d6a87
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_PMU_TYPES_H_
>> +#define _XE_PMU_TYPES_H_
>> +
>> +#include <linux/perf_event.h>
>> +#include <linux/spinlock_types.h>
>> +#include <uapi/drm/xe_drm.h>
>> +
>> +enum {
>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>> + __XE_NUM_PMU_SAMPLERS
>
> OK: irq_count is missing here since these are read from device...
>
>> +};
>> +
>> +struct xe_pmu_sample {
>> + u64 cur;
>> +};
>
> This was also discussed for i915 PMU, no point having a struct with a
> single u64 member. Might as well just use u64 wherever we are using
> struct xe_pmu_sample.
OK.
>
>> +
>> +#define XE_MAX_GT_PER_TILE 2
>
> Why per tile? The array size should be max_gt_per_device. Just call it
> XE_MAX_GT?
I declared similar to what we have in drivers/gpu/drm/xe/xe_device.h
>
>> +
>> +struct xe_pmu {
>> + /**
>> + * @cpuhp: Struct used for CPU hotplug handling.
>> + */
>> + struct {
>> + struct hlist_node node;
>> + unsigned int cpu;
>> + } cpuhp;
>> + /**
>> + * @base: PMU base.
>> + */
>> + struct pmu base;
>> + /**
>> + * @closed: xe is unregistering.
>> + */
>> + bool closed;
>> + /**
>> + * @name: Name as registered with perf core.
>> + */
>> + const char *name;
>> + /**
>> + * @lock: Lock protecting enable mask and ref count handling.
>> + */
>> + spinlock_t lock;
>> + /**
>> + * @sample: Current and previous (raw) counters.
>> + *
>> + * These counters are updated when the device is awake.
>> + *
>> + */
>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
>
> Change to 2-d array. See above.
>
>> + /**
>> + * @irq_count: Number of interrupts
>> + *
>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>> + * occasional wraparound easily. It's 32bit after all.
>> + */
>> + unsigned long irq_count;
>> + /**
>> + * @events_attr_group: Device events attribute group.
>> + */
>> + struct attribute_group events_attr_group;
>> + /**
>> + * @xe_attr: Memory block holding device attributes.
>> + */
>> + void *xe_attr;
>> + /**
>> + * @pmu_attr: Memory block holding device attributes.
>> + */
>> + void *pmu_attr;
>> +};
>> +
>> +#endif
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 965cd9527ff1..ed097056f944 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>> __u64 reserved[2];
>> };
>>
>> +/* PMU event config IDs */
>> +
>> +/*
>> + * Top 4 bits of every counter are GT id.
>> + */
>> +#define __XE_PMU_GT_SHIFT (60)
>
> To future-proof this, and also because we seem to have plenty of bits
> available, I think we should change this to 56 (instead of 60).
OK
Thanks,
Aravind.
>
>> +
>> +#define ___XE_PMU_OTHER(gt, x) \
>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>> +
>> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
>> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
>> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> --
>> 2.25.1
>>
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-21 11:51 ` Iddamsetty, Aravind
@ 2023-07-21 23:36 ` Dixit, Ashutosh
2023-07-22 6:04 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-21 23:36 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> On 21-07-2023 06:32, Dixit, Ashutosh wrote:
> > On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
> >>
> > More stuff to mull over. You can ignore comments starting with "OK", those
> > are just notes to myself.
> >
> > Also, maybe some time we can add a basic IGT which reads these exposed
> > counters and verifies that we can read them and they are monotonically
> > increasing?
>
> this is the IGT https://patchwork.freedesktop.org/series/119936/ series
> using these counters posted by Venkat.
>
> >
> >> There are a set of engine group busyness counters provided by HW which are
> >> perfect fit to be exposed via PMU perf events.
> >>
> >> BSPEC: 46559, 46560, 46722, 46729
> >
> > Also add these Bspec entries: 71028, 52071
>
> OK.
>
> >
> >>
> >> events can be listed using:
> >> perf list
> >> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> >> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> >> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> >> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> >> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
> >>
> >> and can be read using:
> >>
> >> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> >> time counts unit events
> >> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> >>
> >> The pmu base implementation is taken from i915.
> >>
> >> v2:
> >> Store last known value when device is awake return that while the GT is
> >> suspended and then update the driver copy when read during awake.
> >>
> >> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> >> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> >> ---
> >> drivers/gpu/drm/xe/Makefile | 2 +
> >> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> >> drivers/gpu/drm/xe/xe_device.c | 2 +
> >> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> >> drivers/gpu/drm/xe/xe_gt.c | 2 +
> >> drivers/gpu/drm/xe/xe_irq.c | 22 +
> >> drivers/gpu/drm/xe/xe_module.c | 5 +
> >> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> >> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> >> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> >> include/uapi/drm/xe_drm.h | 16 +
> >> 11 files changed, 902 insertions(+)
> >> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
> >> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
> >> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
> >>
> >> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> >> index 081c57fd8632..e52ab795c566 100644
> >> --- a/drivers/gpu/drm/xe/Makefile
> >> +++ b/drivers/gpu/drm/xe/Makefile
> >> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> >> i915-display/skl_universal_plane.o \
> >> i915-display/skl_watermark.o
> >>
> >> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> >> +
> >> ifeq ($(CONFIG_ACPI),y)
> >> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> >> i915-display/intel_acpi.o \
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >> index 3f664011eaea..c7d9e4634745 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >> @@ -285,6 +285,11 @@
> >> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> >> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
> >>
> >> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
> >> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> >> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> >> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> >> +
> >> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
> >> #define ENABLE_SMALLPL REG_BIT(15)
> >> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> >> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> >> index c7985af85a53..b2c7bd4a97d9 100644
> >> --- a/drivers/gpu/drm/xe/xe_device.c
> >> +++ b/drivers/gpu/drm/xe/xe_device.c
> >> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
> >>
> >> xe_debugfs_register(xe);
> >>
> >> + xe_pmu_register(&xe->pmu);
> >> +
> >> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> >> if (err)
> >> return err;
> >> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> >> index 0226d44a6af2..3ba99aae92b9 100644
> >> --- a/drivers/gpu/drm/xe/xe_device_types.h
> >> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> >> @@ -15,6 +15,7 @@
> >> #include "xe_devcoredump_types.h"
> >> #include "xe_gt_types.h"
> >> #include "xe_platform_types.h"
> >> +#include "xe_pmu.h"
> >> #include "xe_step_types.h"
> >>
> >> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> >> @@ -332,6 +333,9 @@ struct xe_device {
> >> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> >> bool d3cold_allowed;
> >>
> >> + /* @pmu: performance monitoring unit */
> >> + struct xe_pmu pmu;
> >> +
> >
> > Now I am wondering why we don't make the PMU per-gt (or per-tile)? Per-gt
> > would work for these busyness registers and I am not sure how the
> > interrupts are hooked up.
> >
> > In i915 the PMU being device level helped in having a single timer (rather
> > than a per gt timer).
> >
> > Anyway probably not much practical benefit by make it per-gt/per-tile, so
> > maybe leave as is. Just thinking out loud.
>
> we are able to expose per-gt counters so do not see any benefit in
> making pmu per-gt, also i believe struct pmu is per device it will have
> a type associated which is unique for a device.
PMU can be made per gt and named xe-gt0, xe-gt1 etc. if we want. But anyway
leave as is.
>
> >
> >> /* private: */
> >>
> >> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> >> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> >> index 2458397ce8af..96e3720923d4 100644
> >> --- a/drivers/gpu/drm/xe/xe_gt.c
> >> +++ b/drivers/gpu/drm/xe/xe_gt.c
> >> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> >> if (err)
> >> goto err_msg;
> >>
> >> + engine_group_busyness_store(gt);
> >
> > Not sure I follow the reason for doing this at suspend time? If PMU was
> > active there should be a previous value. Why must we take a new sample
> > explicitly here?
>
> the PMU interface can be read even when device is suspend and in such
> cases we should not wake up the device, and if we try to read the
> register when device is suspended it gives spurious counter you can
> check in version#1 of this series we were getting huge values. as we put
> the device to suspend immediately after probe. So storing the last known
> good value before suspend.
No need, see comment at init_samples below.
>
> >
> > To me looks like engine_group_busyness_store should not be needed, see
> > comment below for init_samples too.
> >
> >> +
> >> err = xe_uc_suspend(>->uc);
> >> if (err)
> >> goto err_force_wake;
> >> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> >> index b4ed1e4a3388..cb943fb94ec7 100644
> >> --- a/drivers/gpu/drm/xe/xe_irq.c
> >> +++ b/drivers/gpu/drm/xe/xe_irq.c
> >> @@ -27,6 +27,24 @@
> >> #define IIR(offset) XE_REG(offset + 0x8)
> >> #define IER(offset) XE_REG(offset + 0xc)
> >>
> >> +/*
> >> + * Interrupt statistic for PMU. Increments the counter only if the
> >> + * interrupt originated from the GPU so interrupts from a device which
> >> + * shares the interrupt line are not accounted.
> >> + */
> >> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> >
> > No inline, compiler will do it, but looks like we may want to always_inline
> > this. Also this function should really be in xe_pmu.h? Anyway probably
> > leave as is.
> >
> >> + irqreturn_t res)
> >> +{
> >> + if (unlikely(res != IRQ_HANDLED))
> >> + return;
> >> +
> >> + /*
> >> + * A clever compiler translates that into INC. A not so clever one
> >> + * should at least prevent store tearing.
> >> + */
> >> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
> >> +}
> >> +
> >> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> >> {
> >> u32 val = xe_mmio_read32(mmio, reg);
> >> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
> >>
> >> xe_display_irq_enable(xe, gu_misc_iir);
> >>
> >> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> >> +
> >> return IRQ_HANDLED;
> >> }
> >>
> >> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> >> dg1_intr_enable(xe, false);
> >> xe_display_irq_enable(xe, gu_misc_iir);
> >>
> >> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> >> +
> >> return IRQ_HANDLED;
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> >> index 75e5be939f53..f6fe89748525 100644
> >> --- a/drivers/gpu/drm/xe/xe_module.c
> >> +++ b/drivers/gpu/drm/xe/xe_module.c
> >> @@ -12,6 +12,7 @@
> >> #include "xe_hw_fence.h"
> >> #include "xe_module.h"
> >> #include "xe_pci.h"
> >> +#include "xe_pmu.h"
> >> #include "xe_sched_job.h"
> >>
> >> bool enable_guc = true;
> >> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> >> .init = xe_sched_job_module_init,
> >> .exit = xe_sched_job_module_exit,
> >> },
> >> + {
> >> + .init = xe_pmu_init,
> >> + .exit = xe_pmu_exit,
> >> + },
> >> {
> >> .init = xe_register_pci_driver,
> >> .exit = xe_unregister_pci_driver,
> >> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> >> new file mode 100644
> >> index 000000000000..bef1895be9f7
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> >> @@ -0,0 +1,739 @@
> >> +/*
> >> + * SPDX-License-Identifier: MIT
> >> + *
> >> + * Copyright © 2023 Intel Corporation
> >> + */
> >
> > This SPDX header is for .h files not .c files. Actually, it is for neither :/
>
> But i see this in almost all the files in xe.
Look closely.
> >
> >> +
> >> +#include <drm/drm_drv.h>
> >> +#include <drm/drm_managed.h>
> >> +#include <drm/xe_drm.h>
> >> +
> >> +#include "regs/xe_gt_regs.h"
> >> +#include "xe_device.h"
> >> +#include "xe_gt_clock.h"
> >> +#include "xe_mmio.h"
> >> +
> >> +static cpumask_t xe_pmu_cpumask;
> >> +static unsigned int xe_pmu_target_cpu = -1;
> >> +
> >> +static unsigned int config_gt_id(const u64 config)
> >> +{
> >> + return config >> __XE_PMU_GT_SHIFT;
> >> +}
> >> +
> >> +static u64 config_counter(const u64 config)
> >> +{
> >> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
> >> +}
> >> +
> >> +static unsigned int
> >> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> >> +{
> >> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> >> +
> >> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> >> +
> >> + return idx;
> >> +}
> >
> > The compiler does this for us if we make sample array 2-d.
> >
> >> +
> >> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> >> +{
> >> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
> >> +}
> >> +
> >> +static void
> >> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
> >> +{
> >> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
> >> +}
> >
> > The three functions above are not needed if we make the sample array
> > 2-d. See here:
> >
> > https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
> >
> > Only a part of the patch above was merged (see 8ed0753b527dc) to keep the
> > patch size small, but since for xe we are starting from scratch we can
> > implement the whole approach above (get rid of the read/store helpers
> > entirely, direct assignment without the helpers works).
>
> Ok I'll go over it.
>
> >
> >> +
> >> +static int engine_busyness_sample_type(u64 config)
> >> +{
> >> + int type = 0;
> >> +
> >> + switch (config) {
> >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> >> + break;
> >> + case XE_PMU_COPY_GROUP_BUSY(0):
> >> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> >> + break;
> >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> >> + break;
> >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> >> + break;
> >> + }
> >> +
> >> + return type;
> >> +}
> >> +
> >> +static void xe_pmu_event_destroy(struct perf_event *event)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> +
> >> + drm_WARN_ON(&xe->drm, event->parent);
> >> +
> >> + drm_dev_put(&xe->drm);
> >> +}
> >> +
> >> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> >> +{
> >> + u64 val = 0;
> >> +
> >> + switch (config) {
> >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_COPY_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> >> + break;
> >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> >> + break;
> >> + default:
> >> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> >> + }
> >
> > We need xe_device_mem_access_get, also xe_force_wake_get if applicable,
> > somewhere before reading these registers.
> >
> >> +
> >> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> >> +}
> >> +
> >> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
> >> +{
> >> + int sample_type = engine_busyness_sample_type(config);
> >> + struct xe_device *xe = gt->tile->xe;
> >> + const unsigned int gt_id = gt->info.id;
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> + bool device_awake;
> >> + unsigned long flags;
> >> + u64 val;
> >> +
> >> + /*
> >> + * found no better way to check if device is awake or not. Before
> >
> > xe_device_mem_access_get_if_ongoing (hard to find name).
>
> thanks for sharing looks to be added recently. If we use this we needn't
> use xe_device_mem_access_get.
See comment at init_samples.
>
> >
> >> + * we suspend we set the submission_state.enabled to false.
> >> + */
> >> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> >> + if (device_awake)
> >> + val = __engine_group_busyness_read(gt, config);
> >> +
> >> + spin_lock_irqsave(&pmu->lock, flags);
> >> +
> >> + if (device_awake)
> >> + store_sample(pmu, gt_id, sample_type, val);
> >> + else
> >> + val = read_sample(pmu, gt_id, sample_type);
> >> +
> >> + spin_unlock_irqrestore(&pmu->lock, flags);
> >> +
> >> + return val;
> >> +}
> >> +
> >> +void engine_group_busyness_store(struct xe_gt *gt)
> >> +{
> >> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >> + unsigned int gt_id = gt->info.id;
> >> + unsigned long flags;
> >> +
> >> + spin_lock_irqsave(&pmu->lock, flags);
> >> +
> >> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >> +
> >> + spin_unlock_irqrestore(&pmu->lock, flags);
> >> +}
> >> +
> >> +static int
> >> +config_status(struct xe_device *xe, u64 config)
> >> +{
> >> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> >> + unsigned int gt_id = config_gt_id(config);
> >> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> >> +
> >> + if (gt_id > max_gt_id)
> >> + return -ENOENT;
> >> +
> >> + switch (config_counter(config)) {
> >> + case XE_PMU_INTERRUPTS(0):
> >> + if (gt_id)
> >> + return -ENOENT;
> >
> > OK: this is a global event so we say this is enabled only for gt0.
> >
> >> + break;
> >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >> + case XE_PMU_COPY_GROUP_BUSY(0):
> >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >> + if (GRAPHICS_VER(xe) < 12)
> >
> > Any point checking? xe only supports Gen12+.
>
> hmmm ya good point will remove this.
> >
> >> + return -ENOENT;
> >> + break;
> >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
> >> + return -ENOENT;
> >
> > OK: this makes sense, so we will expose this event only for media gt's.
> >
> >> + break;
> >> + default:
> >> + return -ENOENT;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int xe_pmu_event_init(struct perf_event *event)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> + int ret;
> >> +
> >> + if (pmu->closed)
> >> + return -ENODEV;
> >> +
> >> + if (event->attr.type != event->pmu->type)
> >> + return -ENOENT;
> >> +
> >> + /* unsupported modes and filters */
> >> + if (event->attr.sample_period) /* no sampling */
> >> + return -EINVAL;
> >> +
> >> + if (has_branch_stack(event))
> >> + return -EOPNOTSUPP;
> >> +
> >> + if (event->cpu < 0)
> >> + return -EINVAL;
> >> +
> >> + /* only allow running on one cpu at a time */
> >> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> >> + return -EINVAL;
> >> +
> >> + ret = config_status(xe, event->attr.config);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (!event->parent) {
> >> + drm_dev_get(&xe->drm);
> >> + event->destroy = xe_pmu_event_destroy;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static u64 __xe_pmu_event_read(struct perf_event *event)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> + const unsigned int gt_id = config_gt_id(event->attr.config);
> >> + const u64 config = config_counter(event->attr.config);
> >> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> + u64 val = 0;
> >> +
> >> + switch (config) {
> >> + case XE_PMU_INTERRUPTS(0):
> >> + val = READ_ONCE(pmu->irq_count);
> >
> > OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff would
> > be to take pmu->lock (both while reading and writing irq_count) but that
> > would be expensive in the interrupt handler (as the .h hints). So all we
> > can do is what is done here.
> >
> >> + break;
> >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> >> + case XE_PMU_COPY_GROUP_BUSY(0):
> >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> >> + val = engine_group_busyness_read(gt, config);
> >> + }
> >> +
> >> + return val;
> >> +}
> >> +
> >> +static void xe_pmu_event_read(struct perf_event *event)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> + struct hw_perf_event *hwc = &event->hw;
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> + u64 prev, new;
> >> +
> >> + if (pmu->closed) {
> >> + event->hw.state = PERF_HES_STOPPED;
> >> + return;
> >> + }
> >> +again:
> >> + prev = local64_read(&hwc->prev_count);
> >> + new = __xe_pmu_event_read(event);
> >> +
> >> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> >> + goto again;
> >> +
> >> + local64_add(new - prev, &event->count);
> >> +}
> >> +
> >> +static void xe_pmu_enable(struct perf_event *event)
> >> +{
> >> + /*
> >> + * Store the current counter value so we can report the correct delta
> >> + * for all listeners. Even when the event was already enabled and has
> >> + * an existing non-zero value.
> >> + */
> >> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> >> +}
> >> +
> >> +static void xe_pmu_event_start(struct perf_event *event, int flags)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> +
> >> + if (pmu->closed)
> >> + return;
> >> +
> >> + xe_pmu_enable(event);
> >> + event->hw.state = 0;
> >> +}
> >> +
> >> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
> >> +{
> >> + if (flags & PERF_EF_UPDATE)
> >> + xe_pmu_event_read(event);
> >> +
> >> + event->hw.state = PERF_HES_STOPPED;
> >> +}
> >> +
> >> +static int xe_pmu_event_add(struct perf_event *event, int flags)
> >> +{
> >> + struct xe_device *xe =
> >> + container_of(event->pmu, typeof(*xe), pmu.base);
> >> + struct xe_pmu *pmu = &xe->pmu;
> >> +
> >> + if (pmu->closed)
> >> + return -ENODEV;
> >> +
> >> + if (flags & PERF_EF_START)
> >> + xe_pmu_event_start(event, flags);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void xe_pmu_event_del(struct perf_event *event, int flags)
> >> +{
> >> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
> >> +}
> >> +
> >> +static int xe_pmu_event_event_idx(struct perf_event *event)
> >> +{
> >> + return 0;
> >> +}
> >> +
> >> +struct xe_str_attribute {
> >> + struct device_attribute attr;
> >> + const char *str;
> >> +};
> >> +
> >> +static ssize_t xe_pmu_format_show(struct device *dev,
> >> + struct device_attribute *attr, char *buf)
> >> +{
> >> + struct xe_str_attribute *eattr;
> >> +
> >> + eattr = container_of(attr, struct xe_str_attribute, attr);
> >> + return sprintf(buf, "%s\n", eattr->str);
> >> +}
> >> +
> >> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> >> + (&((struct xe_str_attribute[]) { \
> >> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
> >> + .str = _config, } \
> >> + })[0].attr.attr)
> >> +
> >> +static struct attribute *xe_pmu_format_attrs[] = {
> >> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> >
> > 0-20 means 0-20 bits? Though here we probably have different number of
> > config bits? Probably doesn't matter?
>
> as i understand this is not used anymore so will remove it.
>
> >
> > The string will show up with:
> >
> > cat /sys/devices/xe/format/xe_eventid
> >
> >> + NULL,
> >> +};
> >> +
> >> +static const struct attribute_group xe_pmu_format_attr_group = {
> >> + .name = "format",
> >> + .attrs = xe_pmu_format_attrs,
> >> +};
> >> +
> >> +struct xe_ext_attribute {
> >> + struct device_attribute attr;
> >> + unsigned long val;
> >> +};
> >> +
> >> +static ssize_t xe_pmu_event_show(struct device *dev,
> >> + struct device_attribute *attr, char *buf)
> >> +{
> >> + struct xe_ext_attribute *eattr;
> >> +
> >> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> >> + return sprintf(buf, "config=0x%lx\n", eattr->val);
> >> +}
> >> +
> >> +static ssize_t cpumask_show(struct device *dev,
> >> + struct device_attribute *attr, char *buf)
> >> +{
> >> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
> >> +}
> >> +
> >> +static DEVICE_ATTR_RO(cpumask);
> >> +
> >> +static struct attribute *xe_cpumask_attrs[] = {
> >> + &dev_attr_cpumask.attr,
> >> + NULL,
> >> +};
> >> +
> >> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> >> + .attrs = xe_cpumask_attrs,
> >> +};
> >> +
> >> +#define __event(__counter, __name, __unit) \
> >> +{ \
> >> + .counter = (__counter), \
> >> + .name = (__name), \
> >> + .unit = (__unit), \
> >> + .global = false, \
> >> +}
> >> +
> >> +#define __global_event(__counter, __name, __unit) \
> >> +{ \
> >> + .counter = (__counter), \
> >> + .name = (__name), \
> >> + .unit = (__unit), \
> >> + .global = true, \
> >> +}
> >> +
> >> +static struct xe_ext_attribute *
> >> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
> >> +{
> >> + sysfs_attr_init(&attr->attr.attr);
> >> + attr->attr.attr.name = name;
> >> + attr->attr.attr.mode = 0444;
> >> + attr->attr.show = xe_pmu_event_show;
> >> + attr->val = config;
> >> +
> >> + return ++attr;
> >> +}
> >> +
> >> +static struct perf_pmu_events_attr *
> >> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> >> + const char *str)
> >> +{
> >> + sysfs_attr_init(&attr->attr.attr);
> >> + attr->attr.attr.name = name;
> >> + attr->attr.attr.mode = 0444;
> >> + attr->attr.show = perf_event_sysfs_show;
> >> + attr->event_str = str;
> >> +
> >> + return ++attr;
> >> +}
> >> +
> >> +static struct attribute **
> >> +create_event_attributes(struct xe_pmu *pmu)
> >> +{
> >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> >> + static const struct {
> >> + unsigned int counter;
> >> + const char *name;
> >> + const char *unit;
> >> + bool global;
> >> + } events[] = {
> >> + __global_event(0, "interrupts", NULL),
> >> + __event(1, "render-group-busy", "ns"),
> >> + __event(2, "copy-group-busy", "ns"),
> >> + __event(3, "media-group-busy", "ns"),
> >> + __event(4, "any-engine-group-busy", "ns"),
> >> + };
> >
> > OK: this function is some black magic to expose stuff through
> > PMU. Identical to i915 and seems to be working from the commit message so
> > should be fine.
> >
> >> +
> >> + unsigned int count = 0;
> >> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> >> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> >> + struct attribute **attr = NULL, **attr_iter;
> >> + struct xe_gt *gt;
> >> + unsigned int i, j;
> >> +
> >> + /* Count how many counters we will be exposing. */
> >> + for_each_gt(gt, xe, j) {
> >> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> >> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> >> +
> >> + if (!config_status(xe, config))
> >> + count++;
> >> + }
> >> + }
> >> +
> >> + /* Allocate attribute objects and table. */
> >> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> >> + if (!xe_attr)
> >> + goto err_alloc;
> >> +
> >> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> >> + if (!pmu_attr)
> >> + goto err_alloc;
> >> +
> >> + /* Max one pointer of each attribute type plus a termination entry. */
> >> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> >> + if (!attr)
> >> + goto err_alloc;
> >> +
> >> + xe_iter = xe_attr;
> >> + pmu_iter = pmu_attr;
> >> + attr_iter = attr;
> >> +
> >> + for_each_gt(gt, xe, j) {
> >> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> >> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> >> + char *str;
> >> +
> >> + if (config_status(xe, config))
> >> + continue;
> >> +
> >> + if (events[i].global)
> >> + str = kstrdup(events[i].name, GFP_KERNEL);
> >> + else
> >> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> >> + events[i].name, j);
> >> + if (!str)
> >> + goto err;
> >> +
> >> + *attr_iter++ = &xe_iter->attr.attr;
> >> + xe_iter = add_xe_attr(xe_iter, str, config);
> >> +
> >> + if (events[i].unit) {
> >> + if (events[i].global)
> >> + str = kasprintf(GFP_KERNEL, "%s.unit",
> >> + events[i].name);
> >> + else
> >> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
> >> + events[i].name, j);
> >> + if (!str)
> >> + goto err;
> >> +
> >> + *attr_iter++ = &pmu_iter->attr.attr;
> >> + pmu_iter = add_pmu_attr(pmu_iter, str,
> >> + events[i].unit);
> >> + }
> >> + }
> >> + }
> >> +
> >> + pmu->xe_attr = xe_attr;
> >> + pmu->pmu_attr = pmu_attr;
> >> +
> >> + return attr;
> >> +
> >> +err:
> >> + for (attr_iter = attr; *attr_iter; attr_iter++)
> >> + kfree((*attr_iter)->name);
> >> +
> >> +err_alloc:
> >> + kfree(attr);
> >> + kfree(xe_attr);
> >> + kfree(pmu_attr);
> >> +
> >> + return NULL;
> >> +}
> >> +
> >> +static void free_event_attributes(struct xe_pmu *pmu)
> >> +{
> >> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> >> +
> >> + for (; *attr_iter; attr_iter++)
> >> + kfree((*attr_iter)->name);
> >> +
> >> + kfree(pmu->events_attr_group.attrs);
> >> + kfree(pmu->xe_attr);
> >> + kfree(pmu->pmu_attr);
> >> +
> >> + pmu->events_attr_group.attrs = NULL;
> >> + pmu->xe_attr = NULL;
> >> + pmu->pmu_attr = NULL;
> >> +}
> >> +
> >> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> >> +{
> >> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> >> +
> >> + XE_BUG_ON(!pmu->base.event_init);
> >> +
> >> + /* Select the first online CPU as a designated reader. */
> >> + if (cpumask_empty(&xe_pmu_cpumask))
> >> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
> >> +{
> >> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> >> + unsigned int target = xe_pmu_target_cpu;
> >> +
> >> + XE_BUG_ON(!pmu->base.event_init);
> >> +
> >> + /*
> >> + * Unregistering an instance generates a CPU offline event which we must
> >> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
> >> + */
> >> + if (pmu->closed)
> >> + return 0;
> >> +
> >> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> >> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
> >> +
> >> + /* Migrate events if there is a valid target */
> >> + if (target < nr_cpu_ids) {
> >> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> >> + xe_pmu_target_cpu = target;
> >> + }
> >> + }
> >> +
> >> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> >> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> >> + pmu->cpuhp.cpu = target;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> >> +
> >> +int xe_pmu_init(void)
> >> +{
> >> + int ret;
> >> +
> >> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> >> + "perf/x86/intel/xe:online",
> >> + xe_pmu_cpu_online,
> >> + xe_pmu_cpu_offline);
> >> + if (ret < 0)
> >> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> >> + ret);
> >> + else
> >> + cpuhp_slot = ret;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +void xe_pmu_exit(void)
> >> +{
> >> + if (cpuhp_slot != CPUHP_INVALID)
> >> + cpuhp_remove_multi_state(cpuhp_slot);
> >> +}
> >> +
> >> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
> >> +{
> >> + if (cpuhp_slot == CPUHP_INVALID)
> >> + return -EINVAL;
> >> +
> >> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> >> +}
> >> +
> >> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
> >> +{
> >> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
> >> +}
> >> +
> >> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
> >> +{
> >> + struct xe_pmu *pmu = arg;
> >> +
> >> + if (!pmu->base.event_init)
> >> + return;
> >> +
> >> + /*
> >> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
> >> + * ensures all currently executing ones will have exited before we
> >> + * proceed with unregistration.
> >> + */
> >> + pmu->closed = true;
> >> + synchronize_rcu();
> >> +
> >> + xe_pmu_unregister_cpuhp_state(pmu);
> >> +
> >> + perf_pmu_unregister(&pmu->base);
> >> + pmu->base.event_init = NULL;
> >> + kfree(pmu->base.attr_groups);
> >> + kfree(pmu->name);
> >> + free_event_attributes(pmu);
> >> +}
> >> +
> >> +static void init_samples(struct xe_pmu *pmu)
> >> +{
> >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> >> + struct xe_gt *gt;
> >> + unsigned int i;
> >> +
> >> + for_each_gt(gt, xe, i)
> >> + engine_group_busyness_store(gt);
> >> +}
> >> +
> >> +void xe_pmu_register(struct xe_pmu *pmu)
> >
> > Why void, why not int? PMU failure is non fatal error?
>
> Ya device is functional , it is only that these counters are not
> available. Hence didn't want to fail the driver load.
> >
> >> +{
> >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> >> + const struct attribute_group *attr_groups[] = {
> >> + &xe_pmu_format_attr_group,
> >> + &pmu->events_attr_group,
> >> + &xe_pmu_cpumask_attr_group,
> >
> > Can someone please explain what this cpumask/cpuhotplug stuff does and
> > whether it needs to be in this patch? There's something here:
>
> comments from original patch series in
> i915:https://patchwork.kernel.org/project/intel-gfx/patch/20170802123249.14194-5-tvrtko.ursulin@linux.intel.com/
>
> "IIRC an uncore PMU should expose a cpumask through sysfs, and then perf
> tools will read that mask and auto-magically limit the number of CPUs it
> instantiates the counter on."
>
> and ours are global counters not per cpu so we limit to just to single cpu.
>
> And as i understand we use the cpuhotplug support to migrate too new cpu
> incase the earlier one goes offline.
OK, leave as is.
>
> >
> > b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
> >
> > I'd rather just have the basic PMU infra and the events in this patch and
> > punt this cpumask/cpuhotplug stuff to a later patch, unless someone can say
> > what it does.
> >
> > Though perf_pmu_register seems to be doing some per cpu stuff so likely
> > this is needed. But amdgpu_pmu only has event and format attributes.
> >
> > Mostly leave as is I guess.
> >
> >> + NULL
> >> + };
> >> +
> >> + int ret = -ENOMEM;
> >> +
> >> + spin_lock_init(&pmu->lock);
> >> + pmu->cpuhp.cpu = -1;
> >> + init_samples(pmu);
> >
> > Why init_samples here? Can't we init the particular sample in
> > xe_pmu_event_init or even xe_pmu_event_start?
> >
> > Init'ing here may be too soon since the event might not be enabled for a
> > long time. So really this needs to move to xe_pmu_event_init or
> > xe_pmu_event_start.
>
> The device is put to suspend immediately after driver probe, typically
> pmu is opened even before any workload is run so essentially device is
> still in suspend state hence we cannot access registers so storing the
> last known value in init_samples. otherwise we see the bug in v#1 of series.
>
> >
> > Actually this is already happening in xe_pmu_enable. We just need to decide
> > when we want to wake the device up and when we don't. So maybe wake the
> > device up at start (use xe_device_mem_access_get) and not wake up during
> > read (xe_device_mem_access_get_if_ongoing etc.)?
Just going to repeat this again:
xe_pmu_event_start calls xe_pmu_enable. In xe_pmu_enable use
xe_device_mem_access_get before calling __xe_pmu_event_read. This will wake
the device up and get a valid value in event->hw.prev_count.
In xe_pmu_event_read, use xe_device_mem_access_get_if_ongoing, to read the
event without waking the device up (and return previous value etc.).
Or, pass a flag in to __xe_pmu_event_read and to engine_group_busyness_read
and __engine_group_busyness_read. The flag will say whether or not to wake
up the device. If the flag says wake the device up, call
xe_device_mem_access_get and xe_force_wake_get, maybe in
__engine_group_busyness_read, before reading device registers. If the flag
says don't wake up the device call xe_device_mem_access_get_if_ongoing.
This way we:
* don't need to call init_samples in xe_pmu_register
* we don't need engine_group_busyness_store
* we don't need to specifically call engine_group_busyness_store in xe_gt_suspend
The correct sample is read by waking up the device in xe_pmu_event_start.
Hopefully this is clear now.
>
> >
> >> +
> >> + pmu->name = kasprintf(GFP_KERNEL,
> >> + "xe_%s",
> >> + dev_name(xe->drm.dev));
> >> + if (pmu->name)
> >> + /* tools/perf reserves colons as special. */
> >> + strreplace((char *)pmu->name, ':', '_');
> >> +
> >> + if (!pmu->name)
> >> + goto err;
> >> +
> >> + pmu->events_attr_group.name = "events";
> >> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> >> + if (!pmu->events_attr_group.attrs)
> >> + goto err_name;
> >> +
> >> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
> >> + GFP_KERNEL);
> >> + if (!pmu->base.attr_groups)
> >> + goto err_attr;
> >> +
> >> + pmu->base.module = THIS_MODULE;
> >> + pmu->base.task_ctx_nr = perf_invalid_context;
> >> + pmu->base.event_init = xe_pmu_event_init;
> >> + pmu->base.add = xe_pmu_event_add;
> >> + pmu->base.del = xe_pmu_event_del;
> >> + pmu->base.start = xe_pmu_event_start;
> >> + pmu->base.stop = xe_pmu_event_stop;
> >> + pmu->base.read = xe_pmu_event_read;
> >> + pmu->base.event_idx = xe_pmu_event_event_idx;
> >> +
> >> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> >> + if (ret)
> >> + goto err_groups;
> >> +
> >> + ret = xe_pmu_register_cpuhp_state(pmu);
> >> + if (ret)
> >> + goto err_unreg;
> >> +
> >> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
> >> + XE_WARN_ON(ret);
> >
> > We should just follow the regular error rewind here too and let
> > drm_notice() at the end print the error. This is what other drivers calling
> > drmm_add_action_or_reset seem to be doing.
>
> Ok ok.
> >
> >> +
> >> + return;
> >> +
> >> +err_unreg:
> >> + perf_pmu_unregister(&pmu->base);
> >> +err_groups:
> >> + kfree(pmu->base.attr_groups);
> >> +err_attr:
> >> + pmu->base.event_init = NULL;
> >> + free_event_attributes(pmu);
> >> +err_name:
> >> + kfree(pmu->name);
> >> +err:
> >> + drm_notice(&xe->drm, "Failed to register PMU!\n");
> >> +}
> >> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> >> new file mode 100644
> >> index 000000000000..d3f47f4ab343
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> >> @@ -0,0 +1,25 @@
> >> +/* SPDX-License-Identifier: MIT */
> >> +/*
> >> + * Copyright © 2023 Intel Corporation
> >> + */
> >> +
> >> +#ifndef _XE_PMU_H_
> >> +#define _XE_PMU_H_
> >> +
> >> +#include "xe_gt_types.h"
> >> +#include "xe_pmu_types.h"
> >> +
> >> +#ifdef CONFIG_PERF_EVENTS
> >
> > nit but maybe this should be:
> >
> > #if IS_ENABLED(CONFIG_PERF_EVENTS)
> >
> > or,
> >
> > #if IS_BUILTIN(CONFIG_PERF_EVENTS)
> >
> > Note CONFIG_PERF_EVENTS is a boolean kconfig option.
> >
> > See similar macro IS_REACHABLE() in i915_hwmon.h.
> >
> >> +int xe_pmu_init(void);
> >> +void xe_pmu_exit(void);
> >> +void xe_pmu_register(struct xe_pmu *pmu);
> >> +void engine_group_busyness_store(struct xe_gt *gt);
> >
> > Add xe_pmu_ prefix if function is needed (hopefully not).
>
> OK
> >
> >> +#else
> >> +static inline int xe_pmu_init(void) { return 0; }
> >> +static inline void xe_pmu_exit(void) {}
> >> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
> >> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
> >> +#endif
> >> +
> >> +#endif
> >> +
> >> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
> >> new file mode 100644
> >> index 000000000000..e87edd4d6a87
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> >> @@ -0,0 +1,80 @@
> >> +/* SPDX-License-Identifier: MIT */
> >> +/*
> >> + * Copyright © 2023 Intel Corporation
> >> + */
> >> +
> >> +#ifndef _XE_PMU_TYPES_H_
> >> +#define _XE_PMU_TYPES_H_
> >> +
> >> +#include <linux/perf_event.h>
> >> +#include <linux/spinlock_types.h>
> >> +#include <uapi/drm/xe_drm.h>
> >> +
> >> +enum {
> >> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> >> + __XE_SAMPLE_COPY_GROUP_BUSY,
> >> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >> + __XE_NUM_PMU_SAMPLERS
> >
> > OK: irq_count is missing here since these are read from device...
> >
> >> +};
> >> +
> >> +struct xe_pmu_sample {
> >> + u64 cur;
> >> +};
> >
> > This was also discussed for i915 PMU, no point having a struct with a
> > single u64 member. Might as well just use u64 wherever we are using
> > struct xe_pmu_sample.
>
> OK.
> >
> >> +
> >> +#define XE_MAX_GT_PER_TILE 2
> >
> > Why per tile? The array size should be max_gt_per_device. Just call it
> > XE_MAX_GT?
>
> I declared similar to what we have in drivers/gpu/drm/xe/xe_device.h
Our 2-d array size is for the device, not per tile. So let's use XE_MAX_GT.
> >
> >> +
> >> +struct xe_pmu {
> >> + /**
> >> + * @cpuhp: Struct used for CPU hotplug handling.
> >> + */
> >> + struct {
> >> + struct hlist_node node;
> >> + unsigned int cpu;
> >> + } cpuhp;
> >> + /**
> >> + * @base: PMU base.
> >> + */
> >> + struct pmu base;
> >> + /**
> >> + * @closed: xe is unregistering.
> >> + */
> >> + bool closed;
> >> + /**
> >> + * @name: Name as registered with perf core.
> >> + */
> >> + const char *name;
> >> + /**
> >> + * @lock: Lock protecting enable mask and ref count handling.
> >> + */
> >> + spinlock_t lock;
> >> + /**
> >> + * @sample: Current and previous (raw) counters.
> >> + *
> >> + * These counters are updated when the device is awake.
> >> + *
> >> + */
> >> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
> >
> > Change to 2-d array. See above.
> >
> >> + /**
> >> + * @irq_count: Number of interrupts
> >> + *
> >> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> >> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> >> + * occasional wraparound easily. It's 32bit after all.
> >> + */
> >> + unsigned long irq_count;
> >> + /**
> >> + * @events_attr_group: Device events attribute group.
> >> + */
> >> + struct attribute_group events_attr_group;
> >> + /**
> >> + * @xe_attr: Memory block holding device attributes.
> >> + */
> >> + void *xe_attr;
> >> + /**
> >> + * @pmu_attr: Memory block holding device attributes.
> >> + */
> >> + void *pmu_attr;
> >> +};
> >> +
> >> +#endif
> >> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> >> index 965cd9527ff1..ed097056f944 100644
> >> --- a/include/uapi/drm/xe_drm.h
> >> +++ b/include/uapi/drm/xe_drm.h
> >> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> >> __u64 reserved[2];
> >> };
> >>
> >> +/* PMU event config IDs */
> >> +
> >> +/*
> >> + * Top 4 bits of every counter are GT id.
> >> + */
> >> +#define __XE_PMU_GT_SHIFT (60)
> >
> > To future-proof this, and also because we seem to have plenty of bits
> > available, I think we should change this to 56 (instead of 60).
>
> OK
>
> Thanks,
> Aravind.
> >
> >> +
> >> +#define ___XE_PMU_OTHER(gt, x) \
> >> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> >> +
> >> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
> >> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
> >> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
> >> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
> >> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
> >> +
> >> #if defined(__cplusplus)
> >> }
> >> #endif
> >> --
> >> 2.25.1
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-21 23:36 ` Dixit, Ashutosh
@ 2023-07-22 6:04 ` Dixit, Ashutosh
2023-07-24 8:03 ` Iddamsetty, Aravind
2023-07-24 9:38 ` Iddamsetty, Aravind
0 siblings, 2 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-22 6:04 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>
> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >
> Hi Aravind,
>
> > On 21-07-2023 06:32, Dixit, Ashutosh wrote:
> > > On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
> > >>
> > > More stuff to mull over. You can ignore comments starting with "OK", those
> > > are just notes to myself.
> > >
> > > Also, maybe some time we can add a basic IGT which reads these exposed
> > > counters and verifies that we can read them and they are monotonically
> > > increasing?
> >
> > this is the IGT https://patchwork.freedesktop.org/series/119936/ series
> > using these counters posted by Venkat.
> >
> > >
> > >> There are a set of engine group busyness counters provided by HW which are
> > >> perfect fit to be exposed via PMU perf events.
> > >>
> > >> BSPEC: 46559, 46560, 46722, 46729
> > >
> > > Also add these Bspec entries: 71028, 52071
> >
> > OK.
> >
> > >
> > >>
> > >> events can be listed using:
> > >> perf list
> > >> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
> > >> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
> > >> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
> > >> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
> > >> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
> > >>
> > >> and can be read using:
> > >>
> > >> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
> > >> time counts unit events
> > >> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
> > >>
> > >> The pmu base implementation is taken from i915.
> > >>
> > >> v2:
> > >> Store last known value when device is awake return that while the GT is
> > >> suspended and then update the driver copy when read during awake.
> > >>
> > >> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > >> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> > >> ---
> > >> drivers/gpu/drm/xe/Makefile | 2 +
> > >> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
> > >> drivers/gpu/drm/xe/xe_device.c | 2 +
> > >> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> > >> drivers/gpu/drm/xe/xe_gt.c | 2 +
> > >> drivers/gpu/drm/xe/xe_irq.c | 22 +
> > >> drivers/gpu/drm/xe/xe_module.c | 5 +
> > >> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
> > >> drivers/gpu/drm/xe/xe_pmu.h | 25 +
> > >> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
> > >> include/uapi/drm/xe_drm.h | 16 +
> > >> 11 files changed, 902 insertions(+)
> > >> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
> > >> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
> > >> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
> > >>
> > >> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > >> index 081c57fd8632..e52ab795c566 100644
> > >> --- a/drivers/gpu/drm/xe/Makefile
> > >> +++ b/drivers/gpu/drm/xe/Makefile
> > >> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> > >> i915-display/skl_universal_plane.o \
> > >> i915-display/skl_watermark.o
> > >>
> > >> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> > >> +
> > >> ifeq ($(CONFIG_ACPI),y)
> > >> xe-$(CONFIG_DRM_XE_DISPLAY) += \
> > >> i915-display/intel_acpi.o \
> > >> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > >> index 3f664011eaea..c7d9e4634745 100644
> > >> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > >> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > >> @@ -285,6 +285,11 @@
> > >> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> > >> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
> > >>
> > >> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
> > >> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
> > >> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
> > >> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
> > >> +
> > >> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
> > >> #define ENABLE_SMALLPL REG_BIT(15)
> > >> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> > >> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > >> index c7985af85a53..b2c7bd4a97d9 100644
> > >> --- a/drivers/gpu/drm/xe/xe_device.c
> > >> +++ b/drivers/gpu/drm/xe/xe_device.c
> > >> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
> > >>
> > >> xe_debugfs_register(xe);
> > >>
> > >> + xe_pmu_register(&xe->pmu);
> > >> +
> > >> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> > >> if (err)
> > >> return err;
> > >> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > >> index 0226d44a6af2..3ba99aae92b9 100644
> > >> --- a/drivers/gpu/drm/xe/xe_device_types.h
> > >> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > >> @@ -15,6 +15,7 @@
> > >> #include "xe_devcoredump_types.h"
> > >> #include "xe_gt_types.h"
> > >> #include "xe_platform_types.h"
> > >> +#include "xe_pmu.h"
> > >> #include "xe_step_types.h"
> > >>
> > >> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> > >> @@ -332,6 +333,9 @@ struct xe_device {
> > >> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
> > >> bool d3cold_allowed;
> > >>
> > >> + /* @pmu: performance monitoring unit */
> > >> + struct xe_pmu pmu;
> > >> +
> > >
> > > Now I am wondering why we don't make the PMU per-gt (or per-tile)? Per-gt
> > > would work for these busyness registers and I am not sure how the
> > > interrupts are hooked up.
> > >
> > > In i915 the PMU being device level helped in having a single timer (rather
> > > than a per gt timer).
> > >
> > > Anyway probably not much practical benefit by make it per-gt/per-tile, so
> > > maybe leave as is. Just thinking out loud.
> >
> > we are able to expose per-gt counters so do not see any benefit in
> > making pmu per-gt, also i believe struct pmu is per device it will have
> > a type associated which is unique for a device.
>
> PMU can be made per gt and named xe-gt0, xe-gt1 etc. if we want. But anyway
> leave as is.
>
> >
> > >
> > >> /* private: */
> > >>
> > >> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> > >> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > >> index 2458397ce8af..96e3720923d4 100644
> > >> --- a/drivers/gpu/drm/xe/xe_gt.c
> > >> +++ b/drivers/gpu/drm/xe/xe_gt.c
> > >> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> > >> if (err)
> > >> goto err_msg;
> > >>
> > >> + engine_group_busyness_store(gt);
> > >
> > > Not sure I follow the reason for doing this at suspend time? If PMU was
> > > active there should be a previous value. Why must we take a new sample
> > > explicitly here?
> >
> > the PMU interface can be read even when device is suspend and in such
> > cases we should not wake up the device, and if we try to read the
> > register when device is suspended it gives spurious counter you can
> > check in version#1 of this series we were getting huge values. as we put
> > the device to suspend immediately after probe. So storing the last known
> > good value before suspend.
>
> No need, see comment at init_samples below.
Sorry, you are right, I changed my mind about this, I see your point. See
more discussion on this at init_samples below.
>
> >
> > >
> > > To me looks like engine_group_busyness_store should not be needed, see
> > > comment below for init_samples too.
> > >
> > >> +
> > >> err = xe_uc_suspend(>->uc);
> > >> if (err)
> > >> goto err_force_wake;
> > >> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > >> index b4ed1e4a3388..cb943fb94ec7 100644
> > >> --- a/drivers/gpu/drm/xe/xe_irq.c
> > >> +++ b/drivers/gpu/drm/xe/xe_irq.c
> > >> @@ -27,6 +27,24 @@
> > >> #define IIR(offset) XE_REG(offset + 0x8)
> > >> #define IER(offset) XE_REG(offset + 0xc)
> > >>
> > >> +/*
> > >> + * Interrupt statistic for PMU. Increments the counter only if the
> > >> + * interrupt originated from the GPU so interrupts from a device which
> > >> + * shares the interrupt line are not accounted.
> > >> + */
> > >> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
> > >
> > > No inline, compiler will do it, but looks like we may want to always_inline
> > > this. Also this function should really be in xe_pmu.h? Anyway probably
> > > leave as is.
> > >
> > >> + irqreturn_t res)
> > >> +{
> > >> + if (unlikely(res != IRQ_HANDLED))
> > >> + return;
> > >> +
> > >> + /*
> > >> + * A clever compiler translates that into INC. A not so clever one
> > >> + * should at least prevent store tearing.
> > >> + */
> > >> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
> > >> +}
> > >> +
> > >> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> > >> {
> > >> u32 val = xe_mmio_read32(mmio, reg);
> > >> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
> > >>
> > >> xe_display_irq_enable(xe, gu_misc_iir);
> > >>
> > >> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> > >> +
> > >> return IRQ_HANDLED;
> > >> }
> > >>
> > >> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > >> dg1_intr_enable(xe, false);
> > >> xe_display_irq_enable(xe, gu_misc_iir);
> > >>
> > >> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
> > >> +
> > >> return IRQ_HANDLED;
> > >> }
> > >>
> > >> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> > >> index 75e5be939f53..f6fe89748525 100644
> > >> --- a/drivers/gpu/drm/xe/xe_module.c
> > >> +++ b/drivers/gpu/drm/xe/xe_module.c
> > >> @@ -12,6 +12,7 @@
> > >> #include "xe_hw_fence.h"
> > >> #include "xe_module.h"
> > >> #include "xe_pci.h"
> > >> +#include "xe_pmu.h"
> > >> #include "xe_sched_job.h"
> > >>
> > >> bool enable_guc = true;
> > >> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
> > >> .init = xe_sched_job_module_init,
> > >> .exit = xe_sched_job_module_exit,
> > >> },
> > >> + {
> > >> + .init = xe_pmu_init,
> > >> + .exit = xe_pmu_exit,
> > >> + },
> > >> {
> > >> .init = xe_register_pci_driver,
> > >> .exit = xe_unregister_pci_driver,
> > >> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
> > >> new file mode 100644
> > >> index 000000000000..bef1895be9f7
> > >> --- /dev/null
> > >> +++ b/drivers/gpu/drm/xe/xe_pmu.c
> > >> @@ -0,0 +1,739 @@
> > >> +/*
> > >> + * SPDX-License-Identifier: MIT
> > >> + *
> > >> + * Copyright © 2023 Intel Corporation
> > >> + */
> > >
> > > This SPDX header is for .h files not .c files. Actually, it is for neither :/
> >
> > But i see this in almost all the files in xe.
>
> Look closely.
>
> > >
> > >> +
> > >> +#include <drm/drm_drv.h>
> > >> +#include <drm/drm_managed.h>
> > >> +#include <drm/xe_drm.h>
> > >> +
> > >> +#include "regs/xe_gt_regs.h"
> > >> +#include "xe_device.h"
> > >> +#include "xe_gt_clock.h"
> > >> +#include "xe_mmio.h"
> > >> +
> > >> +static cpumask_t xe_pmu_cpumask;
> > >> +static unsigned int xe_pmu_target_cpu = -1;
> > >> +
> > >> +static unsigned int config_gt_id(const u64 config)
> > >> +{
> > >> + return config >> __XE_PMU_GT_SHIFT;
> > >> +}
> > >> +
> > >> +static u64 config_counter(const u64 config)
> > >> +{
> > >> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
> > >> +}
> > >> +
> > >> +static unsigned int
> > >> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> > >> +{
> > >> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
> > >> +
> > >> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> > >> +
> > >> + return idx;
> > >> +}
> > >
> > > The compiler does this for us if we make sample array 2-d.
> > >
> > >> +
> > >> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
> > >> +{
> > >> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
> > >> +}
> > >> +
> > >> +static void
> > >> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
> > >> +{
> > >> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
> > >> +}
> > >
> > > The three functions above are not needed if we make the sample array
> > > 2-d. See here:
> > >
> > > https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
> > >
> > > Only a part of the patch above was merged (see 8ed0753b527dc) to keep the
> > > patch size small, but since for xe we are starting from scratch we can
> > > implement the whole approach above (get rid of the read/store helpers
> > > entirely, direct assignment without the helpers works).
> >
> > Ok I'll go over it.
> >
> > >
> > >> +
> > >> +static int engine_busyness_sample_type(u64 config)
> > >> +{
> > >> + int type = 0;
> > >> +
> > >> + switch (config) {
> > >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> > >> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
> > >> + break;
> > >> + case XE_PMU_COPY_GROUP_BUSY(0):
> > >> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
> > >> + break;
> > >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> > >> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
> > >> + break;
> > >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> > >> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
> > >> + break;
> > >> + }
> > >> +
> > >> + return type;
> > >> +}
> > >> +
> > >> +static void xe_pmu_event_destroy(struct perf_event *event)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> +
> > >> + drm_WARN_ON(&xe->drm, event->parent);
> > >> +
> > >> + drm_dev_put(&xe->drm);
> > >> +}
> > >> +
> > >> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
> > >> +{
> > >> + u64 val = 0;
> > >> +
> > >> + switch (config) {
> > >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> > >> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
> > >> + break;
> > >> + case XE_PMU_COPY_GROUP_BUSY(0):
> > >> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
> > >> + break;
> > >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> > >> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
> > >> + break;
> > >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> > >> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
> > >> + break;
> > >> + default:
> > >> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
> > >> + }
> > >
> > > We need xe_device_mem_access_get, also xe_force_wake_get if applicable,
> > > somewhere before reading these registers.
> > >
> > >> +
> > >> + return xe_gt_clock_interval_to_ns(gt, val * 16);
> > >> +}
> > >> +
> > >> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
> > >> +{
> > >> + int sample_type = engine_busyness_sample_type(config);
> > >> + struct xe_device *xe = gt->tile->xe;
> > >> + const unsigned int gt_id = gt->info.id;
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> + bool device_awake;
> > >> + unsigned long flags;
> > >> + u64 val;
> > >> +
> > >> + /*
> > >> + * found no better way to check if device is awake or not. Before
> > >
> > > xe_device_mem_access_get_if_ongoing (hard to find name).
> >
> > thanks for sharing looks to be added recently. If we use this we needn't
> > use xe_device_mem_access_get.
>
> See comment at init_samples.
>
> >
> > >
> > >> + * we suspend we set the submission_state.enabled to false.
> > >> + */
> > >> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
> > >> + if (device_awake)
> > >> + val = __engine_group_busyness_read(gt, config);
> > >> +
> > >> + spin_lock_irqsave(&pmu->lock, flags);
> > >> +
> > >> + if (device_awake)
> > >> + store_sample(pmu, gt_id, sample_type, val);
> > >> + else
> > >> + val = read_sample(pmu, gt_id, sample_type);
> > >> +
> > >> + spin_unlock_irqrestore(&pmu->lock, flags);
> > >> +
> > >> + return val;
> > >> +}
> > >> +
> > >> +void engine_group_busyness_store(struct xe_gt *gt)
> > >> +{
> > >> + struct xe_pmu *pmu = >->tile->xe->pmu;
> > >> + unsigned int gt_id = gt->info.id;
> > >> + unsigned long flags;
> > >> +
> > >> + spin_lock_irqsave(&pmu->lock, flags);
> > >> +
> > >> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> > >> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> > >> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> > >> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> > >> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> > >> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> > >> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> > >> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
Here why should we store everything, we should store only those events
which are enabled?
Also it would good if the above can be done in a loop somehow. 4 is fine
but if we add events later, a loop will be nice, if possible.
> > >> +
> > >> + spin_unlock_irqrestore(&pmu->lock, flags);
> > >> +}
> > >> +
> > >> +static int
> > >> +config_status(struct xe_device *xe, u64 config)
> > >> +{
> > >> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
> > >> + unsigned int gt_id = config_gt_id(config);
> > >> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> > >> +
> > >> + if (gt_id > max_gt_id)
> > >> + return -ENOENT;
> > >> +
> > >> + switch (config_counter(config)) {
> > >> + case XE_PMU_INTERRUPTS(0):
> > >> + if (gt_id)
> > >> + return -ENOENT;
> > >
> > > OK: this is a global event so we say this is enabled only for gt0.
> > >
> > >> + break;
> > >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> > >> + case XE_PMU_COPY_GROUP_BUSY(0):
> > >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> > >> + if (GRAPHICS_VER(xe) < 12)
> > >
> > > Any point checking? xe only supports Gen12+.
> >
> > hmmm ya good point will remove this.
> > >
> > >> + return -ENOENT;
> > >> + break;
> > >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> > >> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
> > >> + return -ENOENT;
> > >
> > > OK: this makes sense, so we will expose this event only for media gt's.
> > >
> > >> + break;
> > >> + default:
> > >> + return -ENOENT;
> > >> + }
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static int xe_pmu_event_init(struct perf_event *event)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> + int ret;
> > >> +
> > >> + if (pmu->closed)
> > >> + return -ENODEV;
> > >> +
> > >> + if (event->attr.type != event->pmu->type)
> > >> + return -ENOENT;
> > >> +
> > >> + /* unsupported modes and filters */
> > >> + if (event->attr.sample_period) /* no sampling */
> > >> + return -EINVAL;
> > >> +
> > >> + if (has_branch_stack(event))
> > >> + return -EOPNOTSUPP;
> > >> +
> > >> + if (event->cpu < 0)
> > >> + return -EINVAL;
> > >> +
> > >> + /* only allow running on one cpu at a time */
> > >> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
> > >> + return -EINVAL;
> > >> +
> > >> + ret = config_status(xe, event->attr.config);
> > >> + if (ret)
> > >> + return ret;
> > >> +
> > >> + if (!event->parent) {
> > >> + drm_dev_get(&xe->drm);
> > >> + event->destroy = xe_pmu_event_destroy;
> > >> + }
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static u64 __xe_pmu_event_read(struct perf_event *event)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> + const unsigned int gt_id = config_gt_id(event->attr.config);
> > >> + const u64 config = config_counter(event->attr.config);
> > >> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> + u64 val = 0;
> > >> +
> > >> + switch (config) {
> > >> + case XE_PMU_INTERRUPTS(0):
> > >> + val = READ_ONCE(pmu->irq_count);
> > >
> > > OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff would
> > > be to take pmu->lock (both while reading and writing irq_count) but that
> > > would be expensive in the interrupt handler (as the .h hints). So all we
> > > can do is what is done here.
> > >
> > >> + break;
> > >> + case XE_PMU_RENDER_GROUP_BUSY(0):
> > >> + case XE_PMU_COPY_GROUP_BUSY(0):
> > >> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
> > >> + case XE_PMU_MEDIA_GROUP_BUSY(0):
> > >> + val = engine_group_busyness_read(gt, config);
> > >> + }
> > >> +
> > >> + return val;
> > >> +}
> > >> +
> > >> +static void xe_pmu_event_read(struct perf_event *event)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> + struct hw_perf_event *hwc = &event->hw;
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> + u64 prev, new;
> > >> +
> > >> + if (pmu->closed) {
> > >> + event->hw.state = PERF_HES_STOPPED;
> > >> + return;
> > >> + }
> > >> +again:
> > >> + prev = local64_read(&hwc->prev_count);
> > >> + new = __xe_pmu_event_read(event);
> > >> +
> > >> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
> > >> + goto again;
> > >> +
> > >> + local64_add(new - prev, &event->count);
> > >> +}
> > >> +
> > >> +static void xe_pmu_enable(struct perf_event *event)
> > >> +{
> > >> + /*
> > >> + * Store the current counter value so we can report the correct delta
> > >> + * for all listeners. Even when the event was already enabled and has
> > >> + * an existing non-zero value.
> > >> + */
> > >> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
> > >> +}
> > >> +
> > >> +static void xe_pmu_event_start(struct perf_event *event, int flags)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> +
> > >> + if (pmu->closed)
> > >> + return;
> > >> +
> > >> + xe_pmu_enable(event);
> > >> + event->hw.state = 0;
> > >> +}
> > >> +
> > >> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
> > >> +{
> > >> + if (flags & PERF_EF_UPDATE)
> > >> + xe_pmu_event_read(event);
> > >> +
> > >> + event->hw.state = PERF_HES_STOPPED;
> > >> +}
> > >> +
> > >> +static int xe_pmu_event_add(struct perf_event *event, int flags)
> > >> +{
> > >> + struct xe_device *xe =
> > >> + container_of(event->pmu, typeof(*xe), pmu.base);
> > >> + struct xe_pmu *pmu = &xe->pmu;
> > >> +
> > >> + if (pmu->closed)
> > >> + return -ENODEV;
> > >> +
> > >> + if (flags & PERF_EF_START)
> > >> + xe_pmu_event_start(event, flags);
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static void xe_pmu_event_del(struct perf_event *event, int flags)
> > >> +{
> > >> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
> > >> +}
> > >> +
> > >> +static int xe_pmu_event_event_idx(struct perf_event *event)
> > >> +{
> > >> + return 0;
> > >> +}
> > >> +
> > >> +struct xe_str_attribute {
> > >> + struct device_attribute attr;
> > >> + const char *str;
> > >> +};
> > >> +
> > >> +static ssize_t xe_pmu_format_show(struct device *dev,
> > >> + struct device_attribute *attr, char *buf)
> > >> +{
> > >> + struct xe_str_attribute *eattr;
> > >> +
> > >> + eattr = container_of(attr, struct xe_str_attribute, attr);
> > >> + return sprintf(buf, "%s\n", eattr->str);
> > >> +}
> > >> +
> > >> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
> > >> + (&((struct xe_str_attribute[]) { \
> > >> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
> > >> + .str = _config, } \
> > >> + })[0].attr.attr)
> > >> +
> > >> +static struct attribute *xe_pmu_format_attrs[] = {
> > >> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
> > >
> > > 0-20 means 0-20 bits? Though here we probably have different number of
> > > config bits? Probably doesn't matter?
> >
> > as i understand this is not used anymore so will remove it.
> >
> > >
> > > The string will show up with:
> > >
> > > cat /sys/devices/xe/format/xe_eventid
> > >
> > >> + NULL,
> > >> +};
> > >> +
> > >> +static const struct attribute_group xe_pmu_format_attr_group = {
> > >> + .name = "format",
> > >> + .attrs = xe_pmu_format_attrs,
> > >> +};
> > >> +
> > >> +struct xe_ext_attribute {
> > >> + struct device_attribute attr;
> > >> + unsigned long val;
> > >> +};
> > >> +
> > >> +static ssize_t xe_pmu_event_show(struct device *dev,
> > >> + struct device_attribute *attr, char *buf)
> > >> +{
> > >> + struct xe_ext_attribute *eattr;
> > >> +
> > >> + eattr = container_of(attr, struct xe_ext_attribute, attr);
> > >> + return sprintf(buf, "config=0x%lx\n", eattr->val);
> > >> +}
> > >> +
> > >> +static ssize_t cpumask_show(struct device *dev,
> > >> + struct device_attribute *attr, char *buf)
> > >> +{
> > >> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
> > >> +}
> > >> +
> > >> +static DEVICE_ATTR_RO(cpumask);
> > >> +
> > >> +static struct attribute *xe_cpumask_attrs[] = {
> > >> + &dev_attr_cpumask.attr,
> > >> + NULL,
> > >> +};
> > >> +
> > >> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
> > >> + .attrs = xe_cpumask_attrs,
> > >> +};
> > >> +
> > >> +#define __event(__counter, __name, __unit) \
> > >> +{ \
> > >> + .counter = (__counter), \
> > >> + .name = (__name), \
> > >> + .unit = (__unit), \
> > >> + .global = false, \
> > >> +}
> > >> +
> > >> +#define __global_event(__counter, __name, __unit) \
> > >> +{ \
> > >> + .counter = (__counter), \
> > >> + .name = (__name), \
> > >> + .unit = (__unit), \
> > >> + .global = true, \
> > >> +}
> > >> +
> > >> +static struct xe_ext_attribute *
> > >> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
> > >> +{
> > >> + sysfs_attr_init(&attr->attr.attr);
> > >> + attr->attr.attr.name = name;
> > >> + attr->attr.attr.mode = 0444;
> > >> + attr->attr.show = xe_pmu_event_show;
> > >> + attr->val = config;
> > >> +
> > >> + return ++attr;
> > >> +}
> > >> +
> > >> +static struct perf_pmu_events_attr *
> > >> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
> > >> + const char *str)
> > >> +{
> > >> + sysfs_attr_init(&attr->attr.attr);
> > >> + attr->attr.attr.name = name;
> > >> + attr->attr.attr.mode = 0444;
> > >> + attr->attr.show = perf_event_sysfs_show;
> > >> + attr->event_str = str;
> > >> +
> > >> + return ++attr;
> > >> +}
> > >> +
> > >> +static struct attribute **
> > >> +create_event_attributes(struct xe_pmu *pmu)
> > >> +{
> > >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> > >> + static const struct {
> > >> + unsigned int counter;
> > >> + const char *name;
> > >> + const char *unit;
> > >> + bool global;
> > >> + } events[] = {
> > >> + __global_event(0, "interrupts", NULL),
> > >> + __event(1, "render-group-busy", "ns"),
> > >> + __event(2, "copy-group-busy", "ns"),
> > >> + __event(3, "media-group-busy", "ns"),
> > >> + __event(4, "any-engine-group-busy", "ns"),
> > >> + };
> > >
> > > OK: this function is some black magic to expose stuff through
> > > PMU. Identical to i915 and seems to be working from the commit message so
> > > should be fine.
> > >
> > >> +
> > >> + unsigned int count = 0;
> > >> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
> > >> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
> > >> + struct attribute **attr = NULL, **attr_iter;
> > >> + struct xe_gt *gt;
> > >> + unsigned int i, j;
> > >> +
> > >> + /* Count how many counters we will be exposing. */
> > >> + for_each_gt(gt, xe, j) {
> > >> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> > >> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> > >> +
> > >> + if (!config_status(xe, config))
> > >> + count++;
> > >> + }
> > >> + }
> > >> +
> > >> + /* Allocate attribute objects and table. */
> > >> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
> > >> + if (!xe_attr)
> > >> + goto err_alloc;
> > >> +
> > >> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
> > >> + if (!pmu_attr)
> > >> + goto err_alloc;
> > >> +
> > >> + /* Max one pointer of each attribute type plus a termination entry. */
> > >> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
> > >> + if (!attr)
> > >> + goto err_alloc;
> > >> +
> > >> + xe_iter = xe_attr;
> > >> + pmu_iter = pmu_attr;
> > >> + attr_iter = attr;
> > >> +
> > >> + for_each_gt(gt, xe, j) {
> > >> + for (i = 0; i < ARRAY_SIZE(events); i++) {
> > >> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
> > >> + char *str;
> > >> +
> > >> + if (config_status(xe, config))
> > >> + continue;
> > >> +
> > >> + if (events[i].global)
> > >> + str = kstrdup(events[i].name, GFP_KERNEL);
> > >> + else
> > >> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
> > >> + events[i].name, j);
> > >> + if (!str)
> > >> + goto err;
> > >> +
> > >> + *attr_iter++ = &xe_iter->attr.attr;
> > >> + xe_iter = add_xe_attr(xe_iter, str, config);
> > >> +
> > >> + if (events[i].unit) {
> > >> + if (events[i].global)
> > >> + str = kasprintf(GFP_KERNEL, "%s.unit",
> > >> + events[i].name);
> > >> + else
> > >> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
> > >> + events[i].name, j);
> > >> + if (!str)
> > >> + goto err;
> > >> +
> > >> + *attr_iter++ = &pmu_iter->attr.attr;
> > >> + pmu_iter = add_pmu_attr(pmu_iter, str,
> > >> + events[i].unit);
> > >> + }
> > >> + }
> > >> + }
> > >> +
> > >> + pmu->xe_attr = xe_attr;
> > >> + pmu->pmu_attr = pmu_attr;
> > >> +
> > >> + return attr;
> > >> +
> > >> +err:
> > >> + for (attr_iter = attr; *attr_iter; attr_iter++)
> > >> + kfree((*attr_iter)->name);
> > >> +
> > >> +err_alloc:
> > >> + kfree(attr);
> > >> + kfree(xe_attr);
> > >> + kfree(pmu_attr);
> > >> +
> > >> + return NULL;
> > >> +}
> > >> +
> > >> +static void free_event_attributes(struct xe_pmu *pmu)
> > >> +{
> > >> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
> > >> +
> > >> + for (; *attr_iter; attr_iter++)
> > >> + kfree((*attr_iter)->name);
> > >> +
> > >> + kfree(pmu->events_attr_group.attrs);
> > >> + kfree(pmu->xe_attr);
> > >> + kfree(pmu->pmu_attr);
> > >> +
> > >> + pmu->events_attr_group.attrs = NULL;
> > >> + pmu->xe_attr = NULL;
> > >> + pmu->pmu_attr = NULL;
> > >> +}
> > >> +
> > >> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
> > >> +{
> > >> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> > >> +
> > >> + XE_BUG_ON(!pmu->base.event_init);
> > >> +
> > >> + /* Select the first online CPU as a designated reader. */
> > >> + if (cpumask_empty(&xe_pmu_cpumask))
> > >> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
> > >> +{
> > >> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
> > >> + unsigned int target = xe_pmu_target_cpu;
> > >> +
> > >> + XE_BUG_ON(!pmu->base.event_init);
> > >> +
> > >> + /*
> > >> + * Unregistering an instance generates a CPU offline event which we must
> > >> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
> > >> + */
> > >> + if (pmu->closed)
> > >> + return 0;
> > >> +
> > >> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
> > >> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
> > >> +
> > >> + /* Migrate events if there is a valid target */
> > >> + if (target < nr_cpu_ids) {
> > >> + cpumask_set_cpu(target, &xe_pmu_cpumask);
> > >> + xe_pmu_target_cpu = target;
> > >> + }
> > >> + }
> > >> +
> > >> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
> > >> + perf_pmu_migrate_context(&pmu->base, cpu, target);
> > >> + pmu->cpuhp.cpu = target;
> > >> + }
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
> > >> +
> > >> +int xe_pmu_init(void)
> > >> +{
> > >> + int ret;
> > >> +
> > >> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> > >> + "perf/x86/intel/xe:online",
> > >> + xe_pmu_cpu_online,
> > >> + xe_pmu_cpu_offline);
> > >> + if (ret < 0)
> > >> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
> > >> + ret);
> > >> + else
> > >> + cpuhp_slot = ret;
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +void xe_pmu_exit(void)
> > >> +{
> > >> + if (cpuhp_slot != CPUHP_INVALID)
> > >> + cpuhp_remove_multi_state(cpuhp_slot);
> > >> +}
> > >> +
> > >> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
> > >> +{
> > >> + if (cpuhp_slot == CPUHP_INVALID)
> > >> + return -EINVAL;
> > >> +
> > >> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
> > >> +}
> > >> +
> > >> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
> > >> +{
> > >> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
> > >> +}
> > >> +
> > >> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
> > >> +{
> > >> + struct xe_pmu *pmu = arg;
> > >> +
> > >> + if (!pmu->base.event_init)
> > >> + return;
> > >> +
> > >> + /*
> > >> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
> > >> + * ensures all currently executing ones will have exited before we
> > >> + * proceed with unregistration.
> > >> + */
> > >> + pmu->closed = true;
> > >> + synchronize_rcu();
> > >> +
> > >> + xe_pmu_unregister_cpuhp_state(pmu);
> > >> +
> > >> + perf_pmu_unregister(&pmu->base);
> > >> + pmu->base.event_init = NULL;
> > >> + kfree(pmu->base.attr_groups);
> > >> + kfree(pmu->name);
> > >> + free_event_attributes(pmu);
> > >> +}
> > >> +
> > >> +static void init_samples(struct xe_pmu *pmu)
> > >> +{
> > >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> > >> + struct xe_gt *gt;
> > >> + unsigned int i;
> > >> +
> > >> + for_each_gt(gt, xe, i)
> > >> + engine_group_busyness_store(gt);
> > >> +}
> > >> +
> > >> +void xe_pmu_register(struct xe_pmu *pmu)
> > >
> > > Why void, why not int? PMU failure is non fatal error?
> >
> > Ya device is functional , it is only that these counters are not
> > available. Hence didn't want to fail the driver load.
> > >
> > >> +{
> > >> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
> > >> + const struct attribute_group *attr_groups[] = {
> > >> + &xe_pmu_format_attr_group,
> > >> + &pmu->events_attr_group,
> > >> + &xe_pmu_cpumask_attr_group,
> > >
> > > Can someone please explain what this cpumask/cpuhotplug stuff does and
> > > whether it needs to be in this patch? There's something here:
> >
> > comments from original patch series in
> > i915:https://patchwork.kernel.org/project/intel-gfx/patch/20170802123249.14194-5-tvrtko.ursulin@linux.intel.com/
> >
> > "IIRC an uncore PMU should expose a cpumask through sysfs, and then perf
> > tools will read that mask and auto-magically limit the number of CPUs it
> > instantiates the counter on."
> >
> > and ours are global counters not per cpu so we limit to just to single cpu.
> >
> > And as i understand we use the cpuhotplug support to migrate too new cpu
> > incase the earlier one goes offline.
>
> OK, leave as is.
>
> >
> > >
> > > b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
> > >
> > > I'd rather just have the basic PMU infra and the events in this patch and
> > > punt this cpumask/cpuhotplug stuff to a later patch, unless someone can say
> > > what it does.
> > >
> > > Though perf_pmu_register seems to be doing some per cpu stuff so likely
> > > this is needed. But amdgpu_pmu only has event and format attributes.
> > >
> > > Mostly leave as is I guess.
> > >
> > >> + NULL
> > >> + };
> > >> +
> > >> + int ret = -ENOMEM;
> > >> +
> > >> + spin_lock_init(&pmu->lock);
> > >> + pmu->cpuhp.cpu = -1;
> > >> + init_samples(pmu);
> > >
> > > Why init_samples here? Can't we init the particular sample in
> > > xe_pmu_event_init or even xe_pmu_event_start?
> > >
> > > Init'ing here may be too soon since the event might not be enabled for a
> > > long time. So really this needs to move to xe_pmu_event_init or
> > > xe_pmu_event_start.
> >
> > The device is put to suspend immediately after driver probe, typically
> > pmu is opened even before any workload is run so essentially device is
> > still in suspend state hence we cannot access registers so storing the
> > last known value in init_samples. otherwise we see the bug in v#1 of series.
> >
> > >
> > > Actually this is already happening in xe_pmu_enable. We just need to decide
> > > when we want to wake the device up and when we don't. So maybe wake the
> > > device up at start (use xe_device_mem_access_get) and not wake up during
> > > read (xe_device_mem_access_get_if_ongoing etc.)?
>
> Just going to repeat this again:
>
> xe_pmu_event_start calls xe_pmu_enable. In xe_pmu_enable use
> xe_device_mem_access_get before calling __xe_pmu_event_read. This will wake
> the device up and get a valid value in event->hw.prev_count.
>
> In xe_pmu_event_read, use xe_device_mem_access_get_if_ongoing, to read the
> event without waking the device up (and return previous value etc.).
>
> Or, pass a flag in to __xe_pmu_event_read and to engine_group_busyness_read
> and __engine_group_busyness_read. The flag will say whether or not to wake
> up the device. If the flag says wake the device up, call
> xe_device_mem_access_get and xe_force_wake_get, maybe in
> __engine_group_busyness_read, before reading device registers. If the flag
> says don't wake up the device call xe_device_mem_access_get_if_ongoing.
>
> This way we:
> * don't need to call init_samples in xe_pmu_register
> * we don't need engine_group_busyness_store
> * we don't need to specifically call engine_group_busyness_store in xe_gt_suspend
>
> The correct sample is read by waking up the device in xe_pmu_event_start.
>
> Hopefully this is clear now.
Actually I think it is not necessary to do anything in xe_pmu_event_start,
as long as we keep the engine_group_busyness_store in xe_gt_suspend (so we
can just use xe_device_mem_access_get_if_ongoing, don't need
xe_device_mem_access_get as you said).
Afais, the problem of huge values in v1 was due to reading the device
registers when device was not awake. That problem we've already solved in
v2 where in engine_group_busyness_read() we only read if the device is
awake and skip and return the previous value when the device is not
awake. So that fixes the problem of huge values.
The problem in this patch (I thought) is that we are effectively sampling
the registers each time perf calls xe_pmu_event_read, say every 1 sec. So
we are sampling the registers every 1 sec. When we sample (every 1 sec) if
the device is awake we will return the correct ns value, if device is
asleep we will return the old value. If the device wakes up and does some
work in the 1 sec period but then again suspends will miss that
activity. That is the problem that is being solved by storing the samples
in xe_gt_suspend().
i915 solved this problem using a 5 ms timer but I like the solution of
sampling in xe_gt_suspend better, so let's keep it.
But init_samples is not needed, afais we don't need to do anything in
xe_pmu_register or in xe_pmu_event_start (and we don't need to use
xe_device_mem_access_get). xe_gt_suspend will take care of storing the
register values before the device suspends.
Hopefully it makes sense now, sorry for the confusion.
Ashutosh
>
> >
> > >
> > >> +
> > >> + pmu->name = kasprintf(GFP_KERNEL,
> > >> + "xe_%s",
> > >> + dev_name(xe->drm.dev));
> > >> + if (pmu->name)
> > >> + /* tools/perf reserves colons as special. */
> > >> + strreplace((char *)pmu->name, ':', '_');
> > >> +
> > >> + if (!pmu->name)
> > >> + goto err;
> > >> +
> > >> + pmu->events_attr_group.name = "events";
> > >> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
> > >> + if (!pmu->events_attr_group.attrs)
> > >> + goto err_name;
> > >> +
> > >> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
> > >> + GFP_KERNEL);
> > >> + if (!pmu->base.attr_groups)
> > >> + goto err_attr;
> > >> +
> > >> + pmu->base.module = THIS_MODULE;
> > >> + pmu->base.task_ctx_nr = perf_invalid_context;
> > >> + pmu->base.event_init = xe_pmu_event_init;
> > >> + pmu->base.add = xe_pmu_event_add;
> > >> + pmu->base.del = xe_pmu_event_del;
> > >> + pmu->base.start = xe_pmu_event_start;
> > >> + pmu->base.stop = xe_pmu_event_stop;
> > >> + pmu->base.read = xe_pmu_event_read;
> > >> + pmu->base.event_idx = xe_pmu_event_event_idx;
> > >> +
> > >> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
> > >> + if (ret)
> > >> + goto err_groups;
> > >> +
> > >> + ret = xe_pmu_register_cpuhp_state(pmu);
> > >> + if (ret)
> > >> + goto err_unreg;
> > >> +
> > >> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
> > >> + XE_WARN_ON(ret);
> > >
> > > We should just follow the regular error rewind here too and let
> > > drm_notice() at the end print the error. This is what other drivers calling
> > > drmm_add_action_or_reset seem to be doing.
> >
> > Ok ok.
> > >
> > >> +
> > >> + return;
> > >> +
> > >> +err_unreg:
> > >> + perf_pmu_unregister(&pmu->base);
> > >> +err_groups:
> > >> + kfree(pmu->base.attr_groups);
> > >> +err_attr:
> > >> + pmu->base.event_init = NULL;
> > >> + free_event_attributes(pmu);
> > >> +err_name:
> > >> + kfree(pmu->name);
> > >> +err:
> > >> + drm_notice(&xe->drm, "Failed to register PMU!\n");
> > >> +}
> > >> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
> > >> new file mode 100644
> > >> index 000000000000..d3f47f4ab343
> > >> --- /dev/null
> > >> +++ b/drivers/gpu/drm/xe/xe_pmu.h
> > >> @@ -0,0 +1,25 @@
> > >> +/* SPDX-License-Identifier: MIT */
> > >> +/*
> > >> + * Copyright © 2023 Intel Corporation
> > >> + */
> > >> +
> > >> +#ifndef _XE_PMU_H_
> > >> +#define _XE_PMU_H_
> > >> +
> > >> +#include "xe_gt_types.h"
> > >> +#include "xe_pmu_types.h"
> > >> +
> > >> +#ifdef CONFIG_PERF_EVENTS
> > >
> > > nit but maybe this should be:
> > >
> > > #if IS_ENABLED(CONFIG_PERF_EVENTS)
> > >
> > > or,
> > >
> > > #if IS_BUILTIN(CONFIG_PERF_EVENTS)
> > >
> > > Note CONFIG_PERF_EVENTS is a boolean kconfig option.
> > >
> > > See similar macro IS_REACHABLE() in i915_hwmon.h.
> > >
> > >> +int xe_pmu_init(void);
> > >> +void xe_pmu_exit(void);
> > >> +void xe_pmu_register(struct xe_pmu *pmu);
> > >> +void engine_group_busyness_store(struct xe_gt *gt);
> > >
> > > Add xe_pmu_ prefix if function is needed (hopefully not).
> >
> > OK
> > >
> > >> +#else
> > >> +static inline int xe_pmu_init(void) { return 0; }
> > >> +static inline void xe_pmu_exit(void) {}
> > >> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
> > >> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
> > >> +#endif
> > >> +
> > >> +#endif
> > >> +
> > >> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
> > >> new file mode 100644
> > >> index 000000000000..e87edd4d6a87
> > >> --- /dev/null
> > >> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
> > >> @@ -0,0 +1,80 @@
> > >> +/* SPDX-License-Identifier: MIT */
> > >> +/*
> > >> + * Copyright © 2023 Intel Corporation
> > >> + */
> > >> +
> > >> +#ifndef _XE_PMU_TYPES_H_
> > >> +#define _XE_PMU_TYPES_H_
> > >> +
> > >> +#include <linux/perf_event.h>
> > >> +#include <linux/spinlock_types.h>
> > >> +#include <uapi/drm/xe_drm.h>
> > >> +
> > >> +enum {
> > >> + __XE_SAMPLE_RENDER_GROUP_BUSY,
> > >> + __XE_SAMPLE_COPY_GROUP_BUSY,
> > >> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
> > >> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> > >> + __XE_NUM_PMU_SAMPLERS
> > >
> > > OK: irq_count is missing here since these are read from device...
> > >
> > >> +};
> > >> +
> > >> +struct xe_pmu_sample {
> > >> + u64 cur;
> > >> +};
> > >
> > > This was also discussed for i915 PMU, no point having a struct with a
> > > single u64 member. Might as well just use u64 wherever we are using
> > > struct xe_pmu_sample.
> >
> > OK.
> > >
> > >> +
> > >> +#define XE_MAX_GT_PER_TILE 2
> > >
> > > Why per tile? The array size should be max_gt_per_device. Just call it
> > > XE_MAX_GT?
> >
> > I declared similar to what we have in drivers/gpu/drm/xe/xe_device.h
>
> Our 2-d array size is for the device, not per tile. So let's use XE_MAX_GT.
>
> > >
> > >> +
> > >> +struct xe_pmu {
> > >> + /**
> > >> + * @cpuhp: Struct used for CPU hotplug handling.
> > >> + */
> > >> + struct {
> > >> + struct hlist_node node;
> > >> + unsigned int cpu;
> > >> + } cpuhp;
> > >> + /**
> > >> + * @base: PMU base.
> > >> + */
> > >> + struct pmu base;
> > >> + /**
> > >> + * @closed: xe is unregistering.
> > >> + */
> > >> + bool closed;
> > >> + /**
> > >> + * @name: Name as registered with perf core.
> > >> + */
> > >> + const char *name;
> > >> + /**
> > >> + * @lock: Lock protecting enable mask and ref count handling.
> > >> + */
> > >> + spinlock_t lock;
> > >> + /**
> > >> + * @sample: Current and previous (raw) counters.
> > >> + *
> > >> + * These counters are updated when the device is awake.
> > >> + *
> > >> + */
> > >> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
> > >
> > > Change to 2-d array. See above.
> > >
> > >> + /**
> > >> + * @irq_count: Number of interrupts
> > >> + *
> > >> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
> > >> + * 4e9 interrupts are a lot and postprocessing can really deal with an
> > >> + * occasional wraparound easily. It's 32bit after all.
> > >> + */
> > >> + unsigned long irq_count;
> > >> + /**
> > >> + * @events_attr_group: Device events attribute group.
> > >> + */
> > >> + struct attribute_group events_attr_group;
> > >> + /**
> > >> + * @xe_attr: Memory block holding device attributes.
> > >> + */
> > >> + void *xe_attr;
> > >> + /**
> > >> + * @pmu_attr: Memory block holding device attributes.
> > >> + */
> > >> + void *pmu_attr;
> > >> +};
> > >> +
> > >> +#endif
> > >> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > >> index 965cd9527ff1..ed097056f944 100644
> > >> --- a/include/uapi/drm/xe_drm.h
> > >> +++ b/include/uapi/drm/xe_drm.h
> > >> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
> > >> __u64 reserved[2];
> > >> };
> > >>
> > >> +/* PMU event config IDs */
> > >> +
> > >> +/*
> > >> + * Top 4 bits of every counter are GT id.
> > >> + */
> > >> +#define __XE_PMU_GT_SHIFT (60)
> > >
> > > To future-proof this, and also because we seem to have plenty of bits
> > > available, I think we should change this to 56 (instead of 60).
> >
> > OK
> >
> > Thanks,
> > Aravind.
> > >
> > >> +
> > >> +#define ___XE_PMU_OTHER(gt, x) \
> > >> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
> > >> +
> > >> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
> > >> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
> > >> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
> > >> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
> > >> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
> > >> +
> > >> #if defined(__cplusplus)
> > >> }
> > >> #endif
> > >> --
> > >> 2.25.1
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-22 6:04 ` Dixit, Ashutosh
@ 2023-07-24 8:03 ` Iddamsetty, Aravind
2023-07-24 9:00 ` Ursulin, Tvrtko
2023-07-24 15:52 ` Dixit, Ashutosh
2023-07-24 9:38 ` Iddamsetty, Aravind
1 sibling, 2 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-24 8:03 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 22-07-2023 11:34, Dixit, Ashutosh wrote:
Hi Ashutosh,
> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>
>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>
>> Hi Aravind,
>>
>>> On 21-07-2023 06:32, Dixit, Ashutosh wrote:
>>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>>>>
>>>> More stuff to mull over. You can ignore comments starting with "OK", those
>>>> are just notes to myself.
>>>>
>>>> Also, maybe some time we can add a basic IGT which reads these exposed
>>>> counters and verifies that we can read them and they are monotonically
>>>> increasing?
>>>
>>> this is the IGT https://patchwork.freedesktop.org/series/119936/ series
>>> using these counters posted by Venkat.
>>>
>>>>
>>>>> There are a set of engine group busyness counters provided by HW which are
>>>>> perfect fit to be exposed via PMU perf events.
>>>>>
>>>>> BSPEC: 46559, 46560, 46722, 46729
>>>>
>>>> Also add these Bspec entries: 71028, 52071
>>>
>>> OK.
>>>
>>>>
>>>>>
>>>>> events can be listed using:
>>>>> perf list
>>>>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>>>>
>>>>> and can be read using:
>>>>>
>>>>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>>>>> time counts unit events
>>>>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>>
>>>>> The pmu base implementation is taken from i915.
>>>>>
>>>>> v2:
>>>>> Store last known value when device is awake return that while the GT is
>>>>> suspended and then update the driver copy when read during awake.
>>>>>
>>>>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/xe/Makefile | 2 +
>>>>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>>>>> drivers/gpu/drm/xe/xe_device.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>>>>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>>>>> drivers/gpu/drm/xe/xe_module.c | 5 +
>>>>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>>>>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>>>>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>>>>> include/uapi/drm/xe_drm.h | 16 +
>>>>> 11 files changed, 902 insertions(+)
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>>>> index 081c57fd8632..e52ab795c566 100644
>>>>> --- a/drivers/gpu/drm/xe/Makefile
>>>>> +++ b/drivers/gpu/drm/xe/Makefile
>>>>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>>>> i915-display/skl_universal_plane.o \
>>>>> i915-display/skl_watermark.o
>>>>>
>>>>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>>>>> +
>>>>> ifeq ($(CONFIG_ACPI),y)
>>>>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>>>> i915-display/intel_acpi.o \
>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> index 3f664011eaea..c7d9e4634745 100644
>>>>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> @@ -285,6 +285,11 @@
>>>>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>>>>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>>>>
>>>>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
>>>>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>>>>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>>>>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>>>>> +
>>>>> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
>>>>> #define ENABLE_SMALLPL REG_BIT(15)
>>>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>>>>> index c7985af85a53..b2c7bd4a97d9 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_device.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_device.c
>>>>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>>>>
>>>>> xe_debugfs_register(xe);
>>>>>
>>>>> + xe_pmu_register(&xe->pmu);
>>>>> +
>>>>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>>>>> if (err)
>>>>> return err;
>>>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>>>>> index 0226d44a6af2..3ba99aae92b9 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>>>> @@ -15,6 +15,7 @@
>>>>> #include "xe_devcoredump_types.h"
>>>>> #include "xe_gt_types.h"
>>>>> #include "xe_platform_types.h"
>>>>> +#include "xe_pmu.h"
>>>>> #include "xe_step_types.h"
>>>>>
>>>>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>>>>> @@ -332,6 +333,9 @@ struct xe_device {
>>>>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>>>>> bool d3cold_allowed;
>>>>>
>>>>> + /* @pmu: performance monitoring unit */
>>>>> + struct xe_pmu pmu;
>>>>> +
>>>>
>>>> Now I am wondering why we don't make the PMU per-gt (or per-tile)? Per-gt
>>>> would work for these busyness registers and I am not sure how the
>>>> interrupts are hooked up.
>>>>
>>>> In i915 the PMU being device level helped in having a single timer (rather
>>>> than a per gt timer).
>>>>
>>>> Anyway probably not much practical benefit by make it per-gt/per-tile, so
>>>> maybe leave as is. Just thinking out loud.
>>>
>>> we are able to expose per-gt counters so do not see any benefit in
>>> making pmu per-gt, also i believe struct pmu is per device it will have
>>> a type associated which is unique for a device.
>>
>> PMU can be made per gt and named xe-gt0, xe-gt1 etc. if we want. But anyway
>> leave as is.
>>
>>>
>>>>
>>>>> /* private: */
>>>>>
>>>>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>>>> index 2458397ce8af..96e3720923d4 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_gt.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>>>>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>>>>> if (err)
>>>>> goto err_msg;
>>>>>
>>>>> + engine_group_busyness_store(gt);
>>>>
>>>> Not sure I follow the reason for doing this at suspend time? If PMU was
>>>> active there should be a previous value. Why must we take a new sample
>>>> explicitly here?
>>>
>>> the PMU interface can be read even when device is suspend and in such
>>> cases we should not wake up the device, and if we try to read the
>>> register when device is suspended it gives spurious counter you can
>>> check in version#1 of this series we were getting huge values. as we put
>>> the device to suspend immediately after probe. So storing the last known
>>> good value before suspend.
>>
>> No need, see comment at init_samples below.
>
> Sorry, you are right, I changed my mind about this, I see your point. See
> more discussion on this at init_samples below.
>
>>
>>>
>>>>
>>>> To me looks like engine_group_busyness_store should not be needed, see
>>>> comment below for init_samples too.
>>>>
>>>>> +
>>>>> err = xe_uc_suspend(>->uc);
>>>>> if (err)
>>>>> goto err_force_wake;
>>>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>>>> index b4ed1e4a3388..cb943fb94ec7 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>>>> @@ -27,6 +27,24 @@
>>>>> #define IIR(offset) XE_REG(offset + 0x8)
>>>>> #define IER(offset) XE_REG(offset + 0xc)
>>>>>
>>>>> +/*
>>>>> + * Interrupt statistic for PMU. Increments the counter only if the
>>>>> + * interrupt originated from the GPU so interrupts from a device which
>>>>> + * shares the interrupt line are not accounted.
>>>>> + */
>>>>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>>>>
>>>> No inline, compiler will do it, but looks like we may want to always_inline
>>>> this. Also this function should really be in xe_pmu.h? Anyway probably
>>>> leave as is.
>>>>
>>>>> + irqreturn_t res)
>>>>> +{
>>>>> + if (unlikely(res != IRQ_HANDLED))
>>>>> + return;
>>>>> +
>>>>> + /*
>>>>> + * A clever compiler translates that into INC. A not so clever one
>>>>> + * should at least prevent store tearing.
>>>>> + */
>>>>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1);
>>>>> +}
>>>>> +
>>>>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
>>>>> {
>>>>> u32 val = xe_mmio_read32(mmio, reg);
>>>>> @@ -325,6 +343,8 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>>>>>
>>>>> xe_display_irq_enable(xe, gu_misc_iir);
>>>>>
>>>>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>>>>> +
>>>>> return IRQ_HANDLED;
>>>>> }
>>>>>
>>>>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>>>>> dg1_intr_enable(xe, false);
>>>>> xe_display_irq_enable(xe, gu_misc_iir);
>>>>>
>>>>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>>>>> +
>>>>> return IRQ_HANDLED;
>>>>> }
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>>>>> index 75e5be939f53..f6fe89748525 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_module.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_module.c
>>>>> @@ -12,6 +12,7 @@
>>>>> #include "xe_hw_fence.h"
>>>>> #include "xe_module.h"
>>>>> #include "xe_pci.h"
>>>>> +#include "xe_pmu.h"
>>>>> #include "xe_sched_job.h"
>>>>>
>>>>> bool enable_guc = true;
>>>>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>>>>> .init = xe_sched_job_module_init,
>>>>> .exit = xe_sched_job_module_exit,
>>>>> },
>>>>> + {
>>>>> + .init = xe_pmu_init,
>>>>> + .exit = xe_pmu_exit,
>>>>> + },
>>>>> {
>>>>> .init = xe_register_pci_driver,
>>>>> .exit = xe_unregister_pci_driver,
>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>>>>> new file mode 100644
>>>>> index 000000000000..bef1895be9f7
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>>>>> @@ -0,0 +1,739 @@
>>>>> +/*
>>>>> + * SPDX-License-Identifier: MIT
>>>>> + *
>>>>> + * Copyright © 2023 Intel Corporation
>>>>> + */
>>>>
>>>> This SPDX header is for .h files not .c files. Actually, it is for neither :/
>>>
>>> But i see this in almost all the files in xe.
>>
>> Look closely.
>>
>>>>
>>>>> +
>>>>> +#include <drm/drm_drv.h>
>>>>> +#include <drm/drm_managed.h>
>>>>> +#include <drm/xe_drm.h>
>>>>> +
>>>>> +#include "regs/xe_gt_regs.h"
>>>>> +#include "xe_device.h"
>>>>> +#include "xe_gt_clock.h"
>>>>> +#include "xe_mmio.h"
>>>>> +
>>>>> +static cpumask_t xe_pmu_cpumask;
>>>>> +static unsigned int xe_pmu_target_cpu = -1;
>>>>> +
>>>>> +static unsigned int config_gt_id(const u64 config)
>>>>> +{
>>>>> + return config >> __XE_PMU_GT_SHIFT;
>>>>> +}
>>>>> +
>>>>> +static u64 config_counter(const u64 config)
>>>>> +{
>>>>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT);
>>>>> +}
>>>>> +
>>>>> +static unsigned int
>>>>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>>>>> +{
>>>>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>>>>> +
>>>>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>>>>> +
>>>>> + return idx;
>>>>> +}
>>>>
>>>> The compiler does this for us if we make sample array 2-d.
>>>>
>>>>> +
>>>>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>>>>> +{
>>>>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
>>>>> +}
>>>>> +
>>>>> +static void
>>>>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample, u64 val)
>>>>> +{
>>>>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
>>>>> +}
>>>>
>>>> The three functions above are not needed if we make the sample array
>>>> 2-d. See here:
>>>>
>>>> https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
>>>>
>>>> Only a part of the patch above was merged (see 8ed0753b527dc) to keep the
>>>> patch size small, but since for xe we are starting from scratch we can
>>>> implement the whole approach above (get rid of the read/store helpers
>>>> entirely, direct assignment without the helpers works).
>>>
>>> Ok I'll go over it.
>>>
>>>>
>>>>> +
>>>>> +static int engine_busyness_sample_type(u64 config)
>>>>> +{
>>>>> + int type = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>>>>> + break;
>>>>> + }
>>>>> +
>>>>> + return type;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_destroy(struct perf_event *event)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> +
>>>>> + drm_WARN_ON(&xe->drm, event->parent);
>>>>> +
>>>>> + drm_dev_put(&xe->drm);
>>>>> +}
>>>>> +
>>>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64 config)
>>>>> +{
>>>>> + u64 val = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>>>>> + break;
>>>>> + default:
>>>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>>>>> + }
>>>>
>>>> We need xe_device_mem_access_get, also xe_force_wake_get if applicable,
>>>> somewhere before reading these registers.
>>>>
>>>>> +
>>>>> + return xe_gt_clock_interval_to_ns(gt, val * 16);
>>>>> +}
>>>>> +
>>>>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64 config)
>>>>> +{
>>>>> + int sample_type = engine_busyness_sample_type(config);
>>>>> + struct xe_device *xe = gt->tile->xe;
>>>>> + const unsigned int gt_id = gt->info.id;
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + bool device_awake;
>>>>> + unsigned long flags;
>>>>> + u64 val;
>>>>> +
>>>>> + /*
>>>>> + * found no better way to check if device is awake or not. Before
>>>>
>>>> xe_device_mem_access_get_if_ongoing (hard to find name).
>>>
>>> thanks for sharing looks to be added recently. If we use this we needn't
>>> use xe_device_mem_access_get.
>>
>> See comment at init_samples.
>>
>>>
>>>>
>>>>> + * we suspend we set the submission_state.enabled to false.
>>>>> + */
>>>>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>>>>> + if (device_awake)
>>>>> + val = __engine_group_busyness_read(gt, config);
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + if (device_awake)
>>>>> + store_sample(pmu, gt_id, sample_type, val);
>>>>> + else
>>>>> + val = read_sample(pmu, gt_id, sample_type);
>>>>> +
>>>>> + spin_unlock_irqrestore(&pmu->lock, flags);
>>>>> +
>>>>> + return val;
>>>>> +}
>>>>> +
>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>> +{
>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>> + unsigned int gt_id = gt->info.id;
>>>>> + unsigned long flags;
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>
> Here why should we store everything, we should store only those events
> which are enabled?
The events are enabled only when they are opened which can happen after
the device is suspended hence we need to store all. As in the present
case device is put to suspend immediately after probe and event is
opened post driver load is done.
>
> Also it would good if the above can be done in a loop somehow. 4 is fine
> but if we add events later, a loop will be nice, if possible.
I do not think loop would solve the furture events as there can be
selective i.e only few needs to be stored. pure counters like interrupts
need not be stored.
>
>>>>> +
>>>>> + spin_unlock_irqrestore(&pmu->lock, flags);
>>>>> +}
>>>>> +
>>>>> +static int
>>>>> +config_status(struct xe_device *xe, u64 config)
>>>>> +{
>>>>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>>>>> + unsigned int gt_id = config_gt_id(config);
>>>>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>>>>> +
>>>>> + if (gt_id > max_gt_id)
>>>>> + return -ENOENT;
>>>>> +
>>>>> + switch (config_counter(config)) {
>>>>> + case XE_PMU_INTERRUPTS(0):
>>>>> + if (gt_id)
>>>>> + return -ENOENT;
>>>>
>>>> OK: this is a global event so we say this is enabled only for gt0.
>>>>
>>>>> + break;
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + if (GRAPHICS_VER(xe) < 12)
>>>>
>>>> Any point checking? xe only supports Gen12+.
>>>
>>> hmmm ya good point will remove this.
>>>>
>>>>> + return -ENOENT;
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
>>>>> + return -ENOENT;
>>>>
>>>> OK: this makes sense, so we will expose this event only for media gt's.
>>>>
>>>>> + break;
>>>>> + default:
>>>>> + return -ENOENT;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_event_init(struct perf_event *event)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + int ret;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return -ENODEV;
>>>>> +
>>>>> + if (event->attr.type != event->pmu->type)
>>>>> + return -ENOENT;
>>>>> +
>>>>> + /* unsupported modes and filters */
>>>>> + if (event->attr.sample_period) /* no sampling */
>>>>> + return -EINVAL;
>>>>> +
>>>>> + if (has_branch_stack(event))
>>>>> + return -EOPNOTSUPP;
>>>>> +
>>>>> + if (event->cpu < 0)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + /* only allow running on one cpu at a time */
>>>>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>>>>> + return -EINVAL;
>>>>> +
>>>>> + ret = config_status(xe, event->attr.config);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (!event->parent) {
>>>>> + drm_dev_get(&xe->drm);
>>>>> + event->destroy = xe_pmu_event_destroy;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static u64 __xe_pmu_event_read(struct perf_event *event)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>>>>> + const u64 config = config_counter(event->attr.config);
>>>>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + u64 val = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_INTERRUPTS(0):
>>>>> + val = READ_ONCE(pmu->irq_count);
>>>>
>>>> OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff would
>>>> be to take pmu->lock (both while reading and writing irq_count) but that
>>>> would be expensive in the interrupt handler (as the .h hints). So all we
>>>> can do is what is done here.
>>>>
>>>>> + break;
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + val = engine_group_busyness_read(gt, config);
>>>>> + }
>>>>> +
>>>>> + return val;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_read(struct perf_event *event)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct hw_perf_event *hwc = &event->hw;
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + u64 prev, new;
>>>>> +
>>>>> + if (pmu->closed) {
>>>>> + event->hw.state = PERF_HES_STOPPED;
>>>>> + return;
>>>>> + }
>>>>> +again:
>>>>> + prev = local64_read(&hwc->prev_count);
>>>>> + new = __xe_pmu_event_read(event);
>>>>> +
>>>>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>>>>> + goto again;
>>>>> +
>>>>> + local64_add(new - prev, &event->count);
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_enable(struct perf_event *event)
>>>>> +{
>>>>> + /*
>>>>> + * Store the current counter value so we can report the correct delta
>>>>> + * for all listeners. Even when the event was already enabled and has
>>>>> + * an existing non-zero value.
>>>>> + */
>>>>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_start(struct perf_event *event, int flags)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return;
>>>>> +
>>>>> + xe_pmu_enable(event);
>>>>> + event->hw.state = 0;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_stop(struct perf_event *event, int flags)
>>>>> +{
>>>>> + if (flags & PERF_EF_UPDATE)
>>>>> + xe_pmu_event_read(event);
>>>>> +
>>>>> + event->hw.state = PERF_HES_STOPPED;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_event_add(struct perf_event *event, int flags)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return -ENODEV;
>>>>> +
>>>>> + if (flags & PERF_EF_START)
>>>>> + xe_pmu_event_start(event, flags);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_del(struct perf_event *event, int flags)
>>>>> +{
>>>>> + xe_pmu_event_stop(event, PERF_EF_UPDATE);
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_event_event_idx(struct perf_event *event)
>>>>> +{
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +struct xe_str_attribute {
>>>>> + struct device_attribute attr;
>>>>> + const char *str;
>>>>> +};
>>>>> +
>>>>> +static ssize_t xe_pmu_format_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf)
>>>>> +{
>>>>> + struct xe_str_attribute *eattr;
>>>>> +
>>>>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>>>>> + return sprintf(buf, "%s\n", eattr->str);
>>>>> +}
>>>>> +
>>>>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>>>>> + (&((struct xe_str_attribute[]) { \
>>>>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
>>>>> + .str = _config, } \
>>>>> + })[0].attr.attr)
>>>>> +
>>>>> +static struct attribute *xe_pmu_format_attrs[] = {
>>>>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>>>>
>>>> 0-20 means 0-20 bits? Though here we probably have different number of
>>>> config bits? Probably doesn't matter?
>>>
>>> as i understand this is not used anymore so will remove it.
>>>
>>>>
>>>> The string will show up with:
>>>>
>>>> cat /sys/devices/xe/format/xe_eventid
>>>>
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group xe_pmu_format_attr_group = {
>>>>> + .name = "format",
>>>>> + .attrs = xe_pmu_format_attrs,
>>>>> +};
>>>>> +
>>>>> +struct xe_ext_attribute {
>>>>> + struct device_attribute attr;
>>>>> + unsigned long val;
>>>>> +};
>>>>> +
>>>>> +static ssize_t xe_pmu_event_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf)
>>>>> +{
>>>>> + struct xe_ext_attribute *eattr;
>>>>> +
>>>>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>>>>> + return sprintf(buf, "config=0x%lx\n", eattr->val);
>>>>> +}
>>>>> +
>>>>> +static ssize_t cpumask_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf)
>>>>> +{
>>>>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask);
>>>>> +}
>>>>> +
>>>>> +static DEVICE_ATTR_RO(cpumask);
>>>>> +
>>>>> +static struct attribute *xe_cpumask_attrs[] = {
>>>>> + &dev_attr_cpumask.attr,
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>>>>> + .attrs = xe_cpumask_attrs,
>>>>> +};
>>>>> +
>>>>> +#define __event(__counter, __name, __unit) \
>>>>> +{ \
>>>>> + .counter = (__counter), \
>>>>> + .name = (__name), \
>>>>> + .unit = (__unit), \
>>>>> + .global = false, \
>>>>> +}
>>>>> +
>>>>> +#define __global_event(__counter, __name, __unit) \
>>>>> +{ \
>>>>> + .counter = (__counter), \
>>>>> + .name = (__name), \
>>>>> + .unit = (__unit), \
>>>>> + .global = true, \
>>>>> +}
>>>>> +
>>>>> +static struct xe_ext_attribute *
>>>>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64 config)
>>>>> +{
>>>>> + sysfs_attr_init(&attr->attr.attr);
>>>>> + attr->attr.attr.name = name;
>>>>> + attr->attr.attr.mode = 0444;
>>>>> + attr->attr.show = xe_pmu_event_show;
>>>>> + attr->val = config;
>>>>> +
>>>>> + return ++attr;
>>>>> +}
>>>>> +
>>>>> +static struct perf_pmu_events_attr *
>>>>> +add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
>>>>> + const char *str)
>>>>> +{
>>>>> + sysfs_attr_init(&attr->attr.attr);
>>>>> + attr->attr.attr.name = name;
>>>>> + attr->attr.attr.mode = 0444;
>>>>> + attr->attr.show = perf_event_sysfs_show;
>>>>> + attr->event_str = str;
>>>>> +
>>>>> + return ++attr;
>>>>> +}
>>>>> +
>>>>> +static struct attribute **
>>>>> +create_event_attributes(struct xe_pmu *pmu)
>>>>> +{
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + static const struct {
>>>>> + unsigned int counter;
>>>>> + const char *name;
>>>>> + const char *unit;
>>>>> + bool global;
>>>>> + } events[] = {
>>>>> + __global_event(0, "interrupts", NULL),
>>>>> + __event(1, "render-group-busy", "ns"),
>>>>> + __event(2, "copy-group-busy", "ns"),
>>>>> + __event(3, "media-group-busy", "ns"),
>>>>> + __event(4, "any-engine-group-busy", "ns"),
>>>>> + };
>>>>
>>>> OK: this function is some black magic to expose stuff through
>>>> PMU. Identical to i915 and seems to be working from the commit message so
>>>> should be fine.
>>>>
>>>>> +
>>>>> + unsigned int count = 0;
>>>>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>>>>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>>>>> + struct attribute **attr = NULL, **attr_iter;
>>>>> + struct xe_gt *gt;
>>>>> + unsigned int i, j;
>>>>> +
>>>>> + /* Count how many counters we will be exposing. */
>>>>> + for_each_gt(gt, xe, j) {
>>>>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>>>>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>>>>> +
>>>>> + if (!config_status(xe, config))
>>>>> + count++;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + /* Allocate attribute objects and table. */
>>>>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>>>>> + if (!xe_attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>>>>> + if (!pmu_attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + /* Max one pointer of each attribute type plus a termination entry. */
>>>>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>>>>> + if (!attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + xe_iter = xe_attr;
>>>>> + pmu_iter = pmu_attr;
>>>>> + attr_iter = attr;
>>>>> +
>>>>> + for_each_gt(gt, xe, j) {
>>>>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>>>>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>>>>> + char *str;
>>>>> +
>>>>> + if (config_status(xe, config))
>>>>> + continue;
>>>>> +
>>>>> + if (events[i].global)
>>>>> + str = kstrdup(events[i].name, GFP_KERNEL);
>>>>> + else
>>>>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>>>>> + events[i].name, j);
>>>>> + if (!str)
>>>>> + goto err;
>>>>> +
>>>>> + *attr_iter++ = &xe_iter->attr.attr;
>>>>> + xe_iter = add_xe_attr(xe_iter, str, config);
>>>>> +
>>>>> + if (events[i].unit) {
>>>>> + if (events[i].global)
>>>>> + str = kasprintf(GFP_KERNEL, "%s.unit",
>>>>> + events[i].name);
>>>>> + else
>>>>> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
>>>>> + events[i].name, j);
>>>>> + if (!str)
>>>>> + goto err;
>>>>> +
>>>>> + *attr_iter++ = &pmu_iter->attr.attr;
>>>>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>>>>> + events[i].unit);
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + pmu->xe_attr = xe_attr;
>>>>> + pmu->pmu_attr = pmu_attr;
>>>>> +
>>>>> + return attr;
>>>>> +
>>>>> +err:
>>>>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>>>>> + kfree((*attr_iter)->name);
>>>>> +
>>>>> +err_alloc:
>>>>> + kfree(attr);
>>>>> + kfree(xe_attr);
>>>>> + kfree(pmu_attr);
>>>>> +
>>>>> + return NULL;
>>>>> +}
>>>>> +
>>>>> +static void free_event_attributes(struct xe_pmu *pmu)
>>>>> +{
>>>>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>>>>> +
>>>>> + for (; *attr_iter; attr_iter++)
>>>>> + kfree((*attr_iter)->name);
>>>>> +
>>>>> + kfree(pmu->events_attr_group.attrs);
>>>>> + kfree(pmu->xe_attr);
>>>>> + kfree(pmu->pmu_attr);
>>>>> +
>>>>> + pmu->events_attr_group.attrs = NULL;
>>>>> + pmu->xe_attr = NULL;
>>>>> + pmu->pmu_attr = NULL;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
>>>>> +{
>>>>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
>>>>> +
>>>>> + XE_BUG_ON(!pmu->base.event_init);
>>>>> +
>>>>> + /* Select the first online CPU as a designated reader. */
>>>>> + if (cpumask_empty(&xe_pmu_cpumask))
>>>>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
>>>>> +{
>>>>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
>>>>> + unsigned int target = xe_pmu_target_cpu;
>>>>> +
>>>>> + XE_BUG_ON(!pmu->base.event_init);
>>>>> +
>>>>> + /*
>>>>> + * Unregistering an instance generates a CPU offline event which we must
>>>>> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
>>>>> + */
>>>>> + if (pmu->closed)
>>>>> + return 0;
>>>>> +
>>>>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>>>>> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
>>>>> +
>>>>> + /* Migrate events if there is a valid target */
>>>>> + if (target < nr_cpu_ids) {
>>>>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>>>>> + xe_pmu_target_cpu = target;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>>>>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>>>>> + pmu->cpuhp.cpu = target;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>>>>> +
>>>>> +int xe_pmu_init(void)
>>>>> +{
>>>>> + int ret;
>>>>> +
>>>>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>>>>> + "perf/x86/intel/xe:online",
>>>>> + xe_pmu_cpu_online,
>>>>> + xe_pmu_cpu_offline);
>>>>> + if (ret < 0)
>>>>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>>>>> + ret);
>>>>> + else
>>>>> + cpuhp_slot = ret;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +void xe_pmu_exit(void)
>>>>> +{
>>>>> + if (cpuhp_slot != CPUHP_INVALID)
>>>>> + cpuhp_remove_multi_state(cpuhp_slot);
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu)
>>>>> +{
>>>>> + if (cpuhp_slot == CPUHP_INVALID)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu)
>>>>> +{
>>>>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_unregister(struct drm_device *device, void *arg)
>>>>> +{
>>>>> + struct xe_pmu *pmu = arg;
>>>>> +
>>>>> + if (!pmu->base.event_init)
>>>>> + return;
>>>>> +
>>>>> + /*
>>>>> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
>>>>> + * ensures all currently executing ones will have exited before we
>>>>> + * proceed with unregistration.
>>>>> + */
>>>>> + pmu->closed = true;
>>>>> + synchronize_rcu();
>>>>> +
>>>>> + xe_pmu_unregister_cpuhp_state(pmu);
>>>>> +
>>>>> + perf_pmu_unregister(&pmu->base);
>>>>> + pmu->base.event_init = NULL;
>>>>> + kfree(pmu->base.attr_groups);
>>>>> + kfree(pmu->name);
>>>>> + free_event_attributes(pmu);
>>>>> +}
>>>>> +
>>>>> +static void init_samples(struct xe_pmu *pmu)
>>>>> +{
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + struct xe_gt *gt;
>>>>> + unsigned int i;
>>>>> +
>>>>> + for_each_gt(gt, xe, i)
>>>>> + engine_group_busyness_store(gt);
>>>>> +}
>>>>> +
>>>>> +void xe_pmu_register(struct xe_pmu *pmu)
>>>>
>>>> Why void, why not int? PMU failure is non fatal error?
>>>
>>> Ya device is functional , it is only that these counters are not
>>> available. Hence didn't want to fail the driver load.
>>>>
>>>>> +{
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + const struct attribute_group *attr_groups[] = {
>>>>> + &xe_pmu_format_attr_group,
>>>>> + &pmu->events_attr_group,
>>>>> + &xe_pmu_cpumask_attr_group,
>>>>
>>>> Can someone please explain what this cpumask/cpuhotplug stuff does and
>>>> whether it needs to be in this patch? There's something here:
>>>
>>> comments from original patch series in
>>> i915:https://patchwork.kernel.org/project/intel-gfx/patch/20170802123249.14194-5-tvrtko.ursulin@linux.intel.com/
>>>
>>> "IIRC an uncore PMU should expose a cpumask through sysfs, and then perf
>>> tools will read that mask and auto-magically limit the number of CPUs it
>>> instantiates the counter on."
>>>
>>> and ours are global counters not per cpu so we limit to just to single cpu.
>>>
>>> And as i understand we use the cpuhotplug support to migrate too new cpu
>>> incase the earlier one goes offline.
>>
>> OK, leave as is.
>>
>>>
>>>>
>>>> b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
>>>>
>>>> I'd rather just have the basic PMU infra and the events in this patch and
>>>> punt this cpumask/cpuhotplug stuff to a later patch, unless someone can say
>>>> what it does.
>>>>
>>>> Though perf_pmu_register seems to be doing some per cpu stuff so likely
>>>> this is needed. But amdgpu_pmu only has event and format attributes.
>>>>
>>>> Mostly leave as is I guess.
>>>>
>>>>> + NULL
>>>>> + };
>>>>> +
>>>>> + int ret = -ENOMEM;
>>>>> +
>>>>> + spin_lock_init(&pmu->lock);
>>>>> + pmu->cpuhp.cpu = -1;
>>>>> + init_samples(pmu);
>>>>
>>>> Why init_samples here? Can't we init the particular sample in
>>>> xe_pmu_event_init or even xe_pmu_event_start?
>>>>
>>>> Init'ing here may be too soon since the event might not be enabled for a
>>>> long time. So really this needs to move to xe_pmu_event_init or
>>>> xe_pmu_event_start.
>>>
>>> The device is put to suspend immediately after driver probe, typically
>>> pmu is opened even before any workload is run so essentially device is
>>> still in suspend state hence we cannot access registers so storing the
>>> last known value in init_samples. otherwise we see the bug in v#1 of series.
>>>
>>>>
>>>> Actually this is already happening in xe_pmu_enable. We just need to decide
>>>> when we want to wake the device up and when we don't. So maybe wake the
>>>> device up at start (use xe_device_mem_access_get) and not wake up during
>>>> read (xe_device_mem_access_get_if_ongoing etc.)?
>>
>> Just going to repeat this again:
>>
>> xe_pmu_event_start calls xe_pmu_enable. In xe_pmu_enable use
>> xe_device_mem_access_get before calling __xe_pmu_event_read. This will wake
>> the device up and get a valid value in event->hw.prev_count.
>>
>> In xe_pmu_event_read, use xe_device_mem_access_get_if_ongoing, to read the
>> event without waking the device up (and return previous value etc.).
>>
>> Or, pass a flag in to __xe_pmu_event_read and to engine_group_busyness_read
>> and __engine_group_busyness_read. The flag will say whether or not to wake
>> up the device. If the flag says wake the device up, call
>> xe_device_mem_access_get and xe_force_wake_get, maybe in
>> __engine_group_busyness_read, before reading device registers. If the flag
>> says don't wake up the device call xe_device_mem_access_get_if_ongoing.
>>
>> This way we:
>> * don't need to call init_samples in xe_pmu_register
>> * we don't need engine_group_busyness_store
>> * we don't need to specifically call engine_group_busyness_store in xe_gt_suspend
>>
>> The correct sample is read by waking up the device in xe_pmu_event_start.
>>
>> Hopefully this is clear now.
>
> Actually I think it is not necessary to do anything in xe_pmu_event_start,
> as long as we keep the engine_group_busyness_store in xe_gt_suspend (so we
> can just use xe_device_mem_access_get_if_ongoing, don't need
> xe_device_mem_access_get as you said).
>
> Afais, the problem of huge values in v1 was due to reading the device
> registers when device was not awake. That problem we've already solved in
> v2 where in engine_group_busyness_read() we only read if the device is
> awake and skip and return the previous value when the device is not
> awake. So that fixes the problem of huge values.
>
> The problem in this patch (I thought) is that we are effectively sampling
> the registers each time perf calls xe_pmu_event_read, say every 1 sec. So
> we are sampling the registers every 1 sec. When we sample (every 1 sec) if
> the device is awake we will return the correct ns value, if device is
> asleep we will return the old value. If the device wakes up and does some
> work in the 1 sec period but then again suspends will miss that
> activity. That is the problem that is being solved by storing the samples
> in xe_gt_suspend().
>
> i915 solved this problem using a 5 ms timer but I like the solution of
> sampling in xe_gt_suspend better, so let's keep it.
>
> But init_samples is not needed, afais we don't need to do anything in
> xe_pmu_register or in xe_pmu_event_start (and we don't need to use
> xe_device_mem_access_get). xe_gt_suspend will take care of storing the
> register values before the device suspends.
>
> Hopefully it makes sense now, sorry for the confusion.
yes you are right we do not need init_samples.
Thanks,
Aravind.
>
> Ashutosh
>
>>
>>>
>>>>
>>>>> +
>>>>> + pmu->name = kasprintf(GFP_KERNEL,
>>>>> + "xe_%s",
>>>>> + dev_name(xe->drm.dev));
>>>>> + if (pmu->name)
>>>>> + /* tools/perf reserves colons as special. */
>>>>> + strreplace((char *)pmu->name, ':', '_');
>>>>> +
>>>>> + if (!pmu->name)
>>>>> + goto err;
>>>>> +
>>>>> + pmu->events_attr_group.name = "events";
>>>>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>>>>> + if (!pmu->events_attr_group.attrs)
>>>>> + goto err_name;
>>>>> +
>>>>> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
>>>>> + GFP_KERNEL);
>>>>> + if (!pmu->base.attr_groups)
>>>>> + goto err_attr;
>>>>> +
>>>>> + pmu->base.module = THIS_MODULE;
>>>>> + pmu->base.task_ctx_nr = perf_invalid_context;
>>>>> + pmu->base.event_init = xe_pmu_event_init;
>>>>> + pmu->base.add = xe_pmu_event_add;
>>>>> + pmu->base.del = xe_pmu_event_del;
>>>>> + pmu->base.start = xe_pmu_event_start;
>>>>> + pmu->base.stop = xe_pmu_event_stop;
>>>>> + pmu->base.read = xe_pmu_event_read;
>>>>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>>>>> +
>>>>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>>>>> + if (ret)
>>>>> + goto err_groups;
>>>>> +
>>>>> + ret = xe_pmu_register_cpuhp_state(pmu);
>>>>> + if (ret)
>>>>> + goto err_unreg;
>>>>> +
>>>>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
>>>>> + XE_WARN_ON(ret);
>>>>
>>>> We should just follow the regular error rewind here too and let
>>>> drm_notice() at the end print the error. This is what other drivers calling
>>>> drmm_add_action_or_reset seem to be doing.
>>>
>>> Ok ok.
>>>>
>>>>> +
>>>>> + return;
>>>>> +
>>>>> +err_unreg:
>>>>> + perf_pmu_unregister(&pmu->base);
>>>>> +err_groups:
>>>>> + kfree(pmu->base.attr_groups);
>>>>> +err_attr:
>>>>> + pmu->base.event_init = NULL;
>>>>> + free_event_attributes(pmu);
>>>>> +err_name:
>>>>> + kfree(pmu->name);
>>>>> +err:
>>>>> + drm_notice(&xe->drm, "Failed to register PMU!\n");
>>>>> +}
>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h b/drivers/gpu/drm/xe/xe_pmu.h
>>>>> new file mode 100644
>>>>> index 000000000000..d3f47f4ab343
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>>>>> @@ -0,0 +1,25 @@
>>>>> +/* SPDX-License-Identifier: MIT */
>>>>> +/*
>>>>> + * Copyright © 2023 Intel Corporation
>>>>> + */
>>>>> +
>>>>> +#ifndef _XE_PMU_H_
>>>>> +#define _XE_PMU_H_
>>>>> +
>>>>> +#include "xe_gt_types.h"
>>>>> +#include "xe_pmu_types.h"
>>>>> +
>>>>> +#ifdef CONFIG_PERF_EVENTS
>>>>
>>>> nit but maybe this should be:
>>>>
>>>> #if IS_ENABLED(CONFIG_PERF_EVENTS)
>>>>
>>>> or,
>>>>
>>>> #if IS_BUILTIN(CONFIG_PERF_EVENTS)
>>>>
>>>> Note CONFIG_PERF_EVENTS is a boolean kconfig option.
>>>>
>>>> See similar macro IS_REACHABLE() in i915_hwmon.h.
>>>>
>>>>> +int xe_pmu_init(void);
>>>>> +void xe_pmu_exit(void);
>>>>> +void xe_pmu_register(struct xe_pmu *pmu);
>>>>> +void engine_group_busyness_store(struct xe_gt *gt);
>>>>
>>>> Add xe_pmu_ prefix if function is needed (hopefully not).
>>>
>>> OK
>>>>
>>>>> +#else
>>>>> +static inline int xe_pmu_init(void) { return 0; }
>>>>> +static inline void xe_pmu_exit(void) {}
>>>>> +static inline void xe_pmu_register(struct xe_pmu *pmu) {}
>>>>> +static inline void engine_group_busyness_store(struct xe_gt *gt) {}
>>>>> +#endif
>>>>> +
>>>>> +#endif
>>>>> +
>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
>>>>> new file mode 100644
>>>>> index 000000000000..e87edd4d6a87
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>>>>> @@ -0,0 +1,80 @@
>>>>> +/* SPDX-License-Identifier: MIT */
>>>>> +/*
>>>>> + * Copyright © 2023 Intel Corporation
>>>>> + */
>>>>> +
>>>>> +#ifndef _XE_PMU_TYPES_H_
>>>>> +#define _XE_PMU_TYPES_H_
>>>>> +
>>>>> +#include <linux/perf_event.h>
>>>>> +#include <linux/spinlock_types.h>
>>>>> +#include <uapi/drm/xe_drm.h>
>>>>> +
>>>>> +enum {
>>>>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __XE_NUM_PMU_SAMPLERS
>>>>
>>>> OK: irq_count is missing here since these are read from device...
>>>>
>>>>> +};
>>>>> +
>>>>> +struct xe_pmu_sample {
>>>>> + u64 cur;
>>>>> +};
>>>>
>>>> This was also discussed for i915 PMU, no point having a struct with a
>>>> single u64 member. Might as well just use u64 wherever we are using
>>>> struct xe_pmu_sample.
>>>
>>> OK.
>>>>
>>>>> +
>>>>> +#define XE_MAX_GT_PER_TILE 2
>>>>
>>>> Why per tile? The array size should be max_gt_per_device. Just call it
>>>> XE_MAX_GT?
>>>
>>> I declared similar to what we have in drivers/gpu/drm/xe/xe_device.h
>>
>> Our 2-d array size is for the device, not per tile. So let's use XE_MAX_GT.
>>
>>>>
>>>>> +
>>>>> +struct xe_pmu {
>>>>> + /**
>>>>> + * @cpuhp: Struct used for CPU hotplug handling.
>>>>> + */
>>>>> + struct {
>>>>> + struct hlist_node node;
>>>>> + unsigned int cpu;
>>>>> + } cpuhp;
>>>>> + /**
>>>>> + * @base: PMU base.
>>>>> + */
>>>>> + struct pmu base;
>>>>> + /**
>>>>> + * @closed: xe is unregistering.
>>>>> + */
>>>>> + bool closed;
>>>>> + /**
>>>>> + * @name: Name as registered with perf core.
>>>>> + */
>>>>> + const char *name;
>>>>> + /**
>>>>> + * @lock: Lock protecting enable mask and ref count handling.
>>>>> + */
>>>>> + spinlock_t lock;
>>>>> + /**
>>>>> + * @sample: Current and previous (raw) counters.
>>>>> + *
>>>>> + * These counters are updated when the device is awake.
>>>>> + *
>>>>> + */
>>>>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE * __XE_NUM_PMU_SAMPLERS];
>>>>
>>>> Change to 2-d array. See above.
>>>>
>>>>> + /**
>>>>> + * @irq_count: Number of interrupts
>>>>> + *
>>>>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>>>>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>>>>> + * occasional wraparound easily. It's 32bit after all.
>>>>> + */
>>>>> + unsigned long irq_count;
>>>>> + /**
>>>>> + * @events_attr_group: Device events attribute group.
>>>>> + */
>>>>> + struct attribute_group events_attr_group;
>>>>> + /**
>>>>> + * @xe_attr: Memory block holding device attributes.
>>>>> + */
>>>>> + void *xe_attr;
>>>>> + /**
>>>>> + * @pmu_attr: Memory block holding device attributes.
>>>>> + */
>>>>> + void *pmu_attr;
>>>>> +};
>>>>> +
>>>>> +#endif
>>>>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>>>>> index 965cd9527ff1..ed097056f944 100644
>>>>> --- a/include/uapi/drm/xe_drm.h
>>>>> +++ b/include/uapi/drm/xe_drm.h
>>>>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>>>>> __u64 reserved[2];
>>>>> };
>>>>>
>>>>> +/* PMU event config IDs */
>>>>> +
>>>>> +/*
>>>>> + * Top 4 bits of every counter are GT id.
>>>>> + */
>>>>> +#define __XE_PMU_GT_SHIFT (60)
>>>>
>>>> To future-proof this, and also because we seem to have plenty of bits
>>>> available, I think we should change this to 56 (instead of 60).
>>>
>>> OK
>>>
>>> Thanks,
>>> Aravind.
>>>>
>>>>> +
>>>>> +#define ___XE_PMU_OTHER(gt, x) \
>>>>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>>>>> +
>>>>> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
>>>>> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
>>>>> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
>>>>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
>>>>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
>>>>> +
>>>>> #if defined(__cplusplus)
>>>>> }
>>>>> #endif
>>>>> --
>>>>> 2.25.1
>>
>> Thanks.
>> --
>> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 8:03 ` Iddamsetty, Aravind
@ 2023-07-24 9:00 ` Ursulin, Tvrtko
2023-07-24 15:52 ` Dixit, Ashutosh
2023-07-24 15:52 ` Dixit, Ashutosh
1 sibling, 1 reply; 59+ messages in thread
From: Ursulin, Tvrtko @ 2023-07-24 9:00 UTC (permalink / raw)
To: Iddamsetty, Aravind, Dixit, Ashutosh
Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org
[Top-post since my dual email setup and this is the wrong one, sorry.]
Glancing over the discussion - small correction - i915 did not solve the problem of hardware counters and sleeping device with the timer but with the park/unpark hooks.
More similar to these group busyness counters would be the RC6, and you will notice there is nothing in the i915 sampling timer about RC6. There is just some complicated code in park/unpark to estimate RC6 while parked. But the estimation is beside the point for engine group busyness since it is the opposite metric (grows on busy vs grows idle).
And I think you converged to the same solution already, so I just wanted to correct the 5ms timer inaccuracy.
Regards,
Tvrtko
-----Original Message-----
From: Iddamsetty, Aravind <aravind.iddamsetty@intel.com>
Sent: Monday, July 24, 2023 9:03 AM
To: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Cc: intel-xe@lists.freedesktop.org; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; Upadhyay, Tejas <tejas.upadhyay@intel.com>
Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
On 22-07-2023 11:34, Dixit, Ashutosh wrote:
Hi Ashutosh,
> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>
>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>
>> Hi Aravind,
>>
>>> On 21-07-2023 06:32, Dixit, Ashutosh wrote:
>>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>>>>
>>>> More stuff to mull over. You can ignore comments starting with
>>>> "OK", those are just notes to myself.
>>>>
>>>> Also, maybe some time we can add a basic IGT which reads these
>>>> exposed counters and verifies that we can read them and they are
>>>> monotonically increasing?
>>>
>>> this is the IGT https://patchwork.freedesktop.org/series/119936/
>>> series using these counters posted by Venkat.
>>>
>>>>
>>>>> There are a set of engine group busyness counters provided by HW
>>>>> which are perfect fit to be exposed via PMU perf events.
>>>>>
>>>>> BSPEC: 46559, 46560, 46722, 46729
>>>>
>>>> Also add these Bspec entries: 71028, 52071
>>>
>>> OK.
>>>
>>>>
>>>>>
>>>>> events can be listed using:
>>>>> perf list
>>>>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>>>>
>>>>> and can be read using:
>>>>>
>>>>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>>>>> time counts unit events
>>>>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>>
>>>>> The pmu base implementation is taken from i915.
>>>>>
>>>>> v2:
>>>>> Store last known value when device is awake return that while the
>>>>> GT is suspended and then update the driver copy when read during awake.
>>>>>
>>>>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/xe/Makefile | 2 +
>>>>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>>>>> drivers/gpu/drm/xe/xe_device.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>>>>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>>>>> drivers/gpu/drm/xe/xe_module.c | 5 +
>>>>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>>>>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>>>>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>>>>> include/uapi/drm/xe_drm.h | 16 +
>>>>> 11 files changed, 902 insertions(+) create mode 100644
>>>>> drivers/gpu/drm/xe/xe_pmu.c create mode 100644
>>>>> drivers/gpu/drm/xe/xe_pmu.h create mode 100644
>>>>> drivers/gpu/drm/xe/xe_pmu_types.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/Makefile
>>>>> b/drivers/gpu/drm/xe/Makefile index 081c57fd8632..e52ab795c566
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/xe/Makefile
>>>>> +++ b/drivers/gpu/drm/xe/Makefile
>>>>> @@ -217,6 +217,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>>>> i915-display/skl_universal_plane.o \
>>>>> i915-display/skl_watermark.o
>>>>>
>>>>> +xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>>>>> +
>>>>> ifeq ($(CONFIG_ACPI),y)
>>>>> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>>>> i915-display/intel_acpi.o \
>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> index 3f664011eaea..c7d9e4634745 100644
>>>>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> @@ -285,6 +285,11 @@
>>>>> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
>>>>> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>>>>>
>>>>> +#define XE_OAG_RC0_ANY_ENGINE_BUSY_FREE XE_REG(0xdb80)
>>>>> +#define XE_OAG_ANY_MEDIA_FF_BUSY_FREE XE_REG(0xdba0)
>>>>> +#define XE_OAG_BLT_BUSY_FREE XE_REG(0xdbbc)
>>>>> +#define XE_OAG_RENDER_BUSY_FREE XE_REG(0xdbdc)
>>>>> +
>>>>> #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
>>>>> #define ENABLE_SMALLPL REG_BIT(15)
>>>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>>>>> b/drivers/gpu/drm/xe/xe_device.c index c7985af85a53..b2c7bd4a97d9
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_device.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_device.c
>>>>> @@ -328,6 +328,8 @@ int xe_device_probe(struct xe_device *xe)
>>>>>
>>>>> xe_debugfs_register(xe);
>>>>>
>>>>> + xe_pmu_register(&xe->pmu);
>>>>> +
>>>>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>>>>> if (err)
>>>>> return err;
>>>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>>>>> b/drivers/gpu/drm/xe/xe_device_types.h
>>>>> index 0226d44a6af2..3ba99aae92b9 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>>>> @@ -15,6 +15,7 @@
>>>>> #include "xe_devcoredump_types.h"
>>>>> #include "xe_gt_types.h"
>>>>> #include "xe_platform_types.h"
>>>>> +#include "xe_pmu.h"
>>>>> #include "xe_step_types.h"
>>>>>
>>>>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) @@ -332,6 +333,9 @@ struct
>>>>> xe_device {
>>>>> /** @d3cold_allowed: Indicates if d3cold is a valid device state */
>>>>> bool d3cold_allowed;
>>>>>
>>>>> + /* @pmu: performance monitoring unit */
>>>>> + struct xe_pmu pmu;
>>>>> +
>>>>
>>>> Now I am wondering why we don't make the PMU per-gt (or per-tile)?
>>>> Per-gt would work for these busyness registers and I am not sure
>>>> how the interrupts are hooked up.
>>>>
>>>> In i915 the PMU being device level helped in having a single timer
>>>> (rather than a per gt timer).
>>>>
>>>> Anyway probably not much practical benefit by make it
>>>> per-gt/per-tile, so maybe leave as is. Just thinking out loud.
>>>
>>> we are able to expose per-gt counters so do not see any benefit in
>>> making pmu per-gt, also i believe struct pmu is per device it will
>>> have a type associated which is unique for a device.
>>
>> PMU can be made per gt and named xe-gt0, xe-gt1 etc. if we want. But
>> anyway leave as is.
>>
>>>
>>>>
>>>>> /* private: */
>>>>>
>>>>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) diff --git
>>>>> a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index
>>>>> 2458397ce8af..96e3720923d4 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_gt.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>>>>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>>>>> if (err)
>>>>> goto err_msg;
>>>>>
>>>>> + engine_group_busyness_store(gt);
>>>>
>>>> Not sure I follow the reason for doing this at suspend time? If PMU
>>>> was active there should be a previous value. Why must we take a new
>>>> sample explicitly here?
>>>
>>> the PMU interface can be read even when device is suspend and in
>>> such cases we should not wake up the device, and if we try to read
>>> the register when device is suspended it gives spurious counter you
>>> can check in version#1 of this series we were getting huge values.
>>> as we put the device to suspend immediately after probe. So storing
>>> the last known good value before suspend.
>>
>> No need, see comment at init_samples below.
>
> Sorry, you are right, I changed my mind about this, I see your point.
> See more discussion on this at init_samples below.
>
>>
>>>
>>>>
>>>> To me looks like engine_group_busyness_store should not be needed,
>>>> see comment below for init_samples too.
>>>>
>>>>> +
>>>>> err = xe_uc_suspend(>->uc);
>>>>> if (err)
>>>>> goto err_force_wake;
>>>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c
>>>>> b/drivers/gpu/drm/xe/xe_irq.c index b4ed1e4a3388..cb943fb94ec7
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>>>> @@ -27,6 +27,24 @@
>>>>> #define IIR(offset) XE_REG(offset + 0x8)
>>>>> #define IER(offset) XE_REG(offset + 0xc)
>>>>>
>>>>> +/*
>>>>> + * Interrupt statistic for PMU. Increments the counter only if
>>>>> +the
>>>>> + * interrupt originated from the GPU so interrupts from a device
>>>>> +which
>>>>> + * shares the interrupt line are not accounted.
>>>>> + */
>>>>> +static inline void xe_pmu_irq_stats(struct xe_device *xe,
>>>>
>>>> No inline, compiler will do it, but looks like we may want to
>>>> always_inline this. Also this function should really be in
>>>> xe_pmu.h? Anyway probably leave as is.
>>>>
>>>>> + irqreturn_t res)
>>>>> +{
>>>>> + if (unlikely(res != IRQ_HANDLED))
>>>>> + return;
>>>>> +
>>>>> + /*
>>>>> + * A clever compiler translates that into INC. A not so clever one
>>>>> + * should at least prevent store tearing.
>>>>> + */
>>>>> + WRITE_ONCE(xe->pmu.irq_count, xe->pmu.irq_count + 1); }
>>>>> +
>>>>> static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg
>>>>> reg) {
>>>>> u32 val = xe_mmio_read32(mmio, reg); @@ -325,6 +343,8 @@ static
>>>>> irqreturn_t xelp_irq_handler(int irq, void *arg)
>>>>>
>>>>> xe_display_irq_enable(xe, gu_misc_iir);
>>>>>
>>>>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>>>>> +
>>>>> return IRQ_HANDLED;
>>>>> }
>>>>>
>>>>> @@ -414,6 +434,8 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>>>>> dg1_intr_enable(xe, false);
>>>>> xe_display_irq_enable(xe, gu_misc_iir);
>>>>>
>>>>> + xe_pmu_irq_stats(xe, IRQ_HANDLED);
>>>>> +
>>>>> return IRQ_HANDLED;
>>>>> }
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.c
>>>>> b/drivers/gpu/drm/xe/xe_module.c index 75e5be939f53..f6fe89748525
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_module.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_module.c
>>>>> @@ -12,6 +12,7 @@
>>>>> #include "xe_hw_fence.h"
>>>>> #include "xe_module.h"
>>>>> #include "xe_pci.h"
>>>>> +#include "xe_pmu.h"
>>>>> #include "xe_sched_job.h"
>>>>>
>>>>> bool enable_guc = true;
>>>>> @@ -49,6 +50,10 @@ static const struct init_funcs init_funcs[] = {
>>>>> .init = xe_sched_job_module_init,
>>>>> .exit = xe_sched_job_module_exit,
>>>>> },
>>>>> + {
>>>>> + .init = xe_pmu_init,
>>>>> + .exit = xe_pmu_exit,
>>>>> + },
>>>>> {
>>>>> .init = xe_register_pci_driver,
>>>>> .exit = xe_unregister_pci_driver, diff --git
>>>>> a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c new
>>>>> file mode 100644 index 000000000000..bef1895be9f7
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>>>>> @@ -0,0 +1,739 @@
>>>>> +/*
>>>>> + * SPDX-License-Identifier: MIT
>>>>> + *
>>>>> + * Copyright © 2023 Intel Corporation */
>>>>
>>>> This SPDX header is for .h files not .c files. Actually, it is for
>>>> neither :/
>>>
>>> But i see this in almost all the files in xe.
>>
>> Look closely.
>>
>>>>
>>>>> +
>>>>> +#include <drm/drm_drv.h>
>>>>> +#include <drm/drm_managed.h>
>>>>> +#include <drm/xe_drm.h>
>>>>> +
>>>>> +#include "regs/xe_gt_regs.h"
>>>>> +#include "xe_device.h"
>>>>> +#include "xe_gt_clock.h"
>>>>> +#include "xe_mmio.h"
>>>>> +
>>>>> +static cpumask_t xe_pmu_cpumask;
>>>>> +static unsigned int xe_pmu_target_cpu = -1;
>>>>> +
>>>>> +static unsigned int config_gt_id(const u64 config) {
>>>>> + return config >> __XE_PMU_GT_SHIFT; }
>>>>> +
>>>>> +static u64 config_counter(const u64 config) {
>>>>> + return config & ~(~0ULL << __XE_PMU_GT_SHIFT); }
>>>>> +
>>>>> +static unsigned int
>>>>> +__sample_idx(struct xe_pmu *pmu, unsigned int gt_id, int sample)
>>>>> +{
>>>>> + unsigned int idx = gt_id * __XE_NUM_PMU_SAMPLERS + sample;
>>>>> +
>>>>> + XE_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
>>>>> +
>>>>> + return idx;
>>>>> +}
>>>>
>>>> The compiler does this for us if we make sample array 2-d.
>>>>
>>>>> +
>>>>> +static u64 read_sample(struct xe_pmu *pmu, unsigned int gt_id,
>>>>> +int sample) {
>>>>> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; }
>>>>> +
>>>>> +static void
>>>>> +store_sample(struct xe_pmu *pmu, unsigned int gt_id, int sample,
>>>>> +u64 val) {
>>>>> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; }
>>>>
>>>> The three functions above are not needed if we make the sample
>>>> array 2-d. See here:
>>>>
>>>> https://patchwork.freedesktop.org/patch/538887/?series=118225&rev=1
>>>>
>>>> Only a part of the patch above was merged (see 8ed0753b527dc) to
>>>> keep the patch size small, but since for xe we are starting from
>>>> scratch we can implement the whole approach above (get rid of the
>>>> read/store helpers entirely, direct assignment without the helpers works).
>>>
>>> Ok I'll go over it.
>>>
>>>>
>>>>> +
>>>>> +static int engine_busyness_sample_type(u64 config) {
>>>>> + int type = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_RENDER_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_COPY_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_MEDIA_GROUP_BUSY;
>>>>> + break;
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + type = __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY;
>>>>> + break;
>>>>> + }
>>>>> +
>>>>> + return type;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_destroy(struct perf_event *event) {
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> +
>>>>> + drm_WARN_ON(&xe->drm, event->parent);
>>>>> +
>>>>> + drm_dev_put(&xe->drm);
>>>>> +}
>>>>> +
>>>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, u64
>>>>> +config) {
>>>>> + u64 val = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE);
>>>>> + break;
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE);
>>>>> + break;
>>>>> + default:
>>>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n");
>>>>> + }
>>>>
>>>> We need xe_device_mem_access_get, also xe_force_wake_get if
>>>> applicable, somewhere before reading these registers.
>>>>
>>>>> +
>>>>> + return xe_gt_clock_interval_to_ns(gt, val * 16); }
>>>>> +
>>>>> +static u64 engine_group_busyness_read(struct xe_gt *gt, u64
>>>>> +config) {
>>>>> + int sample_type = engine_busyness_sample_type(config);
>>>>> + struct xe_device *xe = gt->tile->xe;
>>>>> + const unsigned int gt_id = gt->info.id;
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + bool device_awake;
>>>>> + unsigned long flags;
>>>>> + u64 val;
>>>>> +
>>>>> + /*
>>>>> + * found no better way to check if device is awake or not.
>>>>> +Before
>>>>
>>>> xe_device_mem_access_get_if_ongoing (hard to find name).
>>>
>>> thanks for sharing looks to be added recently. If we use this we
>>> needn't use xe_device_mem_access_get.
>>
>> See comment at init_samples.
>>
>>>
>>>>
>>>>> + * we suspend we set the submission_state.enabled to false.
>>>>> + */
>>>>> + device_awake = gt->uc.guc.submission_state.enabled ? true : false;
>>>>> + if (device_awake)
>>>>> + val = __engine_group_busyness_read(gt, config);
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + if (device_awake)
>>>>> + store_sample(pmu, gt_id, sample_type, val);
>>>>> + else
>>>>> + val = read_sample(pmu, gt_id, sample_type);
>>>>> +
>>>>> + spin_unlock_irqrestore(&pmu->lock, flags);
>>>>> +
>>>>> + return val;
>>>>> +}
>>>>> +
>>>>> +void engine_group_busyness_store(struct xe_gt *gt) {
>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>> + unsigned int gt_id = gt->info.id;
>>>>> + unsigned long flags;
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt,
>>>>> +XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>
> Here why should we store everything, we should store only those events
> which are enabled?
The events are enabled only when they are opened which can happen after the device is suspended hence we need to store all. As in the present case device is put to suspend immediately after probe and event is opened post driver load is done.
>
> Also it would good if the above can be done in a loop somehow. 4 is
> fine but if we add events later, a loop will be nice, if possible.
I do not think loop would solve the furture events as there can be selective i.e only few needs to be stored. pure counters like interrupts need not be stored.
>
>>>>> +
>>>>> + spin_unlock_irqrestore(&pmu->lock, flags); }
>>>>> +
>>>>> +static int
>>>>> +config_status(struct xe_device *xe, u64 config) {
>>>>> + unsigned int max_gt_id = xe->info.gt_count > 1 ? 1 : 0;
>>>>> + unsigned int gt_id = config_gt_id(config);
>>>>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>>>>> +
>>>>> + if (gt_id > max_gt_id)
>>>>> + return -ENOENT;
>>>>> +
>>>>> + switch (config_counter(config)) {
>>>>> + case XE_PMU_INTERRUPTS(0):
>>>>> + if (gt_id)
>>>>> + return -ENOENT;
>>>>
>>>> OK: this is a global event so we say this is enabled only for gt0.
>>>>
>>>>> + break;
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + if (GRAPHICS_VER(xe) < 12)
>>>>
>>>> Any point checking? xe only supports Gen12+.
>>>
>>> hmmm ya good point will remove this.
>>>>
>>>>> + return -ENOENT;
>>>>> + break;
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + if (MEDIA_VER(xe) >= 13 && gt->info.type != XE_GT_TYPE_MEDIA)
>>>>> + return -ENOENT;
>>>>
>>>> OK: this makes sense, so we will expose this event only for media gt's.
>>>>
>>>>> + break;
>>>>> + default:
>>>>> + return -ENOENT;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_event_init(struct perf_event *event) {
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + int ret;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return -ENODEV;
>>>>> +
>>>>> + if (event->attr.type != event->pmu->type)
>>>>> + return -ENOENT;
>>>>> +
>>>>> + /* unsupported modes and filters */
>>>>> + if (event->attr.sample_period) /* no sampling */
>>>>> + return -EINVAL;
>>>>> +
>>>>> + if (has_branch_stack(event))
>>>>> + return -EOPNOTSUPP;
>>>>> +
>>>>> + if (event->cpu < 0)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + /* only allow running on one cpu at a time */
>>>>> + if (!cpumask_test_cpu(event->cpu, &xe_pmu_cpumask))
>>>>> + return -EINVAL;
>>>>> +
>>>>> + ret = config_status(xe, event->attr.config);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (!event->parent) {
>>>>> + drm_dev_get(&xe->drm);
>>>>> + event->destroy = xe_pmu_event_destroy;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static u64 __xe_pmu_event_read(struct perf_event *event) {
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + const unsigned int gt_id = config_gt_id(event->attr.config);
>>>>> + const u64 config = config_counter(event->attr.config);
>>>>> + struct xe_gt *gt = xe_device_get_gt(xe, gt_id);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + u64 val = 0;
>>>>> +
>>>>> + switch (config) {
>>>>> + case XE_PMU_INTERRUPTS(0):
>>>>> + val = READ_ONCE(pmu->irq_count);
>>>>
>>>> OK: The correct way to do this READ_ONCE/WRITE_ONCE irq_count stuff
>>>> would be to take pmu->lock (both while reading and writing
>>>> irq_count) but that would be expensive in the interrupt handler (as
>>>> the .h hints). So all we can do is what is done here.
>>>>
>>>>> + break;
>>>>> + case XE_PMU_RENDER_GROUP_BUSY(0):
>>>>> + case XE_PMU_COPY_GROUP_BUSY(0):
>>>>> + case XE_PMU_ANY_ENGINE_GROUP_BUSY(0):
>>>>> + case XE_PMU_MEDIA_GROUP_BUSY(0):
>>>>> + val = engine_group_busyness_read(gt, config);
>>>>> + }
>>>>> +
>>>>> + return val;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_read(struct perf_event *event) {
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct hw_perf_event *hwc = &event->hw;
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> + u64 prev, new;
>>>>> +
>>>>> + if (pmu->closed) {
>>>>> + event->hw.state = PERF_HES_STOPPED;
>>>>> + return;
>>>>> + }
>>>>> +again:
>>>>> + prev = local64_read(&hwc->prev_count);
>>>>> + new = __xe_pmu_event_read(event);
>>>>> +
>>>>> + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
>>>>> + goto again;
>>>>> +
>>>>> + local64_add(new - prev, &event->count); }
>>>>> +
>>>>> +static void xe_pmu_enable(struct perf_event *event) {
>>>>> + /*
>>>>> + * Store the current counter value so we can report the correct delta
>>>>> + * for all listeners. Even when the event was already enabled and has
>>>>> + * an existing non-zero value.
>>>>> + */
>>>>> + local64_set(&event->hw.prev_count, __xe_pmu_event_read(event));
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_start(struct perf_event *event, int
>>>>> +flags) {
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return;
>>>>> +
>>>>> + xe_pmu_enable(event);
>>>>> + event->hw.state = 0;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_stop(struct perf_event *event, int
>>>>> +flags) {
>>>>> + if (flags & PERF_EF_UPDATE)
>>>>> + xe_pmu_event_read(event);
>>>>> +
>>>>> + event->hw.state = PERF_HES_STOPPED; }
>>>>> +
>>>>> +static int xe_pmu_event_add(struct perf_event *event, int flags)
>>>>> +{
>>>>> + struct xe_device *xe =
>>>>> + container_of(event->pmu, typeof(*xe), pmu.base);
>>>>> + struct xe_pmu *pmu = &xe->pmu;
>>>>> +
>>>>> + if (pmu->closed)
>>>>> + return -ENODEV;
>>>>> +
>>>>> + if (flags & PERF_EF_START)
>>>>> + xe_pmu_event_start(event, flags);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void xe_pmu_event_del(struct perf_event *event, int flags)
>>>>> +{
>>>>> + xe_pmu_event_stop(event, PERF_EF_UPDATE); }
>>>>> +
>>>>> +static int xe_pmu_event_event_idx(struct perf_event *event) {
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +struct xe_str_attribute {
>>>>> + struct device_attribute attr;
>>>>> + const char *str;
>>>>> +};
>>>>> +
>>>>> +static ssize_t xe_pmu_format_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf) {
>>>>> + struct xe_str_attribute *eattr;
>>>>> +
>>>>> + eattr = container_of(attr, struct xe_str_attribute, attr);
>>>>> + return sprintf(buf, "%s\n", eattr->str); }
>>>>> +
>>>>> +#define XE_PMU_FORMAT_ATTR(_name, _config) \
>>>>> + (&((struct xe_str_attribute[]) { \
>>>>> + { .attr = __ATTR(_name, 0444, xe_pmu_format_show, NULL), \
>>>>> + .str = _config, } \
>>>>> + })[0].attr.attr)
>>>>> +
>>>>> +static struct attribute *xe_pmu_format_attrs[] = {
>>>>> + XE_PMU_FORMAT_ATTR(xe_eventid, "config:0-20"),
>>>>
>>>> 0-20 means 0-20 bits? Though here we probably have different number
>>>> of config bits? Probably doesn't matter?
>>>
>>> as i understand this is not used anymore so will remove it.
>>>
>>>>
>>>> The string will show up with:
>>>>
>>>> cat /sys/devices/xe/format/xe_eventid
>>>>
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group xe_pmu_format_attr_group = {
>>>>> + .name = "format",
>>>>> + .attrs = xe_pmu_format_attrs,
>>>>> +};
>>>>> +
>>>>> +struct xe_ext_attribute {
>>>>> + struct device_attribute attr;
>>>>> + unsigned long val;
>>>>> +};
>>>>> +
>>>>> +static ssize_t xe_pmu_event_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf) {
>>>>> + struct xe_ext_attribute *eattr;
>>>>> +
>>>>> + eattr = container_of(attr, struct xe_ext_attribute, attr);
>>>>> + return sprintf(buf, "config=0x%lx\n", eattr->val); }
>>>>> +
>>>>> +static ssize_t cpumask_show(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf) {
>>>>> + return cpumap_print_to_pagebuf(true, buf, &xe_pmu_cpumask); }
>>>>> +
>>>>> +static DEVICE_ATTR_RO(cpumask);
>>>>> +
>>>>> +static struct attribute *xe_cpumask_attrs[] = {
>>>>> + &dev_attr_cpumask.attr,
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group xe_pmu_cpumask_attr_group = {
>>>>> + .attrs = xe_cpumask_attrs,
>>>>> +};
>>>>> +
>>>>> +#define __event(__counter, __name, __unit) \ { \
>>>>> + .counter = (__counter), \
>>>>> + .name = (__name), \
>>>>> + .unit = (__unit), \
>>>>> + .global = false, \
>>>>> +}
>>>>> +
>>>>> +#define __global_event(__counter, __name, __unit) \ { \
>>>>> + .counter = (__counter), \
>>>>> + .name = (__name), \
>>>>> + .unit = (__unit), \
>>>>> + .global = true, \
>>>>> +}
>>>>> +
>>>>> +static struct xe_ext_attribute *
>>>>> +add_xe_attr(struct xe_ext_attribute *attr, const char *name, u64
>>>>> +config) {
>>>>> + sysfs_attr_init(&attr->attr.attr);
>>>>> + attr->attr.attr.name = name;
>>>>> + attr->attr.attr.mode = 0444;
>>>>> + attr->attr.show = xe_pmu_event_show;
>>>>> + attr->val = config;
>>>>> +
>>>>> + return ++attr;
>>>>> +}
>>>>> +
>>>>> +static struct perf_pmu_events_attr * add_pmu_attr(struct
>>>>> +perf_pmu_events_attr *attr, const char *name,
>>>>> + const char *str)
>>>>> +{
>>>>> + sysfs_attr_init(&attr->attr.attr);
>>>>> + attr->attr.attr.name = name;
>>>>> + attr->attr.attr.mode = 0444;
>>>>> + attr->attr.show = perf_event_sysfs_show;
>>>>> + attr->event_str = str;
>>>>> +
>>>>> + return ++attr;
>>>>> +}
>>>>> +
>>>>> +static struct attribute **
>>>>> +create_event_attributes(struct xe_pmu *pmu) {
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + static const struct {
>>>>> + unsigned int counter;
>>>>> + const char *name;
>>>>> + const char *unit;
>>>>> + bool global;
>>>>> + } events[] = {
>>>>> + __global_event(0, "interrupts", NULL),
>>>>> + __event(1, "render-group-busy", "ns"),
>>>>> + __event(2, "copy-group-busy", "ns"),
>>>>> + __event(3, "media-group-busy", "ns"),
>>>>> + __event(4, "any-engine-group-busy", "ns"),
>>>>> + };
>>>>
>>>> OK: this function is some black magic to expose stuff through PMU.
>>>> Identical to i915 and seems to be working from the commit message
>>>> so should be fine.
>>>>
>>>>> +
>>>>> + unsigned int count = 0;
>>>>> + struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
>>>>> + struct xe_ext_attribute *xe_attr = NULL, *xe_iter;
>>>>> + struct attribute **attr = NULL, **attr_iter;
>>>>> + struct xe_gt *gt;
>>>>> + unsigned int i, j;
>>>>> +
>>>>> + /* Count how many counters we will be exposing. */
>>>>> + for_each_gt(gt, xe, j) {
>>>>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>>>>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>>>>> +
>>>>> + if (!config_status(xe, config))
>>>>> + count++;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + /* Allocate attribute objects and table. */
>>>>> + xe_attr = kcalloc(count, sizeof(*xe_attr), GFP_KERNEL);
>>>>> + if (!xe_attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>>>>> + if (!pmu_attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + /* Max one pointer of each attribute type plus a termination entry. */
>>>>> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>>>>> + if (!attr)
>>>>> + goto err_alloc;
>>>>> +
>>>>> + xe_iter = xe_attr;
>>>>> + pmu_iter = pmu_attr;
>>>>> + attr_iter = attr;
>>>>> +
>>>>> + for_each_gt(gt, xe, j) {
>>>>> + for (i = 0; i < ARRAY_SIZE(events); i++) {
>>>>> + u64 config = ___XE_PMU_OTHER(j, events[i].counter);
>>>>> + char *str;
>>>>> +
>>>>> + if (config_status(xe, config))
>>>>> + continue;
>>>>> +
>>>>> + if (events[i].global)
>>>>> + str = kstrdup(events[i].name, GFP_KERNEL);
>>>>> + else
>>>>> + str = kasprintf(GFP_KERNEL, "%s-gt%u",
>>>>> + events[i].name, j);
>>>>> + if (!str)
>>>>> + goto err;
>>>>> +
>>>>> + *attr_iter++ = &xe_iter->attr.attr;
>>>>> + xe_iter = add_xe_attr(xe_iter, str, config);
>>>>> +
>>>>> + if (events[i].unit) {
>>>>> + if (events[i].global)
>>>>> + str = kasprintf(GFP_KERNEL, "%s.unit",
>>>>> + events[i].name);
>>>>> + else
>>>>> + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
>>>>> + events[i].name, j);
>>>>> + if (!str)
>>>>> + goto err;
>>>>> +
>>>>> + *attr_iter++ = &pmu_iter->attr.attr;
>>>>> + pmu_iter = add_pmu_attr(pmu_iter, str,
>>>>> + events[i].unit);
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + pmu->xe_attr = xe_attr;
>>>>> + pmu->pmu_attr = pmu_attr;
>>>>> +
>>>>> + return attr;
>>>>> +
>>>>> +err:
>>>>> + for (attr_iter = attr; *attr_iter; attr_iter++)
>>>>> + kfree((*attr_iter)->name);
>>>>> +
>>>>> +err_alloc:
>>>>> + kfree(attr);
>>>>> + kfree(xe_attr);
>>>>> + kfree(pmu_attr);
>>>>> +
>>>>> + return NULL;
>>>>> +}
>>>>> +
>>>>> +static void free_event_attributes(struct xe_pmu *pmu) {
>>>>> + struct attribute **attr_iter = pmu->events_attr_group.attrs;
>>>>> +
>>>>> + for (; *attr_iter; attr_iter++)
>>>>> + kfree((*attr_iter)->name);
>>>>> +
>>>>> + kfree(pmu->events_attr_group.attrs);
>>>>> + kfree(pmu->xe_attr);
>>>>> + kfree(pmu->pmu_attr);
>>>>> +
>>>>> + pmu->events_attr_group.attrs = NULL;
>>>>> + pmu->xe_attr = NULL;
>>>>> + pmu->pmu_attr = NULL;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_cpu_online(unsigned int cpu, struct hlist_node
>>>>> +*node) {
>>>>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
>>>>> +cpuhp.node);
>>>>> +
>>>>> + XE_BUG_ON(!pmu->base.event_init);
>>>>> +
>>>>> + /* Select the first online CPU as a designated reader. */
>>>>> + if (cpumask_empty(&xe_pmu_cpumask))
>>>>> + cpumask_set_cpu(cpu, &xe_pmu_cpumask);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_cpu_offline(unsigned int cpu, struct hlist_node
>>>>> +*node) {
>>>>> + struct xe_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
>>>>> + unsigned int target = xe_pmu_target_cpu;
>>>>> +
>>>>> + XE_BUG_ON(!pmu->base.event_init);
>>>>> +
>>>>> + /*
>>>>> + * Unregistering an instance generates a CPU offline event which we must
>>>>> + * ignore to avoid incorrectly modifying the shared xe_pmu_cpumask.
>>>>> + */
>>>>> + if (pmu->closed)
>>>>> + return 0;
>>>>> +
>>>>> + if (cpumask_test_and_clear_cpu(cpu, &xe_pmu_cpumask)) {
>>>>> + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
>>>>> +
>>>>> + /* Migrate events if there is a valid target */
>>>>> + if (target < nr_cpu_ids) {
>>>>> + cpumask_set_cpu(target, &xe_pmu_cpumask);
>>>>> + xe_pmu_target_cpu = target;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
>>>>> + perf_pmu_migrate_context(&pmu->base, cpu, target);
>>>>> + pmu->cpuhp.cpu = target;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
>>>>> +
>>>>> +int xe_pmu_init(void)
>>>>> +{
>>>>> + int ret;
>>>>> +
>>>>> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>>>>> + "perf/x86/intel/xe:online",
>>>>> + xe_pmu_cpu_online,
>>>>> + xe_pmu_cpu_offline);
>>>>> + if (ret < 0)
>>>>> + pr_notice("Failed to setup cpuhp state for xe PMU! (%d)\n",
>>>>> + ret);
>>>>> + else
>>>>> + cpuhp_slot = ret;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +void xe_pmu_exit(void)
>>>>> +{
>>>>> + if (cpuhp_slot != CPUHP_INVALID)
>>>>> + cpuhp_remove_multi_state(cpuhp_slot);
>>>>> +}
>>>>> +
>>>>> +static int xe_pmu_register_cpuhp_state(struct xe_pmu *pmu) {
>>>>> + if (cpuhp_slot == CPUHP_INVALID)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node); }
>>>>> +
>>>>> +static void xe_pmu_unregister_cpuhp_state(struct xe_pmu *pmu) {
>>>>> + cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node); }
>>>>> +
>>>>> +static void xe_pmu_unregister(struct drm_device *device, void
>>>>> +*arg) {
>>>>> + struct xe_pmu *pmu = arg;
>>>>> +
>>>>> + if (!pmu->base.event_init)
>>>>> + return;
>>>>> +
>>>>> + /*
>>>>> + * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
>>>>> + * ensures all currently executing ones will have exited before we
>>>>> + * proceed with unregistration.
>>>>> + */
>>>>> + pmu->closed = true;
>>>>> + synchronize_rcu();
>>>>> +
>>>>> + xe_pmu_unregister_cpuhp_state(pmu);
>>>>> +
>>>>> + perf_pmu_unregister(&pmu->base);
>>>>> + pmu->base.event_init = NULL;
>>>>> + kfree(pmu->base.attr_groups);
>>>>> + kfree(pmu->name);
>>>>> + free_event_attributes(pmu);
>>>>> +}
>>>>> +
>>>>> +static void init_samples(struct xe_pmu *pmu) {
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + struct xe_gt *gt;
>>>>> + unsigned int i;
>>>>> +
>>>>> + for_each_gt(gt, xe, i)
>>>>> + engine_group_busyness_store(gt); }
>>>>> +
>>>>> +void xe_pmu_register(struct xe_pmu *pmu)
>>>>
>>>> Why void, why not int? PMU failure is non fatal error?
>>>
>>> Ya device is functional , it is only that these counters are not
>>> available. Hence didn't want to fail the driver load.
>>>>
>>>>> +{
>>>>> + struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
>>>>> + const struct attribute_group *attr_groups[] = {
>>>>> + &xe_pmu_format_attr_group,
>>>>> + &pmu->events_attr_group,
>>>>> + &xe_pmu_cpumask_attr_group,
>>>>
>>>> Can someone please explain what this cpumask/cpuhotplug stuff does
>>>> and whether it needs to be in this patch? There's something here:
>>>
>>> comments from original patch series in
>>> i915:https://patchwork.kernel.org/project/intel-gfx/patch/2017080212
>>> 3249.14194-5-tvrtko.ursulin@linux.intel.com/
>>>
>>> "IIRC an uncore PMU should expose a cpumask through sysfs, and then
>>> perf tools will read that mask and auto-magically limit the number
>>> of CPUs it instantiates the counter on."
>>>
>>> and ours are global counters not per cpu so we limit to just to single cpu.
>>>
>>> And as i understand we use the cpuhotplug support to migrate too new
>>> cpu incase the earlier one goes offline.
>>
>> OK, leave as is.
>>
>>>
>>>>
>>>> b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf
>>>> queries")
>>>>
>>>> I'd rather just have the basic PMU infra and the events in this
>>>> patch and punt this cpumask/cpuhotplug stuff to a later patch,
>>>> unless someone can say what it does.
>>>>
>>>> Though perf_pmu_register seems to be doing some per cpu stuff so
>>>> likely this is needed. But amdgpu_pmu only has event and format attributes.
>>>>
>>>> Mostly leave as is I guess.
>>>>
>>>>> + NULL
>>>>> + };
>>>>> +
>>>>> + int ret = -ENOMEM;
>>>>> +
>>>>> + spin_lock_init(&pmu->lock);
>>>>> + pmu->cpuhp.cpu = -1;
>>>>> + init_samples(pmu);
>>>>
>>>> Why init_samples here? Can't we init the particular sample in
>>>> xe_pmu_event_init or even xe_pmu_event_start?
>>>>
>>>> Init'ing here may be too soon since the event might not be enabled
>>>> for a long time. So really this needs to move to xe_pmu_event_init
>>>> or xe_pmu_event_start.
>>>
>>> The device is put to suspend immediately after driver probe,
>>> typically pmu is opened even before any workload is run so
>>> essentially device is still in suspend state hence we cannot access
>>> registers so storing the last known value in init_samples. otherwise we see the bug in v#1 of series.
>>>
>>>>
>>>> Actually this is already happening in xe_pmu_enable. We just need
>>>> to decide when we want to wake the device up and when we don't. So
>>>> maybe wake the device up at start (use xe_device_mem_access_get)
>>>> and not wake up during read (xe_device_mem_access_get_if_ongoing etc.)?
>>
>> Just going to repeat this again:
>>
>> xe_pmu_event_start calls xe_pmu_enable. In xe_pmu_enable use
>> xe_device_mem_access_get before calling __xe_pmu_event_read. This
>> will wake the device up and get a valid value in event->hw.prev_count.
>>
>> In xe_pmu_event_read, use xe_device_mem_access_get_if_ongoing, to
>> read the event without waking the device up (and return previous value etc.).
>>
>> Or, pass a flag in to __xe_pmu_event_read and to
>> engine_group_busyness_read and __engine_group_busyness_read. The flag
>> will say whether or not to wake up the device. If the flag says wake
>> the device up, call xe_device_mem_access_get and xe_force_wake_get,
>> maybe in __engine_group_busyness_read, before reading device
>> registers. If the flag says don't wake up the device call xe_device_mem_access_get_if_ongoing.
>>
>> This way we:
>> * don't need to call init_samples in xe_pmu_register
>> * we don't need engine_group_busyness_store
>> * we don't need to specifically call engine_group_busyness_store in
>> xe_gt_suspend
>>
>> The correct sample is read by waking up the device in xe_pmu_event_start.
>>
>> Hopefully this is clear now.
>
> Actually I think it is not necessary to do anything in
> xe_pmu_event_start, as long as we keep the engine_group_busyness_store
> in xe_gt_suspend (so we can just use
> xe_device_mem_access_get_if_ongoing, don't need xe_device_mem_access_get as you said).
>
> Afais, the problem of huge values in v1 was due to reading the device
> registers when device was not awake. That problem we've already solved
> in
> v2 where in engine_group_busyness_read() we only read if the device is
> awake and skip and return the previous value when the device is not
> awake. So that fixes the problem of huge values.
>
> The problem in this patch (I thought) is that we are effectively
> sampling the registers each time perf calls xe_pmu_event_read, say
> every 1 sec. So we are sampling the registers every 1 sec. When we
> sample (every 1 sec) if the device is awake we will return the correct
> ns value, if device is asleep we will return the old value. If the
> device wakes up and does some work in the 1 sec period but then again
> suspends will miss that activity. That is the problem that is being
> solved by storing the samples in xe_gt_suspend().
>
> i915 solved this problem using a 5 ms timer but I like the solution of
> sampling in xe_gt_suspend better, so let's keep it.
>
> But init_samples is not needed, afais we don't need to do anything in
> xe_pmu_register or in xe_pmu_event_start (and we don't need to use
> xe_device_mem_access_get). xe_gt_suspend will take care of storing the
> register values before the device suspends.
>
> Hopefully it makes sense now, sorry for the confusion.
yes you are right we do not need init_samples.
Thanks,
Aravind.
>
> Ashutosh
>
>>
>>>
>>>>
>>>>> +
>>>>> + pmu->name = kasprintf(GFP_KERNEL,
>>>>> + "xe_%s",
>>>>> + dev_name(xe->drm.dev));
>>>>> + if (pmu->name)
>>>>> + /* tools/perf reserves colons as special. */
>>>>> + strreplace((char *)pmu->name, ':', '_');
>>>>> +
>>>>> + if (!pmu->name)
>>>>> + goto err;
>>>>> +
>>>>> + pmu->events_attr_group.name = "events";
>>>>> + pmu->events_attr_group.attrs = create_event_attributes(pmu);
>>>>> + if (!pmu->events_attr_group.attrs)
>>>>> + goto err_name;
>>>>> +
>>>>> + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
>>>>> + GFP_KERNEL);
>>>>> + if (!pmu->base.attr_groups)
>>>>> + goto err_attr;
>>>>> +
>>>>> + pmu->base.module = THIS_MODULE;
>>>>> + pmu->base.task_ctx_nr = perf_invalid_context;
>>>>> + pmu->base.event_init = xe_pmu_event_init;
>>>>> + pmu->base.add = xe_pmu_event_add;
>>>>> + pmu->base.del = xe_pmu_event_del;
>>>>> + pmu->base.start = xe_pmu_event_start;
>>>>> + pmu->base.stop = xe_pmu_event_stop;
>>>>> + pmu->base.read = xe_pmu_event_read;
>>>>> + pmu->base.event_idx = xe_pmu_event_event_idx;
>>>>> +
>>>>> + ret = perf_pmu_register(&pmu->base, pmu->name, -1);
>>>>> + if (ret)
>>>>> + goto err_groups;
>>>>> +
>>>>> + ret = xe_pmu_register_cpuhp_state(pmu);
>>>>> + if (ret)
>>>>> + goto err_unreg;
>>>>> +
>>>>> + ret = drmm_add_action_or_reset(&xe->drm, xe_pmu_unregister, pmu);
>>>>> + XE_WARN_ON(ret);
>>>>
>>>> We should just follow the regular error rewind here too and let
>>>> drm_notice() at the end print the error. This is what other drivers
>>>> calling drmm_add_action_or_reset seem to be doing.
>>>
>>> Ok ok.
>>>>
>>>>> +
>>>>> + return;
>>>>> +
>>>>> +err_unreg:
>>>>> + perf_pmu_unregister(&pmu->base);
>>>>> +err_groups:
>>>>> + kfree(pmu->base.attr_groups);
>>>>> +err_attr:
>>>>> + pmu->base.event_init = NULL;
>>>>> + free_event_attributes(pmu);
>>>>> +err_name:
>>>>> + kfree(pmu->name);
>>>>> +err:
>>>>> + drm_notice(&xe->drm, "Failed to register PMU!\n"); }
>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu.h
>>>>> b/drivers/gpu/drm/xe/xe_pmu.h new file mode 100644 index
>>>>> 000000000000..d3f47f4ab343
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu.h
>>>>> @@ -0,0 +1,25 @@
>>>>> +/* SPDX-License-Identifier: MIT */
>>>>> +/*
>>>>> + * Copyright © 2023 Intel Corporation */
>>>>> +
>>>>> +#ifndef _XE_PMU_H_
>>>>> +#define _XE_PMU_H_
>>>>> +
>>>>> +#include "xe_gt_types.h"
>>>>> +#include "xe_pmu_types.h"
>>>>> +
>>>>> +#ifdef CONFIG_PERF_EVENTS
>>>>
>>>> nit but maybe this should be:
>>>>
>>>> #if IS_ENABLED(CONFIG_PERF_EVENTS)
>>>>
>>>> or,
>>>>
>>>> #if IS_BUILTIN(CONFIG_PERF_EVENTS)
>>>>
>>>> Note CONFIG_PERF_EVENTS is a boolean kconfig option.
>>>>
>>>> See similar macro IS_REACHABLE() in i915_hwmon.h.
>>>>
>>>>> +int xe_pmu_init(void);
>>>>> +void xe_pmu_exit(void);
>>>>> +void xe_pmu_register(struct xe_pmu *pmu); void
>>>>> +engine_group_busyness_store(struct xe_gt *gt);
>>>>
>>>> Add xe_pmu_ prefix if function is needed (hopefully not).
>>>
>>> OK
>>>>
>>>>> +#else
>>>>> +static inline int xe_pmu_init(void) { return 0; } static inline
>>>>> +void xe_pmu_exit(void) {} static inline void
>>>>> +xe_pmu_register(struct xe_pmu *pmu) {} static inline void
>>>>> +engine_group_busyness_store(struct xe_gt *gt) {} #endif
>>>>> +
>>>>> +#endif
>>>>> +
>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h
>>>>> b/drivers/gpu/drm/xe/xe_pmu_types.h
>>>>> new file mode 100644
>>>>> index 000000000000..e87edd4d6a87
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu_types.h
>>>>> @@ -0,0 +1,80 @@
>>>>> +/* SPDX-License-Identifier: MIT */
>>>>> +/*
>>>>> + * Copyright © 2023 Intel Corporation */
>>>>> +
>>>>> +#ifndef _XE_PMU_TYPES_H_
>>>>> +#define _XE_PMU_TYPES_H_
>>>>> +
>>>>> +#include <linux/perf_event.h>
>>>>> +#include <linux/spinlock_types.h> #include <uapi/drm/xe_drm.h>
>>>>> +
>>>>> +enum {
>>>>> + __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __XE_NUM_PMU_SAMPLERS
>>>>
>>>> OK: irq_count is missing here since these are read from device...
>>>>
>>>>> +};
>>>>> +
>>>>> +struct xe_pmu_sample {
>>>>> + u64 cur;
>>>>> +};
>>>>
>>>> This was also discussed for i915 PMU, no point having a struct with
>>>> a single u64 member. Might as well just use u64 wherever we are
>>>> using struct xe_pmu_sample.
>>>
>>> OK.
>>>>
>>>>> +
>>>>> +#define XE_MAX_GT_PER_TILE 2
>>>>
>>>> Why per tile? The array size should be max_gt_per_device. Just call
>>>> it XE_MAX_GT?
>>>
>>> I declared similar to what we have in drivers/gpu/drm/xe/xe_device.h
>>
>> Our 2-d array size is for the device, not per tile. So let's use XE_MAX_GT.
>>
>>>>
>>>>> +
>>>>> +struct xe_pmu {
>>>>> + /**
>>>>> + * @cpuhp: Struct used for CPU hotplug handling.
>>>>> + */
>>>>> + struct {
>>>>> + struct hlist_node node;
>>>>> + unsigned int cpu;
>>>>> + } cpuhp;
>>>>> + /**
>>>>> + * @base: PMU base.
>>>>> + */
>>>>> + struct pmu base;
>>>>> + /**
>>>>> + * @closed: xe is unregistering.
>>>>> + */
>>>>> + bool closed;
>>>>> + /**
>>>>> + * @name: Name as registered with perf core.
>>>>> + */
>>>>> + const char *name;
>>>>> + /**
>>>>> + * @lock: Lock protecting enable mask and ref count handling.
>>>>> + */
>>>>> + spinlock_t lock;
>>>>> + /**
>>>>> + * @sample: Current and previous (raw) counters.
>>>>> + *
>>>>> + * These counters are updated when the device is awake.
>>>>> + *
>>>>> + */
>>>>> + struct xe_pmu_sample sample[XE_MAX_GT_PER_TILE *
>>>>> +__XE_NUM_PMU_SAMPLERS];
>>>>
>>>> Change to 2-d array. See above.
>>>>
>>>>> + /**
>>>>> + * @irq_count: Number of interrupts
>>>>> + *
>>>>> + * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
>>>>> + * 4e9 interrupts are a lot and postprocessing can really deal with an
>>>>> + * occasional wraparound easily. It's 32bit after all.
>>>>> + */
>>>>> + unsigned long irq_count;
>>>>> + /**
>>>>> + * @events_attr_group: Device events attribute group.
>>>>> + */
>>>>> + struct attribute_group events_attr_group;
>>>>> + /**
>>>>> + * @xe_attr: Memory block holding device attributes.
>>>>> + */
>>>>> + void *xe_attr;
>>>>> + /**
>>>>> + * @pmu_attr: Memory block holding device attributes.
>>>>> + */
>>>>> + void *pmu_attr;
>>>>> +};
>>>>> +
>>>>> +#endif
>>>>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>>>>> index 965cd9527ff1..ed097056f944 100644
>>>>> --- a/include/uapi/drm/xe_drm.h
>>>>> +++ b/include/uapi/drm/xe_drm.h
>>>>> @@ -990,6 +990,22 @@ struct drm_xe_vm_madvise {
>>>>> __u64 reserved[2];
>>>>> };
>>>>>
>>>>> +/* PMU event config IDs */
>>>>> +
>>>>> +/*
>>>>> + * Top 4 bits of every counter are GT id.
>>>>> + */
>>>>> +#define __XE_PMU_GT_SHIFT (60)
>>>>
>>>> To future-proof this, and also because we seem to have plenty of
>>>> bits available, I think we should change this to 56 (instead of 60).
>>>
>>> OK
>>>
>>> Thanks,
>>> Aravind.
>>>>
>>>>> +
>>>>> +#define ___XE_PMU_OTHER(gt, x) \
>>>>> + (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
>>>>> +
>>>>> +#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
>>>>> +#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
>>>>> +#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
>>>>> +#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
>>>>> +#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
>>>>> +
>>>>> #if defined(__cplusplus)
>>>>> }
>>>>> #endif
>>>>> --
>>>>> 2.25.1
>>
>> Thanks.
>> --
>> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 9:00 ` Ursulin, Tvrtko
@ 2023-07-24 15:52 ` Dixit, Ashutosh
0 siblings, 0 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-24 15:52 UTC (permalink / raw)
To: Ursulin, Tvrtko; +Cc: Bommu, Krishnaiah, intel-xe@lists.freedesktop.org
On Mon, 24 Jul 2023 02:00:13 -0700, Ursulin, Tvrtko wrote:
>
>
> [Top-post since my dual email setup and this is the wrong one, sorry.]
>
> Glancing over the discussion - small correction - i915 did not solve the
> problem of hardware counters and sleeping device with the timer but with
> the park/unpark hooks.
>
> More similar to these group busyness counters would be the RC6, and you
> will notice there is nothing in the i915 sampling timer about RC6. There
> is just some complicated code in park/unpark to estimate RC6 while
> parked. But the estimation is beside the point for engine group busyness
> since it is the opposite metric (grows on busy vs grows idle).
>
> And I think you converged to the same solution already, so I just wanted
> to correct the 5ms timer inaccuracy.
Agreed. For a moment I was fantasizing that the timer would not be needed
in i915 either and we could just sample the values when parking, but that's
not true.
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 8:03 ` Iddamsetty, Aravind
2023-07-24 9:00 ` Ursulin, Tvrtko
@ 2023-07-24 15:52 ` Dixit, Ashutosh
2023-07-24 16:05 ` Iddamsetty, Aravind
1 sibling, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-24 15:52 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Mon, 24 Jul 2023 01:03:23 -0700, Iddamsetty, Aravind wrote:
Hi Aravind,
> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>> > On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>> +{
> >>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >>>>> + unsigned int gt_id = gt->info.id;
> >>>>> + unsigned long flags;
> >>>>> +
> >>>>> + spin_lock_irqsave(&pmu->lock, flags);
> >>>>> +
> >>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >
> > Here why should we store everything, we should store only those events
> > which are enabled?
>
> The events are enabled only when they are opened which can happen after
> the device is suspended hence we need to store all. As in the present
> case device is put to suspend immediately after probe and event is
> opened post driver load is done.
I don't think we can justify doing expensive PCIe reads and increasing the
time to go into runtime suspend, when PMU might not being used at all.
If we store only enabled samples and start storing them only after they are
enabled, what would be the consequence of this? The first non-zero sample
seen by the perf tool would be wrong and later samples will be fine?
If there is a consequence, we might have to go back to what I was saying
earlier about waking the device up and reading the enabled counter when
xe_pmu_event_start happens, to initialize the counter values. I am assuming
this will work?
Doing this IMO would be better than always doing these PCIe reads on
runtime suspend even when PMU is not being used.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 15:52 ` Dixit, Ashutosh
@ 2023-07-24 16:05 ` Iddamsetty, Aravind
2023-07-24 16:31 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-24 16:05 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 24-07-2023 21:22, Dixit, Ashutosh wrote:
Hi Ashutosh,
> On Mon, 24 Jul 2023 01:03:23 -0700, Iddamsetty, Aravind wrote:
>
> Hi Aravind,
>
>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>>>> +{
>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>>>> + unsigned int gt_id = gt->info.id;
>>>>>>> + unsigned long flags;
>>>>>>> +
>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>>>> +
>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>>>
>>> Here why should we store everything, we should store only those events
>>> which are enabled?
>>
>> The events are enabled only when they are opened which can happen after
>> the device is suspended hence we need to store all. As in the present
>> case device is put to suspend immediately after probe and event is
>> opened post driver load is done.
>
> I don't think we can justify doing expensive PCIe reads and increasing the
> time to go into runtime suspend, when PMU might not being used at all.
>
> If we store only enabled samples and start storing them only after they are
> enabled, what would be the consequence of this? The first non-zero sample
> seen by the perf tool would be wrong and later samples will be fine?
Why do you say it is wrong perf reports relative from the time an event
is opened.
>
> If there is a consequence, we might have to go back to what I was saying
> earlier about waking the device up and reading the enabled counter when
> xe_pmu_event_start happens, to initialize the counter values. I am assuming
> this will work?
xe_pmu_event_start can be called when device is in suspend so we shall
not wake up the device i.e event being enabled when in suspend, so if we
do not store while going to suspend we will not have any value to
consider when event is enabled after suspend as we need to present
relative value.
>
> Doing this IMO would be better than always doing these PCIe reads on
> runtime suspend even when PMU is not being used
we have been doing these in i915 not sure if it affected any timing
requirements for runtime suspend.
Thanks,
Aravind.
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 16:05 ` Iddamsetty, Aravind
@ 2023-07-24 16:31 ` Dixit, Ashutosh
2023-07-25 11:38 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-24 16:31 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
>
> On 24-07-2023 21:22, Dixit, Ashutosh wrote:
> Hi Ashutosh,
>
> > On Mon, 24 Jul 2023 01:03:23 -0700, Iddamsetty, Aravind wrote:
> >
> > Hi Aravind,
> >
> >> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> >>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>>>> +{
> >>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >>>>>>> + unsigned int gt_id = gt->info.id;
> >>>>>>> + unsigned long flags;
> >>>>>>> +
> >>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
> >>>>>>> +
> >>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >>>
> >>> Here why should we store everything, we should store only those events
> >>> which are enabled?
> >>
> >> The events are enabled only when they are opened which can happen after
> >> the device is suspended hence we need to store all. As in the present
> >> case device is put to suspend immediately after probe and event is
> >> opened post driver load is done.
> >
> > I don't think we can justify doing expensive PCIe reads and increasing the
> > time to go into runtime suspend, when PMU might not being used at all.
> >
> > If we store only enabled samples and start storing them only after they are
> > enabled, what would be the consequence of this? The first non-zero sample
> > seen by the perf tool would be wrong and later samples will be fine?
>
> Why do you say it is wrong perf reports relative from the time an event
> is opened.
I am asking you what is the consequence. Initial values will all be zero
and then there is some activity and we get a non zero value but this will
include all the previous activity so the first difference we send to perf
will be large/wrong I think.
>
> >
> > If there is a consequence, we might have to go back to what I was saying
> > earlier about waking the device up and reading the enabled counter when
> > xe_pmu_event_start happens, to initialize the counter values. I am assuming
> > this will work?
>
> xe_pmu_event_start can be called when device is in suspend so we shall
> not wake up the device i.e event being enabled when in suspend, so if we
> do not store while going to suspend we will not have any value to
> consider when event is enabled after suspend as we need to present
> relative value.
That is why I am saying wake up the device and initialize the counters in
xe_pmu_event_start.
> >
> > Doing this IMO would be better than always doing these PCIe reads on
> > runtime suspend even when PMU is not being used
>
> we have been doing these in i915 not sure if it affected any timing
> requirements for runtime suspend.
Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
when RC6 event is not enabled or PMU might not be used.
@Tvrtko, any comments here?
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-24 16:31 ` Dixit, Ashutosh
@ 2023-07-25 11:38 ` Iddamsetty, Aravind
2023-08-07 21:16 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-25 11:38 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 24-07-2023 22:01, Dixit, Ashutosh wrote:
> On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
>>
>> On 24-07-2023 21:22, Dixit, Ashutosh wrote:
>> Hi Ashutosh,
>>
>>> On Mon, 24 Jul 2023 01:03:23 -0700, Iddamsetty, Aravind wrote:
>>>
>>> Hi Aravind,
>>>
>>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>>>>>> +{
>>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>>>>>> + unsigned int gt_id = gt->info.id;
>>>>>>>>> + unsigned long flags;
>>>>>>>>> +
>>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>>>>>> +
>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>>>>>
>>>>> Here why should we store everything, we should store only those events
>>>>> which are enabled?
>>>>
>>>> The events are enabled only when they are opened which can happen after
>>>> the device is suspended hence we need to store all. As in the present
>>>> case device is put to suspend immediately after probe and event is
>>>> opened post driver load is done.
>>>
>>> I don't think we can justify doing expensive PCIe reads and increasing the
>>> time to go into runtime suspend, when PMU might not being used at all.
>>>
>>> If we store only enabled samples and start storing them only after they are
>>> enabled, what would be the consequence of this? The first non-zero sample
>>> seen by the perf tool would be wrong and later samples will be fine?
>>
>> Why do you say it is wrong perf reports relative from the time an event
>> is opened.
>
> I am asking you what is the consequence. Initial values will all be zero
> and then there is some activity and we get a non zero value but this will
> include all the previous activity so the first difference we send to perf
> will be large/wrong I think.
correct if we just store the enabled events in suspend, any other event
will have 0 initial value and when we read the register later it will
have all the accumulation and since past value we have is 0 we would end
up reporting the entire value which is wrong.
>
>>
>>>
>>> If there is a consequence, we might have to go back to what I was saying
>>> earlier about waking the device up and reading the enabled counter when
>>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
>>> this will work?
>>
>> xe_pmu_event_start can be called when device is in suspend so we shall
>> not wake up the device i.e event being enabled when in suspend, so if we
>> do not store while going to suspend we will not have any value to
>> consider when event is enabled after suspend as we need to present
>> relative value.
>
> That is why I am saying wake up the device and initialize the counters in
> xe_pmu_event_start.
Afaik since PMU doesn't take DRM reference we shall not wake up the
device. if we were allowed to wake up the device why do we even need to
store during suspend. when ever PMU event is opened we could wake up the
device and read the register directly.
Thanks,
Aravind.
>
>>>
>>> Doing this IMO would be better than always doing these PCIe reads on
>>> runtime suspend even when PMU is not being used
>>
>> we have been doing these in i915 not sure if it affected any timing
>> requirements for runtime suspend.
>
> Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
> when RC6 event is not enabled or PMU might not be used.
>
> @Tvrtko, any comments here?
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-25 11:38 ` Iddamsetty, Aravind
@ 2023-08-07 21:16 ` Dixit, Ashutosh
2023-08-07 22:22 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-08-07 21:16 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> On 24-07-2023 22:01, Dixit, Ashutosh wrote:
> > On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
> >>
> >>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> >>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>>>>>> +{
> >>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >>>>>>>>> + unsigned int gt_id = gt->info.id;
> >>>>>>>>> + unsigned long flags;
> >>>>>>>>> +
> >>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
> >>>>>>>>> +
> >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >>>>>
> >>>>> Here why should we store everything, we should store only those events
> >>>>> which are enabled?
> >>>>
> >>>> The events are enabled only when they are opened which can happen after
> >>>> the device is suspended hence we need to store all. As in the present
> >>>> case device is put to suspend immediately after probe and event is
> >>>> opened post driver load is done.
> >>>
> >>> I don't think we can justify doing expensive PCIe reads and increasing the
> >>> time to go into runtime suspend, when PMU might not being used at all.
> >>>
> >>> If we store only enabled samples and start storing them only after they are
> >>> enabled, what would be the consequence of this? The first non-zero sample
> >>> seen by the perf tool would be wrong and later samples will be fine?
> >>
> >> Why do you say it is wrong perf reports relative from the time an event
> >> is opened.
> >
> > I am asking you what is the consequence. Initial values will all be zero
> > and then there is some activity and we get a non zero value but this will
> > include all the previous activity so the first difference we send to perf
> > will be large/wrong I think.
>
> correct if we just store the enabled events in suspend, any other event
> will have 0 initial value and when we read the register later it will
> have all the accumulation and since past value we have is 0 we would end
> up reporting the entire value which is wrong.
Ok, agreed, so we need to do "something".
>
> >
> >>
> >>>
> >>> If there is a consequence, we might have to go back to what I was saying
> >>> earlier about waking the device up and reading the enabled counter when
> >>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
> >>> this will work?
> >>
> >> xe_pmu_event_start can be called when device is in suspend so we shall
> >> not wake up the device i.e event being enabled when in suspend, so if we
> >> do not store while going to suspend we will not have any value to
> >> consider when event is enabled after suspend as we need to present
> >> relative value.
> >
> > That is why I am saying wake up the device and initialize the counters in
> > xe_pmu_event_start.
>
> Afaik since PMU doesn't take DRM reference we shall not wake up the
> device.
Not sure what you mean because PMU does do this:
drm_dev_get(&xe->drm);
Anyway I don't think it has anything to do with waking up the device since
that is done via xe_device_mem_access_get.
> if we were allowed to wake up the device why do we even need to
> store during suspend. when ever PMU event is opened we could wake up the
> device and read the register directly.
No. That is why we are saving the counters during suspend so we don't have
to wake up the device just to read the counters. So the issue is only how
to *initialize* the counters.
You are saying we initialize by saving all counters during suspend, whether
or not they are enabled, which I don't agree with. I am saying we should
only read and store the counters which are enabled during normal
operation. And to initialize we wake the device up during
xe_pmu_event_start and store the counter value. Alternatively, we can zero
out the enabled counters during xe_pmu_event_start (the counters are RW)
but in any case that will also need waking up the device.
So this way we only wake up the device for initialization but not
afterwards.
Since this is the "base" patch we should try to set up a good
infrastructure in this patch so that other stuff which is exposed via PMU
can be easily added later.
> >>>
> >>> Doing this IMO would be better than always doing these PCIe reads on
> >>> runtime suspend even when PMU is not being used
> >>
> >> we have been doing these in i915 not sure if it affected any timing
> >> requirements for runtime suspend.
> >
> > Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
> > when RC6 event is not enabled or PMU might not be used.
> >
> > @Tvrtko, any comments here?
> >
> > Thanks.
> > --
> > Ashutosh
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-08-07 21:16 ` Dixit, Ashutosh
@ 2023-08-07 22:22 ` Dixit, Ashutosh
2023-08-08 13:45 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-08-07 22:22 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Mon, 07 Aug 2023 14:16:59 -0700, Dixit, Ashutosh wrote:
>
Hi Aravind,
> On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
> > On 24-07-2023 22:01, Dixit, Ashutosh wrote:
> > > On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
> > >>
> > >>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> > >>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> > >>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> > >>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> > >>>>>>>>> +{
> > >>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> > >>>>>>>>> + unsigned int gt_id = gt->info.id;
> > >>>>>>>>> + unsigned long flags;
> > >>>>>>>>> +
> > >>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
> > >>>>>>>>> +
> > >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> > >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> > >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> > >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> > >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> > >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> > >>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> > >>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> > >>>>>
> > >>>>> Here why should we store everything, we should store only those events
> > >>>>> which are enabled?
> > >>>>
> > >>>> The events are enabled only when they are opened which can happen after
> > >>>> the device is suspended hence we need to store all. As in the present
> > >>>> case device is put to suspend immediately after probe and event is
> > >>>> opened post driver load is done.
> > >>>
> > >>> I don't think we can justify doing expensive PCIe reads and increasing the
> > >>> time to go into runtime suspend, when PMU might not being used at all.
> > >>>
> > >>> If we store only enabled samples and start storing them only after they are
> > >>> enabled, what would be the consequence of this? The first non-zero sample
> > >>> seen by the perf tool would be wrong and later samples will be fine?
> > >>
> > >> Why do you say it is wrong perf reports relative from the time an event
> > >> is opened.
> > >
> > > I am asking you what is the consequence. Initial values will all be zero
> > > and then there is some activity and we get a non zero value but this will
> > > include all the previous activity so the first difference we send to perf
> > > will be large/wrong I think.
> >
> > correct if we just store the enabled events in suspend, any other event
> > will have 0 initial value and when we read the register later it will
> > have all the accumulation and since past value we have is 0 we would end
> > up reporting the entire value which is wrong.
>
> Ok, agreed, so we need to do "something".
>
> >
> > >
> > >>
> > >>>
> > >>> If there is a consequence, we might have to go back to what I was saying
> > >>> earlier about waking the device up and reading the enabled counter when
> > >>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
> > >>> this will work?
> > >>
> > >> xe_pmu_event_start can be called when device is in suspend so we shall
> > >> not wake up the device i.e event being enabled when in suspend, so if we
> > >> do not store while going to suspend we will not have any value to
> > >> consider when event is enabled after suspend as we need to present
> > >> relative value.
> > >
> > > That is why I am saying wake up the device and initialize the counters in
> > > xe_pmu_event_start.
> >
> > Afaik since PMU doesn't take DRM reference we shall not wake up the
> > device.
>
> Not sure what you mean because PMU does do this:
>
> drm_dev_get(&xe->drm);
>
> Anyway I don't think it has anything to do with waking up the device since
> that is done via xe_device_mem_access_get.
>
> > if we were allowed to wake up the device why do we even need to
> > store during suspend. when ever PMU event is opened we could wake up the
> > device and read the register directly.
>
> No. That is why we are saving the counters during suspend so we don't have
> to wake up the device just to read the counters. So the issue is only how
> to *initialize* the counters.
>
> You are saying we initialize by saving all counters during suspend, whether
> or not they are enabled, which I don't agree with. I am saying we should
> only read and store the counters which are enabled during normal
> operation. And to initialize we wake the device up during
> xe_pmu_event_start and store the counter value. Alternatively, we can zero
> out the enabled counters during xe_pmu_event_start (the counters are RW)
> but in any case that will also need waking up the device.
>
> So this way we only wake up the device for initialization but not
> afterwards.
>
> Since this is the "base" patch we should try to set up a good
> infrastructure in this patch so that other stuff which is exposed via PMU
> can be easily added later.
After thinking a bit more about this, though I think this needs to be done,
I won't insist that we do this in this patch, we can review and do this in
a subsequent patch (if no one else objects).
So let's skip this for now. So if you can generate a new version of the
patch after addressing all of the other review comments, we can review that
again and try to get it merged.
Thanks.
--
Ashutosh
> > >>>
> > >>> Doing this IMO would be better than always doing these PCIe reads on
> > >>> runtime suspend even when PMU is not being used
> > >>
> > >> we have been doing these in i915 not sure if it affected any timing
> > >> requirements for runtime suspend.
> > >
> > > Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
> > > when RC6 event is not enabled or PMU might not be used.
> > >
> > > @Tvrtko, any comments here?
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-08-07 22:22 ` Dixit, Ashutosh
@ 2023-08-08 13:45 ` Iddamsetty, Aravind
2023-08-08 15:18 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-08-08 13:45 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 08-08-2023 03:52, Dixit, Ashutosh wrote:
> On Mon, 07 Aug 2023 14:16:59 -0700, Dixit, Ashutosh wrote:
>>
>
> Hi Aravind,
Hi Ashutosh,
I have sent a new revision, but commenting here for few comments.
>
>> On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
>>> On 24-07-2023 22:01, Dixit, Ashutosh wrote:
>>>> On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
>>>>>
>>>>>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>>>>>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>>>>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>>>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>>>>>>>>> +{
>>>>>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>>>>>>>>> + unsigned int gt_id = gt->info.id;
>>>>>>>>>>>> + unsigned long flags;
>>>>>>>>>>>> +
>>>>>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>>>>>>>>> +
>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>>>>>>>>
>>>>>>>> Here why should we store everything, we should store only those events
>>>>>>>> which are enabled?
>>>>>>>
>>>>>>> The events are enabled only when they are opened which can happen after
>>>>>>> the device is suspended hence we need to store all. As in the present
>>>>>>> case device is put to suspend immediately after probe and event is
>>>>>>> opened post driver load is done.
>>>>>>
>>>>>> I don't think we can justify doing expensive PCIe reads and increasing the
>>>>>> time to go into runtime suspend, when PMU might not being used at all.
>>>>>>
>>>>>> If we store only enabled samples and start storing them only after they are
>>>>>> enabled, what would be the consequence of this? The first non-zero sample
>>>>>> seen by the perf tool would be wrong and later samples will be fine?
>>>>>
>>>>> Why do you say it is wrong perf reports relative from the time an event
>>>>> is opened.
>>>>
>>>> I am asking you what is the consequence. Initial values will all be zero
>>>> and then there is some activity and we get a non zero value but this will
>>>> include all the previous activity so the first difference we send to perf
>>>> will be large/wrong I think.
>>>
>>> correct if we just store the enabled events in suspend, any other event
>>> will have 0 initial value and when we read the register later it will
>>> have all the accumulation and since past value we have is 0 we would end
>>> up reporting the entire value which is wrong.
>>
>> Ok, agreed, so we need to do "something".
>>
>>>
>>>>
>>>>>
>>>>>>
>>>>>> If there is a consequence, we might have to go back to what I was saying
>>>>>> earlier about waking the device up and reading the enabled counter when
>>>>>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
>>>>>> this will work?
>>>>>
>>>>> xe_pmu_event_start can be called when device is in suspend so we shall
>>>>> not wake up the device i.e event being enabled when in suspend, so if we
>>>>> do not store while going to suspend we will not have any value to
>>>>> consider when event is enabled after suspend as we need to present
>>>>> relative value.
>>>>
>>>> That is why I am saying wake up the device and initialize the counters in
>>>> xe_pmu_event_start.
>>>
>>> Afaik since PMU doesn't take DRM reference we shall not wake up the
>>> device.
>>
>> Not sure what you mean because PMU does do this:
>>
>> drm_dev_get(&xe->drm);
sorry it was my misunderstanding here, please ignore.
>>
>> Anyway I don't think it has anything to do with waking up the device since
>> that is done via xe_device_mem_access_get.
>>
>>> if we were allowed to wake up the device why do we even need to
>>> store during suspend. when ever PMU event is opened we could wake up the
>>> device and read the register directly.
>>
>> No. That is why we are saving the counters during suspend so we don't have
>> to wake up the device just to read the counters. So the issue is only how
>> to *initialize* the counters.
>>
>> You are saying we initialize by saving all counters during suspend, whether
>> or not they are enabled, which I don't agree with. I am saying we should
>> only read and store the counters which are enabled during normal
>> operation. And to initialize we wake the device up during
>> xe_pmu_event_start and store the counter value. Alternatively, we can zero
>> out the enabled counters during xe_pmu_event_start (the counters are RW)
>> but in any case that will also need waking up the device.
when the driver is initially loaded there might not be any users of
device and immediately it might enter suspend, so at the time of suspend
there no event enabled, but the pmu can be opened just after suspend
wihtout any actual work on device so device still resides in suspend, so
we should not be waking the device just to read the register in
event_start or any of the callbacks without any real workload or user of
the device.
so ideally if the device didn't enter suspend, the counter is
initialized in the first read when device is still awake.
Thanks,
Aravind.
>>
>> So this way we only wake up the device for initialization but not
>> afterwards.
>>
>> Since this is the "base" patch we should try to set up a good
>> infrastructure in this patch so that other stuff which is exposed via PMU
>> can be easily added later.
>
> After thinking a bit more about this, though I think this needs to be done,
> I won't insist that we do this in this patch, we can review and do this in
> a subsequent patch (if no one else objects).
>
> So let's skip this for now. So if you can generate a new version of the
> patch after addressing all of the other review comments, we can review that
> again and try to get it merged.
>
> Thanks.
> --
> Ashutosh
>
>>>>>>
>>>>>> Doing this IMO would be better than always doing these PCIe reads on
>>>>>> runtime suspend even when PMU is not being used
>>>>>
>>>>> we have been doing these in i915 not sure if it affected any timing
>>>>> requirements for runtime suspend.
>>>>
>>>> Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
>>>> when RC6 event is not enabled or PMU might not be used.
>>>>
>>>> @Tvrtko, any comments here?
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-08-08 13:45 ` Iddamsetty, Aravind
@ 2023-08-08 15:18 ` Dixit, Ashutosh
2023-08-09 4:26 ` Iddamsetty, Aravind
0 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-08-08 15:18 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 08 Aug 2023 06:45:36 -0700, Iddamsetty, Aravind wrote:
>
Hi Aravind,
> On 08-08-2023 03:52, Dixit, Ashutosh wrote:
> > On Mon, 07 Aug 2023 14:16:59 -0700, Dixit, Ashutosh wrote:
> I have sent a new revision, but commenting here for few comments.
> >
> >> On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
> >>> On 24-07-2023 22:01, Dixit, Ashutosh wrote:
> >>>> On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
> >>>>>
> >>>>>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> >>>>>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >>>>>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>>>>>>>>> +{
> >>>>>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >>>>>>>>>>>> + unsigned int gt_id = gt->info.id;
> >>>>>>>>>>>> + unsigned long flags;
> >>>>>>>>>>>> +
> >>>>>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
> >>>>>>>>>>>> +
> >>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >>>>>>>>
> >>>>>>>> Here why should we store everything, we should store only those events
> >>>>>>>> which are enabled?
> >>>>>>>
> >>>>>>> The events are enabled only when they are opened which can happen after
> >>>>>>> the device is suspended hence we need to store all. As in the present
> >>>>>>> case device is put to suspend immediately after probe and event is
> >>>>>>> opened post driver load is done.
> >>>>>>
> >>>>>> I don't think we can justify doing expensive PCIe reads and increasing the
> >>>>>> time to go into runtime suspend, when PMU might not being used at all.
> >>>>>>
> >>>>>> If we store only enabled samples and start storing them only after they are
> >>>>>> enabled, what would be the consequence of this? The first non-zero sample
> >>>>>> seen by the perf tool would be wrong and later samples will be fine?
> >>>>>
> >>>>> Why do you say it is wrong perf reports relative from the time an event
> >>>>> is opened.
> >>>>
> >>>> I am asking you what is the consequence. Initial values will all be zero
> >>>> and then there is some activity and we get a non zero value but this will
> >>>> include all the previous activity so the first difference we send to perf
> >>>> will be large/wrong I think.
> >>>
> >>> correct if we just store the enabled events in suspend, any other event
> >>> will have 0 initial value and when we read the register later it will
> >>> have all the accumulation and since past value we have is 0 we would end
> >>> up reporting the entire value which is wrong.
> >>
> >> Ok, agreed, so we need to do "something".
> >>
> >>>
> >>>>
> >>>>>
> >>>>>>
> >>>>>> If there is a consequence, we might have to go back to what I was saying
> >>>>>> earlier about waking the device up and reading the enabled counter when
> >>>>>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
> >>>>>> this will work?
> >>>>>
> >>>>> xe_pmu_event_start can be called when device is in suspend so we shall
> >>>>> not wake up the device i.e event being enabled when in suspend, so if we
> >>>>> do not store while going to suspend we will not have any value to
> >>>>> consider when event is enabled after suspend as we need to present
> >>>>> relative value.
> >>>>
> >>>> That is why I am saying wake up the device and initialize the counters in
> >>>> xe_pmu_event_start.
> >>>
> >>> Afaik since PMU doesn't take DRM reference we shall not wake up the
> >>> device.
> >>
> >> Not sure what you mean because PMU does do this:
> >>
> >> drm_dev_get(&xe->drm);
>
> sorry it was my misunderstanding here, please ignore.
>
> >>
> >> Anyway I don't think it has anything to do with waking up the device since
> >> that is done via xe_device_mem_access_get.
> >>
> >>> if we were allowed to wake up the device why do we even need to
> >>> store during suspend. when ever PMU event is opened we could wake up the
> >>> device and read the register directly.
> >>
> >> No. That is why we are saving the counters during suspend so we don't have
> >> to wake up the device just to read the counters. So the issue is only how
> >> to *initialize* the counters.
> >>
> >> You are saying we initialize by saving all counters during suspend, whether
> >> or not they are enabled, which I don't agree with. I am saying we should
> >> only read and store the counters which are enabled during normal
> >> operation. And to initialize we wake the device up during
> >> xe_pmu_event_start and store the counter value. Alternatively, we can zero
> >> out the enabled counters during xe_pmu_event_start (the counters are RW)
> >> but in any case that will also need waking up the device.
>
> when the driver is initially loaded there might not be any users of
> device and immediately it might enter suspend, so at the time of suspend
> there no event enabled, but the pmu can be opened just after suspend
> wihtout any actual work on device so device still resides in suspend, so
> we should not be waking the device just to read the register in
> event_start or any of the callbacks without any real workload or user of
> the device.
>
> so ideally if the device didn't enter suspend, the counter is
> initialized in the first read when device is still awake.
Yes, I understand. But the issue is why are we reading (doing expensive
reads across PCIe) and saving all these registers for PMU when it's
possible PMU might not be used at all and none of these events might be
enabled at all?
So to me the lesser evil is to wake up the device at xe_pmu_event_start
time and initialize the counters. We are only waking the device up once at
init time, not during normal operation. Whereas in your case, you are
reading and saving these registers continuously each time we suspend,
whether or not PMU is or will be used.
> >> So this way we only wake up the device for initialization but not
> >> afterwards.
> >>
> >> Since this is the "base" patch we should try to set up a good
> >> infrastructure in this patch so that other stuff which is exposed via PMU
> >> can be easily added later.
> >
> > After thinking a bit more about this, though I think this needs to be done,
> > I won't insist that we do this in this patch, we can review and do this in
> > a subsequent patch (if no one else objects).
> >
> > So let's skip this for now. So if you can generate a new version of the
> > patch after addressing all of the other review comments, we can review that
> > again and try to get it merged.
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >>>>>>
> >>>>>> Doing this IMO would be better than always doing these PCIe reads on
> >>>>>> runtime suspend even when PMU is not being used
> >>>>>
> >>>>> we have been doing these in i915 not sure if it affected any timing
> >>>>> requirements for runtime suspend.
> >>>>
> >>>> Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
> >>>> when RC6 event is not enabled or PMU might not be used.
> >>>>
> >>>> @Tvrtko, any comments here?
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-08-08 15:18 ` Dixit, Ashutosh
@ 2023-08-09 4:26 ` Iddamsetty, Aravind
2023-08-09 5:02 ` Dixit, Ashutosh
0 siblings, 1 reply; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-08-09 4:26 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 08-08-2023 20:48, Dixit, Ashutosh wrote:
Hi Ashutosh,
> On Tue, 08 Aug 2023 06:45:36 -0700, Iddamsetty, Aravind wrote:
>>
>
> Hi Aravind,
>
>> On 08-08-2023 03:52, Dixit, Ashutosh wrote:
>>> On Mon, 07 Aug 2023 14:16:59 -0700, Dixit, Ashutosh wrote:
>> I have sent a new revision, but commenting here for few comments.
>>>
>>>> On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
>>>>> On 24-07-2023 22:01, Dixit, Ashutosh wrote:
>>>>>> On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
>>>>>>>
>>>>>>>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
>>>>>>>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>>>>>>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>>>>>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>>>>>>>>>>> + unsigned int gt_id = gt->info.id;
>>>>>>>>>>>>>> + unsigned long flags;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>>>>>>>>>>
>>>>>>>>>> Here why should we store everything, we should store only those events
>>>>>>>>>> which are enabled?
>>>>>>>>>
>>>>>>>>> The events are enabled only when they are opened which can happen after
>>>>>>>>> the device is suspended hence we need to store all. As in the present
>>>>>>>>> case device is put to suspend immediately after probe and event is
>>>>>>>>> opened post driver load is done.
>>>>>>>>
>>>>>>>> I don't think we can justify doing expensive PCIe reads and increasing the
>>>>>>>> time to go into runtime suspend, when PMU might not being used at all.
>>>>>>>>
>>>>>>>> If we store only enabled samples and start storing them only after they are
>>>>>>>> enabled, what would be the consequence of this? The first non-zero sample
>>>>>>>> seen by the perf tool would be wrong and later samples will be fine?
>>>>>>>
>>>>>>> Why do you say it is wrong perf reports relative from the time an event
>>>>>>> is opened.
>>>>>>
>>>>>> I am asking you what is the consequence. Initial values will all be zero
>>>>>> and then there is some activity and we get a non zero value but this will
>>>>>> include all the previous activity so the first difference we send to perf
>>>>>> will be large/wrong I think.
>>>>>
>>>>> correct if we just store the enabled events in suspend, any other event
>>>>> will have 0 initial value and when we read the register later it will
>>>>> have all the accumulation and since past value we have is 0 we would end
>>>>> up reporting the entire value which is wrong.
>>>>
>>>> Ok, agreed, so we need to do "something".
>>>>
>>>>>
>>>>>>
>>>>>>>
>>>>>>>>
>>>>>>>> If there is a consequence, we might have to go back to what I was saying
>>>>>>>> earlier about waking the device up and reading the enabled counter when
>>>>>>>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
>>>>>>>> this will work?
>>>>>>>
>>>>>>> xe_pmu_event_start can be called when device is in suspend so we shall
>>>>>>> not wake up the device i.e event being enabled when in suspend, so if we
>>>>>>> do not store while going to suspend we will not have any value to
>>>>>>> consider when event is enabled after suspend as we need to present
>>>>>>> relative value.
>>>>>>
>>>>>> That is why I am saying wake up the device and initialize the counters in
>>>>>> xe_pmu_event_start.
>>>>>
>>>>> Afaik since PMU doesn't take DRM reference we shall not wake up the
>>>>> device.
>>>>
>>>> Not sure what you mean because PMU does do this:
>>>>
>>>> drm_dev_get(&xe->drm);
>>
>> sorry it was my misunderstanding here, please ignore.
>>
>>>>
>>>> Anyway I don't think it has anything to do with waking up the device since
>>>> that is done via xe_device_mem_access_get.
>>>>
>>>>> if we were allowed to wake up the device why do we even need to
>>>>> store during suspend. when ever PMU event is opened we could wake up the
>>>>> device and read the register directly.
>>>>
>>>> No. That is why we are saving the counters during suspend so we don't have
>>>> to wake up the device just to read the counters. So the issue is only how
>>>> to *initialize* the counters.
>>>>
>>>> You are saying we initialize by saving all counters during suspend, whether
>>>> or not they are enabled, which I don't agree with. I am saying we should
>>>> only read and store the counters which are enabled during normal
>>>> operation. And to initialize we wake the device up during
>>>> xe_pmu_event_start and store the counter value. Alternatively, we can zero
>>>> out the enabled counters during xe_pmu_event_start (the counters are RW)
>>>> but in any case that will also need waking up the device.
>>
>> when the driver is initially loaded there might not be any users of
>> device and immediately it might enter suspend, so at the time of suspend
>> there no event enabled, but the pmu can be opened just after suspend
>> wihtout any actual work on device so device still resides in suspend, so
>> we should not be waking the device just to read the register in
>> event_start or any of the callbacks without any real workload or user of
>> the device.
>>
>> so ideally if the device didn't enter suspend, the counter is
>> initialized in the first read when device is still awake.
>
> Yes, I understand. But the issue is why are we reading (doing expensive
> reads across PCIe) and saving all these registers for PMU when it's
> possible PMU might not be used at all and none of these events might be
> enabled at all?
>
> So to me the lesser evil is to wake up the device at xe_pmu_event_start
> time and initialize the counters. We are only waking the device up once at
> init time, not during normal operation. Whereas in your case, you are
> reading and saving these registers continuously each time we suspend,
> whether or not PMU is or will be used.
I'm not sure which is costly saving the registers during suspend or
waking the device on even_init we shall remember that the same event can
be opened by multiple listeners so that will make the device wake up
multiple times had the device got suspended in between opening those events.
and suppose if we do multiple PCIe reads are you suspecting it will
affect any timing requirements if the suspend has any and I have little
doubt there if PCIe reads will take so long to miss any timings atleast
in this case. But anyways as you said we can take this up later, if we
know we will be adding more such counters in future.
Thanks,
Aravind.
>
>>>> So this way we only wake up the device for initialization but not
>>>> afterwards.
>>>>
>>>> Since this is the "base" patch we should try to set up a good
>>>> infrastructure in this patch so that other stuff which is exposed via PMU
>>>> can be easily added later.
>>>
>>> After thinking a bit more about this, though I think this needs to be done,
>>> I won't insist that we do this in this patch, we can review and do this in
>>> a subsequent patch (if no one else objects).
>>>
>>> So let's skip this for now. So if you can generate a new version of the
>>> patch after addressing all of the other review comments, we can review that
>>> again and try to get it merged.
>>>
>>> Thanks.
>>> --
>>> Ashutosh
>>>
>>>>>>>>
>>>>>>>> Doing this IMO would be better than always doing these PCIe reads on
>>>>>>>> runtime suspend even when PMU is not being used
>>>>>>>
>>>>>>> we have been doing these in i915 not sure if it affected any timing
>>>>>>> requirements for runtime suspend.
>>>>>>
>>>>>> Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
>>>>>> when RC6 event is not enabled or PMU might not be used.
>>>>>>
>>>>>> @Tvrtko, any comments here?
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-08-09 4:26 ` Iddamsetty, Aravind
@ 2023-08-09 5:02 ` Dixit, Ashutosh
0 siblings, 0 replies; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-08-09 5:02 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 08 Aug 2023 21:26:20 -0700, Iddamsetty, Aravind wrote:
>
> On 08-08-2023 20:48, Dixit, Ashutosh wrote:
> > On Tue, 08 Aug 2023 06:45:36 -0700, Iddamsetty, Aravind wrote:
> >> On 08-08-2023 03:52, Dixit, Ashutosh wrote:
> >>> On Mon, 07 Aug 2023 14:16:59 -0700, Dixit, Ashutosh wrote:
> >> I have sent a new revision, but commenting here for few comments.
> >>>
> >>>> On Tue, 25 Jul 2023 04:38:45 -0700, Iddamsetty, Aravind wrote:
> >>>>> On 24-07-2023 22:01, Dixit, Ashutosh wrote:
> >>>>>> On Mon, 24 Jul 2023 09:05:53 -0700, Iddamsetty, Aravind wrote:
> >>>>>>>
> >>>>>>>>> On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> >>>>>>>>>>> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
> >>>>>>>>>>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
> >>>>>>>>>>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
> >>>>>>>>>>>>>> +{
> >>>>>>>>>>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
> >>>>>>>>>>>>>> + unsigned int gt_id = gt->info.id;
> >>>>>>>>>>>>>> + unsigned long flags;
> >>>>>>>>>>>>>> +
> >>>>>>>>>>>>>> + spin_lock_irqsave(&pmu->lock, flags);
> >>>>>>>>>>>>>> +
> >>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
> >>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
> >>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
> >>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
> >>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
> >>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
> >>>>>>>>>>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
> >>>>>>>>>>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
> >>>>>>>>>>
> >>>>>>>>>> Here why should we store everything, we should store only those events
> >>>>>>>>>> which are enabled?
> >>>>>>>>>
> >>>>>>>>> The events are enabled only when they are opened which can happen after
> >>>>>>>>> the device is suspended hence we need to store all. As in the present
> >>>>>>>>> case device is put to suspend immediately after probe and event is
> >>>>>>>>> opened post driver load is done.
> >>>>>>>>
> >>>>>>>> I don't think we can justify doing expensive PCIe reads and increasing the
> >>>>>>>> time to go into runtime suspend, when PMU might not being used at all.
> >>>>>>>>
> >>>>>>>> If we store only enabled samples and start storing them only after they are
> >>>>>>>> enabled, what would be the consequence of this? The first non-zero sample
> >>>>>>>> seen by the perf tool would be wrong and later samples will be fine?
> >>>>>>>
> >>>>>>> Why do you say it is wrong perf reports relative from the time an event
> >>>>>>> is opened.
> >>>>>>
> >>>>>> I am asking you what is the consequence. Initial values will all be zero
> >>>>>> and then there is some activity and we get a non zero value but this will
> >>>>>> include all the previous activity so the first difference we send to perf
> >>>>>> will be large/wrong I think.
> >>>>>
> >>>>> correct if we just store the enabled events in suspend, any other event
> >>>>> will have 0 initial value and when we read the register later it will
> >>>>> have all the accumulation and since past value we have is 0 we would end
> >>>>> up reporting the entire value which is wrong.
> >>>>
> >>>> Ok, agreed, so we need to do "something".
> >>>>
> >>>>>
> >>>>>>
> >>>>>>>
> >>>>>>>>
> >>>>>>>> If there is a consequence, we might have to go back to what I was saying
> >>>>>>>> earlier about waking the device up and reading the enabled counter when
> >>>>>>>> xe_pmu_event_start happens, to initialize the counter values. I am assuming
> >>>>>>>> this will work?
> >>>>>>>
> >>>>>>> xe_pmu_event_start can be called when device is in suspend so we shall
> >>>>>>> not wake up the device i.e event being enabled when in suspend, so if we
> >>>>>>> do not store while going to suspend we will not have any value to
> >>>>>>> consider when event is enabled after suspend as we need to present
> >>>>>>> relative value.
> >>>>>>
> >>>>>> That is why I am saying wake up the device and initialize the counters in
> >>>>>> xe_pmu_event_start.
> >>>>>
> >>>>> Afaik since PMU doesn't take DRM reference we shall not wake up the
> >>>>> device.
> >>>>
> >>>> Not sure what you mean because PMU does do this:
> >>>>
> >>>> drm_dev_get(&xe->drm);
> >>
> >> sorry it was my misunderstanding here, please ignore.
> >>
> >>>>
> >>>> Anyway I don't think it has anything to do with waking up the device since
> >>>> that is done via xe_device_mem_access_get.
> >>>>
> >>>>> if we were allowed to wake up the device why do we even need to
> >>>>> store during suspend. when ever PMU event is opened we could wake up the
> >>>>> device and read the register directly.
> >>>>
> >>>> No. That is why we are saving the counters during suspend so we don't have
> >>>> to wake up the device just to read the counters. So the issue is only how
> >>>> to *initialize* the counters.
> >>>>
> >>>> You are saying we initialize by saving all counters during suspend, whether
> >>>> or not they are enabled, which I don't agree with. I am saying we should
> >>>> only read and store the counters which are enabled during normal
> >>>> operation. And to initialize we wake the device up during
> >>>> xe_pmu_event_start and store the counter value. Alternatively, we can zero
> >>>> out the enabled counters during xe_pmu_event_start (the counters are RW)
> >>>> but in any case that will also need waking up the device.
> >>
> >> when the driver is initially loaded there might not be any users of
> >> device and immediately it might enter suspend, so at the time of suspend
> >> there no event enabled, but the pmu can be opened just after suspend
> >> wihtout any actual work on device so device still resides in suspend, so
> >> we should not be waking the device just to read the register in
> >> event_start or any of the callbacks without any real workload or user of
> >> the device.
> >>
> >> so ideally if the device didn't enter suspend, the counter is
> >> initialized in the first read when device is still awake.
> >
> > Yes, I understand. But the issue is why are we reading (doing expensive
> > reads across PCIe) and saving all these registers for PMU when it's
> > possible PMU might not be used at all and none of these events might be
> > enabled at all?
> >
> > So to me the lesser evil is to wake up the device at xe_pmu_event_start
> > time and initialize the counters. We are only waking the device up once at
> > init time, not during normal operation. Whereas in your case, you are
> > reading and saving these registers continuously each time we suspend,
> > whether or not PMU is or will be used.
>
> I'm not sure which is costly saving the registers during suspend or
> waking the device on even_init we shall remember that the same event can
> be opened by multiple listeners so that will make the device wake up
> multiple times had the device got suspended in between opening those
> events.
Such optimizations should be possible, that is if we already have the
counter values initialized (say non-zero) don't wake up the device.
>
> and suppose if we do multiple PCIe reads are you suspecting it will
> affect any timing requirements if the suspend has any and I have little
> doubt there if PCIe reads will take so long to miss any timings atleast
> in this case. But anyways as you said we can take this up later, if we
> know we will be adding more such counters in future.
Yes, let's take this up later.
Thanks.
--
Ashutosh
> >
> >>>> So this way we only wake up the device for initialization but not
> >>>> afterwards.
> >>>>
> >>>> Since this is the "base" patch we should try to set up a good
> >>>> infrastructure in this patch so that other stuff which is exposed via PMU
> >>>> can be easily added later.
> >>>
> >>> After thinking a bit more about this, though I think this needs to be done,
> >>> I won't insist that we do this in this patch, we can review and do this in
> >>> a subsequent patch (if no one else objects).
> >>>
> >>> So let's skip this for now. So if you can generate a new version of the
> >>> patch after addressing all of the other review comments, we can review that
> >>> again and try to get it merged.
> >>>
> >>> Thanks.
> >>> --
> >>> Ashutosh
> >>>
> >>>>>>>>
> >>>>>>>> Doing this IMO would be better than always doing these PCIe reads on
> >>>>>>>> runtime suspend even when PMU is not being used
> >>>>>>>
> >>>>>>> we have been doing these in i915 not sure if it affected any timing
> >>>>>>> requirements for runtime suspend.
> >>>>>>
> >>>>>> Hmm i915 indeed seems to be reading the RC6 residency in __gt_park even
> >>>>>> when RC6 event is not enabled or PMU might not be used.
> >>>>>>
> >>>>>> @Tvrtko, any comments here?
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-22 6:04 ` Dixit, Ashutosh
2023-07-24 8:03 ` Iddamsetty, Aravind
@ 2023-07-24 9:38 ` Iddamsetty, Aravind
1 sibling, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-24 9:38 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 22-07-2023 11:34, Dixit, Ashutosh wrote:
> On Fri, 21 Jul 2023 16:36:02 -0700, Dixit, Ashutosh wrote:
>>
>> On Fri, 21 Jul 2023 04:51:09 -0700, Iddamsetty, Aravind wrote:
>>>
>> Hi Aravind,
>>
>>> On 21-07-2023 06:32, Dixit, Ashutosh wrote:
>>>> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>>>>
>>>> More stuff to mull over. You can ignore comments starting with "OK", those
>>>> are just notes to myself.
>>>>
>>>> Also, maybe some time we can add a basic IGT which reads these exposed
>>>> counters and verifies that we can read them and they are monotonically
>>>> increasing?
>>>
>>> this is the IGT https://patchwork.freedesktop.org/series/119936/ series
>>> using these counters posted by Venkat.
>>>
>>>>
>>>>> There are a set of engine group busyness counters provided by HW which are
>>>>> perfect fit to be exposed via PMU perf events.
>>>>>
>>>>> BSPEC: 46559, 46560, 46722, 46729
>>>>
>>>> Also add these Bspec entries: 71028, 52071
>>>
>>> OK.
>>>
>>>>
>>>>>
>>>>> events can be listed using:
>>>>> perf list
>>>>> xe_0000_03_00.0/any-engine-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/copy-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/interrupts/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/media-group-busy-gt0/ [Kernel PMU event]
>>>>> xe_0000_03_00.0/render-group-busy-gt0/ [Kernel PMU event]
>>>>>
>>>>> and can be read using:
>>>>>
>>>>> perf stat -e "xe_0000_8c_00.0/render-group-busy-gt0/" -I 1000
>>>>> time counts unit events
>>>>> 1.001139062 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 2.003294678 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 3.005199582 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 4.007076497 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 5.008553068 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 6.010531563 43520 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 7.012468029 44800 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 8.013463515 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 9.015300183 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.017233010 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>> 10.971934120 0 ns xe_0000_8c_00.0/render-group-busy-gt0/
>>>>>
>>>>> The pmu base implementation is taken from i915.
>>>>>
>>>>> v2:
>>>>> Store last known value when device is awake return that while the GT is
>>>>> suspended and then update the driver copy when read during awake.
>>>>>
>>>>> Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>> Co-developed-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/xe/Makefile | 2 +
>>>>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +
>>>>> drivers/gpu/drm/xe/xe_device.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>>>>> drivers/gpu/drm/xe/xe_gt.c | 2 +
>>>>> drivers/gpu/drm/xe/xe_irq.c | 22 +
>>>>> drivers/gpu/drm/xe/xe_module.c | 5 +
>>>>> drivers/gpu/drm/xe/xe_pmu.c | 739 +++++++++++++++++++++++++++
>>>>> drivers/gpu/drm/xe/xe_pmu.h | 25 +
>>>>> drivers/gpu/drm/xe/xe_pmu_types.h | 80 +++
>>>>> include/uapi/drm/xe_drm.h | 16 +
>>>>> 11 files changed, 902 insertions(+)
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.c
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu.h
>>>>> create mode 100644 drivers/gpu/drm/xe/xe_pmu_types.h
>>>>>
<snip>
>>>>> +
>>>>> +void engine_group_busyness_store(struct xe_gt *gt)
>>>>> +{
>>>>> + struct xe_pmu *pmu = >->tile->xe->pmu;
>>>>> + unsigned int gt_id = gt->info.id;
>>>>> + unsigned long flags;
>>>>> +
>>>>> + spin_lock_irqsave(&pmu->lock, flags);
>>>>> +
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_RENDER_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_RENDER_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_COPY_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_COPY_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_MEDIA_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_MEDIA_GROUP_BUSY(0)));
>>>>> + store_sample(pmu, gt_id, __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY,
>>>>> + __engine_group_busyness_read(gt, XE_PMU_ANY_ENGINE_GROUP_BUSY(0)));
>
> Here why should we store everything, we should store only those events
> which are enabled?
>
> Also it would good if the above can be done in a loop somehow. 4 is fine
> but if we add events later, a loop will be nice, if possible.
i got your point. i could do something like this
for (i = __XE_SAMPLE_RENDER_GROUP_BUSY; i < __XE_NUM_PMU_SAMPLERS; i++) {
val = __engine_group_busyness_read(gt, i);
pmu->sample[gt_id][i] = val;
}
Thanks,
Aravind.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-06-27 12:21 ` [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface Aravind Iddamsetty
` (5 preceding siblings ...)
2023-07-21 1:02 ` Dixit, Ashutosh
@ 2023-07-22 14:39 ` Dixit, Ashutosh
2023-07-24 8:02 ` Iddamsetty, Aravind
6 siblings, 1 reply; 59+ messages in thread
From: Dixit, Ashutosh @ 2023-07-22 14:39 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 2458397ce8af..96e3720923d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
> if (err)
> goto err_msg;
>
> + engine_group_busyness_store(gt);
> +
> err = xe_uc_suspend(>->uc);
> if (err)
> goto err_force_wake;
Also, another tiny point, let's not call engine_group_busyness_store
directly from here. Let's expose a xe_pmu_suspend() in xe_pmu.h and call
that from here and have xe_pmu_suspend call engine_group_busyness_store.
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface
2023-07-22 14:39 ` Dixit, Ashutosh
@ 2023-07-24 8:02 ` Iddamsetty, Aravind
0 siblings, 0 replies; 59+ messages in thread
From: Iddamsetty, Aravind @ 2023-07-24 8:02 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Bommu Krishnaiah, intel-xe, Tvrtko Ursulin
On 22-07-2023 20:09, Dixit, Ashutosh wrote:
> On Tue, 27 Jun 2023 05:21:13 -0700, Aravind Iddamsetty wrote:
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>> index 2458397ce8af..96e3720923d4 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -593,6 +593,8 @@ int xe_gt_suspend(struct xe_gt *gt)
>> if (err)
>> goto err_msg;
>>
>> + engine_group_busyness_store(gt);
>> +
>> err = xe_uc_suspend(>->uc);
>> if (err)
>> goto err_force_wake;
>
> Also, another tiny point, let's not call engine_group_busyness_store
> directly from here. Let's expose a xe_pmu_suspend() in xe_pmu.h and call
> that from here and have xe_pmu_suspend call engine_group_busyness_store.
Ok makes sense.
Thanks,
Aravind.
^ permalink raw reply [flat|nested] 59+ messages in thread