[PATCH v2 00/11] Enable CMRR in fixed-RR VRR path

[PATCH v2 00/11] Enable CMRR in fixed-RR VRR path

[Mitul Golani]

The existing CMRR fractional-timing code was permanently
disabled (if (!HAS_CMRR || true)), eDP-only, and relied
on a heuristic to guess when the fractional path was needed.
This series reworks it into a generic, debugfs-driven feature,
which later will be controlled via userspace when respective
uapi will be in-palce.

Mitul Golani (11):
  drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control
  drm/i915/vrr: compute CMRR fractional timings generically
  drm/i915/vrr: dump CMRR state in the crtc state dump
  drm/i915/vrr: Move CMRR hw registers to fix refresh rate path
  drm/i915/vrr: Enable/Disable CMRR based on enable/disable
    preconditions
  drm/i915/display: Move CMRR crtc_state members under VRR
  drm/i915/vrr: Fix the CMRR enabling/disabling sequence
  drm/i915/vrr: Compare state and HW registers if platform supports CMRR
  drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode
  drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled
  drm/i915/vrr: Enable cmrr

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |   4 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |  12 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 360 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 7 files changed, 293 insertions(+), 93 deletions(-)

-- 
2.48.1

[PATCH v2 01/11] drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control

[Mitul Golani]

Add a per-CRTC debugfs entry 'vrr/cmrr' and a debugfs file
(numerator/denominator) that indicates user intended target
refresh rate and video mode requirement.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 105 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 4 files changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 08004c1ba03f..1ce6e73ec83c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -48,6 +48,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "intel_tc.h"
 
@@ -1393,6 +1394,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
 	intel_drrs_crtc_debugfs_add(crtc);
 	intel_fbc_crtc_debugfs_add(crtc);
 	hsw_ips_crtc_debugfs_add(crtc);
+	intel_vrr_crtc_debugfs_add(crtc);
 
 	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
 			    &i915_current_bpc_fops);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6cd102a3b610..897a1ffd7b79 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1545,6 +1545,11 @@ struct intel_crtc {
 		u64 flip_count;
 	} dc_balance;
 
+	struct {
+		u32 numerator;
+		u32 denominator;
+	} cmrr;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index cd380fe8fd01..41118883b845 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -4,6 +4,10 @@
  *
  */
 
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
@@ -1231,3 +1235,104 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
 
 	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
 }
+
+static int cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
+{
+	char *sep;
+	int ret;
+
+	/*
+	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
+	 * is the requested refresh rate in KHz (refresh rate in Hz * 1000)
+	 * and the denominator selects the timing: 1000 for a 1:1 ratio
+	 * (no video timing) or 1001 for the 1000/1001 video timing.
+	 */
+
+	sep = strchr(str, '/');
+	if (!sep)
+		return -EINVAL;
+
+	*sep = '\0';
+
+	ret = kstrtou32(strim(str), 10, numerator);
+	if (ret)
+		return ret;
+
+	ret = kstrtou32(strim(sep + 1), 10, denominator);
+	if (ret)
+		return ret;
+
+	if (*numerator == 0)
+		return -EINVAL;
+
+	if (*denominator != 1000 && *denominator != 1001)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int intel_vrr_cmrr_show(struct seq_file *m, void *data)
+{
+	struct intel_crtc *crtc = m->private;
+
+	seq_printf(m, "%u/%u\n", crtc->cmrr.numerator, crtc->cmrr.denominator);
+
+	return 0;
+}
+
+static int intel_vrr_cmrr_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, intel_vrr_cmrr_show, inode->i_private);
+}
+
+static ssize_t intel_vrr_cmrr_write(struct file *file, const char __user *ubuf,
+				    size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct intel_crtc *crtc = m->private;
+	u32 numerator, denominator;
+	char kbuf[32];
+	int ret;
+
+	if (len >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, ubuf, len))
+		return -EFAULT;
+
+	kbuf[len] = '\0';
+
+	ret = cmrr_parse_ratio(kbuf, &numerator, &denominator);
+	if (ret)
+		return ret;
+
+	crtc->cmrr.numerator = numerator;
+	crtc->cmrr.denominator = denominator;
+
+	return len;
+}
+
+static const struct file_operations intel_vrr_cmrr_fops = {
+	.owner = THIS_MODULE,
+	.open = intel_vrr_cmrr_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = intel_vrr_cmrr_write,
+};
+
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct dentry *vrr_dir;
+
+	if (!HAS_VRR(display))
+		return;
+
+	vrr_dir = debugfs_create_dir("vrr", crtc->base.debugfs_entry);
+
+	if (HAS_CMRR(display))
+		debugfs_create_file("cmrr", 0600, vrr_dir, crtc,
+				    &intel_vrr_cmrr_fops);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 55e9c429f579..19c7990be1b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
 
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

Re: [PATCH v2 01/11] drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control

[Jani Nikula]

On Tue, 16 Jun 2026, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add a per-CRTC debugfs entry 'vrr/cmrr' and a debugfs file
> (numerator/denominator) that indicates user intended target
> refresh rate and video mode requirement.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  |   2 +
>  .../drm/i915/display/intel_display_types.h    |   5 +
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 105 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>  4 files changed, 114 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 08004c1ba03f..1ce6e73ec83c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -48,6 +48,7 @@
>  #include "intel_psr.h"
>  #include "intel_psr_regs.h"
>  #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>  #include "intel_wm.h"
>  #include "intel_tc.h"
>  
> @@ -1393,6 +1394,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>  	intel_drrs_crtc_debugfs_add(crtc);
>  	intel_fbc_crtc_debugfs_add(crtc);
>  	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>  
>  	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>  			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6cd102a3b610..897a1ffd7b79 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1545,6 +1545,11 @@ struct intel_crtc {
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_cmrr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->cmrr.numerator, crtc->cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_cmrr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_cmrr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_cmrr_write(struct file *file, const char __user *ubuf,
> +				    size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->cmrr.numerator = numerator;
> +	crtc->cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +
> +static const struct file_operations intel_vrr_cmrr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_cmrr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_cmrr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct dentry *vrr_dir;
> +
> +	if (!HAS_VRR(display))
> +		return;
> +
> +	vrr_dir = debugfs_create_dir("vrr", crtc->base.debugfs_entry);

Please give rationale for adding a directory.

Driver specific debugfs files should have a prefix. Using just "vrr"
blocks using it as a generic drm debugfs file. Please let's use "intel_"
going forward (instead of "i915_" that we've had before xe).

> +
> +	if (HAS_CMRR(display))
> +		debugfs_create_file("cmrr", 0600, vrr_dir, crtc,
> +				    &intel_vrr_cmrr_fops);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>  int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>  
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>  #endif /* __INTEL_VRR_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH v2 01/11] drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control

[Borah, Chaitanya Kumar]

On 6/16/2026 8:12 PM, Mitul Golani wrote:
> Add a per-CRTC debugfs entry 'vrr/cmrr' and a debugfs file
> (numerator/denominator) that indicates user intended target
> refresh rate and video mode requirement.
> 

Please add more details regarding the semantics of the debugfs entry.

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>   .../drm/i915/display/intel_display_types.h    |   5 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 105 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>   4 files changed, 114 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 08004c1ba03f..1ce6e73ec83c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -48,6 +48,7 @@
>   #include "intel_psr.h"
>   #include "intel_psr_regs.h"
>   #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>   #include "intel_wm.h"
>   #include "intel_tc.h"
>   
> @@ -1393,6 +1394,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>   	intel_drrs_crtc_debugfs_add(crtc);
>   	intel_fbc_crtc_debugfs_add(crtc);
>   	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>   
>   	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>   			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6cd102a3b610..897a1ffd7b79 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1545,6 +1545,11 @@ struct intel_crtc {
>   		u64 flip_count;
>   	} dc_balance;
>   
> +	struct {
> +		u32 numerator;
> +		u32 denominator;
> +	} cmrr;
> +

Please make it explicity that these are use to force CMRR refresh rates.

Something like *force_cmrr* would work better.

>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index cd380fe8fd01..41118883b845 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -4,6 +4,10 @@
>    *
>    */
>   
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/string.h>
> +
>   #include <drm/drm_print.h>
>   
>   #include "intel_alpm.h"
> @@ -1231,3 +1235,104 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>   
>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>   }
> +
> +static int cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
> +{
> +	char *sep;
> +	int ret;
> +
> +	/*
> +	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
> +	 * is the requested refresh rate in KHz

incorrect it is milli-Hz

For 60Hz, numerator will be 60000.

(refresh rate in Hz * 1000)
> +	 * and the denominator selects the timing: 1000 for a 1:1 ratio
> +	 * (no video timing) or 1001 for the 1000/1001 video timing.
> +	 */
> +
> +	sep = strchr(str, '/');
> +	if (!sep)
> +		return -EINVAL;
> +
> +	*sep = '\0';
> +
> +	ret = kstrtou32(strim(str), 10, numerator);
> +	if (ret)
> +		return ret;
> +
> +	ret = kstrtou32(strim(sep + 1), 10, denominator);
> +	if (ret)
> +		return ret;
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;

We could use some check for the numerator too. Perhaps some common 
refresh rates or the ones that we expect IGTs to be written or valid 
once from the edid. Check could be either here or in compute_config.

> +
> +	return 0;
> +}
> +
> +static int intel_vrr_cmrr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->cmrr.numerator, crtc->cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_cmrr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_cmrr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_cmrr_write(struct file *file, const char __user *ubuf,
> +				    size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->cmrr.numerator = numerator;
> +	crtc->cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +

Please add *_debugfs_* to the function (that explicitly handles the 
debugfs) that are missing it.

> +static const struct file_operations intel_vrr_cmrr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_cmrr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_cmrr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct dentry *vrr_dir;
> +
> +	if (!HAS_VRR(display))
> +		return;
> +
> +	vrr_dir = debugfs_create_dir("vrr", crtc->base.debugfs_entry);
> +
> +	if (HAS_CMRR(display))
> +		debugfs_create_file("cmrr", 0600, vrr_dir, crtc,
> +				    &intel_vrr_cmrr_fops);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_VRR_H__ */

[PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Mitul Golani]

Replace the disabled, eDP-only, fractional-CMRR code
with a generic, transcoder-agnostic computation driven by an
explicit per-CRTC target. Compute CMRR_M and CMRR_N timings
based on video mode reqirement if CMRR is required to be enabled.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
 2 files changed, 63 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 897a1ffd7b79..39e11362630c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1548,6 +1548,8 @@ struct intel_crtc {
 	struct {
 		u32 numerator;
 		u32 denominator;
+		/* Derived during atomic check: 1000/1001 video timing required */
+		bool video_mode;
 	} cmrr;
 
 	int scanline_offset;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 41118883b845..e36c0cab096a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -26,9 +26,6 @@
 #include "skl_prefill.h"
 #include "skl_watermark.h"
 
-#define FIXED_POINT_PRECISION		100
-#define CMRR_PRECISION_TOLERANCE	10
-
 /*
  * Tunable parameters for DC Balance correction.
  * These are captured based on experimentations.
@@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
-static bool
-is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+static void
+intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
-
-	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!HAS_CMRR(display) || true)
-		return false;
-
-	actual_refresh_k =
-		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
-	pixel_clock_per_line =
-		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
-	calculated_refresh_k =
-		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
-
-	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
-		return false;
-
-	return true;
-}
-
-static unsigned int
-cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
-{
-	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
 	u64 adjusted_pixel_rate;
-	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int requested_refresh_rate, current_refresh_rate;
+	int multiplier_m = 1, multiplier_n = 1;
 
-	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+	if (!HAS_CMRR(display))
+		return;
 
-	if (video_mode_required) {
-		multiplier_m = 1001;
-		multiplier_n = 1000;
-	}
+	/* No CMRR ratio configured through debugfs */
+	if (!crtc->cmrr.numerator)
+		return;
 
-	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-					      multiplier_n);
-	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->cmrr.cmrr_n);
-	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+	/*
+	 * The numerator encodes the requested refresh rate in kHz, so the
+	 * requested refresh rate in Hz is numerator / 1000. It must match the
+	 * refresh rate of the current mode.
+	 */
+	requested_refresh_rate = crtc->cmrr.numerator / 1000;
+	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+
+	if (requested_refresh_rate != current_refresh_rate) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
+				crtc->base.base.id, crtc->base.name,
+				requested_refresh_rate, current_refresh_rate);
+		return;
+	}
 
-	return vtotal;
-}
+	/*
+	 * A 1:1 ratio (denominator == 1000) means no video timing is required
+	 * Any other ratio (e.g. 1000/1001) requires the video timing.
+	 */
+	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
+	if (crtc->cmrr.video_mode) {
+		multiplier_m = 1000;
+		multiplier_n = 1001;
+	}
 
-static
-void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
-{
 	/*
-	 * TODO: Compute precise target refresh rate to determine
-	 * if video_mode_required should be true. Currently set to
-	 * false due to uncertainty about the precise target
-	 * refresh Rate.
+	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
+	 *
+	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
+	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
+	 *
+	 * where multiplier_m/multiplier_n = 1000/1001 when the
+	 * video timing is required, else 1/1. The integer vtotal
+	 * term is tracked in SW (it is the programmed mode vtotal)
+	 * while the fractional part represented by cmrr_m/cmrr_n
+	 * is tracked in HW.
 	 */
-	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
-	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 
-	crtc_state->cmrr.enable = true;
-	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+	crtc_state->cmrr.cmrr_n =
+		mul_u32_u32(requested_refresh_rate * adjusted_mode->crtc_htotal,
+			    multiplier_m);
+	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
+	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+
+	return;
 }
 
 static
@@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int vmin, vmax;
 
@@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		vmax = vmin;
 	}
 
-	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
+	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
-	else if (is_cmrr_frac_required(crtc_state) && is_edp)
-		intel_vrr_compute_cmrr_timings(crtc_state);
-	else
+	} else {
 		intel_vrr_compute_fixed_rr_timings(crtc_state);
 
+		/*
+		 * CMRR is a fixed average Vtotal mode and is only computed on
+		 * the fixed refresh rate path. It is generic across transcoders
+		 * and gated on platform support and a valid debugfs ratio.
+		 */
+		intel_vrr_cmrr_compute_config(crtc_state);
+	}
+
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-- 
2.48.1

Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Jani Nikula]

On Tue, 16 Jun 2026, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Replace the disabled, eDP-only, fractional-CMRR code
> with a generic, transcoder-agnostic computation driven by an
> explicit per-CRTC target. Compute CMRR_M and CMRR_N timings
> based on video mode reqirement if CMRR is required to be enabled.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
>  2 files changed, 63 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 897a1ffd7b79..39e11362630c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1548,6 +1548,8 @@ struct intel_crtc {
>  	struct {
>  		u32 numerator;
>  		u32 denominator;
> +		/* Derived during atomic check: 1000/1001 video timing required */
> +		bool video_mode;

compute config must not change permanent state, only crtc state.

Moreover, the video_mode here is just a funcion of denominator, so why
do we cache it when it can be computed on the fly?

>  	} cmrr;
>  
>  	int scanline_offset;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 41118883b845..e36c0cab096a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -26,9 +26,6 @@
>  #include "skl_prefill.h"
>  #include "skl_watermark.h"
>  
> -#define FIXED_POINT_PRECISION		100
> -#define CMRR_PRECISION_TOLERANCE	10
> -
>  /*
>   * Tunable parameters for DC Balance correction.
>   * These are captured based on experimentations.
> @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>  	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>  }
>  
> -static bool
> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> +static void
> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> -
> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> -	if (!HAS_CMRR(display) || true)
> -		return false;
> -
> -	actual_refresh_k =
> -		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
> -	pixel_clock_per_line =
> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
> -	calculated_refresh_k =
> -		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
> -
> -	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
> -		return false;
> -
> -	return true;
> -}
> -
> -static unsigned int
> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
> -{
> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
>  	u64 adjusted_pixel_rate;
> -	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int requested_refresh_rate, current_refresh_rate;
> +	int multiplier_m = 1, multiplier_n = 1;
>  
> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +	if (!HAS_CMRR(display))
> +		return;
>  
> -	if (video_mode_required) {
> -		multiplier_m = 1001;
> -		multiplier_n = 1000;
> -	}
> +	/* No CMRR ratio configured through debugfs */
> +	if (!crtc->cmrr.numerator)
> +		return;
>  
> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -					      multiplier_n);
> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->cmrr.cmrr_n);
> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +	/*
> +	 * The numerator encodes the requested refresh rate in kHz, so the
> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> +	 * refresh rate of the current mode.
> +	 */
> +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +
> +	if (requested_refresh_rate != current_refresh_rate) {
> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
> +				crtc->base.base.id, crtc->base.name,
> +				requested_refresh_rate, current_refresh_rate);
> +		return;
> +	}
>  
> -	return vtotal;
> -}
> +	/*
> +	 * A 1:1 ratio (denominator == 1000) means no video timing is required
> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> +	 */
> +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
> +	if (crtc->cmrr.video_mode) {
> +		multiplier_m = 1000;
> +		multiplier_n = 1001;
> +	}
>  
> -static
> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
> -{
>  	/*
> -	 * TODO: Compute precise target refresh rate to determine
> -	 * if video_mode_required should be true. Currently set to
> -	 * false due to uncertainty about the precise target
> -	 * refresh Rate.
> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> +	 *
> +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
> +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> +	 *
> +	 * where multiplier_m/multiplier_n = 1000/1001 when the
> +	 * video timing is required, else 1/1. The integer vtotal
> +	 * term is tracked in SW (it is the programmed mode vtotal)
> +	 * while the fractional part represented by cmrr_m/cmrr_n
> +	 * is tracked in HW.
>  	 */
> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>  
> -	crtc_state->cmrr.enable = true;
> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +	crtc_state->cmrr.cmrr_n =
> +		mul_u32_u32(requested_refresh_rate * adjusted_mode->crtc_htotal,
> +			    multiplier_m);
> +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
> +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +
> +	return;
>  }
>  
>  static
> @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -	bool is_edp = intel_dp_is_edp(intel_dp);
>  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	int vmin, vmax;
>  
> @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  		vmax = vmin;
>  	}
>  
> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>  		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> -		intel_vrr_compute_cmrr_timings(crtc_state);
> -	else
> +	} else {
>  		intel_vrr_compute_fixed_rr_timings(crtc_state);
>  
> +		/*
> +		 * CMRR is a fixed average Vtotal mode and is only computed on
> +		 * the fixed refresh rate path. It is generic across transcoders
> +		 * and gated on platform support and a valid debugfs ratio.
> +		 */
> +		intel_vrr_cmrr_compute_config(crtc_state);
> +	}
> +
>  	if (HAS_AS_SDP(display)) {
>  		crtc_state->vrr.vsync_start =
>  			(crtc_state->hw.adjusted_mode.crtc_vtotal -

-- 
Jani Nikula, Intel

RE: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: 17 June 2026 17:30
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Borah, Chaitanya Kumar
> <chaitanya.kumar.borah@intel.com>
> Subject: Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional
> timings generically
> 
> On Tue, 16 Jun 2026, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> wrote:
> > Replace the disabled, eDP-only, fractional-CMRR code with a generic,
> > transcoder-agnostic computation driven by an explicit per-CRTC target.
> > Compute CMRR_M and CMRR_N timings based on video mode reqirement if
> > CMRR is required to be enabled.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |   2 +
> >  drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
> >  2 files changed, 63 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 897a1ffd7b79..39e11362630c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1548,6 +1548,8 @@ struct intel_crtc {
> >  	struct {
> >  		u32 numerator;
> >  		u32 denominator;
> > +		/* Derived during atomic check: 1000/1001 video timing
> required */
> > +		bool video_mode;
> 
> compute config must not change permanent state, only crtc state.
> 
> Moreover, the video_mode here is just a funcion of denominator, so why do
> we cache it when it can be computed on the fly?

Right, no explicit requirement, can be configured on the fly. 

Thanks for review, I will make the change and float with next revision.

Regards,
Mitul

> 
> >  	} cmrr;
> >
> >  	int scanline_offset;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 41118883b845..e36c0cab096a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -26,9 +26,6 @@
> >  #include "skl_prefill.h"
> >  #include "skl_watermark.h"
> >
> > -#define FIXED_POINT_PRECISION		100
> > -#define CMRR_PRECISION_TOLERANCE	10
> > -
> >  /*
> >   * Tunable parameters for DC Balance correction.
> >   * These are captured based on experimentations.
> > @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct
> intel_crtc_state *crtc_state)
> >  	return intel_vrr_vmax_vtotal(crtc_state) -
> > crtc_state->vrr.guardband;  }
> >
> > -static bool
> > -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> > +static void
> > +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_display *display = to_intel_display(crtc_state);
> > -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_display_mode *adjusted_mode =
> > &crtc_state->hw.adjusted_mode;
> > -
> > -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> > -	if (!HAS_CMRR(display) || true)
> > -		return false;
> > -
> > -	actual_refresh_k =
> > -		drm_mode_vrefresh(adjusted_mode) *
> FIXED_POINT_PRECISION;
> > -	pixel_clock_per_line =
> > -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
> >crtc_htotal;
> > -	calculated_refresh_k =
> > -		pixel_clock_per_line * FIXED_POINT_PRECISION /
> adjusted_mode->crtc_vtotal;
> > -
> > -	if ((actual_refresh_k - calculated_refresh_k) <
> CMRR_PRECISION_TOLERANCE)
> > -		return false;
> > -
> > -	return true;
> > -}
> > -
> > -static unsigned int
> > -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
> > video_mode_required) -{
> > -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> >  	u64 adjusted_pixel_rate;
> > -	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	int requested_refresh_rate, current_refresh_rate;
> > +	int multiplier_m = 1, multiplier_n = 1;
> >
> > -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +	if (!HAS_CMRR(display))
> > +		return;
> >
> > -	if (video_mode_required) {
> > -		multiplier_m = 1001;
> > -		multiplier_n = 1000;
> > -	}
> > +	/* No CMRR ratio configured through debugfs */
> > +	if (!crtc->cmrr.numerator)
> > +		return;
> >
> > -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
> adjusted_mode->crtc_htotal,
> > -					      multiplier_n);
> > -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
> >crtc_clock * 1000, multiplier_n),
> > -				  crtc_state->cmrr.cmrr_n);
> > -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
> 1000, multiplier_m);
> > -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
> >cmrr.cmrr_n);
> > +	/*
> > +	 * The numerator encodes the requested refresh rate in kHz, so the
> > +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> > +	 * refresh rate of the current mode.
> > +	 */
> > +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
> > +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +
> > +	if (requested_refresh_rate != current_refresh_rate) {
> > +		drm_dbg_kms(display->drm,
> > +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
> does not match current mode refresh rate %d Hz\n",
> > +				crtc->base.base.id, crtc->base.name,
> > +				requested_refresh_rate,
> current_refresh_rate);
> > +		return;
> > +	}
> >
> > -	return vtotal;
> > -}
> > +	/*
> > +	 * A 1:1 ratio (denominator == 1000) means no video timing is
> required
> > +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> > +	 */
> > +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
> > +	if (crtc->cmrr.video_mode) {
> > +		multiplier_m = 1000;
> > +		multiplier_n = 1001;
> > +	}
> >
> > -static
> > -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
> > *crtc_state) -{
> >  	/*
> > -	 * TODO: Compute precise target refresh rate to determine
> > -	 * if video_mode_required should be true. Currently set to
> > -	 * false due to uncertainty about the precise target
> > -	 * refresh Rate.
> > +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> > +	 *
> > +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
> > +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> > +	 *
> > +	 * where multiplier_m/multiplier_n = 1000/1001 when the
> > +	 * video timing is required, else 1/1. The integer vtotal
> > +	 * term is tracked in SW (it is the programmed mode vtotal)
> > +	 * while the fractional part represented by cmrr_m/cmrr_n
> > +	 * is tracked in HW.
> >  	 */
> > -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> > -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> > -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> >
> > -	crtc_state->cmrr.enable = true;
> > -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> > +	crtc_state->cmrr.cmrr_n =
> > +		mul_u32_u32(requested_refresh_rate * adjusted_mode-
> >crtc_htotal,
> > +			    multiplier_m);
> > +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
> 1000) * multiplier_n;
> > +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate,
> > +crtc_state->cmrr.cmrr_n);
> > +
> > +	return;
> >  }
> >
> >  static
> > @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >  	struct intel_display *display = to_intel_display(crtc_state);
> >  	struct intel_connector *connector =
> >  		to_intel_connector(conn_state->connector);
> > -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> > -	bool is_edp = intel_dp_is_edp(intel_dp);
> >  	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> >  	int vmin, vmax;
> >
> > @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >  		vmax = vmin;
> >  	}
> >
> > -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> > +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
> >  		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> > -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> > -		intel_vrr_compute_cmrr_timings(crtc_state);
> > -	else
> > +	} else {
> >  		intel_vrr_compute_fixed_rr_timings(crtc_state);
> >
> > +		/*
> > +		 * CMRR is a fixed average Vtotal mode and is only computed
> on
> > +		 * the fixed refresh rate path. It is generic across transcoders
> > +		 * and gated on platform support and a valid debugfs ratio.
> > +		 */
> > +		intel_vrr_cmrr_compute_config(crtc_state);
> > +	}
> > +
> >  	if (HAS_AS_SDP(display)) {
> >  		crtc_state->vrr.vsync_start =
> >  			(crtc_state->hw.adjusted_mode.crtc_vtotal -
> 
> --
> Jani Nikula, Intel

Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Borah, Chaitanya Kumar]

On 6/16/2026 8:12 PM, Mitul Golani wrote:
> Replace the disabled,

I guess it is still disabled at this point, so the commit message is a 
bit misleading.

eDP-only,

Should be a separate patch.

fractional-CMRR code
> with a generic, transcoder-agnostic computation driven by an
> explicit per-CRTC target. Compute CMRR_M and CMRR_N timings
> based on video mode reqirement

typo

  if CMRR is required to be enabled.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_types.h    |   2 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
>   2 files changed, 63 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 897a1ffd7b79..39e11362630c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1548,6 +1548,8 @@ struct intel_crtc {
>   	struct {
>   		u32 numerator;
>   		u32 denominator;
> +		/* Derived during atomic check: 1000/1001 video timing required */
> +		bool video_mode;

I am not sure why this is needed at all, since you can just use the 
numerator and denominator to derive if it is a video mode within 
compute_config.

>   	} cmrr;
>   
>   	int scanline_offset;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 41118883b845..e36c0cab096a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -26,9 +26,6 @@
>   #include "skl_prefill.h"
>   #include "skl_watermark.h"
>   
> -#define FIXED_POINT_PRECISION		100
> -#define CMRR_PRECISION_TOLERANCE	10
> -
>   /*
>    * Tunable parameters for DC Balance correction.
>    * These are captured based on experimentations.
> @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>   }
>   
> -static bool
> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> +static void
> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> -
> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> -	if (!HAS_CMRR(display) || true)
> -		return false;
> -
> -	actual_refresh_k =
> -		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
> -	pixel_clock_per_line =
> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
> -	calculated_refresh_k =
> -		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
> -
> -	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
> -		return false;
> -
> -	return true;
> -}
> -
> -static unsigned int
> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
> -{
> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
>   	u64 adjusted_pixel_rate;
> -	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int requested_refresh_rate, current_refresh_rate;
> +	int multiplier_m = 1, multiplier_n = 1;
>   
> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +	if (!HAS_CMRR(display))
> +		return;
>   
> -	if (video_mode_required) {
> -		multiplier_m = 1001;
> -		multiplier_n = 1000;
> -	}
> +	/* No CMRR ratio configured through debugfs */
> +	if (!crtc->cmrr.numerator)
> +		return;
>   
> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -					      multiplier_n);
> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->cmrr.cmrr_n);
> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +	/*
> +	 * The numerator encodes the requested refresh rate in kHz, so the

Not accurate, because numerator/divider together provides the refresh 
rate. If anything the numerator is in mHz as commented in patch 1.

> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> +	 * refresh rate of the current mode.
> +	 */
> +	requested_refresh_rate = crtc->cmrr.numerator / 1000;

Integer division loses precision. It can be used in the comparison below 
but incorrect to use it in actual M and N value calculations done later.

> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +
> +	if (requested_refresh_rate != current_refresh_rate) {
> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
> +				crtc->base.base.id, crtc->base.name,
> +				requested_refresh_rate, current_refresh_rate);
> +		return;
> +	}
>   
> -	return vtotal;
> -}
> +	/*
> +	 * A 1:1 ratio (denominator == 1000) means no video timing is required
> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> +	 */
> +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
> +	if (crtc->cmrr.video_mode) {
> +		multiplier_m = 1000;
> +		multiplier_n = 1001;
> +	}

more intuitive to use names like rr_multiplier, rr_divider. Also the 
names are reversed now.

>   
> -static
> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
> -{
>   	/*
> -	 * TODO: Compute precise target refresh rate to determine
> -	 * if video_mode_required should be true. Currently set to
> -	 * false due to uncertainty about the precise target
> -	 * refresh Rate.
> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> +	 *
> +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
> +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> +	 *
> +	 * where multiplier_m/multiplier_n = 1000/1001 when the
> +	 * video timing is required, else 1/1. The integer vtotal
> +	 * term is tracked in SW (it is the programmed mode vtotal)
> +	 * while the fractional part represented by cmrr_m/cmrr_n
> +	 * is tracked in HW.
>   	 */
> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>   
> -	crtc_state->cmrr.enable = true;
> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

where do we set this flag now?

> +	crtc_state->cmrr.cmrr_n =
> +		mul_u32_u32(requested_refresh_rate * adjusted_mode->crtc_htotal,
> +			    multiplier_m);
> +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;

Please align the calculation as per BSpec-68925, calculate the cmrr 
votal here and retain the cmrr_get_vtotal semantics.

> +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +
> +	return;
>   }
>   
>   static
> @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	struct intel_connector *connector =
>   		to_intel_connector(conn_state->connector);
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -	bool is_edp = intel_dp_is_edp(intel_dp);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>   	int vmin, vmax;
>   
> @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   		vmax = vmin;
>   	}
>   
> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> -		intel_vrr_compute_cmrr_timings(crtc_state);
> -	else
> +	} else {
>   		intel_vrr_compute_fixed_rr_timings(crtc_state);
>   
> +		/*
> +		 * CMRR is a fixed average Vtotal mode and is only computed on
> +		 * the fixed refresh rate path. It is generic across transcoders
> +		 * and gated on platform support and a valid debugfs ratio.
> +		 */
> +		intel_vrr_cmrr_compute_config(crtc_state);
> +	}
> +
>   	if (HAS_AS_SDP(display)) {
>   		crtc_state->vrr.vsync_start =
>   			(crtc_state->hw.adjusted_mode.crtc_vtotal -

RE: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 06 July 2026 17:29
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings
> generically
> 
> 
> 
> On 6/16/2026 8:12 PM, Mitul Golani wrote:
> > Replace the disabled,
> 
> I guess it is still disabled at this point, so the commit message is a bit
> misleading.
> 
> eDP-only,
> 
> Should be a separate patch.
> 
> fractional-CMRR code
> > with a generic, transcoder-agnostic computation driven by an explicit
> > per-CRTC target. Compute CMRR_M and CMRR_N timings based on video
> mode
> > reqirement
> 
> typo
> 
>   if CMRR is required to be enabled.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   .../drm/i915/display/intel_display_types.h    |   2 +
> >   drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
> >   2 files changed, 63 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 897a1ffd7b79..39e11362630c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1548,6 +1548,8 @@ struct intel_crtc {
> >   	struct {
> >   		u32 numerator;
> >   		u32 denominator;
> > +		/* Derived during atomic check: 1000/1001 video timing
> required */
> > +		bool video_mode;
> 
> I am not sure why this is needed at all, since you can just use the numerator
> and denominator to derive if it is a video mode within compute_config.
> 
> >   	} cmrr;
> >
> >   	int scanline_offset;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 41118883b845..e36c0cab096a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -26,9 +26,6 @@
> >   #include "skl_prefill.h"
> >   #include "skl_watermark.h"
> >
> > -#define FIXED_POINT_PRECISION		100
> > -#define CMRR_PRECISION_TOLERANCE	10
> > -
> >   /*
> >    * Tunable parameters for DC Balance correction.
> >    * These are captured based on experimentations.
> > @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct
> intel_crtc_state *crtc_state)
> >   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
> >   }
> >
> > -static bool
> > -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> > +static void
> > +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_display_mode *adjusted_mode =
> > &crtc_state->hw.adjusted_mode;
> > -
> > -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> > -	if (!HAS_CMRR(display) || true)
> > -		return false;
> > -
> > -	actual_refresh_k =
> > -		drm_mode_vrefresh(adjusted_mode) *
> FIXED_POINT_PRECISION;
> > -	pixel_clock_per_line =
> > -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
> >crtc_htotal;
> > -	calculated_refresh_k =
> > -		pixel_clock_per_line * FIXED_POINT_PRECISION /
> adjusted_mode->crtc_vtotal;
> > -
> > -	if ((actual_refresh_k - calculated_refresh_k) <
> CMRR_PRECISION_TOLERANCE)
> > -		return false;
> > -
> > -	return true;
> > -}
> > -
> > -static unsigned int
> > -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
> > video_mode_required) -{
> > -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> >   	u64 adjusted_pixel_rate;
> > -	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	int requested_refresh_rate, current_refresh_rate;
> > +	int multiplier_m = 1, multiplier_n = 1;
> >
> > -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +	if (!HAS_CMRR(display))
> > +		return;
> >
> > -	if (video_mode_required) {
> > -		multiplier_m = 1001;
> > -		multiplier_n = 1000;
> > -	}
> > +	/* No CMRR ratio configured through debugfs */
> > +	if (!crtc->cmrr.numerator)
> > +		return;
> >
> > -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
> adjusted_mode->crtc_htotal,
> > -					      multiplier_n);
> > -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
> >crtc_clock * 1000, multiplier_n),
> > -				  crtc_state->cmrr.cmrr_n);
> > -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
> 1000, multiplier_m);
> > -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
> >cmrr.cmrr_n);
> > +	/*
> > +	 * The numerator encodes the requested refresh rate in kHz, so the
> 
> Not accurate, because numerator/divider together provides the refresh rate.
> If anything the numerator is in mHz as commented in patch 1.
> 
> > +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> > +	 * refresh rate of the current mode.
> > +	 */
> > +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
> 
> Integer division loses precision. It can be used in the comparison below but
> incorrect to use it in actual M and N value calculations done later.
> 
> > +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +
> > +	if (requested_refresh_rate != current_refresh_rate) {
> > +		drm_dbg_kms(display->drm,
> > +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
> does not match current mode refresh rate %d Hz\n",
> > +				crtc->base.base.id, crtc->base.name,
> > +				requested_refresh_rate,
> current_refresh_rate);
> > +		return;
> > +	}
> >
> > -	return vtotal;
> > -}
> > +	/*
> > +	 * A 1:1 ratio (denominator == 1000) means no video timing is
> required
> > +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> > +	 */
> > +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
> > +	if (crtc->cmrr.video_mode) {
> > +		multiplier_m = 1000;
> > +		multiplier_n = 1001;
> > +	}
> 
> more intuitive to use names like rr_multiplier, rr_divider. Also the names are
> reversed now.
> 
> >
> > -static
> > -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
> > *crtc_state) -{
> >   	/*
> > -	 * TODO: Compute precise target refresh rate to determine
> > -	 * if video_mode_required should be true. Currently set to
> > -	 * false due to uncertainty about the precise target
> > -	 * refresh Rate.
> > +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> > +	 *
> > +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
> > +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> > +	 *
> > +	 * where multiplier_m/multiplier_n = 1000/1001 when the
> > +	 * video timing is required, else 1/1. The integer vtotal
> > +	 * term is tracked in SW (it is the programmed mode vtotal)
> > +	 * while the fractional part represented by cmrr_m/cmrr_n
> > +	 * is tracked in HW.
> >   	 */
> > -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> > -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> > -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> >
> > -	crtc_state->cmrr.enable = true;
> > -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> 
> where do we set this flag now?

I915_MODE_FLAG_VRR is intentionally not set for CMRR. CMRR is implemented as a subset of the fixed-refresh-rate path. The older TODO in the readout predates that design decision and I'll clean it up. cmrr.enable will be set in the dedicated CMRR-enable patch at the end of the series.

Regards,
Mitul

> 
> > +	crtc_state->cmrr.cmrr_n =
> > +		mul_u32_u32(requested_refresh_rate * adjusted_mode-
> >crtc_htotal,
> > +			    multiplier_m);
> > +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
> 1000) *
> > +multiplier_n;
> 
> Please align the calculation as per BSpec-68925, calculate the cmrr votal here
> and retain the cmrr_get_vtotal semantics.
> 
> > +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate,
> > +crtc_state->cmrr.cmrr_n);
> > +
> > +	return;
> >   }
> >
> >   static
> > @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   	struct intel_display *display = to_intel_display(crtc_state);
> >   	struct intel_connector *connector =
> >   		to_intel_connector(conn_state->connector);
> > -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> > -	bool is_edp = intel_dp_is_edp(intel_dp);
> >   	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> >   	int vmin, vmax;
> >
> > @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   		vmax = vmin;
> >   	}
> >
> > -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> > +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
> >   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> > -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> > -		intel_vrr_compute_cmrr_timings(crtc_state);
> > -	else
> > +	} else {
> >   		intel_vrr_compute_fixed_rr_timings(crtc_state);
> >
> > +		/*
> > +		 * CMRR is a fixed average Vtotal mode and is only computed
> on
> > +		 * the fixed refresh rate path. It is generic across transcoders
> > +		 * and gated on platform support and a valid debugfs ratio.
> > +		 */
> > +		intel_vrr_cmrr_compute_config(crtc_state);
> > +	}
> > +
> >   	if (HAS_AS_SDP(display)) {
> >   		crtc_state->vrr.vsync_start =
> >   			(crtc_state->hw.adjusted_mode.crtc_vtotal -

Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Borah, Chaitanya Kumar]

On 7/13/2026 6:31 PM, Golani, Mitulkumar Ajitkumar wrote:
> 
> 
>> -----Original Message-----
>> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
>> Sent: 06 July 2026 17:29
>> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>
>> Subject: Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings
>> generically
>>
>>
>>
>> On 6/16/2026 8:12 PM, Mitul Golani wrote:
>>> Replace the disabled,
>>
>> I guess it is still disabled at this point, so the commit message is a bit
>> misleading.
>>
>> eDP-only,
>>
>> Should be a separate patch.
>>
>> fractional-CMRR code
>>> with a generic, transcoder-agnostic computation driven by an explicit
>>> per-CRTC target. Compute CMRR_M and CMRR_N timings based on video
>> mode
>>> reqirement
>>
>> typo
>>
>>    if CMRR is required to be enabled.
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    .../drm/i915/display/intel_display_types.h    |   2 +
>>>    drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
>>>    2 files changed, 63 insertions(+), 60 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 897a1ffd7b79..39e11362630c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1548,6 +1548,8 @@ struct intel_crtc {
>>>    	struct {
>>>    		u32 numerator;
>>>    		u32 denominator;
>>> +		/* Derived during atomic check: 1000/1001 video timing
>> required */
>>> +		bool video_mode;
>>
>> I am not sure why this is needed at all, since you can just use the numerator
>> and denominator to derive if it is a video mode within compute_config.
>>
>>>    	} cmrr;
>>>
>>>    	int scanline_offset;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 41118883b845..e36c0cab096a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -26,9 +26,6 @@
>>>    #include "skl_prefill.h"
>>>    #include "skl_watermark.h"
>>>
>>> -#define FIXED_POINT_PRECISION		100
>>> -#define CMRR_PRECISION_TOLERANCE	10
>>> -
>>>    /*
>>>     * Tunable parameters for DC Balance correction.
>>>     * These are captured based on experimentations.
>>> @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct
>> intel_crtc_state *crtc_state)
>>>    	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>>>    }
>>>
>>> -static bool
>>> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
>>> +static void
>>> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>>>    {
>>>    	struct intel_display *display = to_intel_display(crtc_state);
>>> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>    	struct drm_display_mode *adjusted_mode =
>>> &crtc_state->hw.adjusted_mode;
>>> -
>>> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
>>> -	if (!HAS_CMRR(display) || true)
>>> -		return false;
>>> -
>>> -	actual_refresh_k =
>>> -		drm_mode_vrefresh(adjusted_mode) *
>> FIXED_POINT_PRECISION;
>>> -	pixel_clock_per_line =
>>> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
>>> crtc_htotal;
>>> -	calculated_refresh_k =
>>> -		pixel_clock_per_line * FIXED_POINT_PRECISION /
>> adjusted_mode->crtc_vtotal;
>>> -
>>> -	if ((actual_refresh_k - calculated_refresh_k) <
>> CMRR_PRECISION_TOLERANCE)
>>> -		return false;
>>> -
>>> -	return true;
>>> -}
>>> -
>>> -static unsigned int
>>> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
>>> video_mode_required) -{
>>> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
>>>    	u64 adjusted_pixel_rate;
>>> -	struct drm_display_mode *adjusted_mode = &crtc_state-
>>> hw.adjusted_mode;
>>> +	int requested_refresh_rate, current_refresh_rate;
>>> +	int multiplier_m = 1, multiplier_n = 1;
>>>
>>> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
>>> +	if (!HAS_CMRR(display))
>>> +		return;
>>>
>>> -	if (video_mode_required) {
>>> -		multiplier_m = 1001;
>>> -		multiplier_n = 1000;
>>> -	}
>>> +	/* No CMRR ratio configured through debugfs */
>>> +	if (!crtc->cmrr.numerator)
>>> +		return;
>>>
>>> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
>> adjusted_mode->crtc_htotal,
>>> -					      multiplier_n);
>>> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
>>> crtc_clock * 1000, multiplier_n),
>>> -				  crtc_state->cmrr.cmrr_n);
>>> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
>> 1000, multiplier_m);
>>> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
>>> cmrr.cmrr_n);
>>> +	/*
>>> +	 * The numerator encodes the requested refresh rate in kHz, so the
>>
>> Not accurate, because numerator/divider together provides the refresh rate.
>> If anything the numerator is in mHz as commented in patch 1.
>>
>>> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
>>> +	 * refresh rate of the current mode.
>>> +	 */
>>> +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
>>
>> Integer division loses precision. It can be used in the comparison below but
>> incorrect to use it in actual M and N value calculations done later.
>>
>>> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
>>> +
>>> +	if (requested_refresh_rate != current_refresh_rate) {
>>> +		drm_dbg_kms(display->drm,
>>> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
>> does not match current mode refresh rate %d Hz\n",
>>> +				crtc->base.base.id, crtc->base.name,
>>> +				requested_refresh_rate,
>> current_refresh_rate);
>>> +		return;
>>> +	}
>>>
>>> -	return vtotal;
>>> -}
>>> +	/*
>>> +	 * A 1:1 ratio (denominator == 1000) means no video timing is
>> required
>>> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
>>> +	 */
>>> +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
>>> +	if (crtc->cmrr.video_mode) {
>>> +		multiplier_m = 1000;
>>> +		multiplier_n = 1001;
>>> +	}
>>
>> more intuitive to use names like rr_multiplier, rr_divider. Also the names are
>> reversed now.
>>
>>>
>>> -static
>>> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
>>> *crtc_state) -{
>>>    	/*
>>> -	 * TODO: Compute precise target refresh rate to determine
>>> -	 * if video_mode_required should be true. Currently set to
>>> -	 * false due to uncertainty about the precise target
>>> -	 * refresh Rate.
>>> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
>>> +	 *
>>> +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
>>> +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
>>> +	 *
>>> +	 * where multiplier_m/multiplier_n = 1000/1001 when the
>>> +	 * video timing is required, else 1/1. The integer vtotal
>>> +	 * term is tracked in SW (it is the programmed mode vtotal)
>>> +	 * while the fractional part represented by cmrr_m/cmrr_n
>>> +	 * is tracked in HW.
>>>    	 */
>>> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
>>> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
>>> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>>>
>>> -	crtc_state->cmrr.enable = true;
>>> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>
>> where do we set this flag now?
> 
> I915_MODE_FLAG_VRR is intentionally not set for CMRR. CMRR is implemented as a subset of the fixed-refresh-rate path. The older TODO in the readout predates that design decision and I'll clean it up. cmrr.enable will be set in the dedicated CMRR-enable patch at the end of the series.
> 

Please call it out in the commit message. Otherwise, the change looks 
out of place.

> Regards,
> Mitul
> 
>>
>>> +	crtc_state->cmrr.cmrr_n =
>>> +		mul_u32_u32(requested_refresh_rate * adjusted_mode-
>>> crtc_htotal,
>>> +			    multiplier_m);
>>> +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
>> 1000) *
>>> +multiplier_n;
>>
>> Please align the calculation as per BSpec-68925, calculate the cmrr votal here
>> and retain the cmrr_get_vtotal semantics.
>>
>>> +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate,
>>> +crtc_state->cmrr.cmrr_n);
>>> +
>>> +	return;
>>>    }
>>>
>>>    static
>>> @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state
>> *crtc_state,
>>>    	struct intel_display *display = to_intel_display(crtc_state);
>>>    	struct intel_connector *connector =
>>>    		to_intel_connector(conn_state->connector);
>>> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
>>> -	bool is_edp = intel_dp_is_edp(intel_dp);
>>>    	struct drm_display_mode *adjusted_mode = &crtc_state-
>>> hw.adjusted_mode;
>>>    	int vmin, vmax;
>>>
>>> @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state
>> *crtc_state,
>>>    		vmax = vmin;
>>>    	}
>>>
>>> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
>>> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>>>    		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
>>> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
>>> -		intel_vrr_compute_cmrr_timings(crtc_state);
>>> -	else
>>> +	} else {
>>>    		intel_vrr_compute_fixed_rr_timings(crtc_state);
>>>
>>> +		/*
>>> +		 * CMRR is a fixed average Vtotal mode and is only computed
>> on
>>> +		 * the fixed refresh rate path. It is generic across transcoders
>>> +		 * and gated on platform support and a valid debugfs ratio.
>>> +		 */
>>> +		intel_vrr_cmrr_compute_config(crtc_state);
>>> +	}
>>> +
>>>    	if (HAS_AS_SDP(display)) {
>>>    		crtc_state->vrr.vsync_start =
>>>    			(crtc_state->hw.adjusted_mode.crtc_vtotal -
> 

RE: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 06 July 2026 17:29
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings
> generically
> 
> 
> 
> On 6/16/2026 8:12 PM, Mitul Golani wrote:
> > Replace the disabled,
> 
> I guess it is still disabled at this point, so the commit message is a bit
> misleading.
> 
> eDP-only,
> 
> Should be a separate patch.

Since this patch rewrites the CMRR compute path as a transcoder-agnostic helper, keeping the old eDP-only gate did not make sense; if this is acceptable, I’ll call this out explicitly in the commit message.

> 
> fractional-CMRR code
> > with a generic, transcoder-agnostic computation driven by an explicit
> > per-CRTC target. Compute CMRR_M and CMRR_N timings based on video
> mode
> > reqirement
> 
> typo
> 
>   if CMRR is required to be enabled.

I will update with next revision. 

Thanks

> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   .../drm/i915/display/intel_display_types.h    |   2 +
> >   drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
> >   2 files changed, 63 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 897a1ffd7b79..39e11362630c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1548,6 +1548,8 @@ struct intel_crtc {
> >   	struct {
> >   		u32 numerator;
> >   		u32 denominator;
> > +		/* Derived during atomic check: 1000/1001 video timing
> required */
> > +		bool video_mode;
> 
> I am not sure why this is needed at all, since you can just use the numerator
> and denominator to derive if it is a video mode within compute_config.

Agree, Same opinion  from Jani too. I will update in next revision.

> 
> >   	} cmrr;
> >
> >   	int scanline_offset;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 41118883b845..e36c0cab096a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -26,9 +26,6 @@
> >   #include "skl_prefill.h"
> >   #include "skl_watermark.h"
> >
> > -#define FIXED_POINT_PRECISION		100
> > -#define CMRR_PRECISION_TOLERANCE	10
> > -
> >   /*
> >    * Tunable parameters for DC Balance correction.
> >    * These are captured based on experimentations.
> > @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct
> intel_crtc_state *crtc_state)
> >   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
> >   }
> >
> > -static bool
> > -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> > +static void
> > +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_display_mode *adjusted_mode =
> > &crtc_state->hw.adjusted_mode;
> > -
> > -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> > -	if (!HAS_CMRR(display) || true)
> > -		return false;
> > -
> > -	actual_refresh_k =
> > -		drm_mode_vrefresh(adjusted_mode) *
> FIXED_POINT_PRECISION;
> > -	pixel_clock_per_line =
> > -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
> >crtc_htotal;
> > -	calculated_refresh_k =
> > -		pixel_clock_per_line * FIXED_POINT_PRECISION /
> adjusted_mode->crtc_vtotal;
> > -
> > -	if ((actual_refresh_k - calculated_refresh_k) <
> CMRR_PRECISION_TOLERANCE)
> > -		return false;
> > -
> > -	return true;
> > -}
> > -
> > -static unsigned int
> > -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
> > video_mode_required) -{
> > -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> >   	u64 adjusted_pixel_rate;
> > -	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	int requested_refresh_rate, current_refresh_rate;
> > +	int multiplier_m = 1, multiplier_n = 1;
> >
> > -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +	if (!HAS_CMRR(display))
> > +		return;
> >
> > -	if (video_mode_required) {
> > -		multiplier_m = 1001;
> > -		multiplier_n = 1000;
> > -	}
> > +	/* No CMRR ratio configured through debugfs */
> > +	if (!crtc->cmrr.numerator)
> > +		return;
> >
> > -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
> adjusted_mode->crtc_htotal,
> > -					      multiplier_n);
> > -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
> >crtc_clock * 1000, multiplier_n),
> > -				  crtc_state->cmrr.cmrr_n);
> > -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
> 1000, multiplier_m);
> > -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
> >cmrr.cmrr_n);
> > +	/*
> > +	 * The numerator encodes the requested refresh rate in kHz, so the
> 
> Not accurate, because numerator/divider together provides the refresh rate.
> If anything the numerator is in mHz as commented in patch 1.
> 
> > +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> > +	 * refresh rate of the current mode.
> > +	 */
> > +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
> 
> Integer division loses precision. It can be used in the comparison below but
> incorrect to use it in actual M and N value calculations done later.

Good catch, I agree, this will loose precision later. I will fix this in next revision.

> 
> > +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +
> > +	if (requested_refresh_rate != current_refresh_rate) {
> > +		drm_dbg_kms(display->drm,
> > +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
> does not match current mode refresh rate %d Hz\n",
> > +				crtc->base.base.id, crtc->base.name,
> > +				requested_refresh_rate,
> current_refresh_rate);
> > +		return;
> > +	}
> >
> > -	return vtotal;
> > -}
> > +	/*
> > +	 * A 1:1 ratio (denominator == 1000) means no video timing is
> required
> > +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> > +	 */
> > +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
> > +	if (crtc->cmrr.video_mode) {
> > +		multiplier_m = 1000;
> > +		multiplier_n = 1001;
> > +	}
> 
> more intuitive to use names like rr_multiplier, rr_divider. Also the names are
> reversed now.

No worries, In-intention to create better readability of this code, I will update in next revision, although these names were picked based on existing algo jargons from Bspec.

> 
> >
> > -static
> > -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
> > *crtc_state) -{
> >   	/*
> > -	 * TODO: Compute precise target refresh rate to determine
> > -	 * if video_mode_required should be true. Currently set to
> > -	 * false due to uncertainty about the precise target
> > -	 * refresh Rate.
> > +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> > +	 *
> > +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
> > +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> > +	 *
> > +	 * where multiplier_m/multiplier_n = 1000/1001 when the
> > +	 * video timing is required, else 1/1. The integer vtotal
> > +	 * term is tracked in SW (it is the programmed mode vtotal)
> > +	 * while the fractional part represented by cmrr_m/cmrr_n
> > +	 * is tracked in HW.
> >   	 */
> > -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> > -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> > -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> >
> > -	crtc_state->cmrr.enable = true;
> > -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> 
> where do we set this flag now?
> 
> > +	crtc_state->cmrr.cmrr_n =
> > +		mul_u32_u32(requested_refresh_rate * adjusted_mode-
> >crtc_htotal,
> > +			    multiplier_m);
> > +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
> 1000) *
> > +multiplier_n;
> 
> Please align the calculation as per BSpec-68925, calculate the cmrr votal here
> and retain the cmrr_get_vtotal semantics.
> 
> > +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate,
> > +crtc_state->cmrr.cmrr_n);
> > +
> > +	return;
> >   }
> >
> >   static
> > @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   	struct intel_display *display = to_intel_display(crtc_state);
> >   	struct intel_connector *connector =
> >   		to_intel_connector(conn_state->connector);
> > -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> > -	bool is_edp = intel_dp_is_edp(intel_dp);
> >   	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> >   	int vmin, vmax;
> >
> > @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   		vmax = vmin;
> >   	}
> >
> > -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> > +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
> >   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> > -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> > -		intel_vrr_compute_cmrr_timings(crtc_state);
> > -	else
> > +	} else {
> >   		intel_vrr_compute_fixed_rr_timings(crtc_state);
> >
> > +		/*
> > +		 * CMRR is a fixed average Vtotal mode and is only computed
> on
> > +		 * the fixed refresh rate path. It is generic across transcoders
> > +		 * and gated on platform support and a valid debugfs ratio.
> > +		 */
> > +		intel_vrr_cmrr_compute_config(crtc_state);
> > +	}
> > +
> >   	if (HAS_AS_SDP(display)) {
> >   		crtc_state->vrr.vsync_start =
> >   			(crtc_state->hw.adjusted_mode.crtc_vtotal -

Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically

[Borah, Chaitanya Kumar]

On 7/13/2026 7:27 PM, Golani, Mitulkumar Ajitkumar wrote:
> 
> 
>> -----Original Message-----
>> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
>> Sent: 06 July 2026 17:29
>> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>
>> Subject: Re: [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings
>> generically
>>
>>
>>
>> On 6/16/2026 8:12 PM, Mitul Golani wrote:
>>> Replace the disabled,
>>
>> I guess it is still disabled at this point, so the commit message is a bit
>> misleading.
>>
>> eDP-only,
>>
>> Should be a separate patch.
> 
> Since this patch rewrites the CMRR compute path as a transcoder-agnostic helper, keeping the old eDP-only gate did not make sense; if this is acceptable, I’ll call this out explicitly in the commit message.
> 

I guess this would work because the whole CMRR path currently is dead 
code anyway. Making it explicit in the commit message should be fine.
Same goes for the disabling part.

>>
>> fractional-CMRR code
>>> with a generic, transcoder-agnostic computation driven by an explicit
>>> per-CRTC target. Compute CMRR_M and CMRR_N timings based on video
>> mode
>>> reqirement
>>
>> typo
>>
>>    if CMRR is required to be enabled.
> 
> I will update with next revision.
> 
> Thanks
> 
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    .../drm/i915/display/intel_display_types.h    |   2 +
>>>    drivers/gpu/drm/i915/display/intel_vrr.c      | 121 +++++++++---------
>>>    2 files changed, 63 insertions(+), 60 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 897a1ffd7b79..39e11362630c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1548,6 +1548,8 @@ struct intel_crtc {
>>>    	struct {
>>>    		u32 numerator;
>>>    		u32 denominator;
>>> +		/* Derived during atomic check: 1000/1001 video timing
>> required */
>>> +		bool video_mode;
>>
>> I am not sure why this is needed at all, since you can just use the numerator
>> and denominator to derive if it is a video mode within compute_config.
> 
> Agree, Same opinion  from Jani too. I will update in next revision.
> 
>>
>>>    	} cmrr;
>>>
>>>    	int scanline_offset;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 41118883b845..e36c0cab096a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -26,9 +26,6 @@
>>>    #include "skl_prefill.h"
>>>    #include "skl_watermark.h"
>>>
>>> -#define FIXED_POINT_PRECISION		100
>>> -#define CMRR_PRECISION_TOLERANCE	10
>>> -
>>>    /*
>>>     * Tunable parameters for DC Balance correction.
>>>     * These are captured based on experimentations.
>>> @@ -186,69 +183,69 @@ int intel_vrr_vmax_vblank_start(const struct
>> intel_crtc_state *crtc_state)
>>>    	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>>>    }
>>>
>>> -static bool
>>> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
>>> +static void
>>> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>>>    {
>>>    	struct intel_display *display = to_intel_display(crtc_state);
>>> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>    	struct drm_display_mode *adjusted_mode =
>>> &crtc_state->hw.adjusted_mode;
>>> -
>>> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
>>> -	if (!HAS_CMRR(display) || true)
>>> -		return false;
>>> -
>>> -	actual_refresh_k =
>>> -		drm_mode_vrefresh(adjusted_mode) *
>> FIXED_POINT_PRECISION;
>>> -	pixel_clock_per_line =
>>> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
>>> crtc_htotal;
>>> -	calculated_refresh_k =
>>> -		pixel_clock_per_line * FIXED_POINT_PRECISION /
>> adjusted_mode->crtc_vtotal;
>>> -
>>> -	if ((actual_refresh_k - calculated_refresh_k) <
>> CMRR_PRECISION_TOLERANCE)
>>> -		return false;
>>> -
>>> -	return true;
>>> -}
>>> -
>>> -static unsigned int
>>> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
>>> video_mode_required) -{
>>> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
>>>    	u64 adjusted_pixel_rate;
>>> -	struct drm_display_mode *adjusted_mode = &crtc_state-
>>> hw.adjusted_mode;
>>> +	int requested_refresh_rate, current_refresh_rate;
>>> +	int multiplier_m = 1, multiplier_n = 1;
>>>
>>> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
>>> +	if (!HAS_CMRR(display))
>>> +		return;
>>>
>>> -	if (video_mode_required) {
>>> -		multiplier_m = 1001;
>>> -		multiplier_n = 1000;
>>> -	}
>>> +	/* No CMRR ratio configured through debugfs */
>>> +	if (!crtc->cmrr.numerator)
>>> +		return;
>>>
>>> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
>> adjusted_mode->crtc_htotal,
>>> -					      multiplier_n);
>>> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
>>> crtc_clock * 1000, multiplier_n),
>>> -				  crtc_state->cmrr.cmrr_n);
>>> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
>> 1000, multiplier_m);
>>> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
>>> cmrr.cmrr_n);
>>> +	/*
>>> +	 * The numerator encodes the requested refresh rate in kHz, so the
>>
>> Not accurate, because numerator/divider together provides the refresh rate.
>> If anything the numerator is in mHz as commented in patch 1.
>>
>>> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
>>> +	 * refresh rate of the current mode.
>>> +	 */
>>> +	requested_refresh_rate = crtc->cmrr.numerator / 1000;
>>
>> Integer division loses precision. It can be used in the comparison below but
>> incorrect to use it in actual M and N value calculations done later.
> 
> Good catch, I agree, this will loose precision later. I will fix this in next revision.
> 
>>
>>> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
>>> +
>>> +	if (requested_refresh_rate != current_refresh_rate) {
>>> +		drm_dbg_kms(display->drm,
>>> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
>> does not match current mode refresh rate %d Hz\n",
>>> +				crtc->base.base.id, crtc->base.name,
>>> +				requested_refresh_rate,
>> current_refresh_rate);
>>> +		return;
>>> +	}
>>>
>>> -	return vtotal;
>>> -}
>>> +	/*
>>> +	 * A 1:1 ratio (denominator == 1000) means no video timing is
>> required
>>> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
>>> +	 */
>>> +	crtc->cmrr.video_mode = crtc->cmrr.denominator != 1000;
>>> +	if (crtc->cmrr.video_mode) {
>>> +		multiplier_m = 1000;
>>> +		multiplier_n = 1001;
>>> +	}
>>
>> more intuitive to use names like rr_multiplier, rr_divider. Also the names are
>> reversed now.
> 
> No worries, In-intention to create better readability of this code, I will update in next revision, although these names were picked based on existing algo jargons from Bspec.
> 
>>
>>>
>>> -static
>>> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
>>> *crtc_state) -{
>>>    	/*
>>> -	 * TODO: Compute precise target refresh rate to determine
>>> -	 * if video_mode_required should be true. Currently set to
>>> -	 * false due to uncertainty about the precise target
>>> -	 * refresh Rate.
>>> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
>>> +	 *
>>> +	 * cmrr_n = requested_refresh_rate x htotal x multiplier_m
>>> +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
>>> +	 *
>>> +	 * where multiplier_m/multiplier_n = 1000/1001 when the
>>> +	 * video timing is required, else 1/1. The integer vtotal
>>> +	 * term is tracked in SW (it is the programmed mode vtotal)
>>> +	 * while the fractional part represented by cmrr_m/cmrr_n
>>> +	 * is tracked in HW.
>>>    	 */
>>> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
>>> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
>>> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>>>
>>> -	crtc_state->cmrr.enable = true;
>>> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>
>> where do we set this flag now?
>>
>>> +	crtc_state->cmrr.cmrr_n =
>>> +		mul_u32_u32(requested_refresh_rate * adjusted_mode-
>>> crtc_htotal,
>>> +			    multiplier_m);
>>> +	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
>> 1000) *
>>> +multiplier_n;
>>
>> Please align the calculation as per BSpec-68925, calculate the cmrr votal here
>> and retain the cmrr_get_vtotal semantics.
>>
>>> +	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate,
>>> +crtc_state->cmrr.cmrr_n);
>>> +
>>> +	return;
>>>    }
>>>
>>>    static
>>> @@ -424,8 +421,6 @@ intel_vrr_compute_config(struct intel_crtc_state
>> *crtc_state,
>>>    	struct intel_display *display = to_intel_display(crtc_state);
>>>    	struct intel_connector *connector =
>>>    		to_intel_connector(conn_state->connector);
>>> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
>>> -	bool is_edp = intel_dp_is_edp(intel_dp);
>>>    	struct drm_display_mode *adjusted_mode = &crtc_state-
>>> hw.adjusted_mode;
>>>    	int vmin, vmax;
>>>
>>> @@ -459,13 +454,19 @@ intel_vrr_compute_config(struct intel_crtc_state
>> *crtc_state,
>>>    		vmax = vmin;
>>>    	}
>>>
>>> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
>>> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>>>    		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
>>> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
>>> -		intel_vrr_compute_cmrr_timings(crtc_state);
>>> -	else
>>> +	} else {
>>>    		intel_vrr_compute_fixed_rr_timings(crtc_state);
>>>
>>> +		/*
>>> +		 * CMRR is a fixed average Vtotal mode and is only computed
>> on
>>> +		 * the fixed refresh rate path. It is generic across transcoders
>>> +		 * and gated on platform support and a valid debugfs ratio.
>>> +		 */
>>> +		intel_vrr_cmrr_compute_config(crtc_state);
>>> +	}
>>> +
>>>    	if (HAS_AS_SDP(display)) {
>>>    		crtc_state->vrr.vsync_start =
>>>    			(crtc_state->hw.adjusted_mode.crtc_vtotal -
> 

[PATCH v2 03/11] drm/i915/vrr: dump CMRR state in the crtc state dump

[Mitul Golani]

Add crtc state dump for CMRR.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4493483f10a9..3a530be64e40 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -311,6 +311,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->vrr.dc_balance.max_increase,
 		   pipe_config->vrr.dc_balance.max_decrease,
 		   pipe_config->vrr.dc_balance.vblank_target);
+	drm_printf(&p, "cmrr: %s, video mode: %s, cmrr_m: %llu, cmrr_n: %llu\n",
+		   str_yes_no(pipe_config->cmrr.enable),
+		   str_yes_no(crtc->cmrr.video_mode),
+		   pipe_config->cmrr.cmrr_m, pipe_config->cmrr.cmrr_n);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v2 04/11] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Mitul Golani]

Move CMRR register writes to fix refresh rate register write path
to consolidate with fix refresh rate implementation.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e36c0cab096a..5678c3a86796 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -329,6 +329,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+		intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+	}
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
@@ -641,17 +652,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->cmrr.enable) {
-		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_n));
-		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_n));
-	}
-
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 	intel_cmtg_set_vrr_timings(crtc_state);
 
-- 
2.48.1

[PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions

[Mitul Golani]

Enable or disable CMRR based on it is being computed and set of
preconditions. Should be enabled when dueing adaptive mode as well
as conditions which sets cmrr.enable gets set similarly to disable case.
Also separate out register writes for both enable and disable case.

Remove VRR_CTL_CMRR_ENABLE write in the current path, add the same
when actually CMRR is enabled.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 81 ++++++++++++++++++++++--
 1 file changed, 76 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5678c3a86796..c979950d32cb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -34,6 +34,43 @@
 #define DCB_CORRECTION_AGGRESSIVENESS	1000 /* ms × 100; 10 ms */
 #define DCB_BLANK_TARGET		50
 
+#define is_enabling(feature, old_crtc_state, new_crtc_state) \
+	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
+	 (new_crtc_state)->feature)
+#define is_disabling(feature, old_crtc_state, new_crtc_state) \
+	((old_crtc_state)->feature && \
+	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
+
+static bool intel_crtc_cmrr_enabling(struct intel_atomic_state *state,
+				     struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!new_crtc_state->hw.active)
+		return false;
+
+	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+		(new_crtc_state->cmrr.enable);
+}
+
+static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!new_crtc_state->hw.active)
+		return false;
+
+	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+			(old_crtc_state->cmrr.enable);
+}
+
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
@@ -831,6 +868,34 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_hw_flipline(crtc_state) - 1);
 }
 
+static void
+intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->cmrr.cmrr_n));
+}
+
+static void
+intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
+}
+
 static void
 intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 {
@@ -934,8 +999,6 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
 	 * when enabling CMRR (but not when disabling CMRR?).
 	 */
-	if (cmrr_enable)
-		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 
@@ -962,10 +1025,15 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	if (!crtc_state->vrr.enable)
 		return;
 
+	if (intel_crtc_cmrr_disabling(state, crtc))
+		intel_vrr_disable_cmrr(crtc_state);
+
 	intel_vrr_set_vrr_timings(crtc_state);
 	intel_vrr_enable_dc_balancing(crtc_state);
 
@@ -976,6 +1044,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
+	struct intel_atomic_state *state = to_intel_atomic_state(old_crtc_state->uapi.state);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
 	if (!old_crtc_state->vrr.enable)
 		return;
@@ -984,6 +1054,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 		intel_vrr_tg_disable(old_crtc_state);
 
 	intel_vrr_disable_dc_balancing(old_crtc_state);
+
+	if (intel_crtc_cmrr_enabling(state, crtc))
+		intel_vrr_enable_cmrr(old_crtc_state);
+
 	intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state->cpu_transcoder);
 }
 
@@ -1066,9 +1140,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	if (HAS_CMRR(display))
-		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
-
 	if (crtc_state->cmrr.enable) {
 		crtc_state->cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
-- 
2.48.1

Re: [PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions

[Borah, Chaitanya Kumar]

On 6/16/2026 8:12 PM, Mitul Golani wrote:
> Enable or disable CMRR based on it is being computed and set of
> preconditions. Should be enabled when dueing adaptive mode as well
> as conditions which sets cmrr.enable gets set similarly to disable case.
> Also separate out register writes for both enable and disable case.
> 

The intention of this patch is unclear to me.

> Remove VRR_CTL_CMRR_ENABLE write in the current path, add the same
> when actually CMRR is enabled.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 81 ++++++++++++++++++++++--
>   1 file changed, 76 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5678c3a86796..c979950d32cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -34,6 +34,43 @@
>   #define DCB_CORRECTION_AGGRESSIVENESS	1000 /* ms × 100; 10 ms */
>   #define DCB_BLANK_TARGET		50
>   
> +#define is_enabling(feature, old_crtc_state, new_crtc_state) \
> +	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
> +	 (new_crtc_state)->feature)
> +#define is_disabling(feature, old_crtc_state, new_crtc_state) \
> +	((old_crtc_state)->feature && \
> +	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
> +
> +static bool intel_crtc_cmrr_enabling(struct intel_atomic_state *state,
> +				     struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!new_crtc_state->hw.active)
> +		return false;
> +
> +	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> +		(new_crtc_state->cmrr.enable);
> +}
> +
> +static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!new_crtc_state->hw.active)
> +		return false;
> +
> +	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> +			(old_crtc_state->cmrr.enable);
> +}
> +
>   bool intel_vrr_is_capable(struct intel_connector *connector)
>   {
>   	struct intel_display *display = to_intel_display(connector);
> @@ -831,6 +868,34 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
>   }
>   
> +static void
> +intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->cmrr.cmrr_n));
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->cmrr.cmrr_n));
> +}
> +
> +static void
> +intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
> +}
> +
>   static void
>   intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
>   {
> @@ -934,8 +999,6 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
>   	 * when enabling CMRR (but not when disabling CMRR?).
>   	 */
> -	if (cmrr_enable)
> -		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
>   
> @@ -962,10 +1025,15 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   
>   	if (!crtc_state->vrr.enable)
>   		return;
>   
> +	if (intel_crtc_cmrr_disabling(state, crtc))
> +		intel_vrr_disable_cmrr(crtc_state);
> +
>   	intel_vrr_set_vrr_timings(crtc_state);
>   	intel_vrr_enable_dc_balancing(crtc_state);
>   
> @@ -976,6 +1044,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
> +	struct intel_atomic_state *state = to_intel_atomic_state(old_crtc_state->uapi.state);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>   
>   	if (!old_crtc_state->vrr.enable)
>   		return;
> @@ -984,6 +1054,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   		intel_vrr_tg_disable(old_crtc_state);
>   
>   	intel_vrr_disable_dc_balancing(old_crtc_state);
> +
> +	if (intel_crtc_cmrr_enabling(state, crtc))
> +		intel_vrr_enable_cmrr(old_crtc_state);
> +
>   	intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state->cpu_transcoder);
>   }
>   
> @@ -1066,9 +1140,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   	trans_vrr_ctl = intel_de_read(display,
>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>   
> -	if (HAS_CMRR(display))
> -		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
> -
>   	if (crtc_state->cmrr.enable) {
>   		crtc_state->cmrr.cmrr_n =
>   			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));

RE: [PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 06 July 2026 17:30
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on
> enable/disable preconditions
> 
> 
> 
> On 6/16/2026 8:12 PM, Mitul Golani wrote:
> > Enable or disable CMRR based on it is being computed and set of
> > preconditions. Should be enabled when dueing adaptive mode as well as
> > conditions which sets cmrr.enable gets set similarly to disable case.
> > Also separate out register writes for both enable and disable case.
> >
> 
> The intention of this patch is unclear to me.

You're right that the intent was muddled, thanks. I've reworked the patch to be much simpler, will float with next revision.

> 
> > Remove VRR_CTL_CMRR_ENABLE write in the current path, add the same
> > when actually CMRR is enabled.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 81 ++++++++++++++++++++++--
> >   1 file changed, 76 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 5678c3a86796..c979950d32cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -34,6 +34,43 @@
> >   #define DCB_CORRECTION_AGGRESSIVENESS	1000 /* ms × 100; 10
> ms */
> >   #define DCB_BLANK_TARGET		50
> >
> > +#define is_enabling(feature, old_crtc_state, new_crtc_state) \
> > +	((!(old_crtc_state)->feature ||
> intel_crtc_needs_modeset(new_crtc_state)) && \
> > +	 (new_crtc_state)->feature)
> > +#define is_disabling(feature, old_crtc_state, new_crtc_state) \
> > +	((old_crtc_state)->feature && \
> > +	 (!(new_crtc_state)->feature ||
> > +intel_crtc_needs_modeset(new_crtc_state)))
> > +
> > +static bool intel_crtc_cmrr_enabling(struct intel_atomic_state *state,
> > +				     struct intel_crtc *crtc)
> > +{
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +
> > +	if (!new_crtc_state->hw.active)
> > +		return false;
> > +
> > +	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> > +		(new_crtc_state->cmrr.enable);
> > +}
> > +
> > +static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
> > +				      struct intel_crtc *crtc)
> > +{
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +
> > +	if (!new_crtc_state->hw.active)
> > +		return false;
> > +
> > +	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> > +			(old_crtc_state->cmrr.enable);
> > +}
> > +
> >   bool intel_vrr_is_capable(struct intel_connector *connector)
> >   {
> >   	struct intel_display *display = to_intel_display(connector); @@
> > -831,6 +868,34 @@ static void intel_vrr_set_vrr_timings(const struct
> intel_crtc_state *crtc_state)
> >   		       intel_vrr_hw_flipline(crtc_state) - 1);
> >   }
> >
> > +static void
> > +intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> > +		       upper_32_bits(crtc_state->cmrr.cmrr_m));
> > +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> > +		       lower_32_bits(crtc_state->cmrr.cmrr_m));
> > +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> > +		       upper_32_bits(crtc_state->cmrr.cmrr_n));
> > +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> > +		       lower_32_bits(crtc_state->cmrr.cmrr_n));
> > +}
> > +
> > +static void
> > +intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> 0);
> > +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> > +0); }
> > +
> >   static void
> >   intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> >   {
> > @@ -934,8 +999,6 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
> >   	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
> >   	 * when enabling CMRR (but not when disabling CMRR?).
> >   	 */
> > -	if (cmrr_enable)
> > -		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> >
> >   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > vrr_ctl);
> >
> > @@ -962,10 +1025,15 @@ static void intel_vrr_tg_disable(const struct
> intel_crtc_state *old_crtc_state)
> >   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > +	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state-
> >uapi.state);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >
> >   	if (!crtc_state->vrr.enable)
> >   		return;
> >
> > +	if (intel_crtc_cmrr_disabling(state, crtc))
> > +		intel_vrr_disable_cmrr(crtc_state);
> > +
> >   	intel_vrr_set_vrr_timings(crtc_state);
> >   	intel_vrr_enable_dc_balancing(crtc_state);
> >
> > @@ -976,6 +1044,8 @@ void intel_vrr_enable(const struct intel_crtc_state
> *crtc_state)
> >   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(old_crtc_state);
> > +	struct intel_atomic_state *state =
> to_intel_atomic_state(old_crtc_state->uapi.state);
> > +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >
> >   	if (!old_crtc_state->vrr.enable)
> >   		return;
> > @@ -984,6 +1054,10 @@ void intel_vrr_disable(const struct intel_crtc_state
> *old_crtc_state)
> >   		intel_vrr_tg_disable(old_crtc_state);
> >
> >   	intel_vrr_disable_dc_balancing(old_crtc_state);
> > +
> > +	if (intel_crtc_cmrr_enabling(state, crtc))
> > +		intel_vrr_enable_cmrr(old_crtc_state);
> > +
> >   	intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state-
> >cpu_transcoder);
> >   }
> >
> > @@ -1066,9 +1140,6 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> >   	trans_vrr_ctl = intel_de_read(display,
> >   				      TRANS_VRR_CTL(display,
> cpu_transcoder));
> >
> > -	if (HAS_CMRR(display))
> > -		crtc_state->cmrr.enable = (trans_vrr_ctl &
> VRR_CTL_CMRR_ENABLE);
> > -
> >   	if (crtc_state->cmrr.enable) {
> >   		crtc_state->cmrr.cmrr_n =
> >   			intel_de_read64_2x32(display,
> TRANS_CMRR_N_LO(display,
> > cpu_transcoder));

[PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state members under VRR

[Mitul Golani]

Move CMRR crtc state members under VRR infrastructure as
it is enabled during fix refresh rate  VRR timing generator
is enabled.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  4 ++--
 drivers/gpu/drm/i915/display/intel_display.c  |  4 ++--
 .../drm/i915/display/intel_display_types.h    |  5 ++++
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 24 +++++++++----------
 5 files changed, 22 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 3a530be64e40..ea337efbe524 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -312,9 +312,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->vrr.dc_balance.max_decrease,
 		   pipe_config->vrr.dc_balance.vblank_target);
 	drm_printf(&p, "cmrr: %s, video mode: %s, cmrr_m: %llu, cmrr_n: %llu\n",
-		   str_yes_no(pipe_config->cmrr.enable),
+		   str_yes_no(pipe_config->vrr.cmrr.enable),
 		   str_yes_no(crtc->cmrr.video_mode),
-		   pipe_config->cmrr.cmrr_m, pipe_config->cmrr.cmrr_n);
+		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e76aa6c8dab6..e067d484858f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -949,8 +949,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 				const struct intel_crtc_state *new_crtc_state)
 {
-	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
-		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
+		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
 }
 
 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11362630c..6096ad02ae45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1400,6 +1400,11 @@ struct intel_crtc_state {
 			u16 max_increase, max_decrease;
 			u16 vblank_target;
 		} dc_balance;
+
+		struct {
+			bool enable;
+			u64 cmrr_n, cmrr_m;
+		} cmrr;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3569e61e7fee..a9054b07d9c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3230,7 +3230,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c979950d32cb..83f25184c66c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -53,7 +53,7 @@ static bool intel_crtc_cmrr_enabling(struct intel_atomic_state *state,
 		return false;
 
 	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
-		(new_crtc_state->cmrr.enable);
+		(new_crtc_state->vrr.cmrr.enable);
 }
 
 static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
@@ -68,7 +68,7 @@ static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
 		return false;
 
 	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
-			(old_crtc_state->cmrr.enable);
+			(old_crtc_state->vrr.cmrr.enable);
 }
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
@@ -276,11 +276,11 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	 * is tracked in HW.
 	 */
 
-	crtc_state->cmrr.cmrr_n =
+	crtc_state->vrr.cmrr.cmrr_n =
 		mul_u32_u32(requested_refresh_rate * adjusted_mode->crtc_htotal,
 			    multiplier_m);
 	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
-	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
 
 	return;
 }
@@ -875,13 +875,13 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-		       upper_32_bits(crtc_state->cmrr.cmrr_m));
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-		       lower_32_bits(crtc_state->cmrr.cmrr_m));
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-		       upper_32_bits(crtc_state->cmrr.cmrr_n));
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-		       lower_32_bits(crtc_state->cmrr.cmrr_n));
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 }
 
 static void
@@ -1038,7 +1038,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
+		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1140,10 +1140,10 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	if (crtc_state->cmrr.enable) {
-		crtc_state->cmrr.cmrr_n =
+	if (crtc_state->vrr.cmrr.enable) {
+		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
-		crtc_state->cmrr.cmrr_m =
+		crtc_state->vrr.cmrr.cmrr_m =
 			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
 	}
 
-- 
2.48.1

Re: [PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state members under VRR

[Jani Nikula]

On Tue, 16 Jun 2026, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Move CMRR crtc state members under VRR infrastructure as
> it is enabled during fix refresh rate  VRR timing generator
> is enabled.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  4 ++--
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++--
>  .../drm/i915/display/intel_display_types.h    |  5 ++++
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 24 +++++++++----------
>  5 files changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 3a530be64e40..ea337efbe524 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -312,9 +312,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  		   pipe_config->vrr.dc_balance.max_decrease,
>  		   pipe_config->vrr.dc_balance.vblank_target);
>  	drm_printf(&p, "cmrr: %s, video mode: %s, cmrr_m: %llu, cmrr_n: %llu\n",
> -		   str_yes_no(pipe_config->cmrr.enable),
> +		   str_yes_no(pipe_config->vrr.cmrr.enable),
>  		   str_yes_no(crtc->cmrr.video_mode),
> -		   pipe_config->cmrr.cmrr_m, pipe_config->cmrr.cmrr_n);
> +		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
>  
>  	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
>  		   DRM_MODE_ARG(&pipe_config->hw.mode));
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e76aa6c8dab6..e067d484858f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -949,8 +949,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>  static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>  				const struct intel_crtc_state *new_crtc_state)
>  {
> -	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> -		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> +	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
> +		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
>  }
>  
>  static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11362630c..6096ad02ae45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1400,6 +1400,11 @@ struct intel_crtc_state {
>  			u16 max_increase, max_decrease;
>  			u16 vblank_target;
>  		} dc_balance;
> +
> +		struct {
> +			bool enable;
> +			u64 cmrr_n, cmrr_m;
> +		} cmrr;

You're leaving the dupes behind?

>  	} vrr;
>  
>  	/* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3569e61e7fee..a9054b07d9c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3230,7 +3230,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	as_sdp->revision = 0x2;
>  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>  
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>  		as_sdp->target_rr_divider = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c979950d32cb..83f25184c66c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -53,7 +53,7 @@ static bool intel_crtc_cmrr_enabling(struct intel_atomic_state *state,
>  		return false;
>  
>  	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> -		(new_crtc_state->cmrr.enable);
> +		(new_crtc_state->vrr.cmrr.enable);
>  }
>  
>  static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
> @@ -68,7 +68,7 @@ static bool intel_crtc_cmrr_disabling(struct intel_atomic_state *state,
>  		return false;
>  
>  	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> -			(old_crtc_state->cmrr.enable);
> +			(old_crtc_state->vrr.cmrr.enable);
>  }
>  
>  bool intel_vrr_is_capable(struct intel_connector *connector)
> @@ -276,11 +276,11 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>  	 * is tracked in HW.
>  	 */
>  
> -	crtc_state->cmrr.cmrr_n =
> +	crtc_state->vrr.cmrr.cmrr_n =
>  		mul_u32_u32(requested_refresh_rate * adjusted_mode->crtc_htotal,
>  			    multiplier_m);
>  	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
>  
>  	return;
>  }
> @@ -875,13 +875,13 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> -		       upper_32_bits(crtc_state->cmrr.cmrr_m));
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>  	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> -		       lower_32_bits(crtc_state->cmrr.cmrr_m));
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>  	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> -		       upper_32_bits(crtc_state->cmrr.cmrr_n));
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>  	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> -		       lower_32_bits(crtc_state->cmrr.cmrr_n));
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>  }
>  
>  static void
> @@ -1038,7 +1038,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>  	intel_vrr_enable_dc_balancing(crtc_state);
>  
>  	if (!intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> +		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
>  }
>  
>  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1140,10 +1140,10 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	trans_vrr_ctl = intel_de_read(display,
>  				      TRANS_VRR_CTL(display, cpu_transcoder));
>  
> -	if (crtc_state->cmrr.enable) {
> -		crtc_state->cmrr.cmrr_n =
> +	if (crtc_state->vrr.cmrr.enable) {
> +		crtc_state->vrr.cmrr.cmrr_n =
>  			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
> -		crtc_state->cmrr.cmrr_m =
> +		crtc_state->vrr.cmrr.cmrr_m =
>  			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
>  	}

-- 
Jani Nikula, Intel

RE: [PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state members under VRR

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: 17 June 2026 17:32
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Borah, Chaitanya Kumar
> <chaitanya.kumar.borah@intel.com>
> Subject: Re: [PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state
> members under VRR
> 
> On Tue, 16 Jun 2026, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> wrote:
> > Move CMRR crtc state members under VRR infrastructure as it is enabled
> > during fix refresh rate  VRR timing generator is enabled.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >  .../drm/i915/display/intel_crtc_state_dump.c  |  4 ++--
> > drivers/gpu/drm/i915/display/intel_display.c  |  4 ++--
> >  .../drm/i915/display/intel_display_types.h    |  5 ++++
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> >  drivers/gpu/drm/i915/display/intel_vrr.c      | 24 +++++++++----------
> >  5 files changed, 22 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > index 3a530be64e40..ea337efbe524 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > @@ -312,9 +312,9 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> >  		   pipe_config->vrr.dc_balance.max_decrease,
> >  		   pipe_config->vrr.dc_balance.vblank_target);
> >  	drm_printf(&p, "cmrr: %s, video mode: %s, cmrr_m: %llu, cmrr_n:
> %llu\n",
> > -		   str_yes_no(pipe_config->cmrr.enable),
> > +		   str_yes_no(pipe_config->vrr.cmrr.enable),
> >  		   str_yes_no(crtc->cmrr.video_mode),
> > -		   pipe_config->cmrr.cmrr_m, pipe_config->cmrr.cmrr_n);
> > +		   pipe_config->vrr.cmrr.cmrr_m, pipe_config-
> >vrr.cmrr.cmrr_n);
> >
> >  	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
> >  		   DRM_MODE_ARG(&pipe_config->hw.mode));
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e76aa6c8dab6..e067d484858f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -949,8 +949,8 @@ static bool vrr_params_changed(const struct
> > intel_crtc_state *old_crtc_state,  static bool cmrr_params_changed(const
> struct intel_crtc_state *old_crtc_state,
> >  				const struct intel_crtc_state *new_crtc_state)
> {
> > -	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m
> ||
> > -		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> > +	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state-
> >vrr.cmrr.cmrr_m ||
> > +		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state-
> >vrr.cmrr.cmrr_n;
> >  }
> >
> >  static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 39e11362630c..6096ad02ae45 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1400,6 +1400,11 @@ struct intel_crtc_state {
> >  			u16 max_increase, max_decrease;
> >  			u16 vblank_target;
> >  		} dc_balance;
> > +
> > +		struct {
> > +			bool enable;
> > +			u64 cmrr_n, cmrr_m;
> > +		} cmrr;
> 
> You're leaving the dupes behind?

Thanks Jani, for Review, I missed. I will update this while floating next revision.

Regards,
Mitul

> 
> >  	} vrr;
> >
> >  	/* Content Match Refresh Rate state */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 3569e61e7fee..a9054b07d9c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3230,7 +3230,7 @@ static void intel_dp_compute_as_sdp(struct
> intel_dp *intel_dp,
> >  	as_sdp->revision = 0x2;
> >  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> >
> > -	if (crtc_state->cmrr.enable) {
> > +	if (crtc_state->vrr.cmrr.enable) {
> >  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
> >  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
> >  		as_sdp->target_rr_divider = true;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index c979950d32cb..83f25184c66c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -53,7 +53,7 @@ static bool intel_crtc_cmrr_enabling(struct
> intel_atomic_state *state,
> >  		return false;
> >
> >  	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> > -		(new_crtc_state->cmrr.enable);
> > +		(new_crtc_state->vrr.cmrr.enable);
> >  }
> >
> >  static bool intel_crtc_cmrr_disabling(struct intel_atomic_state
> > *state, @@ -68,7 +68,7 @@ static bool intel_crtc_cmrr_disabling(struct
> intel_atomic_state *state,
> >  		return false;
> >
> >  	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> > -			(old_crtc_state->cmrr.enable);
> > +			(old_crtc_state->vrr.cmrr.enable);
> >  }
> >
> >  bool intel_vrr_is_capable(struct intel_connector *connector) @@
> > -276,11 +276,11 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state
> *crtc_state)
> >  	 * is tracked in HW.
> >  	 */
> >
> > -	crtc_state->cmrr.cmrr_n =
> > +	crtc_state->vrr.cmrr.cmrr_n =
> >  		mul_u32_u32(requested_refresh_rate * adjusted_mode-
> >crtc_htotal,
> >  			    multiplier_m);
> >  	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock,
> 1000) * multiplier_n;
> > -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
> >cmrr.cmrr_n);
> > +	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate,
> > +crtc_state->vrr.cmrr.cmrr_n);
> >
> >  	return;
> >  }
> > @@ -875,13 +875,13 @@ intel_vrr_enable_cmrr(const struct
> intel_crtc_state *crtc_state)
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> >  	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> > -		       upper_32_bits(crtc_state->cmrr.cmrr_m));
> > +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >  	intel_de_write(display, TRANS_CMRR_M_LO(display,
> cpu_transcoder),
> > -		       lower_32_bits(crtc_state->cmrr.cmrr_m));
> > +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >  	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> > -		       upper_32_bits(crtc_state->cmrr.cmrr_n));
> > +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >  	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> > -		       lower_32_bits(crtc_state->cmrr.cmrr_n));
> > +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >  }
> >
> >  static void
> > @@ -1038,7 +1038,7 @@ void intel_vrr_enable(const struct
> intel_crtc_state *crtc_state)
> >  	intel_vrr_enable_dc_balancing(crtc_state);
> >
> >  	if (!intel_vrr_always_use_vrr_tg(display))
> > -		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> > +		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
> >  }
> >
> >  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> > @@ -1140,10 +1140,10 @@ void intel_vrr_get_config(struct
> intel_crtc_state *crtc_state)
> >  	trans_vrr_ctl = intel_de_read(display,
> >  				      TRANS_VRR_CTL(display,
> cpu_transcoder));
> >
> > -	if (crtc_state->cmrr.enable) {
> > -		crtc_state->cmrr.cmrr_n =
> > +	if (crtc_state->vrr.cmrr.enable) {
> > +		crtc_state->vrr.cmrr.cmrr_n =
> >  			intel_de_read64_2x32(display,
> TRANS_CMRR_N_LO(display, cpu_transcoder));
> > -		crtc_state->cmrr.cmrr_m =
> > +		crtc_state->vrr.cmrr.cmrr_m =
> >  			intel_de_read64_2x32(display,
> TRANS_CMRR_M_LO(display, cpu_transcoder));
> >  	}
> 
> --
> Jani Nikula, Intel

[PATCH v2 07/11] drm/i915/vrr: Fix the CMRR enabling/disabling sequence

[Mitul Golani]

Write TRANS_CMRR_N_HI register last in the sequence of
CMRR register writes, hardware will consider this as a
marker to double buffer the registers at next rising edge
of delayed vblank. Remove the related FIXME comments.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 83f25184c66c..0113f413f04b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -878,10 +878,10 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
 		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
 		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
 		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 }
 
 static void
@@ -892,8 +892,8 @@ intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
-	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
 }
 
 static void
@@ -994,12 +994,6 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
-	/*
-	 * FIXME this might be broken as bspec seems to imply that
-	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
-	 * when enabling CMRR (but not when disabling CMRR?).
-	 */
-
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 
 	intel_cmtg_set_vrr_ctl(crtc_state);
-- 
2.48.1

[PATCH v2 08/11] drm/i915/vrr: Compare state and HW registers if platform supports CMRR

[Mitul Golani]

Irrespctive of cmrr is enabled or not, always need to check the
status of hw register write. Earlier it was masked to cmrr enable.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 0113f413f04b..b2c5b148c487 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1134,7 +1134,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	if (crtc_state->vrr.cmrr.enable) {
+	if (HAS_CMRR(display)) {
 		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
 		crtc_state->vrr.cmrr.cmrr_m =
-- 
2.48.1

[PATCH v2 09/11] drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode

[Mitul Golani]

CMRR is subset of fix refresh rate, it is exclusive from
Adaptive mode, it does not need to set a separate mode flag during
state checker. Remove the pre-added TODO for the same.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b2c5b148c487..92ded2e68b01 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1202,11 +1202,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_vrr_get_dc_balance_config(crtc_state);
 
-	/*
-	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
-	 * Since CMRR is currently disabled, set this flag for VRR for now.
-	 * Need to keep this in mind while re-enabling CMRR.
-	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 
-- 
2.48.1

Re: [PATCH v2 09/11] drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode

[Borah, Chaitanya Kumar]

On 6/16/2026 8:12 PM, Mitul Golani wrote:
> CMRR is subset of fix refresh rate, it is exclusive from
> Adaptive mode, it does not need to set a separate mode flag during
> state checker. Remove the pre-added TODO for the same.
> 

Remove it at the same patch that actually renders the comment redundant.

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 5 -----
>   1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b2c5b148c487..92ded2e68b01 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1202,11 +1202,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   
>   	intel_vrr_get_dc_balance_config(crtc_state);
>   
> -	/*
> -	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
> -	 * Since CMRR is currently disabled, set this flag for VRR for now.
> -	 * Need to keep this in mind while re-enabling CMRR.
> -	 */
>   	if (crtc_state->vrr.enable)
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   

[PATCH v2 10/11] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled

[Mitul Golani]

CMRR is mutually exclusive to PSR2, hence return from CMRR if PSR2
is already computed.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 92ded2e68b01..2d5f0f17bf3c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -233,6 +233,9 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	if (!HAS_CMRR(display))
 		return;
 
+	if (crtc_state->has_sel_update)
+		return;
+
 	/* No CMRR ratio configured through debugfs */
 	if (!crtc->cmrr.numerator)
 		return;
-- 
2.48.1

[PATCH v2 11/11] drm/i915/vrr: Enable cmrr

[Mitul Golani]

Enable CMRR during compute config and add related state
checker for the same.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2d5f0f17bf3c..9ef559195c68 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -285,6 +285,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
 	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
 
+	crtc_state->vrr.cmrr.enable = true;
+
 	return;
 }
 
@@ -876,6 +878,7 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
 		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
@@ -885,6 +888,9 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
 		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
 		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+
+	vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void
@@ -892,11 +898,15 @@ intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
+
+	vrr_ctl &= ~VRR_CTL_CMRR_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void
@@ -1138,6 +1148,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (HAS_CMRR(display)) {
+		crtc_state->vrr.cmrr.enable = trans_vrr_ctl & VRR_CTL_CMRR_ENABLE;
 		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
 		crtc_state->vrr.cmrr.cmrr_m =
-- 
2.48.1

Re: [PATCH v2 11/11] drm/i915/vrr: Enable cmrr

[Borah, Chaitanya Kumar]

On 6/16/2026 8:12 PM, Mitul Golani wrote:
> Enable CMRR during compute config and add related state
> checker for the same.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2d5f0f17bf3c..9ef559195c68 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -285,6 +285,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n;
>   	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
>   
> +	crtc_state->vrr.cmrr.enable = true;
> +
>   	return;
>   }
>   
> @@ -876,6 +878,7 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
>   
>   	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
>   		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> @@ -885,6 +888,9 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
>   		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>   	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
>   		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +
> +	vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);


This patch should only enable the feature. It should not add any new 
programming, previous patches should already handle them.

Bspec states that "TRANS_CMRR_N_HI register should be written last in 
this sequence of CMRR register writes." Please confirm if it also 
includes CMRR enable bit in TRANS_VRR_CTL.

Also, this is still true from v1 :

"The target rr divider bit is always set to true in
intel_dp_compute_as_sdp(). This is wrong for non-video mode refresh rates."

Please add change log in commit messages wherever applicable.

==
Chaitanya
>   }
>   
>   static void
> @@ -892,11 +898,15 @@ intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
>   
>   	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
>   	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
>   	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
>   	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
> +
> +	vrr_ctl &= ~VRR_CTL_CMRR_ENABLE;
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
>   }
>   
>   static void
> @@ -1138,6 +1148,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>   
>   	if (HAS_CMRR(display)) {
> +		crtc_state->vrr.cmrr.enable = trans_vrr_ctl & VRR_CTL_CMRR_ENABLE;
>   		crtc_state->vrr.cmrr.cmrr_n =
>   			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
>   		crtc_state->vrr.cmrr.cmrr_m =

✗ CI.checkpatch: warning for Enable CMRR in fixed-RR VRR path

[Patchwork]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path
URL   : https://patchwork.freedesktop.org/series/168613/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 837e6d170bd003387c28e7206e19440d5ed638e1
Author: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Date:   Tue Jun 16 20:12:32 2026 +0530

    drm/i915/vrr: Enable cmrr
    
    Enable CMRR during compute config and add related state
    checker for the same.
    
    Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+ /mt/dim checkpatch 70646d7ea3ac559ed269c0a38cd3699fea4e1eeb drm-intel
514592d1b64c drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control
2c73b5db5aa0 drm/i915/vrr: compute CMRR fractional timings generically
b5d3b3beb328 drm/i915/vrr: dump CMRR state in the crtc state dump
ebec82bb1e09 drm/i915/vrr: Move CMRR hw registers to fix refresh rate path
e54b0c4f6521 drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'feature' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:37:
+#define is_enabling(feature, old_crtc_state, new_crtc_state) \
+	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
+	 (new_crtc_state)->feature)

-:25: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'feature' may be better as '(feature)' to avoid precedence issues
#25: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:37:
+#define is_enabling(feature, old_crtc_state, new_crtc_state) \
+	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
+	 (new_crtc_state)->feature)

-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'new_crtc_state' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:37:
+#define is_enabling(feature, old_crtc_state, new_crtc_state) \
+	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
+	 (new_crtc_state)->feature)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'feature' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:40:
+#define is_disabling(feature, old_crtc_state, new_crtc_state) \
+	((old_crtc_state)->feature && \
+	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))

-:28: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'feature' may be better as '(feature)' to avoid precedence issues
#28: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:40:
+#define is_disabling(feature, old_crtc_state, new_crtc_state) \
+	((old_crtc_state)->feature && \
+	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'new_crtc_state' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:40:
+#define is_disabling(feature, old_crtc_state, new_crtc_state) \
+	((old_crtc_state)->feature && \
+	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))

total: 0 errors, 0 warnings, 6 checks, 127 lines checked
bd595cfa13d5 drm/i915/display: Move CMRR crtc_state members under VRR
376932a29bb3 drm/i915/vrr: Fix the CMRR enabling/disabling sequence
aa6b1186c1ba drm/i915/vrr: Compare state and HW registers if platform supports CMRR
6d41ece355d6 drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode
97a229846fdb drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled
837e6d170bd0 drm/i915/vrr: Enable cmrr

✓ CI.KUnit: success for Enable CMRR in fixed-RR VRR path

[Patchwork]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:59:19] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:59:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:59:54] Starting KUnit Kernel (1/1)...
[14:59:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:59:54] ================== guc_buf (11 subtests) ===================
[14:59:54] [PASSED] test_smallest
[14:59:54] [PASSED] test_largest
[14:59:54] [PASSED] test_granular
[14:59:54] [PASSED] test_unique
[14:59:54] [PASSED] test_overlap
[14:59:54] [PASSED] test_reusable
[14:59:54] [PASSED] test_too_big
[14:59:54] [PASSED] test_flush
[14:59:54] [PASSED] test_lookup
[14:59:54] [PASSED] test_data
[14:59:54] [PASSED] test_class
[14:59:54] ===================== [PASSED] guc_buf =====================
[14:59:54] =================== guc_dbm (7 subtests) ===================
[14:59:54] [PASSED] test_empty
[14:59:54] [PASSED] test_default
[14:59:54] ======================== test_size  ========================
[14:59:54] [PASSED] 4
[14:59:54] [PASSED] 8
[14:59:54] [PASSED] 32
[14:59:54] [PASSED] 256
[14:59:54] ==================== [PASSED] test_size ====================
[14:59:54] ======================= test_reuse  ========================
[14:59:54] [PASSED] 4
[14:59:54] [PASSED] 8
[14:59:54] [PASSED] 32
[14:59:54] [PASSED] 256
[14:59:54] =================== [PASSED] test_reuse ====================
[14:59:54] =================== test_range_overlap  ====================
[14:59:54] [PASSED] 4
[14:59:54] [PASSED] 8
[14:59:54] [PASSED] 32
[14:59:54] [PASSED] 256
[14:59:54] =============== [PASSED] test_range_overlap ================
[14:59:54] =================== test_range_compact  ====================
[14:59:54] [PASSED] 4
[14:59:54] [PASSED] 8
[14:59:54] [PASSED] 32
[14:59:54] [PASSED] 256
[14:59:54] =============== [PASSED] test_range_compact ================
[14:59:54] ==================== test_range_spare  =====================
[14:59:54] [PASSED] 4
[14:59:54] [PASSED] 8
[14:59:54] [PASSED] 32
[14:59:54] [PASSED] 256
[14:59:54] ================ [PASSED] test_range_spare =================
[14:59:54] ===================== [PASSED] guc_dbm =====================
[14:59:54] =================== guc_idm (6 subtests) ===================
[14:59:54] [PASSED] bad_init
[14:59:54] [PASSED] no_init
[14:59:54] [PASSED] init_fini
[14:59:54] [PASSED] check_used
[14:59:54] [PASSED] check_quota
[14:59:54] [PASSED] check_all
[14:59:54] ===================== [PASSED] guc_idm =====================
[14:59:54] ================== no_relay (3 subtests) ===================
[14:59:54] [PASSED] xe_drops_guc2pf_if_not_ready
[14:59:54] [PASSED] xe_drops_guc2vf_if_not_ready
[14:59:54] [PASSED] xe_rejects_send_if_not_ready
[14:59:54] ==================== [PASSED] no_relay =====================
[14:59:54] ================== pf_relay (14 subtests) ==================
[14:59:54] [PASSED] pf_rejects_guc2pf_too_short
[14:59:54] [PASSED] pf_rejects_guc2pf_too_long
[14:59:54] [PASSED] pf_rejects_guc2pf_no_payload
[14:59:54] [PASSED] pf_fails_no_payload
[14:59:54] [PASSED] pf_fails_bad_origin
[14:59:54] [PASSED] pf_fails_bad_type
[14:59:54] [PASSED] pf_txn_reports_error
[14:59:54] [PASSED] pf_txn_sends_pf2guc
[14:59:54] [PASSED] pf_sends_pf2guc
[14:59:54] [SKIPPED] pf_loopback_nop
[14:59:54] [SKIPPED] pf_loopback_echo
[14:59:54] [SKIPPED] pf_loopback_fail
[14:59:54] [SKIPPED] pf_loopback_busy
[14:59:54] [SKIPPED] pf_loopback_retry
[14:59:54] ==================== [PASSED] pf_relay =====================
[14:59:54] ================== vf_relay (3 subtests) ===================
[14:59:54] [PASSED] vf_rejects_guc2vf_too_short
[14:59:54] [PASSED] vf_rejects_guc2vf_too_long
[14:59:54] [PASSED] vf_rejects_guc2vf_no_payload
[14:59:54] ==================== [PASSED] vf_relay =====================
[14:59:54] ================ pf_gt_config (9 subtests) =================
[14:59:54] [PASSED] fair_contexts_1vf
[14:59:54] [PASSED] fair_doorbells_1vf
[14:59:54] [PASSED] fair_ggtt_1vf
[14:59:54] ====================== fair_vram_1vf  ======================
[14:59:54] [PASSED] 3.50 GiB
[14:59:54] [PASSED] 11.5 GiB
[14:59:54] [PASSED] 15.5 GiB
[14:59:54] [PASSED] 31.5 GiB
[14:59:54] [PASSED] 63.5 GiB
[14:59:54] [PASSED] 1.91 GiB
[14:59:54] ================== [PASSED] fair_vram_1vf ==================
[14:59:54] ================ fair_vram_1vf_admin_only  =================
[14:59:54] [PASSED] 3.50 GiB
[14:59:54] [PASSED] 11.5 GiB
[14:59:54] [PASSED] 15.5 GiB
[14:59:54] [PASSED] 31.5 GiB
[14:59:54] [PASSED] 63.5 GiB
[14:59:54] [PASSED] 1.91 GiB
[14:59:54] ============ [PASSED] fair_vram_1vf_admin_only =============
[14:59:54] ====================== fair_contexts  ======================
[14:59:54] [PASSED] 1 VF
[14:59:54] [PASSED] 2 VFs
[14:59:54] [PASSED] 3 VFs
[14:59:54] [PASSED] 4 VFs
[14:59:54] [PASSED] 5 VFs
[14:59:54] [PASSED] 6 VFs
[14:59:54] [PASSED] 7 VFs
[14:59:54] [PASSED] 8 VFs
[14:59:54] [PASSED] 9 VFs
[14:59:54] [PASSED] 10 VFs
[14:59:54] [PASSED] 11 VFs
[14:59:54] [PASSED] 12 VFs
[14:59:54] [PASSED] 13 VFs
[14:59:54] [PASSED] 14 VFs
[14:59:54] [PASSED] 15 VFs
[14:59:54] [PASSED] 16 VFs
[14:59:54] [PASSED] 17 VFs
[14:59:54] [PASSED] 18 VFs
[14:59:54] [PASSED] 19 VFs
[14:59:54] [PASSED] 20 VFs
[14:59:54] [PASSED] 21 VFs
[14:59:54] [PASSED] 22 VFs
[14:59:54] [PASSED] 23 VFs
[14:59:54] [PASSED] 24 VFs
[14:59:54] [PASSED] 25 VFs
[14:59:54] [PASSED] 26 VFs
[14:59:54] [PASSED] 27 VFs
[14:59:54] [PASSED] 28 VFs
[14:59:54] [PASSED] 29 VFs
[14:59:54] [PASSED] 30 VFs
[14:59:54] [PASSED] 31 VFs
[14:59:54] [PASSED] 32 VFs
[14:59:54] [PASSED] 33 VFs
[14:59:54] [PASSED] 34 VFs
[14:59:54] [PASSED] 35 VFs
[14:59:54] [PASSED] 36 VFs
[14:59:54] [PASSED] 37 VFs
[14:59:54] [PASSED] 38 VFs
[14:59:54] [PASSED] 39 VFs
[14:59:54] [PASSED] 40 VFs
[14:59:54] [PASSED] 41 VFs
[14:59:54] [PASSED] 42 VFs
[14:59:54] [PASSED] 43 VFs
[14:59:54] [PASSED] 44 VFs
[14:59:54] [PASSED] 45 VFs
[14:59:54] [PASSED] 46 VFs
[14:59:54] [PASSED] 47 VFs
[14:59:54] [PASSED] 48 VFs
[14:59:54] [PASSED] 49 VFs
[14:59:54] [PASSED] 50 VFs
[14:59:54] [PASSED] 51 VFs
[14:59:54] [PASSED] 52 VFs
[14:59:54] [PASSED] 53 VFs
[14:59:54] [PASSED] 54 VFs
[14:59:54] [PASSED] 55 VFs
[14:59:54] [PASSED] 56 VFs
[14:59:54] [PASSED] 57 VFs
[14:59:54] [PASSED] 58 VFs
[14:59:54] [PASSED] 59 VFs
[14:59:54] [PASSED] 60 VFs
[14:59:54] [PASSED] 61 VFs
[14:59:54] [PASSED] 62 VFs
[14:59:54] [PASSED] 63 VFs
[14:59:54] ================== [PASSED] fair_contexts ==================
[14:59:54] ===================== fair_doorbells  ======================
[14:59:54] [PASSED] 1 VF
[14:59:54] [PASSED] 2 VFs
[14:59:54] [PASSED] 3 VFs
[14:59:54] [PASSED] 4 VFs
[14:59:54] [PASSED] 5 VFs
[14:59:54] [PASSED] 6 VFs
[14:59:54] [PASSED] 7 VFs
[14:59:54] [PASSED] 8 VFs
[14:59:54] [PASSED] 9 VFs
[14:59:54] [PASSED] 10 VFs
[14:59:54] [PASSED] 11 VFs
[14:59:54] [PASSED] 12 VFs
[14:59:54] [PASSED] 13 VFs
[14:59:54] [PASSED] 14 VFs
[14:59:54] [PASSED] 15 VFs
[14:59:54] [PASSED] 16 VFs
[14:59:54] [PASSED] 17 VFs
[14:59:54] [PASSED] 18 VFs
[14:59:54] [PASSED] 19 VFs
[14:59:54] [PASSED] 20 VFs
[14:59:54] [PASSED] 21 VFs
[14:59:54] [PASSED] 22 VFs
[14:59:54] [PASSED] 23 VFs
[14:59:54] [PASSED] 24 VFs
[14:59:54] [PASSED] 25 VFs
[14:59:54] [PASSED] 26 VFs
[14:59:54] [PASSED] 27 VFs
[14:59:54] [PASSED] 28 VFs
[14:59:54] [PASSED] 29 VFs
[14:59:54] [PASSED] 30 VFs
[14:59:54] [PASSED] 31 VFs
[14:59:54] [PASSED] 32 VFs
[14:59:54] [PASSED] 33 VFs
[14:59:54] [PASSED] 34 VFs
[14:59:54] [PASSED] 35 VFs
[14:59:54] [PASSED] 36 VFs
[14:59:54] [PASSED] 37 VFs
[14:59:54] [PASSED] 38 VFs
[14:59:54] [PASSED] 39 VFs
[14:59:54] [PASSED] 40 VFs
[14:59:54] [PASSED] 41 VFs
[14:59:54] [PASSED] 42 VFs
[14:59:54] [PASSED] 43 VFs
[14:59:54] [PASSED] 44 VFs
[14:59:54] [PASSED] 45 VFs
[14:59:54] [PASSED] 46 VFs
[14:59:54] [PASSED] 47 VFs
[14:59:54] [PASSED] 48 VFs
[14:59:54] [PASSED] 49 VFs
[14:59:54] [PASSED] 50 VFs
[14:59:54] [PASSED] 51 VFs
[14:59:54] [PASSED] 52 VFs
[14:59:54] [PASSED] 53 VFs
[14:59:54] [PASSED] 54 VFs
[14:59:54] [PASSED] 55 VFs
[14:59:54] [PASSED] 56 VFs
[14:59:54] [PASSED] 57 VFs
[14:59:54] [PASSED] 58 VFs
[14:59:54] [PASSED] 59 VFs
[14:59:54] [PASSED] 60 VFs
[14:59:54] [PASSED] 61 VFs
[14:59:54] [PASSED] 62 VFs
[14:59:54] [PASSED] 63 VFs
[14:59:54] ================= [PASSED] fair_doorbells ==================
[14:59:54] ======================== fair_ggtt  ========================
[14:59:54] [PASSED] 1 VF
[14:59:54] [PASSED] 2 VFs
[14:59:54] [PASSED] 3 VFs
[14:59:54] [PASSED] 4 VFs
[14:59:54] [PASSED] 5 VFs
[14:59:54] [PASSED] 6 VFs
[14:59:54] [PASSED] 7 VFs
[14:59:54] [PASSED] 8 VFs
[14:59:54] [PASSED] 9 VFs
[14:59:54] [PASSED] 10 VFs
[14:59:54] [PASSED] 11 VFs
[14:59:54] [PASSED] 12 VFs
[14:59:54] [PASSED] 13 VFs
[14:59:54] [PASSED] 14 VFs
[14:59:54] [PASSED] 15 VFs
[14:59:54] [PASSED] 16 VFs
[14:59:54] [PASSED] 17 VFs
[14:59:54] [PASSED] 18 VFs
[14:59:55] [PASSED] 19 VFs
[14:59:55] [PASSED] 20 VFs
[14:59:55] [PASSED] 21 VFs
[14:59:55] [PASSED] 22 VFs
[14:59:55] [PASSED] 23 VFs
[14:59:55] [PASSED] 24 VFs
[14:59:55] [PASSED] 25 VFs
[14:59:55] [PASSED] 26 VFs
[14:59:55] [PASSED] 27 VFs
[14:59:55] [PASSED] 28 VFs
[14:59:55] [PASSED] 29 VFs
[14:59:55] [PASSED] 30 VFs
[14:59:55] [PASSED] 31 VFs
[14:59:55] [PASSED] 32 VFs
[14:59:55] [PASSED] 33 VFs
[14:59:55] [PASSED] 34 VFs
[14:59:55] [PASSED] 35 VFs
[14:59:55] [PASSED] 36 VFs
[14:59:55] [PASSED] 37 VFs
[14:59:55] [PASSED] 38 VFs
[14:59:55] [PASSED] 39 VFs
[14:59:55] [PASSED] 40 VFs
[14:59:55] [PASSED] 41 VFs
[14:59:55] [PASSED] 42 VFs
[14:59:55] [PASSED] 43 VFs
[14:59:55] [PASSED] 44 VFs
[14:59:55] [PASSED] 45 VFs
[14:59:55] [PASSED] 46 VFs
[14:59:55] [PASSED] 47 VFs
[14:59:55] [PASSED] 48 VFs
[14:59:55] [PASSED] 49 VFs
[14:59:55] [PASSED] 50 VFs
[14:59:55] [PASSED] 51 VFs
[14:59:55] [PASSED] 52 VFs
[14:59:55] [PASSED] 53 VFs
[14:59:55] [PASSED] 54 VFs
[14:59:55] [PASSED] 55 VFs
[14:59:55] [PASSED] 56 VFs
[14:59:55] [PASSED] 57 VFs
[14:59:55] [PASSED] 58 VFs
[14:59:55] [PASSED] 59 VFs
[14:59:55] [PASSED] 60 VFs
[14:59:55] [PASSED] 61 VFs
[14:59:55] [PASSED] 62 VFs
[14:59:55] [PASSED] 63 VFs
[14:59:55] ==================== [PASSED] fair_ggtt ====================
[14:59:55] ======================== fair_vram  ========================
[14:59:55] [PASSED] 1 VF
[14:59:55] [PASSED] 2 VFs
[14:59:55] [PASSED] 3 VFs
[14:59:55] [PASSED] 4 VFs
[14:59:55] [PASSED] 5 VFs
[14:59:55] [PASSED] 6 VFs
[14:59:55] [PASSED] 7 VFs
[14:59:55] [PASSED] 8 VFs
[14:59:55] [PASSED] 9 VFs
[14:59:55] [PASSED] 10 VFs
[14:59:55] [PASSED] 11 VFs
[14:59:55] [PASSED] 12 VFs
[14:59:55] [PASSED] 13 VFs
[14:59:55] [PASSED] 14 VFs
[14:59:55] [PASSED] 15 VFs
[14:59:55] [PASSED] 16 VFs
[14:59:55] [PASSED] 17 VFs
[14:59:55] [PASSED] 18 VFs
[14:59:55] [PASSED] 19 VFs
[14:59:55] [PASSED] 20 VFs
[14:59:55] [PASSED] 21 VFs
[14:59:55] [PASSED] 22 VFs
[14:59:55] [PASSED] 23 VFs
[14:59:55] [PASSED] 24 VFs
[14:59:55] [PASSED] 25 VFs
[14:59:55] [PASSED] 26 VFs
[14:59:55] [PASSED] 27 VFs
[14:59:55] [PASSED] 28 VFs
[14:59:55] [PASSED] 29 VFs
[14:59:55] [PASSED] 30 VFs
[14:59:55] [PASSED] 31 VFs
[14:59:55] [PASSED] 32 VFs
[14:59:55] [PASSED] 33 VFs
[14:59:55] [PASSED] 34 VFs
[14:59:55] [PASSED] 35 VFs
[14:59:55] [PASSED] 36 VFs
[14:59:55] [PASSED] 37 VFs
[14:59:55] [PASSED] 38 VFs
[14:59:55] [PASSED] 39 VFs
[14:59:55] [PASSED] 40 VFs
[14:59:55] [PASSED] 41 VFs
[14:59:55] [PASSED] 42 VFs
[14:59:55] [PASSED] 43 VFs
[14:59:55] [PASSED] 44 VFs
[14:59:55] [PASSED] 45 VFs
[14:59:55] [PASSED] 46 VFs
[14:59:55] [PASSED] 47 VFs
[14:59:55] [PASSED] 48 VFs
[14:59:55] [PASSED] 49 VFs
[14:59:55] [PASSED] 50 VFs
[14:59:55] [PASSED] 51 VFs
[14:59:55] [PASSED] 52 VFs
[14:59:55] [PASSED] 53 VFs
[14:59:55] [PASSED] 54 VFs
[14:59:55] [PASSED] 55 VFs
[14:59:55] [PASSED] 56 VFs
[14:59:55] [PASSED] 57 VFs
[14:59:55] [PASSED] 58 VFs
[14:59:55] [PASSED] 59 VFs
[14:59:55] [PASSED] 60 VFs
[14:59:55] [PASSED] 61 VFs
[14:59:55] [PASSED] 62 VFs
[14:59:55] [PASSED] 63 VFs
[14:59:55] ==================== [PASSED] fair_vram ====================
[14:59:55] ================== [PASSED] pf_gt_config ===================
[14:59:55] ===================== lmtt (1 subtest) =====================
[14:59:55] ======================== test_ops  =========================
[14:59:55] [PASSED] 2-level
[14:59:55] [PASSED] multi-level
[14:59:55] ==================== [PASSED] test_ops =====================
[14:59:55] ====================== [PASSED] lmtt =======================
[14:59:55] ================= pf_service (11 subtests) =================
[14:59:55] [PASSED] pf_negotiate_any
[14:59:55] [PASSED] pf_negotiate_base_match
[14:59:55] [PASSED] pf_negotiate_base_newer
[14:59:55] [PASSED] pf_negotiate_base_next
[14:59:55] [SKIPPED] pf_negotiate_base_older
[14:59:55] [PASSED] pf_negotiate_base_prev
[14:59:55] [PASSED] pf_negotiate_latest_match
[14:59:55] [PASSED] pf_negotiate_latest_newer
[14:59:55] [PASSED] pf_negotiate_latest_next
[14:59:55] [SKIPPED] pf_negotiate_latest_older
[14:59:55] [SKIPPED] pf_negotiate_latest_prev
[14:59:55] =================== [PASSED] pf_service ====================
[14:59:55] ================= xe_guc_g2g (2 subtests) ==================
[14:59:55] ============== xe_live_guc_g2g_kunit_default  ==============
[14:59:55] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:59:55] ============== xe_live_guc_g2g_kunit_allmem  ===============
[14:59:55] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:59:55] =================== [SKIPPED] xe_guc_g2g ===================
[14:59:55] =================== xe_mocs (2 subtests) ===================
[14:59:55] ================ xe_live_mocs_kernel_kunit  ================
[14:59:55] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:59:55] ================ xe_live_mocs_reset_kunit  =================
[14:59:55] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:59:55] ==================== [SKIPPED] xe_mocs =====================
[14:59:55] ================= xe_migrate (2 subtests) ==================
[14:59:55] ================= xe_migrate_sanity_kunit  =================
[14:59:55] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:59:55] ================== xe_validate_ccs_kunit  ==================
[14:59:55] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:59:55] =================== [SKIPPED] xe_migrate ===================
[14:59:55] ================== xe_dma_buf (1 subtest) ==================
[14:59:55] ==================== xe_dma_buf_kunit  =====================
[14:59:55] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:59:55] =================== [SKIPPED] xe_dma_buf ===================
[14:59:55] ================= xe_bo_shrink (1 subtest) =================
[14:59:55] =================== xe_bo_shrink_kunit  ====================
[14:59:55] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:59:55] ================== [SKIPPED] xe_bo_shrink ==================
[14:59:55] ==================== xe_bo (2 subtests) ====================
[14:59:55] ================== xe_ccs_migrate_kunit  ===================
[14:59:55] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:59:55] ==================== xe_bo_evict_kunit  ====================
[14:59:55] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:59:55] ===================== [SKIPPED] xe_bo ======================
[14:59:55] ==================== args (13 subtests) ====================
[14:59:55] [PASSED] count_args_test
[14:59:55] [PASSED] call_args_example
[14:59:55] [PASSED] call_args_test
[14:59:55] [PASSED] drop_first_arg_example
[14:59:55] [PASSED] drop_first_arg_test
[14:59:55] [PASSED] first_arg_example
[14:59:55] [PASSED] first_arg_test
[14:59:55] [PASSED] last_arg_example
[14:59:55] [PASSED] last_arg_test
[14:59:55] [PASSED] pick_arg_example
[14:59:55] [PASSED] if_args_example
[14:59:55] [PASSED] if_args_test
[14:59:55] [PASSED] sep_comma_example
[14:59:55] ====================== [PASSED] args =======================
[14:59:55] =================== xe_pci (3 subtests) ====================
[14:59:55] ==================== check_graphics_ip  ====================
[14:59:55] [PASSED] 12.00 Xe_LP
[14:59:55] [PASSED] 12.10 Xe_LP+
[14:59:55] [PASSED] 12.55 Xe_HPG
[14:59:55] [PASSED] 12.60 Xe_HPC
[14:59:55] [PASSED] 12.70 Xe_LPG
[14:59:55] [PASSED] 12.71 Xe_LPG
[14:59:55] [PASSED] 12.74 Xe_LPG+
[14:59:55] [PASSED] 20.01 Xe2_HPG
[14:59:55] [PASSED] 20.02 Xe2_HPG
[14:59:55] [PASSED] 20.04 Xe2_LPG
[14:59:55] [PASSED] 30.00 Xe3_LPG
[14:59:55] [PASSED] 30.01 Xe3_LPG
[14:59:55] [PASSED] 30.03 Xe3_LPG
[14:59:55] [PASSED] 30.04 Xe3_LPG
[14:59:55] [PASSED] 30.05 Xe3_LPG
[14:59:55] [PASSED] 35.10 Xe3p_LPG
[14:59:55] [PASSED] 35.11 Xe3p_XPC
[14:59:55] ================ [PASSED] check_graphics_ip ================
[14:59:55] ===================== check_media_ip  ======================
[14:59:55] [PASSED] 12.00 Xe_M
[14:59:55] [PASSED] 12.55 Xe_HPM
[14:59:55] [PASSED] 13.00 Xe_LPM+
[14:59:55] [PASSED] 13.01 Xe2_HPM
[14:59:55] [PASSED] 20.00 Xe2_LPM
[14:59:55] [PASSED] 30.00 Xe3_LPM
[14:59:55] [PASSED] 30.02 Xe3_LPM
[14:59:55] [PASSED] 35.00 Xe3p_LPM
[14:59:55] [PASSED] 35.03 Xe3p_HPM
[14:59:55] ================= [PASSED] check_media_ip ==================
[14:59:55] =================== check_platform_desc  ===================
[14:59:55] [PASSED] 0x9A60 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A68 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A70 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A40 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A49 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A59 (TIGERLAKE)
[14:59:55] [PASSED] 0x9A78 (TIGERLAKE)
[14:59:55] [PASSED] 0x9AC0 (TIGERLAKE)
[14:59:55] [PASSED] 0x9AC9 (TIGERLAKE)
[14:59:55] [PASSED] 0x9AD9 (TIGERLAKE)
[14:59:55] [PASSED] 0x9AF8 (TIGERLAKE)
[14:59:55] [PASSED] 0x4C80 (ROCKETLAKE)
[14:59:55] [PASSED] 0x4C8A (ROCKETLAKE)
[14:59:55] [PASSED] 0x4C8B (ROCKETLAKE)
[14:59:55] [PASSED] 0x4C8C (ROCKETLAKE)
[14:59:55] [PASSED] 0x4C90 (ROCKETLAKE)
[14:59:55] [PASSED] 0x4C9A (ROCKETLAKE)
[14:59:55] [PASSED] 0x4680 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4682 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4688 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x468A (ALDERLAKE_S)
[14:59:55] [PASSED] 0x468B (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4690 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4692 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4693 (ALDERLAKE_S)
[14:59:55] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46AA (ALDERLAKE_P)
[14:59:55] [PASSED] 0x462A (ALDERLAKE_P)
[14:59:55] [PASSED] 0x4626 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x4628 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:59:55] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:59:55] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:59:55] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:59:55] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:59:55] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:59:55] [PASSED] 0xA721 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA720 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:59:55] [PASSED] 0xA780 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA781 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA782 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA783 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA788 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA789 (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA78A (ALDERLAKE_S)
[14:59:55] [PASSED] 0xA78B (ALDERLAKE_S)
[14:59:55] [PASSED] 0x4905 (DG1)
[14:59:55] [PASSED] 0x4906 (DG1)
[14:59:55] [PASSED] 0x4907 (DG1)
[14:59:55] [PASSED] 0x4908 (DG1)
[14:59:55] [PASSED] 0x4909 (DG1)
[14:59:55] [PASSED] 0x56C0 (DG2)
[14:59:55] [PASSED] 0x56C2 (DG2)
[14:59:55] [PASSED] 0x56C1 (DG2)
[14:59:55] [PASSED] 0x7D51 (METEORLAKE)
[14:59:55] [PASSED] 0x7DD1 (METEORLAKE)
[14:59:55] [PASSED] 0x7D41 (METEORLAKE)
[14:59:55] [PASSED] 0x7D67 (METEORLAKE)
[14:59:55] [PASSED] 0xB640 (METEORLAKE)
[14:59:55] [PASSED] 0x56A0 (DG2)
[14:59:55] [PASSED] 0x56A1 (DG2)
[14:59:55] [PASSED] 0x56A2 (DG2)
[14:59:55] [PASSED] 0x56BE (DG2)
[14:59:55] [PASSED] 0x56BF (DG2)
[14:59:55] [PASSED] 0x5690 (DG2)
[14:59:55] [PASSED] 0x5691 (DG2)
[14:59:55] [PASSED] 0x5692 (DG2)
[14:59:55] [PASSED] 0x56A5 (DG2)
[14:59:55] [PASSED] 0x56A6 (DG2)
[14:59:55] [PASSED] 0x56B0 (DG2)
[14:59:55] [PASSED] 0x56B1 (DG2)
[14:59:55] [PASSED] 0x56BA (DG2)
[14:59:55] [PASSED] 0x56BB (DG2)
[14:59:55] [PASSED] 0x56BC (DG2)
[14:59:55] [PASSED] 0x56BD (DG2)
[14:59:55] [PASSED] 0x5693 (DG2)
[14:59:55] [PASSED] 0x5694 (DG2)
[14:59:55] [PASSED] 0x5695 (DG2)
[14:59:55] [PASSED] 0x56A3 (DG2)
[14:59:55] [PASSED] 0x56A4 (DG2)
[14:59:55] [PASSED] 0x56B2 (DG2)
[14:59:55] [PASSED] 0x56B3 (DG2)
[14:59:55] [PASSED] 0x5696 (DG2)
[14:59:55] [PASSED] 0x5697 (DG2)
[14:59:55] [PASSED] 0xB69 (PVC)
[14:59:55] [PASSED] 0xB6E (PVC)
[14:59:55] [PASSED] 0xBD4 (PVC)
[14:59:55] [PASSED] 0xBD5 (PVC)
[14:59:55] [PASSED] 0xBD6 (PVC)
[14:59:55] [PASSED] 0xBD7 (PVC)
[14:59:55] [PASSED] 0xBD8 (PVC)
[14:59:55] [PASSED] 0xBD9 (PVC)
[14:59:55] [PASSED] 0xBDA (PVC)
[14:59:55] [PASSED] 0xBDB (PVC)
[14:59:55] [PASSED] 0xBE0 (PVC)
[14:59:55] [PASSED] 0xBE1 (PVC)
[14:59:55] [PASSED] 0xBE5 (PVC)
[14:59:55] [PASSED] 0x7D40 (METEORLAKE)
[14:59:55] [PASSED] 0x7D45 (METEORLAKE)
[14:59:55] [PASSED] 0x7D55 (METEORLAKE)
[14:59:55] [PASSED] 0x7D60 (METEORLAKE)
[14:59:55] [PASSED] 0x7DD5 (METEORLAKE)
[14:59:55] [PASSED] 0x6420 (LUNARLAKE)
[14:59:55] [PASSED] 0x64A0 (LUNARLAKE)
[14:59:55] [PASSED] 0x64B0 (LUNARLAKE)
[14:59:55] [PASSED] 0xE202 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE209 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE20B (BATTLEMAGE)
[14:59:55] [PASSED] 0xE20C (BATTLEMAGE)
[14:59:55] [PASSED] 0xE20D (BATTLEMAGE)
[14:59:55] [PASSED] 0xE210 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE211 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE212 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE216 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE220 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE221 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE222 (BATTLEMAGE)
[14:59:55] [PASSED] 0xE223 (BATTLEMAGE)
[14:59:55] [PASSED] 0xB080 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB081 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB082 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB083 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB084 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB085 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB086 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB087 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB08F (PANTHERLAKE)
[14:59:55] [PASSED] 0xB090 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:59:55] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:59:55] [PASSED] 0xFD80 (PANTHERLAKE)
[14:59:55] [PASSED] 0xFD81 (PANTHERLAKE)
[14:59:55] [PASSED] 0xD740 (NOVALAKE_S)
[14:59:55] [PASSED] 0xD741 (NOVALAKE_S)
[14:59:55] [PASSED] 0xD742 (NOVALAKE_S)
[14:59:55] [PASSED] 0xD743 (NOVALAKE_S)
[14:59:55] [PASSED] 0xD745 (NOVALAKE_S)
[14:59:55] [PASSED] 0xD74A (NOVALAKE_S)
[14:59:55] [PASSED] 0xD74B (NOVALAKE_S)
[14:59:55] [PASSED] 0x674C (CRESCENTISLAND)
[14:59:55] [PASSED] 0x674D (CRESCENTISLAND)
[14:59:55] [PASSED] 0x674E (CRESCENTISLAND)
[14:59:55] [PASSED] 0x674F (CRESCENTISLAND)
[14:59:55] [PASSED] 0x6750 (CRESCENTISLAND)
[14:59:55] [PASSED] 0xD750 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD751 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD752 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD753 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD754 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD755 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD756 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD757 (NOVALAKE_P)
[14:59:55] [PASSED] 0xD75F (NOVALAKE_P)
[14:59:55] =============== [PASSED] check_platform_desc ===============
[14:59:55] ===================== [PASSED] xe_pci ======================
[14:59:55] ============= xe_rtp_tables_test (4 subtests) ==============
[14:59:55] ================== xe_rtp_table_gt_test  ===================
[14:59:55] [PASSED] gt_was/14011060649
[14:59:55] [PASSED] gt_was/14011059788
[14:59:55] [PASSED] gt_was/14015795083
[14:59:55] [PASSED] gt_was/16021867713
[14:59:55] [PASSED] gt_was/14019449301
[14:59:55] [PASSED] gt_was/16028005424
[14:59:55] [PASSED] gt_was/14026578760
[14:59:55] [PASSED] gt_was/1409420604
[14:59:55] [PASSED] gt_was/1408615072
[14:59:55] [PASSED] gt_was/22010523718
[14:59:55] [PASSED] gt_was/14011006942
[14:59:55] [PASSED] gt_was/14014830051
[14:59:55] [PASSED] gt_was/18018781329
[14:59:55] [PASSED] gt_was/1509235366
[14:59:55] [PASSED] gt_was/18018781329
[14:59:55] [PASSED] gt_was/16016694945
[14:59:55] [PASSED] gt_was/14018575942
[14:59:55] [PASSED] gt_was/22016670082
[14:59:55] [PASSED] gt_was/22016670082
[14:59:55] [PASSED] gt_was/14017421178
[14:59:55] [PASSED] gt_was/16025250150
[14:59:55] [PASSED] gt_was/14021871409
[14:59:55] [PASSED] gt_was/16021865536
[14:59:55] [PASSED] gt_was/14021486841
[14:59:55] [PASSED] gt_was/14025160223
[14:59:55] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[14:59:55] [PASSED] gt_was/14025635424
[14:59:55] [PASSED] gt_was/16028005424
[14:59:55] ============== [PASSED] xe_rtp_table_gt_test ===============
[14:59:55] ================== xe_rtp_table_gt_test  ===================
[14:59:55] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[14:59:55] [PASSED] gt_tunings/Tuning: 32B Access Enable
[14:59:55] [PASSED] gt_tunings/Tuning: L3 cache
[14:59:55] [PASSED] gt_tunings/Tuning: L3 cache - media
[14:59:55] [PASSED] gt_tunings/Tuning: Compression Overfetch
[14:59:55] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[14:59:55] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[14:59:55] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[14:59:55] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[14:59:55] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[14:59:55] [PASSED] gt_tunings/Tuning: Stateless compression control
[14:59:55] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[14:59:55] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[14:59:55] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[14:59:55] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[14:59:55] ============== [PASSED] xe_rtp_table_gt_test ===============
[14:59:55] ================== xe_rtp_table_oob_test  ==================
[14:59:55] [PASSED] oob_was/1607983814
[14:59:55] [PASSED] oob_was/16010904313
[14:59:55] [PASSED] oob_was/18022495364
[14:59:55] [PASSED] oob_was/22012773006
[14:59:55] [PASSED] oob_was/14014475959
[14:59:55] [PASSED] oob_was/22011391025
[14:59:55] [PASSED] oob_was/22012727170
[14:59:55] [PASSED] oob_was/22012727685
[14:59:55] [PASSED] oob_was/22016596838
[14:59:55] [PASSED] oob_was/18020744125
[14:59:55] [PASSED] oob_was/1409600907
[14:59:55] [PASSED] oob_was/22014953428
[14:59:55] [PASSED] oob_was/16017236439
[14:59:55] [PASSED] oob_was/14019821291
[14:59:55] [PASSED] oob_was/14015076503
[14:59:55] [PASSED] oob_was/14018913170
[14:59:55] [PASSED] oob_was/14018094691
[14:59:55] [PASSED] oob_was/18024947630
[14:59:55] [PASSED] oob_was/16022287689
[14:59:55] [PASSED] oob_was/13011645652
[14:59:55] [PASSED] oob_was/14022293748
[14:59:55] [PASSED] oob_was/22019794406
[14:59:55] [PASSED] oob_was/22019338487
[14:59:55] [PASSED] oob_was/16023588340
[14:59:55] [PASSED] oob_was/14019789679
[14:59:55] [PASSED] oob_was/14022866841
[14:59:55] [PASSED] oob_was/16021333562
[14:59:55] [PASSED] oob_was/14016712196
[14:59:55] [PASSED] oob_was/14015568240
[14:59:55] [PASSED] oob_was/18013179988
[14:59:55] [PASSED] oob_was/1508761755
[14:59:55] [PASSED] oob_was/16023105232
[14:59:55] [PASSED] oob_was/16026508708
[14:59:55] [PASSED] oob_was/14020001231
[14:59:55] [PASSED] oob_was/16023683509
[14:59:55] [PASSED] oob_was/14025515070
[14:59:55] [PASSED] oob_was/15015404425_disable
[14:59:55] [PASSED] oob_was/16026007364
[14:59:55] [PASSED] oob_was/14020316580
[14:59:55] [PASSED] oob_was/14025883347
[14:59:55] [PASSED] oob_was/16029380221
[14:59:55] ============== [PASSED] xe_rtp_table_oob_test ==============
[14:59:55] ================ xe_rtp_table_dev_oob_test  ================
[14:59:55] [PASSED] device_oob_was/22010954014
[14:59:55] [PASSED] device_oob_was/15015404425
[14:59:55] [PASSED] device_oob_was/22019338487_display
[14:59:55] [PASSED] device_oob_was/14022085890
[14:59:55] [PASSED] device_oob_was/14026539277
[14:59:55] [PASSED] device_oob_was/14026633728
[14:59:55] [PASSED] device_oob_was/14026746987
[14:59:55] [PASSED] device_oob_was/14026779378
[14:59:55] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[14:59:55] =============== [PASSED] xe_rtp_tables_test ================
[14:59:55] =================== xe_rtp (3 subtests) ====================
[14:59:55] =================== xe_rtp_rules_tests  ====================
[14:59:55] [PASSED] no
[14:59:55] [PASSED] yes
[14:59:55] [PASSED] no-and-no
[14:59:55] [PASSED] no-and-yes
[14:59:55] [PASSED] yes-and-no
[14:59:55] [PASSED] yes-and-yes
[14:59:55] [PASSED] no-or-no
[14:59:55] [PASSED] no-or-yes
[14:59:55] [PASSED] yes-or-no
[14:59:55] [PASSED] yes-or-yes
[14:59:55] [PASSED] no-yes-or-yes-no
[14:59:55] [PASSED] no-yes-or-yes-yes
[14:59:55] [PASSED] yes-yes-or-no-yes
[14:59:55] [PASSED] yes-yes-or-yes-yes
[14:59:55] [PASSED] no-no-or-yes-or-no
[14:59:55] [PASSED] or
[14:59:55] [PASSED] or-yes
[14:59:55] [PASSED] or-no
[14:59:55] [PASSED] yes-or
[14:59:55] [PASSED] no-or
[14:59:55] [PASSED] no-or-or-yes
[14:59:55] [PASSED] yes-or-or-no
[14:59:55] [PASSED] no-or-or-no
[14:59:55] [PASSED] missing-context-engine-class
[14:59:55] [PASSED] missing-context-engine-class-or-yes
[14:59:55] [PASSED] missing-context-engine-class-or-or-yes
[14:59:55] =============== [PASSED] xe_rtp_rules_tests ================
[14:59:55] =============== xe_rtp_process_to_sr_tests  ================
[14:59:55] [PASSED] coalesce-same-reg
[14:59:55] [PASSED] no-match-no-add
[14:59:55] [PASSED] two-regs-two-entries
[14:59:55] [PASSED] clr-one-set-other
[14:59:55] [PASSED] set-field
[14:59:55] [PASSED] conflict-duplicate
[14:59:55] [PASSED] conflict-not-disjoint
[14:59:55] [PASSED] conflict-reg-type
[14:59:55] [PASSED] bad-mcr-reg-forced-to-regular
[14:59:55] [PASSED] bad-regular-reg-forced-to-mcr
[14:59:55] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:59:55] ================== xe_rtp_process_tests  ===================
[14:59:55] [PASSED] active1
[14:59:55] [PASSED] active2
[14:59:55] [PASSED] active-inactive
[14:59:55] [PASSED] inactive-active
[14:59:55] [PASSED] inactive-active-inactive
[14:59:55] [PASSED] inactive-inactive-inactive
[14:59:55] ============== [PASSED] xe_rtp_process_tests ===============
[14:59:55] ===================== [PASSED] xe_rtp ======================
[14:59:55] ==================== xe_wa (1 subtest) =====================
[14:59:55] ======================== xe_wa_gt  =========================
[14:59:55] [PASSED] TIGERLAKE B0
[14:59:55] [PASSED] DG1 A0
[14:59:55] [PASSED] DG1 B0
[14:59:55] [PASSED] ALDERLAKE_S A0
[14:59:55] [PASSED] ALDERLAKE_S B0
[14:59:55] [PASSED] ALDERLAKE_S C0
[14:59:55] [PASSED] ALDERLAKE_S D0
[14:59:55] [PASSED] ALDERLAKE_P A0
[14:59:55] [PASSED] ALDERLAKE_P B0
[14:59:55] [PASSED] ALDERLAKE_P C0
[14:59:55] [PASSED] ALDERLAKE_S RPLS D0
[14:59:55] [PASSED] ALDERLAKE_P RPLU E0
[14:59:55] [PASSED] DG2 G10 C0
[14:59:55] [PASSED] DG2 G11 B1
[14:59:55] [PASSED] DG2 G12 A1
[14:59:55] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:59:55] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:59:55] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:59:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:59:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:59:55] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:59:55] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:59:55] ==================== [PASSED] xe_wa_gt =====================
[14:59:55] ====================== [PASSED] xe_wa ======================
[14:59:55] ============================================================
[14:59:55] Testing complete. Ran 717 tests: passed: 699, skipped: 18
[14:59:55] Elapsed time: 36.196s total, 4.304s configuring, 31.226s building, 0.636s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:59:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:59:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:00:21] Starting KUnit Kernel (1/1)...
[15:00:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:00:21] ============ drm_test_pick_cmdline (2 subtests) ============
[15:00:21] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:00:21] =============== drm_test_pick_cmdline_named  ===============
[15:00:21] [PASSED] NTSC
[15:00:21] [PASSED] NTSC-J
[15:00:21] [PASSED] PAL
[15:00:21] [PASSED] PAL-M
[15:00:21] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:00:21] ============== [PASSED] drm_test_pick_cmdline ==============
[15:00:21] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:00:21] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:00:21] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:00:21] =========== drm_validate_clone_mode (2 subtests) ===========
[15:00:21] ============== drm_test_check_in_clone_mode  ===============
[15:00:21] [PASSED] in_clone_mode
[15:00:21] [PASSED] not_in_clone_mode
[15:00:21] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:00:21] =============== drm_test_check_valid_clones  ===============
[15:00:21] [PASSED] not_in_clone_mode
[15:00:21] [PASSED] valid_clone
[15:00:21] [PASSED] invalid_clone
[15:00:21] =========== [PASSED] drm_test_check_valid_clones ===========
[15:00:21] ============= [PASSED] drm_validate_clone_mode =============
[15:00:21] ============= drm_validate_modeset (1 subtest) =============
[15:00:21] [PASSED] drm_test_check_connector_changed_modeset
[15:00:21] ============== [PASSED] drm_validate_modeset ===============
[15:00:21] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:00:21] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:00:21] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:00:21] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:00:21] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[15:00:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:00:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:00:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:00:21] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[15:00:21] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:00:21] ============== drm_bridge_alloc (2 subtests) ===============
[15:00:21] [PASSED] drm_test_drm_bridge_alloc_basic
[15:00:21] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:00:21] ================ [PASSED] drm_bridge_alloc =================
[15:00:21] ============= drm_bridge_bus_fmt (5 subtests) ==============
[15:00:21] [PASSED] drm_test_bridge_rgb_yuv_rgb
[15:00:21] [PASSED] drm_test_bridge_must_convert_to_yuv444
[15:00:21] [PASSED] drm_test_bridge_hdmi_auto_rgb
[15:00:21] [PASSED] drm_test_bridge_auto_first
[15:00:21] [PASSED] drm_test_bridge_rgb_yuv_no_path
[15:00:21] =============== [PASSED] drm_bridge_bus_fmt ================
[15:00:21] ============= drm_cmdline_parser (40 subtests) =============
[15:00:21] [PASSED] drm_test_cmdline_force_d_only
[15:00:21] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:00:21] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:00:21] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:00:21] [PASSED] drm_test_cmdline_force_e_only
[15:00:21] [PASSED] drm_test_cmdline_res
[15:00:21] [PASSED] drm_test_cmdline_res_vesa
[15:00:21] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:00:21] [PASSED] drm_test_cmdline_res_rblank
[15:00:21] [PASSED] drm_test_cmdline_res_bpp
[15:00:21] [PASSED] drm_test_cmdline_res_refresh
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:00:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:00:21] [PASSED] drm_test_cmdline_res_margins_force_on
[15:00:21] [PASSED] drm_test_cmdline_res_vesa_margins
[15:00:21] [PASSED] drm_test_cmdline_name
[15:00:21] [PASSED] drm_test_cmdline_name_bpp
[15:00:21] [PASSED] drm_test_cmdline_name_option
[15:00:21] [PASSED] drm_test_cmdline_name_bpp_option
[15:00:21] [PASSED] drm_test_cmdline_rotate_0
[15:00:21] [PASSED] drm_test_cmdline_rotate_90
[15:00:21] [PASSED] drm_test_cmdline_rotate_180
[15:00:21] [PASSED] drm_test_cmdline_rotate_270
[15:00:21] [PASSED] drm_test_cmdline_hmirror
[15:00:21] [PASSED] drm_test_cmdline_vmirror
[15:00:21] [PASSED] drm_test_cmdline_margin_options
[15:00:21] [PASSED] drm_test_cmdline_multiple_options
[15:00:21] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:00:21] [PASSED] drm_test_cmdline_extra_and_option
[15:00:21] [PASSED] drm_test_cmdline_freestanding_options
[15:00:21] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:00:21] [PASSED] drm_test_cmdline_panel_orientation
[15:00:21] ================ drm_test_cmdline_invalid  =================
[15:00:21] [PASSED] margin_only
[15:00:21] [PASSED] interlace_only
[15:00:21] [PASSED] res_missing_x
[15:00:21] [PASSED] res_missing_y
[15:00:21] [PASSED] res_bad_y
[15:00:21] [PASSED] res_missing_y_bpp
[15:00:21] [PASSED] res_bad_bpp
[15:00:21] [PASSED] res_bad_refresh
[15:00:21] [PASSED] res_bpp_refresh_force_on_off
[15:00:21] [PASSED] res_invalid_mode
[15:00:21] [PASSED] res_bpp_wrong_place_mode
[15:00:21] [PASSED] name_bpp_refresh
[15:00:21] [PASSED] name_refresh
[15:00:21] [PASSED] name_refresh_wrong_mode
[15:00:21] [PASSED] name_refresh_invalid_mode
[15:00:21] [PASSED] rotate_multiple
[15:00:21] [PASSED] rotate_invalid_val
[15:00:21] [PASSED] rotate_truncated
[15:00:21] [PASSED] invalid_option
[15:00:21] [PASSED] invalid_tv_option
[15:00:21] [PASSED] truncated_tv_option
[15:00:21] ============ [PASSED] drm_test_cmdline_invalid =============
[15:00:21] =============== drm_test_cmdline_tv_options  ===============
[15:00:21] [PASSED] NTSC
[15:00:21] [PASSED] NTSC_443
[15:00:21] [PASSED] NTSC_J
[15:00:21] [PASSED] PAL
[15:00:21] [PASSED] PAL_M
[15:00:21] [PASSED] PAL_N
[15:00:21] [PASSED] SECAM
[15:00:21] [PASSED] MONO_525
[15:00:21] [PASSED] MONO_625
[15:00:21] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:00:21] =============== [PASSED] drm_cmdline_parser ================
[15:00:21] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:00:21] [PASSED] drm_test_connector_hdmi_init_valid
[15:00:21] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:00:21] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:00:21] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:00:21] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:00:21] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:00:21] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:00:21] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:00:21] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:00:21] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:00:21] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:00:21] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:00:21] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:00:21] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:00:21] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:00:21] [PASSED] drm_test_connector_hdmi_init_null_product
[15:00:21] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:00:21] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:00:21] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:00:21] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:00:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:00:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:00:21] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:00:21] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:00:21] [PASSED] HDMI-A
[15:00:21] [PASSED] HDMI-B
[15:00:21] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:00:21] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:00:21] [PASSED] Unknown
[15:00:21] [PASSED] VGA
[15:00:21] [PASSED] DVI-I
[15:00:21] [PASSED] DVI-D
[15:00:21] [PASSED] DVI-A
[15:00:21] [PASSED] Composite
[15:00:21] [PASSED] SVIDEO
[15:00:21] [PASSED] LVDS
[15:00:21] [PASSED] Component
[15:00:21] [PASSED] DIN
[15:00:21] [PASSED] DP
[15:00:21] [PASSED] TV
[15:00:21] [PASSED] eDP
[15:00:21] [PASSED] Virtual
[15:00:21] [PASSED] DSI
[15:00:21] [PASSED] DPI
[15:00:21] [PASSED] Writeback
[15:00:21] [PASSED] SPI
[15:00:21] [PASSED] USB
[15:00:21] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:00:21] ============ [PASSED] drmm_connector_hdmi_init =============
[15:00:21] ============= drmm_connector_init (3 subtests) =============
[15:00:21] [PASSED] drm_test_drmm_connector_init
[15:00:21] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:00:21] ========= drm_test_drmm_connector_init_type_valid  =========
[15:00:21] [PASSED] Unknown
[15:00:21] [PASSED] VGA
[15:00:21] [PASSED] DVI-I
[15:00:21] [PASSED] DVI-D
[15:00:21] [PASSED] DVI-A
[15:00:21] [PASSED] Composite
[15:00:21] [PASSED] SVIDEO
[15:00:21] [PASSED] LVDS
[15:00:21] [PASSED] Component
[15:00:21] [PASSED] DIN
[15:00:21] [PASSED] DP
[15:00:21] [PASSED] HDMI-A
[15:00:21] [PASSED] HDMI-B
[15:00:21] [PASSED] TV
[15:00:21] [PASSED] eDP
[15:00:21] [PASSED] Virtual
[15:00:21] [PASSED] DSI
[15:00:21] [PASSED] DPI
[15:00:21] [PASSED] Writeback
[15:00:21] [PASSED] SPI
[15:00:21] [PASSED] USB
[15:00:21] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:00:21] =============== [PASSED] drmm_connector_init ===============
[15:00:21] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_init
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:00:21] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:00:21] [PASSED] Unknown
[15:00:21] [PASSED] VGA
[15:00:21] [PASSED] DVI-I
[15:00:21] [PASSED] DVI-D
[15:00:21] [PASSED] DVI-A
[15:00:21] [PASSED] Composite
[15:00:21] [PASSED] SVIDEO
[15:00:21] [PASSED] LVDS
[15:00:21] [PASSED] Component
[15:00:21] [PASSED] DIN
[15:00:21] [PASSED] DP
[15:00:21] [PASSED] HDMI-A
[15:00:21] [PASSED] HDMI-B
[15:00:21] [PASSED] TV
[15:00:21] [PASSED] eDP
[15:00:21] [PASSED] Virtual
[15:00:21] [PASSED] DSI
[15:00:21] [PASSED] DPI
[15:00:21] [PASSED] Writeback
[15:00:21] [PASSED] SPI
[15:00:21] [PASSED] USB
[15:00:21] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:00:21] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:00:21] [PASSED] Unknown
[15:00:21] [PASSED] VGA
[15:00:21] [PASSED] DVI-I
[15:00:21] [PASSED] DVI-D
[15:00:21] [PASSED] DVI-A
[15:00:21] [PASSED] Composite
[15:00:21] [PASSED] SVIDEO
[15:00:21] [PASSED] LVDS
[15:00:21] [PASSED] Component
[15:00:21] [PASSED] DIN
[15:00:21] [PASSED] DP
[15:00:21] [PASSED] HDMI-A
[15:00:21] [PASSED] HDMI-B
[15:00:21] [PASSED] TV
[15:00:21] [PASSED] eDP
[15:00:21] [PASSED] Virtual
[15:00:21] [PASSED] DSI
[15:00:21] [PASSED] DPI
[15:00:21] [PASSED] Writeback
[15:00:21] [PASSED] SPI
[15:00:21] [PASSED] USB
[15:00:21] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:00:21] =========== [PASSED] drm_connector_dynamic_init ============
[15:00:21] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:00:21] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:00:21] ======= drm_connector_dynamic_register (7 subtests) ========
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:00:21] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:00:21] ========= [PASSED] drm_connector_dynamic_register ==========
[15:00:21] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:00:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:00:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:00:21] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:00:21] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:00:21] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:00:21] [PASSED] NTSC
[15:00:21] [PASSED] NTSC-443
[15:00:21] [PASSED] NTSC-J
[15:00:21] [PASSED] PAL
[15:00:21] [PASSED] PAL-M
[15:00:21] [PASSED] PAL-N
[15:00:21] [PASSED] SECAM
[15:00:21] [PASSED] Mono
[15:00:21] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:00:21] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:00:21] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:00:21] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:00:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:00:21] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:00:21] [PASSED] VIC 96
[15:00:21] [PASSED] VIC 97
[15:00:21] [PASSED] VIC 101
[15:00:21] [PASSED] VIC 102
[15:00:21] [PASSED] VIC 106
[15:00:21] [PASSED] VIC 107
[15:00:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:00:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:00:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:00:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:00:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:00:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:00:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:00:21] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:00:21] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:00:21] [PASSED] Automatic
[15:00:21] [PASSED] Full
[15:00:21] [PASSED] Limited 16:235
[15:00:21] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:00:21] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:00:21] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:00:21] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:00:21] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:00:21] [PASSED] RGB
[15:00:21] [PASSED] YUV 4:2:0
[15:00:21] [PASSED] YUV 4:2:2
[15:00:21] [PASSED] YUV 4:4:4
[15:00:21] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:00:21] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:00:21] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:00:21] ============= drm_damage_helper (21 subtests) ==============
[15:00:21] [PASSED] drm_test_damage_iter_no_damage
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:00:21] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:00:21] [PASSED] drm_test_damage_iter_simple_damage
[15:00:21] [PASSED] drm_test_damage_iter_single_damage
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:00:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:00:21] [PASSED] drm_test_damage_iter_damage
[15:00:21] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:00:21] [PASSED] drm_test_damage_iter_damage_one_outside
[15:00:21] [PASSED] drm_test_damage_iter_damage_src_moved
[15:00:21] [PASSED] drm_test_damage_iter_damage_not_visible
[15:00:21] ================ [PASSED] drm_damage_helper ================
[15:00:21] ============== drm_dp_mst_helper (3 subtests) ==============
[15:00:21] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:00:21] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:00:21] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:00:21] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:00:21] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:00:21] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:00:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:00:21] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:00:21] [PASSED] Link rate 2000000 lane count 4
[15:00:21] [PASSED] Link rate 2000000 lane count 2
[15:00:21] [PASSED] Link rate 2000000 lane count 1
[15:00:21] [PASSED] Link rate 1350000 lane count 4
[15:00:21] [PASSED] Link rate 1350000 lane count 2
[15:00:21] [PASSED] Link rate 1350000 lane count 1
[15:00:21] [PASSED] Link rate 1000000 lane count 4
[15:00:21] [PASSED] Link rate 1000000 lane count 2
[15:00:21] [PASSED] Link rate 1000000 lane count 1
[15:00:21] [PASSED] Link rate 810000 lane count 4
[15:00:21] [PASSED] Link rate 810000 lane count 2
[15:00:21] [PASSED] Link rate 810000 lane count 1
[15:00:21] [PASSED] Link rate 540000 lane count 4
[15:00:21] [PASSED] Link rate 540000 lane count 2
[15:00:21] [PASSED] Link rate 540000 lane count 1
[15:00:21] [PASSED] Link rate 270000 lane count 4
[15:00:21] [PASSED] Link rate 270000 lane count 2
[15:00:21] [PASSED] Link rate 270000 lane count 1
[15:00:21] [PASSED] Link rate 162000 lane count 4
[15:00:21] [PASSED] Link rate 162000 lane count 2
[15:00:21] [PASSED] Link rate 162000 lane count 1
[15:00:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:00:21] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:00:21] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:00:21] [PASSED] DP_POWER_UP_PHY with port number
[15:00:21] [PASSED] DP_POWER_DOWN_PHY with port number
[15:00:21] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:00:21] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:00:21] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:00:21] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:00:21] [PASSED] DP_QUERY_PAYLOAD with port number
[15:00:21] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:00:21] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:00:21] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:00:21] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:00:21] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:00:21] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:00:21] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:00:21] [PASSED] DP_REMOTE_I2C_READ with port number
[15:00:21] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:00:21] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:00:21] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:00:21] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:00:21] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:00:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:00:21] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:00:21] ================ [PASSED] drm_dp_mst_helper ================
[15:00:21] ================== drm_exec (7 subtests) ===================
[15:00:21] [PASSED] sanitycheck
[15:00:21] [PASSED] test_lock
[15:00:21] [PASSED] test_lock_unlock
[15:00:21] [PASSED] test_duplicates
[15:00:21] [PASSED] test_prepare
[15:00:21] [PASSED] test_prepare_array
[15:00:21] [PASSED] test_multiple_loops
[15:00:21] ==================== [PASSED] drm_exec =====================
[15:00:21] =========== drm_format_helper_test (17 subtests) ===========
[15:00:21] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:00:21] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:00:21] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:00:21] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:00:21] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:00:21] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:00:21] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:00:21] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:00:21] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:00:21] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:00:21] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:00:21] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:00:21] ==================== drm_test_fb_swab  =====================
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ================ [PASSED] drm_test_fb_swab =================
[15:00:21] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:00:21] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:00:21] [PASSED] single_pixel_source_buffer
[15:00:21] [PASSED] single_pixel_clip_rectangle
[15:00:21] [PASSED] well_known_colors
[15:00:21] [PASSED] destination_pitch
[15:00:21] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:00:21] ================= drm_test_fb_clip_offset  =================
[15:00:21] [PASSED] pass through
[15:00:21] [PASSED] horizontal offset
[15:00:21] [PASSED] vertical offset
[15:00:21] [PASSED] horizontal and vertical offset
[15:00:21] [PASSED] horizontal offset (custom pitch)
[15:00:21] [PASSED] vertical offset (custom pitch)
[15:00:21] [PASSED] horizontal and vertical offset (custom pitch)
[15:00:21] ============= [PASSED] drm_test_fb_clip_offset =============
[15:00:21] =================== drm_test_fb_memcpy  ====================
[15:00:21] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:00:21] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:00:21] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:00:21] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:00:21] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:00:21] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:00:21] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:00:21] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:00:21] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:00:21] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:00:21] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:00:21] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:00:21] =============== [PASSED] drm_test_fb_memcpy ================
[15:00:21] ============= [PASSED] drm_format_helper_test ==============
[15:00:21] ================= drm_format (18 subtests) =================
[15:00:21] [PASSED] drm_test_format_block_width_invalid
[15:00:21] [PASSED] drm_test_format_block_width_one_plane
[15:00:21] [PASSED] drm_test_format_block_width_two_plane
[15:00:21] [PASSED] drm_test_format_block_width_three_plane
[15:00:21] [PASSED] drm_test_format_block_width_tiled
[15:00:21] [PASSED] drm_test_format_block_height_invalid
[15:00:21] [PASSED] drm_test_format_block_height_one_plane
[15:00:21] [PASSED] drm_test_format_block_height_two_plane
[15:00:21] [PASSED] drm_test_format_block_height_three_plane
[15:00:21] [PASSED] drm_test_format_block_height_tiled
[15:00:21] [PASSED] drm_test_format_min_pitch_invalid
[15:00:21] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:00:21] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:00:21] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:00:21] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:00:21] [PASSED] drm_test_format_min_pitch_two_plane
[15:00:21] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:00:21] [PASSED] drm_test_format_min_pitch_tiled
[15:00:21] =================== [PASSED] drm_format ====================
[15:00:21] ============== drm_framebuffer (10 subtests) ===============
[15:00:21] ========== drm_test_framebuffer_check_src_coords  ==========
[15:00:21] [PASSED] Success: source fits into fb
[15:00:21] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:00:21] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:00:21] [PASSED] Fail: overflowing fb with source width
[15:00:21] [PASSED] Fail: overflowing fb with source height
[15:00:21] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:00:21] [PASSED] drm_test_framebuffer_cleanup
[15:00:21] =============== drm_test_framebuffer_create  ===============
[15:00:21] [PASSED] ABGR8888 normal sizes
[15:00:21] [PASSED] ABGR8888 max sizes
[15:00:21] [PASSED] ABGR8888 pitch greater than min required
[15:00:21] [PASSED] ABGR8888 pitch less than min required
[15:00:21] [PASSED] ABGR8888 Invalid width
[15:00:21] [PASSED] ABGR8888 Invalid buffer handle
[15:00:21] [PASSED] No pixel format
[15:00:21] [PASSED] ABGR8888 Width 0
[15:00:21] [PASSED] ABGR8888 Height 0
[15:00:21] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:00:21] [PASSED] ABGR8888 Large buffer offset
[15:00:21] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:00:21] [PASSED] ABGR8888 Invalid flag
[15:00:21] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:00:21] [PASSED] ABGR8888 Valid buffer modifier
[15:00:21] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:00:21] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] NV12 Normal sizes
[15:00:21] [PASSED] NV12 Max sizes
[15:00:21] [PASSED] NV12 Invalid pitch
[15:00:21] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:00:21] [PASSED] NV12 different  modifier per-plane
[15:00:21] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:00:21] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] NV12 Modifier for inexistent plane
[15:00:21] [PASSED] NV12 Handle for inexistent plane
[15:00:21] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:00:21] [PASSED] YVU420 Normal sizes
[15:00:21] [PASSED] YVU420 Max sizes
[15:00:21] [PASSED] YVU420 Invalid pitch
[15:00:21] [PASSED] YVU420 Different pitches
[15:00:21] [PASSED] YVU420 Different buffer offsets/pitches
[15:00:21] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:00:21] [PASSED] YVU420 Valid modifier
[15:00:21] [PASSED] YVU420 Different modifiers per plane
[15:00:21] [PASSED] YVU420 Modifier for inexistent plane
[15:00:21] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:00:21] [PASSED] X0L2 Normal sizes
[15:00:21] [PASSED] X0L2 Max sizes
[15:00:21] [PASSED] X0L2 Invalid pitch
[15:00:21] [PASSED] X0L2 Pitch greater than minimum required
[15:00:21] [PASSED] X0L2 Handle for inexistent plane
[15:00:21] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:00:21] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:00:21] [PASSED] X0L2 Valid modifier
[15:00:21] [PASSED] X0L2 Modifier for inexistent plane
[15:00:21] =========== [PASSED] drm_test_framebuffer_create ===========
[15:00:21] [PASSED] drm_test_framebuffer_free
[15:00:21] [PASSED] drm_test_framebuffer_init
[15:00:21] [PASSED] drm_test_framebuffer_init_bad_format
[15:00:21] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:00:21] [PASSED] drm_test_framebuffer_lookup
[15:00:21] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:00:21] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:00:21] ================= [PASSED] drm_framebuffer =================
[15:00:21] ================ drm_gem_shmem (8 subtests) ================
[15:00:21] [PASSED] drm_gem_shmem_test_obj_create
[15:00:21] [PASSED] drm_gem_shmem_test_obj_create_private
[15:00:21] [PASSED] drm_gem_shmem_test_pin_pages
[15:00:21] [PASSED] drm_gem_shmem_test_vmap
[15:00:21] [PASSED] drm_gem_shmem_test_get_sg_table
[15:00:21] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:00:21] [PASSED] drm_gem_shmem_test_madvise
[15:00:21] [PASSED] drm_gem_shmem_test_purge
[15:00:21] ================== [PASSED] drm_gem_shmem ==================
[15:00:21] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:00:21] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:00:21] [PASSED] Automatic
[15:00:21] [PASSED] Full
[15:00:21] [PASSED] Limited 16:235
[15:00:21] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:00:21] [PASSED] drm_test_check_disable_connector
[15:00:21] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:00:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:00:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:00:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:00:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:00:21] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:00:21] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:00:21] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:00:21] [PASSED] drm_test_check_output_bpc_dvi
[15:00:21] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:00:21] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:00:21] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:00:21] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:00:21] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:00:21] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:00:21] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:00:21] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:00:21] ============ drm_test_check_hdmi_color_format  =============
[15:00:21] [PASSED] AUTO -> RGB
[15:00:21] [PASSED] YCBCR422 -> YUV422
[15:00:21] [PASSED] YCBCR420 -> YUV420
[15:00:21] [PASSED] YCBCR444 -> YUV444
[15:00:21] [PASSED] RGB -> RGB
[15:00:21] ======== [PASSED] drm_test_check_hdmi_color_format =========
[15:00:21] ======== drm_test_check_hdmi_color_format_420_only  ========
[15:00:21] [PASSED] RGB should fail
[15:00:21] [PASSED] YUV444 should fail
[15:00:21] [PASSED] YUV422 should fail
[15:00:21] [PASSED] YUV420 should work
[15:00:21] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[15:00:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:00:21] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:00:21] [PASSED] drm_test_check_broadcast_rgb_value
[15:00:21] [PASSED] drm_test_check_bpc_8_value
[15:00:21] [PASSED] drm_test_check_bpc_10_value
[15:00:21] [PASSED] drm_test_check_bpc_12_value
[15:00:21] [PASSED] drm_test_check_format_value
[15:00:21] [PASSED] drm_test_check_tmds_char_value
[15:00:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:00:21] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[15:00:21] [PASSED] drm_test_check_mode_valid
[15:00:21] [PASSED] drm_test_check_mode_valid_reject
[15:00:21] [PASSED] drm_test_check_mode_valid_reject_rate
[15:00:21] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:00:21] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[15:00:21] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[15:00:21] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[15:00:21] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:00:21] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:00:21] [PASSED] drm_test_check_infoframes
[15:00:21] [PASSED] drm_test_check_reject_avi_infoframe
[15:00:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:00:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:00:21] [PASSED] drm_test_check_reject_audio_infoframe
[15:00:21] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:00:21] ================= drm_managed (2 subtests) =================
[15:00:21] [PASSED] drm_test_managed_release_action
[15:00:21] [PASSED] drm_test_managed_run_action
[15:00:21] =================== [PASSED] drm_managed ===================
[15:00:21] =================== drm_mm (6 subtests) ====================
[15:00:21] [PASSED] drm_test_mm_init
[15:00:21] [PASSED] drm_test_mm_debug
[15:00:21] [PASSED] drm_test_mm_align32
[15:00:21] [PASSED] drm_test_mm_align64
[15:00:21] [PASSED] drm_test_mm_lowest
[15:00:21] [PASSED] drm_test_mm_highest
[15:00:21] ===================== [PASSED] drm_mm ======================
[15:00:21] ============= drm_modes_analog_tv (5 subtests) =============
[15:00:21] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:00:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:00:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:00:21] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:00:21] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:00:21] =============== [PASSED] drm_modes_analog_tv ===============
[15:00:21] ============== drm_plane_helper (2 subtests) ===============
[15:00:21] =============== drm_test_check_plane_state  ================
[15:00:21] [PASSED] clipping_simple
[15:00:21] [PASSED] clipping_rotate_reflect
[15:00:21] [PASSED] positioning_simple
[15:00:21] [PASSED] upscaling
[15:00:21] [PASSED] downscaling
[15:00:21] [PASSED] rounding1
[15:00:21] [PASSED] rounding2
[15:00:21] [PASSED] rounding3
[15:00:21] [PASSED] rounding4
[15:00:21] =========== [PASSED] drm_test_check_plane_state ============
[15:00:21] =========== drm_test_check_invalid_plane_state  ============
[15:00:21] [PASSED] positioning_invalid
[15:00:21] [PASSED] upscaling_invalid
[15:00:21] [PASSED] downscaling_invalid
[15:00:21] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:00:21] ================ [PASSED] drm_plane_helper =================
[15:00:21] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:00:21] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:00:21] [PASSED] None
[15:00:21] [PASSED] PAL
[15:00:21] [PASSED] NTSC
[15:00:21] [PASSED] Both, NTSC Default
[15:00:21] [PASSED] Both, PAL Default
[15:00:21] [PASSED] Both, NTSC Default, with PAL on command-line
[15:00:21] [PASSED] Both, PAL Default, with NTSC on command-line
[15:00:21] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:00:21] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:00:21] ================== drm_rect (9 subtests) ===================
[15:00:21] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:00:21] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:00:21] [PASSED] drm_test_rect_clip_scaled_clipped
[15:00:21] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:00:21] ================= drm_test_rect_intersect  =================
[15:00:21] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:00:21] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:00:21] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:00:21] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:00:21] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:00:21] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:00:21] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:00:21] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:00:21] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:00:21] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:00:21] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:00:21] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:00:21] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:00:21] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:00:21] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:00:21] ============= [PASSED] drm_test_rect_intersect =============
[15:00:21] ================ drm_test_rect_calc_hscale  ================
[15:00:21] [PASSED] normal use
[15:00:21] [PASSED] out of max range
[15:00:21] [PASSED] out of min range
[15:00:21] [PASSED] zero dst
[15:00:21] [PASSED] negative src
[15:00:21] [PASSED] negative dst
[15:00:21] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:00:21] ================ drm_test_rect_calc_vscale  ================
[15:00:21] [PASSED] normal use
[15:00:21] [PASSED] out of max range
[15:00:21] [PASSED] out of min range
[15:00:21] [PASSED] zero dst
[15:00:21] [PASSED] negative src
[15:00:21] [PASSED] negative dst
[15:00:21] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:00:21] ================== drm_test_rect_rotate  ===================
[15:00:21] [PASSED] reflect-x
[15:00:21] [PASSED] reflect-y
[15:00:21] [PASSED] rotate-0
[15:00:21] [PASSED] rotate-90
[15:00:21] [PASSED] rotate-180
[15:00:21] [PASSED] rotate-270
[15:00:21] ============== [PASSED] drm_test_rect_rotate ===============
[15:00:21] ================ drm_test_rect_rotate_inv  =================
[15:00:21] [PASSED] reflect-x
[15:00:21] [PASSED] reflect-y
[15:00:21] [PASSED] rotate-0
[15:00:21] [PASSED] rotate-90
[15:00:21] [PASSED] rotate-180
[15:00:21] [PASSED] rotate-270
[15:00:21] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:00:21] ==================== [PASSED] drm_rect =====================
[15:00:21] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:00:21] ============ drm_test_sysfb_build_fourcc_list  =============
[15:00:21] [PASSED] no native formats
[15:00:21] [PASSED] XRGB8888 as native format
[15:00:21] [PASSED] remove duplicates
[15:00:21] [PASSED] convert alpha formats
[15:00:21] [PASSED] random formats
[15:00:21] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:00:21] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:00:21] ================== drm_fixp (2 subtests) ===================
[15:00:21] [PASSED] drm_test_int2fixp
[15:00:21] [PASSED] drm_test_sm2fixp
[15:00:21] ==================== [PASSED] drm_fixp =====================
[15:00:21] ============================================================
[15:00:21] Testing complete. Ran 639 tests: passed: 639
[15:00:21] Elapsed time: 26.194s total, 1.729s configuring, 24.250s building, 0.196s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:00:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:00:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:00:33] Starting KUnit Kernel (1/1)...
[15:00:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:00:33] ================= ttm_device (5 subtests) ==================
[15:00:33] [PASSED] ttm_device_init_basic
[15:00:33] [PASSED] ttm_device_init_multiple
[15:00:33] [PASSED] ttm_device_fini_basic
[15:00:33] [PASSED] ttm_device_init_no_vma_man
[15:00:33] ================== ttm_device_init_pools  ==================
[15:00:33] [PASSED] No DMA allocations, no DMA32 required
[15:00:33] [PASSED] DMA allocations, DMA32 required
[15:00:33] [PASSED] No DMA allocations, DMA32 required
[15:00:33] [PASSED] DMA allocations, no DMA32 required
[15:00:33] ============== [PASSED] ttm_device_init_pools ==============
[15:00:33] =================== [PASSED] ttm_device ====================
[15:00:33] ================== ttm_pool (8 subtests) ===================
[15:00:33] ================== ttm_pool_alloc_basic  ===================
[15:00:33] [PASSED] One page
[15:00:33] [PASSED] More than one page
[15:00:33] [PASSED] Above the allocation limit
[15:00:33] [PASSED] One page, with coherent DMA mappings enabled
[15:00:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:00:33] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:00:33] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:00:33] [PASSED] One page
[15:00:33] [PASSED] More than one page
[15:00:33] [PASSED] Above the allocation limit
[15:00:33] [PASSED] One page, with coherent DMA mappings enabled
[15:00:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:00:33] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:00:33] [PASSED] ttm_pool_alloc_order_caching_match
[15:00:33] [PASSED] ttm_pool_alloc_caching_mismatch
[15:00:33] [PASSED] ttm_pool_alloc_order_mismatch
[15:00:33] [PASSED] ttm_pool_free_dma_alloc
[15:00:33] [PASSED] ttm_pool_free_no_dma_alloc
[15:00:33] [PASSED] ttm_pool_fini_basic
[15:00:33] ==================== [PASSED] ttm_pool =====================
[15:00:33] ================ ttm_resource (8 subtests) =================
[15:00:33] ================= ttm_resource_init_basic  =================
[15:00:33] [PASSED] Init resource in TTM_PL_SYSTEM
[15:00:33] [PASSED] Init resource in TTM_PL_VRAM
[15:00:33] [PASSED] Init resource in a private placement
[15:00:33] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:00:33] ============= [PASSED] ttm_resource_init_basic =============
[15:00:33] [PASSED] ttm_resource_init_pinned
[15:00:33] [PASSED] ttm_resource_fini_basic
[15:00:33] [PASSED] ttm_resource_manager_init_basic
[15:00:33] [PASSED] ttm_resource_manager_usage_basic
[15:00:33] [PASSED] ttm_resource_manager_set_used_basic
[15:00:33] [PASSED] ttm_sys_man_alloc_basic
[15:00:33] [PASSED] ttm_sys_man_free_basic
[15:00:33] ================== [PASSED] ttm_resource ===================
[15:00:33] =================== ttm_tt (15 subtests) ===================
[15:00:33] ==================== ttm_tt_init_basic  ====================
[15:00:33] [PASSED] Page-aligned size
[15:00:33] [PASSED] Extra pages requested
[15:00:33] ================ [PASSED] ttm_tt_init_basic ================
[15:00:33] [PASSED] ttm_tt_init_misaligned
[15:00:33] [PASSED] ttm_tt_fini_basic
[15:00:33] [PASSED] ttm_tt_fini_sg
[15:00:33] [PASSED] ttm_tt_fini_shmem
[15:00:33] [PASSED] ttm_tt_create_basic
[15:00:33] [PASSED] ttm_tt_create_invalid_bo_type
[15:00:33] [PASSED] ttm_tt_create_ttm_exists
[15:00:33] [PASSED] ttm_tt_create_failed
[15:00:33] [PASSED] ttm_tt_destroy_basic
[15:00:33] [PASSED] ttm_tt_populate_null_ttm
[15:00:33] [PASSED] ttm_tt_populate_populated_ttm
[15:00:33] [PASSED] ttm_tt_unpopulate_basic
[15:00:33] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:00:33] [PASSED] ttm_tt_swapin_basic
[15:00:33] ===================== [PASSED] ttm_tt ======================
[15:00:33] =================== ttm_bo (14 subtests) ===================
[15:00:33] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:00:33] [PASSED] Cannot be interrupted and sleeps
[15:00:33] [PASSED] Cannot be interrupted, locks straight away
[15:00:33] [PASSED] Can be interrupted, sleeps
[15:00:33] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:00:33] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:00:33] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:00:33] [PASSED] ttm_bo_reserve_double_resv
[15:00:33] [PASSED] ttm_bo_reserve_interrupted
[15:00:33] [PASSED] ttm_bo_reserve_deadlock
[15:00:33] [PASSED] ttm_bo_unreserve_basic
[15:00:33] [PASSED] ttm_bo_unreserve_pinned
[15:00:33] [PASSED] ttm_bo_unreserve_bulk
[15:00:33] [PASSED] ttm_bo_fini_basic
[15:00:33] [PASSED] ttm_bo_fini_shared_resv
[15:00:33] [PASSED] ttm_bo_pin_basic
[15:00:33] [PASSED] ttm_bo_pin_unpin_resource
[15:00:33] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:00:33] ===================== [PASSED] ttm_bo ======================
[15:00:33] ============== ttm_bo_validate (22 subtests) ===============
[15:00:33] ============== ttm_bo_init_reserved_sys_man  ===============
[15:00:33] [PASSED] Buffer object for userspace
[15:00:33] [PASSED] Kernel buffer object
[15:00:33] [PASSED] Shared buffer object
[15:00:33] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:00:33] ============== ttm_bo_init_reserved_mock_man  ==============
[15:00:33] [PASSED] Buffer object for userspace
[15:00:33] [PASSED] Kernel buffer object
[15:00:33] [PASSED] Shared buffer object
[15:00:33] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:00:33] [PASSED] ttm_bo_init_reserved_resv
[15:00:33] ================== ttm_bo_validate_basic  ==================
[15:00:33] [PASSED] Buffer object for userspace
[15:00:33] [PASSED] Kernel buffer object
[15:00:33] [PASSED] Shared buffer object
[15:00:33] ============== [PASSED] ttm_bo_validate_basic ==============
[15:00:33] [PASSED] ttm_bo_validate_invalid_placement
[15:00:33] ============= ttm_bo_validate_same_placement  ==============
[15:00:33] [PASSED] System manager
[15:00:33] [PASSED] VRAM manager
[15:00:33] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:00:33] [PASSED] ttm_bo_validate_failed_alloc
[15:00:33] [PASSED] ttm_bo_validate_pinned
[15:00:33] [PASSED] ttm_bo_validate_busy_placement
[15:00:33] ================ ttm_bo_validate_multihop  =================
[15:00:33] [PASSED] Buffer object for userspace
[15:00:33] [PASSED] Kernel buffer object
[15:00:33] [PASSED] Shared buffer object
[15:00:33] ============ [PASSED] ttm_bo_validate_multihop =============
[15:00:33] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:00:33] [PASSED] Buffer object in system domain, no page vector
[15:00:33] [PASSED] Buffer object in system domain with an existing page vector
[15:00:33] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:00:33] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:00:33] [PASSED] Buffer object for userspace
[15:00:33] [PASSED] Kernel buffer object
[15:00:33] [PASSED] Shared buffer object
[15:00:33] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:00:33] [PASSED] ttm_bo_validate_move_fence_signaled
[15:00:33] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:00:33] [PASSED] Waits for GPU
[15:00:33] [PASSED] Tries to lock straight away
[15:00:33] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:00:33] [PASSED] ttm_bo_validate_swapout
[15:00:33] [PASSED] ttm_bo_validate_happy_evict
[15:00:33] [PASSED] ttm_bo_validate_all_pinned_evict
[15:00:33] [PASSED] ttm_bo_validate_allowed_only_evict
[15:00:33] [PASSED] ttm_bo_validate_deleted_evict
[15:00:33] [PASSED] ttm_bo_validate_busy_domain_evict
[15:00:33] [PASSED] ttm_bo_validate_evict_gutting
[15:00:33] [PASSED] ttm_bo_validate_recrusive_evict
[15:00:33] ================= [PASSED] ttm_bo_validate =================
[15:00:33] ============================================================
[15:00:33] Testing complete. Ran 102 tests: passed: 102
[15:00:33] Elapsed time: 11.637s total, 1.763s configuring, 9.660s building, 0.175s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable CMRR in fixed-RR VRR path

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 939 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb_BAT -> xe-pw-168613v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): bat-lnl-2 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb -> xe-pw-168613v1

  IGT_8966: 9b33225c761bfe8c8c266bc56558d75c700029fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb: 70646d7ea3ac559ed269c0a38cd3699fea4e1eeb
  xe-pw-168613v1: 168613v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/index.html

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✗ Xe.CI.FULL: failure for Enable CMRR in fixed-RR VRR path

[Patchwork]

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== Series Details ==

Series: Enable CMRR in fixed-RR VRR path
URL   : https://patchwork.freedesktop.org/series/168613/
State : failure

== Summary ==

CI Bug Log - changes from xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb_FULL -> xe-pw-168613v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-168613v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-168613v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-168613v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [PASS][1] -> [ABORT][2] +11 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-lnl-2/igt@kms_vrr@flip-basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-lnl-5/igt@kms_vrr@flip-basic.html

  
Known issues
------------

  Here are the changes found in xe-pw-168613v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#367])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2887])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#3432])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2252])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#8265])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#6126] / [Intel XE#776])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][10] -> [FAIL][11] ([Intel XE#301])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][12] -> [FAIL][13] ([Intel XE#301] / [Intel XE#3149])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#4141]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2352] / [Intel XE#7399])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2311]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2313]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [PASS][19] -> [SKIP][20] ([Intel XE#7915]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-bmg-10/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-2/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7283]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_pm_backlight@fade:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_pm_backlight@fade.html

  * igt@kms_psr@fbc-pr-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@kms_psr@fbc-pr-sprite-blt.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@xe_eudebug_online@pagefault-read-stress:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7636]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@xe_eudebug_online@pagefault-read-stress.html

  * igt@xe_exec_fault_mode@twice-multi-queue-rebind-imm:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#7136]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@xe_exec_fault_mode@twice-multi-queue-rebind-imm.html

  * igt@xe_exec_multi_queue@max-queues-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#6874]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@xe_exec_multi_queue@max-queues-close-fd-smem.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7866])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@xe_exec_reset@cm-multi-queue-cat-error.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#7138])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-conflict:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#6964])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@xe_multigpu_svm@mgpu-atomic-op-conflict.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2284] / [Intel XE#7370])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-10/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#944])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-1/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][33] ([Intel XE#301]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads:
    - shard-bmg:          [FAIL][35] ([Intel XE#7850]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-bmg-4/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-bmg-3/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][37] ([Intel XE#301]) -> [FAIL][38] ([Intel XE#301] / [Intel XE#3149])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb -> xe-pw-168613v1

  IGT_8966: 9b33225c761bfe8c8c266bc56558d75c700029fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5264-70646d7ea3ac559ed269c0a38cd3699fea4e1eeb: 70646d7ea3ac559ed269c0a38cd3699fea4e1eeb
  xe-pw-168613v1: 168613v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v1/index.html

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