Re: [PATCH v12 00/13] AuxCCS handling and render compression modifiers

[Tvrtko Ursulin <tvrtko.ursulin@igalia.com>]

On 23/09/2025 21:12, Ville Syrjälä wrote:
> On Tue, Sep 23, 2025 at 11:07:53AM +0100, Tvrtko Ursulin wrote:
>> A series to fix and add xe support for AuxCSS framebuffers via DPT.
>>
>> Currently the auxiliary buffer data isn't mapped into the page tables at all so
>> cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
>> had to disable the support.
>>
>> On top of that there are missing flushes, invalidations and similar.
>>
>> Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:
>>
>>    [PLANE:32:plane 1A]: type=PRI
>>            uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
>>            hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
>>
>> Display working fine - no artefacts, no DMAR/PIPE faults.
>>
>> All IGTs pass for me locally.
>>
>> v2:
>>   * More patches added to fix kms_flip_tiling.
>>
>> v3:
>>   * Rebased after some cleanup patches from v2 were merged.
>>   * Added people to Cc as suggested by Rodrigo.
>>   * Adjusted last patch title. (Rodrigo)
>>   * Apply GGTT flushing only to iomapped system memory buffers.
>>
>> v4:
>>   * Added patch for potentially misplaced Wa_14016712196.
>>   * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.
>>
>> v5:
>>   * Split out ring emission changes to smaller patches.
>>   * Fixed MAX_JOB_SIZE_DW even more.
>>   * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.
>>
>>   v6:
>>   * Added AuxCCS invalidation to indirect context workarounds.
>>   * Also added the indirect context handling and some other workarounds. They are
>>     unrelated but the series depends on it.
>>   * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
>>     some reason.
> 
> I was wondering where that went. Someone should actually debug
> that instead of leaving the bogus alignemnt in place.

I do not exactly remember what the failures were but I *think* they were 
sporadic and I definitely fixed some other details since. So I think it 
is possible I incorrectly blamed that patch at the time.  I'll re-send 
it to see what CI will say.

> We do have some unknown alignment issues on i915 as well,
> with async flips specifically. On ADL we've papered over it
> for now. But at least MTL is suffering from somewhat similar
> issues that I failed to immediately understand. We really
> should find someone who has a bit of time to dig into these...
> 
> BTW intel_fb_pin_to_ggtt() also passes the wrong alignment to
> __xe_pin_fb_vma(). I suppose it won't help with DPT alignment
> woes, but it's yet another xe issue that needs fixing.

The last part looks obviously wrong indeed. I can send a fix for that.

Regards,

Tvrtko