From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-xe@lists.freedesktop.org, kernel-dev@igalia.com
Subject: Re: [PATCH v12 11/13] drm/xe: Force flush system memory AuxCCS framebuffers before scan out
Date: Thu, 2 Oct 2025 15:36:40 +0100 [thread overview]
Message-ID: <ffdee2e1-e46a-4c4f-9502-fdd7c65ccb0c@igalia.com> (raw)
In-Reply-To: <7fde2c90-5d3e-406e-9d5b-6620123e2d2e@igalia.com>
On 02/10/2025 15:01, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 26/09/2025 20:35, Ville Syrjälä wrote:
>> On Fri, Sep 26, 2025 at 10:41:56AM +0300, Ville Syrjälä wrote:
>>> I reverse engineered this a bit and there's definitely a
>>> MOCS issue at play.
>>>
>>> First I noticed that if filled the entire MOCS table with
>>> UC the problem went away. I then filled the entire table
>>> with WB and essentially bisected what I need to make UC
>>> to fix it. And I had to repeat that same process starting
>>> from the other end of table.
>>>
>>> Looks like there is some undocumented magic in the hardware.
>>>
>>> MOCS 61 really is special:
>>> - MOCS 61 UC, others WB, select MOCS 61 -> no corruption
>>>
>>> MOCS 0 and 63 are special in other ways:
>>> - MOCS X UC, others WB, select MOCS X -> corruption
>>> - MOCS X+0 UC, others WB, select MOCS X -> corruption
>>> - MOCS X+63 UC, others WB, select MOCS X -> corruption
>>> - MOCS X+0+63 UC, others WB, select MOCS X -> no corruption
>>> where X != 61
>>
>> OK, the MOCS 63 issue was caused by me having L3=WB still in
>> MOCS X. If I change MOCS X to L3=UC, MOCS 63 no longer makes
>> a difference. I suppose that means MOCS 63 is still used for
>> L3 evictions, even though bspec no longer mentions that fact
>> explicitly.
>>
>> So MOCS 0 is the thing that really matters for CCS. And for
>> MOCS 0 only the LLC WB vs. UC selection matters. L3 WB vs. UC
>> doesn't seem to make any difference.
>>
>> It's interesting that MOCS 60 is documented as a "CCS special case",
>> but in reality it's MOCS 0 that matters for CCS. I wonder if some
>> wires got crossed in the hw design and the wrong MOCS entry ended
>> up being used for CCS and no one noticed...
>
> Oh wow, that is an amazing discovery!
>
> I verified it on my end too. Setting MOCS 0 to uncached and cache dirt
> is gone. No need to the explicit cache flush patch on first pin.
>
> Luckily ADL is unsupported so we could change it to UC. I will send a
> series for CI to see what it will say.
Doh, but it would be bad to change it for all uses which actually do not
want UC. Sorry did not wake up fully... So assuming the test CI runs
will be all clear it will still be a difficult situation on what to do.
Regards,
Tvrtko
next prev parent reply other threads:[~2025-10-02 14:36 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 10:07 [PATCH v12 00/13] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-09-23 10:07 ` [PATCH v12 01/13] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-09-23 10:07 ` [PATCH v12 02/13] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2025-10-01 15:47 ` Rodrigo Vivi
2025-09-23 10:07 ` [PATCH v12 03/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-09-23 10:07 ` [PATCH v12 04/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-09-23 10:07 ` [PATCH v12 05/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-09-23 10:07 ` [PATCH v12 06/13] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 07/13] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 08/13] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 09/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 10/13] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 11/13] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-09-23 10:19 ` Ville Syrjälä
2025-09-23 10:48 ` Tvrtko Ursulin
2025-09-23 12:01 ` Ville Syrjälä
2025-09-23 12:25 ` Tvrtko Ursulin
2025-09-23 13:20 ` Ville Syrjälä
2025-09-23 14:40 ` Tvrtko Ursulin
2025-09-23 14:52 ` Ville Syrjälä
2025-09-24 13:09 ` Tvrtko Ursulin
2025-09-24 22:35 ` Ville Syrjälä
2025-09-25 7:24 ` Tvrtko Ursulin
2025-09-25 10:08 ` Tvrtko Ursulin
2025-09-26 7:41 ` Ville Syrjälä
2025-09-26 19:35 ` Ville Syrjälä
2025-10-02 14:01 ` Tvrtko Ursulin
2025-10-02 14:36 ` Tvrtko Ursulin [this message]
2025-10-02 16:23 ` Ville Syrjälä
2025-10-02 17:04 ` Tvrtko Ursulin
2025-10-02 17:14 ` Ville Syrjälä
2025-10-02 22:02 ` Ville Syrjälä
2025-09-23 10:44 ` [PATCH v13 " Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 12/13] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS Tvrtko Ursulin
2025-09-23 10:08 ` [PATCH v12 13/13] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-09-23 10:15 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev15) Patchwork
2025-09-23 10:16 ` ✓ CI.KUnit: success " Patchwork
2025-09-23 11:15 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-23 11:21 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev16) Patchwork
2025-09-23 11:22 ` ✓ CI.KUnit: success " Patchwork
2025-09-23 12:03 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-23 13:26 ` ✗ Xe.CI.Full: failure for AuxCCS handling and render compression modifiers (rev15) Patchwork
2025-09-23 14:12 ` ✗ Xe.CI.Full: failure for AuxCCS handling and render compression modifiers (rev16) Patchwork
2025-09-23 20:12 ` [PATCH v12 00/13] AuxCCS handling and render compression modifiers Ville Syrjälä
2025-09-24 7:59 ` Tvrtko Ursulin
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