* [v7 01/15] drm/i915/display: Add identifiers for driver specific blocks
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-02 7:42 ` [v7, " Murthy, Arun R
2025-12-01 6:46 ` [v7 02/15] drm/i915: Add intel_color_op Uma Shankar
` (18 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add macros to identify intel specific color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
v2:- Prefix enums with INTEL_* (Jani, Suraj)
- Remove unnecessary comments (Jani)
- Commit message improvements (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index f0fa27e365ab..55fd574ba313 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -138,4 +138,12 @@ enum hpd_pin {
HPD_NUM_PINS
};
+enum intel_color_block {
+ INTEL_PLANE_CB_PRE_CSC_LUT,
+ INTEL_PLANE_CB_CSC,
+ INTEL_PLANE_CB_POST_CSC_LUT,
+
+ INTEL_CB_MAX
+};
+
#endif /* __INTEL_DISPLAY_LIMITS_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [v7, 01/15] drm/i915/display: Add identifiers for driver specific blocks
2025-12-01 6:46 ` [v7 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
@ 2025-12-02 7:42 ` Murthy, Arun R
2025-12-02 8:04 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 44+ messages in thread
From: Murthy, Arun R @ 2025-12-02 7:42 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal
On 01-12-2025 12:16, Uma Shankar wrote:
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add macros to identify intel specific color blocks. It will help
> in mapping drm_color_ops to intel color HW blocks
>
> v2:- Prefix enums with INTEL_* (Jani, Suraj)
> - Remove unnecessary comments (Jani)
> - Commit message improvements (Suraj)
>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_limits.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index f0fa27e365ab..55fd574ba313 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -138,4 +138,12 @@ enum hpd_pin {
> HPD_NUM_PINS
> };
>
> +enum intel_color_block {
Can this be intel_plane_color_block/pipeline as we get a new
block/pipeline for crtc which can later be named as
intel_crtc_color_block/pipeline
Thanks and Regards,
Arun R Murthy
-------------------
> + INTEL_PLANE_CB_PRE_CSC_LUT,
> + INTEL_PLANE_CB_CSC,
> + INTEL_PLANE_CB_POST_CSC_LUT,
> +
> + INTEL_CB_MAX
> +};
> +
> #endif /* __INTEL_DISPLAY_LIMITS_H__ */
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7, 01/15] drm/i915/display: Add identifiers for driver specific blocks
2025-12-02 7:42 ` [v7, " Murthy, Arun R
@ 2025-12-02 8:04 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 44+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-02 8:04 UTC (permalink / raw)
To: Murthy, Arun R, Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: ville.syrjala, pekka.paalanen, contact, harry.wentland, mwen,
jadahl, sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On 12/2/2025 1:12 PM, Murthy, Arun R wrote:
> On 01-12-2025 12:16, Uma Shankar wrote:
>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>
>> Add macros to identify intel specific color blocks. It will help
>> in mapping drm_color_ops to intel color HW blocks
>>
>> v2:- Prefix enums with INTEL_* (Jani, Suraj)
>> - Remove unnecessary comments (Jani)
>> - Commit message improvements (Suraj)
>>
>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_limits.h | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/
>> drivers/gpu/drm/i915/display/intel_display_limits.h
>> index f0fa27e365ab..55fd574ba313 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
>> @@ -138,4 +138,12 @@ enum hpd_pin {
>> HPD_NUM_PINS
>> };
>> +enum intel_color_block {
>
> Can this be intel_plane_color_block/pipeline as we get a new block/
> pipeline for crtc which can later be named as intel_crtc_color_block/
> pipeline
I had given it a thought but we don't really need a different enum
because all the intel_colorop code is agnostic to which object it is
attached to. Otherwise we have to create plane and crtc specific colorop
functions without much need of it. So, I envision it as a single colorop
enum type serving both plane and crtc but with appropriate prefix.
enum intel_color_block {
/* Plane color blocks */
INTEL_PLANE_CB_PRE_CSC_LUT,
INTEL_PLANE_CB_CSC,
INTEL_PLANE_CB_POST_CSC_LUT,
INTEL_PLANE_CB_3DLUT,
/* CRTC color blocks */
INTEL_CRTC_CB_PRE_CSC_LUT,
...
INTEL_CB_MAX
};
==
Chaitanya
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
>> + INTEL_PLANE_CB_PRE_CSC_LUT,
>> + INTEL_PLANE_CB_CSC,
>> + INTEL_PLANE_CB_POST_CSC_LUT,
>> +
>> + INTEL_CB_MAX
>> +};
>> +
>> #endif /* __INTEL_DISPLAY_LIMITS_H__ */
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 02/15] drm/i915: Add intel_color_op
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-12-01 6:46 ` [v7 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 14:21 ` kernel test robot
2025-12-01 6:46 ` [v7 03/15] drm/i915/color: Add helper to create intel colorop Uma Shankar
` (17 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add data structure to store intel specific details of colorop
v2:
- Remove dead code
- Convert macro to function (Jani)
- Remove colorop state as it is not being used
- Refactor to separate file
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_colorop.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_colorop.h | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +++++
drivers/gpu/drm/xe/Makefile | 1 +
5 files changed, 30 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.c
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b2250432ae98..7c19d5345d88 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -240,6 +240,7 @@ i915-y += \
display/intel_cdclk.o \
display/intel_cmtg.o \
display/intel_color.o \
+ display/intel_colorop.o \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_crtc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.c b/drivers/gpu/drm/i915/display/intel_colorop.c
new file mode 100644
index 000000000000..eaab50d2d126
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_colorop.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "intel_colorop.h"
+
+struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop)
+{
+ return container_of(colorop, struct intel_colorop, base);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.h b/drivers/gpu/drm/i915/display/intel_colorop.h
new file mode 100644
index 000000000000..23a29a565949
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_colorop.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_COLOROP_H__
+#define __INTEL_COLOROP_H__
+
+#include "intel_display_types.h"
+
+struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop);
+
+#endif /* __INTEL_COLOROP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38702a9e0f50..bb8b8466235a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1985,6 +1985,11 @@ struct intel_dp_mst_encoder {
struct intel_connector *connector;
};
+struct intel_colorop {
+ struct drm_colorop base;
+ enum intel_color_block id;
+};
+
static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector *connector)
{
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index a7e13a676f7d..3420725c4ba8 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -234,6 +234,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_cdclk.o \
i915-display/intel_cmtg.o \
i915-display/intel_color.o \
+ i915-display/intel_colorop.o \
i915-display/intel_combo_phy.o \
i915-display/intel_connector.o \
i915-display/intel_crtc.o \
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [v7 02/15] drm/i915: Add intel_color_op
2025-12-01 6:46 ` [v7 02/15] drm/i915: Add intel_color_op Uma Shankar
@ 2025-12-01 14:21 ` kernel test robot
0 siblings, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 14:21 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[also build test ERROR on linus/master v6.18]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-3-uma.shankar%40intel.com
patch subject: [v7 02/15] drm/i915: Add intel_color_op
config: i386-buildonly-randconfig-006-20251201 (https://download.01.org/0day-ci/archive/20251201/202512012214.cxi2Gair-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251201/202512012214.cxi2Gair-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512012214.cxi2Gair-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_colorop.h:9,
from drivers/gpu/drm/i915/display/intel_colorop.c:5:
drivers/gpu/drm/i915/display/intel_display_types.h:1989:28: error: field 'base' has incomplete type
1989 | struct drm_colorop base;
| ^~~~
In file included from include/linux/container_of.h:5,
from include/linux/plist.h:76,
from include/linux/pm_qos.h:15,
from drivers/gpu/drm/i915/display/intel_display_types.h:29:
drivers/gpu/drm/i915/display/intel_colorop.c: In function 'to_intel_colorop':
>> include/linux/compiler_types.h:552:27: error: expression in static assertion is not an integer
552 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:21:9: note: in expansion of macro 'static_assert'
21 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_colorop.c:9:16: note: in expansion of macro 'container_of'
9 | return container_of(colorop, struct intel_colorop, base);
| ^~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_colorop.c:10:1: warning: control reaches end of non-void function [-Wreturn-type]
10 | }
| ^
vim +10 drivers/gpu/drm/i915/display/intel_colorop.c
6
7 struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop)
8 {
9 return container_of(colorop, struct intel_colorop, base);
> 10 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 03/15] drm/i915/color: Add helper to create intel colorop
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-12-01 6:46 ` [v7 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
2025-12-01 6:46 ` [v7 02/15] drm/i915: Add intel_color_op Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 6:46 ` [v7 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
` (16 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add intel colorop create helper
v2:
- Make function names consistent (Jani)
- Remove redundant code related to colorop state
- Refactor code to separate files
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_colorop.c | 25 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_colorop.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.c b/drivers/gpu/drm/i915/display/intel_colorop.c
index eaab50d2d126..f2fc0d8780ce 100644
--- a/drivers/gpu/drm/i915/display/intel_colorop.c
+++ b/drivers/gpu/drm/i915/display/intel_colorop.c
@@ -8,3 +8,28 @@ struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop)
{
return container_of(colorop, struct intel_colorop, base);
}
+
+struct intel_colorop *intel_colorop_alloc(void)
+{
+ struct intel_colorop *colorop;
+
+ colorop = kzalloc(sizeof(*colorop), GFP_KERNEL);
+ if (!colorop)
+ return ERR_PTR(-ENOMEM);
+
+ return colorop;
+}
+
+struct intel_colorop *intel_colorop_create(enum intel_color_block id)
+{
+ struct intel_colorop *colorop;
+
+ colorop = intel_colorop_alloc();
+
+ if (IS_ERR(colorop))
+ return colorop;
+
+ colorop->id = id;
+
+ return colorop;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.h b/drivers/gpu/drm/i915/display/intel_colorop.h
index 23a29a565949..21d58eb9f3d0 100644
--- a/drivers/gpu/drm/i915/display/intel_colorop.h
+++ b/drivers/gpu/drm/i915/display/intel_colorop.h
@@ -9,5 +9,7 @@
#include "intel_display_types.h"
struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop);
+struct intel_colorop *intel_colorop_alloc(void);
+struct intel_colorop *intel_colorop_create(enum intel_color_block id);
#endif /* __INTEL_COLOROP_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [v7 04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (2 preceding siblings ...)
2025-12-01 6:46 ` [v7 03/15] drm/i915/color: Add helper to create intel colorop Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:02 ` Kandpal, Suraj
` (2 more replies)
2025-12-01 6:46 ` [v7 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
` (15 subsequent siblings)
19 siblings, 3 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add a color pipeline with three colorops in the sequence
1D LUT - 3x4 CTM - 1D LUT
This pipeline can be used to do any color space conversion or HDR
tone mapping
v2: Change namespace to drm_plane_colorop*
v3: Use simpler/pre-existing colorops for first iteration
v4:
- s/*_tf_*/*_color_* (Jani)
- Refactor to separate files (Jani)
- Add missing space in comment (Suraj)
- Consolidate patch that adds/attaches pipeline property
v5:
- Limit MAX_COLOR_PIPELINES to 2.(Suraj)
Increase it as and when we add more pipelines.
- Remove redundant initialization code (Suraj)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_color_pipeline.c | 97 +++++++++++++++++++
.../drm/i915/display/intel_color_pipeline.h | 13 +++
drivers/gpu/drm/xe/Makefile | 1 +
4 files changed, 112 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7c19d5345d88..ca5c69d1cb08 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -241,6 +241,7 @@ i915-y += \
display/intel_cmtg.o \
display/intel_color.o \
display/intel_colorop.o \
+ display/intel_color_pipeline.o \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_crtc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
new file mode 100644
index 000000000000..1415f94dd3e3
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "intel_colorop.h"
+#include "intel_color_pipeline.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "skl_universal_plane.h"
+
+#define MAX_COLOR_PIPELINES 2
+#define PLANE_DEGAMMA_SIZE 128
+#define PLANE_GAMMA_SIZE 32
+
+static
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+{
+ struct intel_colorop *colorop;
+ struct drm_device *dev = plane->dev;
+ int ret;
+ struct drm_colorop *prev_op;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
+
+ ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+ PLANE_DEGAMMA_SIZE,
+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+
+ if (ret)
+ return ret;
+
+ list->type = colorop->base.base.id;
+ list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
+
+ /* TODO: handle failures and clean up */
+ prev_op = &colorop->base;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
+ ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+ prev_op = &colorop->base;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
+ ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+ PLANE_GAMMA_SIZE,
+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+
+ return 0;
+}
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct intel_display *display = to_intel_display(dev);
+ struct drm_property *prop;
+ struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
+ int len = 0;
+ int ret;
+
+ /* Currently expose pipeline only for HDR planes */
+ if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
+ return 0;
+
+ /* Add "Bypass" (i.e. NULL) pipeline */
+ pipelines[len].type = 0;
+ pipelines[len].name = "Bypass";
+ len++;
+
+ /* Add pipeline consisting of transfer functions */
+ ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
+ if (ret)
+ return ret;
+ len++;
+
+ /* Create COLOR_PIPELINE property and attach */
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
+ "COLOR_PIPELINE",
+ pipelines, len);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->color_pipeline_property = prop;
+
+ drm_object_attach_property(&plane->base, prop, 0);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
new file mode 100644
index 000000000000..7f1d32bc9202
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_COLOR_PIPELINE_H__
+#define __INTEL_COLOR_PIPELINE_H__
+
+struct drm_plane;
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane);
+
+#endif /* __INTEL_COLOR_PIPELINE_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3420725c4ba8..89f922d745ba 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -235,6 +235,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_cmtg.o \
i915-display/intel_color.o \
i915-display/intel_colorop.o \
+ i915-display/intel_color_pipeline.o \
i915-display/intel_combo_phy.o \
i915-display/intel_connector.o \
i915-display/intel_crtc.o \
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-01 6:46 ` [v7 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
@ 2025-12-01 9:02 ` Kandpal, Suraj
2025-12-01 15:55 ` kernel test robot
2025-12-02 7:56 ` [v7,04/15] " Murthy, Arun R
2 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:02 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 04/15] drm/i915/color: Create a transfer function color pipeline
>
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add a color pipeline with three colorops in the sequence
>
> 1D LUT - 3x4 CTM - 1D LUT
>
> This pipeline can be used to do any color space conversion or HDR tone
> mapping
>
> v2: Change namespace to drm_plane_colorop*
> v3: Use simpler/pre-existing colorops for first iteration
> v4:
> - s/*_tf_*/*_color_* (Jani)
> - Refactor to separate files (Jani)
> - Add missing space in comment (Suraj)
> - Consolidate patch that adds/attaches pipeline property
> v5:
> - Limit MAX_COLOR_PIPELINES to 2.(Suraj)
> Increase it as and when we add more pipelines.
> - Remove redundant initialization code (Suraj)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_color_pipeline.c | 97 +++++++++++++++++++
> .../drm/i915/display/intel_color_pipeline.h | 13 +++
> drivers/gpu/drm/xe/Makefile | 1 +
> 4 files changed, 112 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7c19d5345d88..ca5c69d1cb08 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -241,6 +241,7 @@ i915-y += \
> display/intel_cmtg.o \
> display/intel_color.o \
> display/intel_colorop.o \
> + display/intel_color_pipeline.o \
> display/intel_combo_phy.o \
> display/intel_connector.o \
> display/intel_crtc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> new file mode 100644
> index 000000000000..1415f94dd3e3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +#include "intel_colorop.h"
> +#include "intel_color_pipeline.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "skl_universal_plane.h"
> +
> +#define MAX_COLOR_PIPELINES 2
> +#define PLANE_DEGAMMA_SIZE 128
> +#define PLANE_GAMMA_SIZE 32
> +
> +static
> +int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct
> +drm_prop_enum_list *list) {
> + struct intel_colorop *colorop;
> + struct drm_device *dev = plane->dev;
> + int ret;
> + struct drm_colorop *prev_op;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
> +
> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base,
> plane,
> + PLANE_DEGAMMA_SIZE,
> +
> DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
> +
> DRM_COLOROP_FLAG_ALLOW_BYPASS);
> +
> + if (ret)
> + return ret;
> +
> + list->type = colorop->base.base.id;
> + list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d",
> +colorop->base.base.id);
> +
> + /* TODO: handle failures and clean up */
> + prev_op = &colorop->base;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> + ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
> +
> DRM_COLOROP_FLAG_ALLOW_BYPASS);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> + prev_op = &colorop->base;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base,
> plane,
> + PLANE_GAMMA_SIZE,
> +
> DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
> +
> DRM_COLOROP_FLAG_ALLOW_BYPASS);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> +
> + return 0;
> +}
> +
> +int intel_color_pipeline_plane_init(struct drm_plane *plane) {
> + struct drm_device *dev = plane->dev;
> + struct intel_display *display = to_intel_display(dev);
> + struct drm_property *prop;
> + struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
> + int len = 0;
> + int ret;
> +
> + /* Currently expose pipeline only for HDR planes */
> + if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
> + return 0;
> +
> + /* Add "Bypass" (i.e. NULL) pipeline */
I think we can do away with th "(i.e NULL)" part since the documentation at drm core does a good job explaining what BYPASS pipeline is
With that fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> + pipelines[len].type = 0;
> + pipelines[len].name = "Bypass";
> + len++;
> +
> + /* Add pipeline consisting of transfer functions */
> + ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
> + if (ret)
> + return ret;
> + len++;
> +
> + /* Create COLOR_PIPELINE property and attach */
> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
> + "COLOR_PIPELINE",
> + pipelines, len);
> + if (!prop)
> + return -ENOMEM;
> +
> + plane->color_pipeline_property = prop;
> +
> + drm_object_attach_property(&plane->base, prop, 0);
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> new file mode 100644
> index 000000000000..7f1d32bc9202
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_COLOR_PIPELINE_H__
> +#define __INTEL_COLOR_PIPELINE_H__
> +
> +struct drm_plane;
> +
> +int intel_color_pipeline_plane_init(struct drm_plane *plane);
> +
> +#endif /* __INTEL_COLOR_PIPELINE_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> 3420725c4ba8..89f922d745ba 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -235,6 +235,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_cmtg.o \
> i915-display/intel_color.o \
> i915-display/intel_colorop.o \
> + i915-display/intel_color_pipeline.o \
> i915-display/intel_combo_phy.o \
> i915-display/intel_connector.o \
> i915-display/intel_crtc.o \
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7 04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-01 6:46 ` [v7 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-12-01 9:02 ` Kandpal, Suraj
@ 2025-12-01 15:55 ` kernel test robot
2025-12-02 7:56 ` [v7,04/15] " Murthy, Arun R
2 siblings, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 15:55 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[also build test ERROR on linus/master v6.18]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-5-uma.shankar%40intel.com
patch subject: [v7 04/15] drm/i915/color: Create a transfer function color pipeline
config: i386-buildonly-randconfig-006-20251201 (https://download.01.org/0day-ci/archive/20251201/202512012314.C2mdxzIy-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251201/202512012314.C2mdxzIy-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512012314.C2mdxzIy-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_colorop.h:9,
from drivers/gpu/drm/i915/display/intel_color_pipeline.c:5:
drivers/gpu/drm/i915/display/intel_display_types.h:1989:28: error: field 'base' has incomplete type
1989 | struct drm_colorop base;
| ^~~~
drivers/gpu/drm/i915/display/intel_color_pipeline.c: In function '_intel_color_pipeline_plane_init':
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:25:15: error: implicit declaration of function 'drm_plane_colorop_curve_1d_lut_init' [-Wimplicit-function-declaration]
25 | ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:27:51: error: 'DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR' undeclared (first use in this function)
27 | DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_color_pipeline.c:27:51: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:28:51: error: 'DRM_COLOROP_FLAG_ALLOW_BYPASS' undeclared (first use in this function)
28 | DRM_COLOROP_FLAG_ALLOW_BYPASS);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:40:15: error: implicit declaration of function 'drm_plane_colorop_ctm_3x4_init' [-Wimplicit-function-declaration]
40 | ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:45:9: error: implicit declaration of function 'drm_colorop_set_next_property'; did you mean 'drm_connector_set_tile_property'? [-Wimplicit-function-declaration]
45 | drm_colorop_set_next_property(prev_op, &colorop->base);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| drm_connector_set_tile_property
drivers/gpu/drm/i915/display/intel_color_pipeline.c: In function 'intel_color_pipeline_plane_init':
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c:92:16: error: 'struct drm_plane' has no member named 'color_pipeline_property'; did you mean 'color_encoding_property'?
92 | plane->color_pipeline_property = prop;
| ^~~~~~~~~~~~~~~~~~~~~~~
| color_encoding_property
vim +/drm_plane_colorop_curve_1d_lut_init +25 drivers/gpu/drm/i915/display/intel_color_pipeline.c
> 5 #include "intel_colorop.h"
6 #include "intel_color_pipeline.h"
7 #include "intel_de.h"
8 #include "intel_display_types.h"
9 #include "skl_universal_plane.h"
10
11 #define MAX_COLOR_PIPELINES 2
12 #define PLANE_DEGAMMA_SIZE 128
13 #define PLANE_GAMMA_SIZE 32
14
15 static
16 int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
17 {
18 struct intel_colorop *colorop;
19 struct drm_device *dev = plane->dev;
20 int ret;
21 struct drm_colorop *prev_op;
22
23 colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
24
> 25 ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
26 PLANE_DEGAMMA_SIZE,
> 27 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
> 28 DRM_COLOROP_FLAG_ALLOW_BYPASS);
29
30 if (ret)
31 return ret;
32
33 list->type = colorop->base.base.id;
34 list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
35
36 /* TODO: handle failures and clean up */
37 prev_op = &colorop->base;
38
39 colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> 40 ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
41 DRM_COLOROP_FLAG_ALLOW_BYPASS);
42 if (ret)
43 return ret;
44
> 45 drm_colorop_set_next_property(prev_op, &colorop->base);
46 prev_op = &colorop->base;
47
48 colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
49 ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
50 PLANE_GAMMA_SIZE,
51 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
52 DRM_COLOROP_FLAG_ALLOW_BYPASS);
53 if (ret)
54 return ret;
55
56 drm_colorop_set_next_property(prev_op, &colorop->base);
57
58 return 0;
59 }
60
61 int intel_color_pipeline_plane_init(struct drm_plane *plane)
62 {
63 struct drm_device *dev = plane->dev;
64 struct intel_display *display = to_intel_display(dev);
65 struct drm_property *prop;
66 struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
67 int len = 0;
68 int ret;
69
70 /* Currently expose pipeline only for HDR planes */
71 if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
72 return 0;
73
74 /* Add "Bypass" (i.e. NULL) pipeline */
75 pipelines[len].type = 0;
76 pipelines[len].name = "Bypass";
77 len++;
78
79 /* Add pipeline consisting of transfer functions */
80 ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
81 if (ret)
82 return ret;
83 len++;
84
85 /* Create COLOR_PIPELINE property and attach */
86 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
87 "COLOR_PIPELINE",
88 pipelines, len);
89 if (!prop)
90 return -ENOMEM;
91
> 92 plane->color_pipeline_property = prop;
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7,04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-01 6:46 ` [v7 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-12-01 9:02 ` Kandpal, Suraj
2025-12-01 15:55 ` kernel test robot
@ 2025-12-02 7:56 ` Murthy, Arun R
2025-12-02 8:20 ` Borah, Chaitanya Kumar
2 siblings, 1 reply; 44+ messages in thread
From: Murthy, Arun R @ 2025-12-02 7:56 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal
On 01-12-2025 12:16, Uma Shankar wrote:
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add a color pipeline with three colorops in the sequence
>
> 1D LUT - 3x4 CTM - 1D LUT
>
> This pipeline can be used to do any color space conversion or HDR
> tone mapping
>
> v2: Change namespace to drm_plane_colorop*
> v3: Use simpler/pre-existing colorops for first iteration
> v4:
> - s/*_tf_*/*_color_* (Jani)
> - Refactor to separate files (Jani)
> - Add missing space in comment (Suraj)
> - Consolidate patch that adds/attaches pipeline property
> v5:
> - Limit MAX_COLOR_PIPELINES to 2.(Suraj)
> Increase it as and when we add more pipelines.
> - Remove redundant initialization code (Suraj)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_color_pipeline.c | 97 +++++++++++++++++++
> .../drm/i915/display/intel_color_pipeline.h | 13 +++
> drivers/gpu/drm/xe/Makefile | 1 +
> 4 files changed, 112 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7c19d5345d88..ca5c69d1cb08 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -241,6 +241,7 @@ i915-y += \
> display/intel_cmtg.o \
> display/intel_color.o \
> display/intel_colorop.o \
> + display/intel_color_pipeline.o \
> display/intel_combo_phy.o \
> display/intel_connector.o \
> display/intel_crtc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> new file mode 100644
> index 000000000000..1415f94dd3e3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +#include "intel_colorop.h"
> +#include "intel_color_pipeline.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "skl_universal_plane.h"
> +
> +#define MAX_COLOR_PIPELINES 2
Should this be same as INTEL_CB_MAX defined in intel_display_limits.h ?
> +#define PLANE_DEGAMMA_SIZE 128
> +#define PLANE_GAMMA_SIZE 32
> +
> +static
> +int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
> +{
> + struct intel_colorop *colorop;
> + struct drm_device *dev = plane->dev;
> + int ret;
> + struct drm_colorop *prev_op;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
> +
> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
> + PLANE_DEGAMMA_SIZE,
> + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
> +
> + if (ret)
> + return ret;
> +
> + list->type = colorop->base.base.id;
> + list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
> +
> + /* TODO: handle failures and clean up */
> + prev_op = &colorop->base;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> + ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> + prev_op = &colorop->base;
> +
> + colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
> + PLANE_GAMMA_SIZE,
> + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> +
> + return 0;
> +}
> +
> +int intel_color_pipeline_plane_init(struct drm_plane *plane)
> +{
> + struct drm_device *dev = plane->dev;
> + struct intel_display *display = to_intel_display(dev);
> + struct drm_property *prop;
> + struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
> + int len = 0;
> + int ret;
> +
> + /* Currently expose pipeline only for HDR planes */
> + if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
> + return 0;
> +
> + /* Add "Bypass" (i.e. NULL) pipeline */
> + pipelines[len].type = 0;
> + pipelines[len].name = "Bypass";
> + len++;
Code for creating Bypass and COLOR_PIPELINE property is there in
drm_core and is exported as drm_plane_create_color_pipeline_property()
Can this function be used to avoid code duplication?
Thanks and Regards,
Arun R Murthy
-------------------
> +
> + /* Add pipeline consisting of transfer functions */
> + ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
> + if (ret)
> + return ret;
> + len++;
> +
> + /* Create COLOR_PIPELINE property and attach */
> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
> + "COLOR_PIPELINE",
> + pipelines, len);
> + if (!prop)
> + return -ENOMEM;
> +
> + plane->color_pipeline_property = prop;
> +
> + drm_object_attach_property(&plane->base, prop, 0);
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> new file mode 100644
> index 000000000000..7f1d32bc9202
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_COLOR_PIPELINE_H__
> +#define __INTEL_COLOR_PIPELINE_H__
> +
> +struct drm_plane;
> +
> +int intel_color_pipeline_plane_init(struct drm_plane *plane);
> +
> +#endif /* __INTEL_COLOR_PIPELINE_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 3420725c4ba8..89f922d745ba 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -235,6 +235,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_cmtg.o \
> i915-display/intel_color.o \
> i915-display/intel_colorop.o \
> + i915-display/intel_color_pipeline.o \
> i915-display/intel_combo_phy.o \
> i915-display/intel_connector.o \
> i915-display/intel_crtc.o \
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7,04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-02 7:56 ` [v7,04/15] " Murthy, Arun R
@ 2025-12-02 8:20 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 44+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-02 8:20 UTC (permalink / raw)
To: Murthy, Arun R, Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: ville.syrjala, pekka.paalanen, contact, harry.wentland, mwen,
jadahl, sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On 12/2/2025 1:26 PM, Murthy, Arun R wrote:
>
> On 01-12-2025 12:16, Uma Shankar wrote:
>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>
>> Add a color pipeline with three colorops in the sequence
>>
>> 1D LUT - 3x4 CTM - 1D LUT
>>
>> This pipeline can be used to do any color space conversion or HDR
>> tone mapping
>>
>> v2: Change namespace to drm_plane_colorop*
>> v3: Use simpler/pre-existing colorops for first iteration
>> v4:
>> - s/*_tf_*/*_color_* (Jani)
>> - Refactor to separate files (Jani)
>> - Add missing space in comment (Suraj)
>> - Consolidate patch that adds/attaches pipeline property
>> v5:
>> - Limit MAX_COLOR_PIPELINES to 2.(Suraj)
>> Increase it as and when we add more pipelines.
>> - Remove redundant initialization code (Suraj)
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile | 1 +
>> .../drm/i915/display/intel_color_pipeline.c | 97 +++++++++++++++++++
>> .../drm/i915/display/intel_color_pipeline.h | 13 +++
>> drivers/gpu/drm/xe/Makefile | 1 +
>> 4 files changed, 112 insertions(+)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
>> create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/
>> Makefile
>> index 7c19d5345d88..ca5c69d1cb08 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -241,6 +241,7 @@ i915-y += \
>> display/intel_cmtg.o \
>> display/intel_color.o \
>> display/intel_colorop.o \
>> + display/intel_color_pipeline.o \
>> display/intel_combo_phy.o \
>> display/intel_connector.o \
>> display/intel_crtc.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/
>> drivers/gpu/drm/i915/display/intel_color_pipeline.c
>> new file mode 100644
>> index 000000000000..1415f94dd3e3
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
>> @@ -0,0 +1,97 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +#include "intel_colorop.h"
>> +#include "intel_color_pipeline.h"
>> +#include "intel_de.h"
>> +#include "intel_display_types.h"
>> +#include "skl_universal_plane.h"
>> +
>> +#define MAX_COLOR_PIPELINES 2
> Should this be same as INTEL_CB_MAX defined in intel_display_limits.h ?
>> +#define PLANE_DEGAMMA_SIZE 128
>> +#define PLANE_GAMMA_SIZE 32
>> +
>> +static
>> +int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct
>> drm_prop_enum_list *list)
>> +{
>> + struct intel_colorop *colorop;
>> + struct drm_device *dev = plane->dev;
>> + int ret;
>> + struct drm_colorop *prev_op;
>> +
>> + colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
>> +
>> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base,
>> plane,
>> + PLANE_DEGAMMA_SIZE,
>> + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
>> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
>> +
>> + if (ret)
>> + return ret;
>> +
>> + list->type = colorop->base.base.id;
>> + list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop-
>> >base.base.id);
>> +
>> + /* TODO: handle failures and clean up */
>> + prev_op = &colorop->base;
>> +
>> + colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
>> + ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
>> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
>> + if (ret)
>> + return ret;
>> +
>> + drm_colorop_set_next_property(prev_op, &colorop->base);
>> + prev_op = &colorop->base;
>> +
>> + colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
>> + ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base,
>> plane,
>> + PLANE_GAMMA_SIZE,
>> + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
>> + DRM_COLOROP_FLAG_ALLOW_BYPASS);
>> + if (ret)
>> + return ret;
>> +
>> + drm_colorop_set_next_property(prev_op, &colorop->base);
>> +
>> + return 0;
>> +}
>> +
>> +int intel_color_pipeline_plane_init(struct drm_plane *plane)
>> +{
>> + struct drm_device *dev = plane->dev;
>> + struct intel_display *display = to_intel_display(dev);
>> + struct drm_property *prop;
>> + struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
>> + int len = 0;
>> + int ret;
>> +
>> + /* Currently expose pipeline only for HDR planes */
>> + if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
>> + return 0;
>> +
>> + /* Add "Bypass" (i.e. NULL) pipeline */
>> + pipelines[len].type = 0;
>> + pipelines[len].name = "Bypass";
>> + len++;
> Code for creating Bypass and COLOR_PIPELINE property is there in
> drm_core and is exported as drm_plane_create_color_pipeline_property()
>
> Can this function be used to avoid code duplication?
Makes sense. Would be added in the next version.
Regards
Chaitanya
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
>> +
>> + /* Add pipeline consisting of transfer functions */
>> + ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
>> + if (ret)
>> + return ret;
>> + len++;
>> +
>> + /* Create COLOR_PIPELINE property and attach */
>> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
>> + "COLOR_PIPELINE",
>> + pipelines, len);
>> + if (!prop)
>> + return -ENOMEM;
>> +
>> + plane->color_pipeline_property = prop;
>> +
>> + drm_object_attach_property(&plane->base, prop, 0);
>> +
>> + return 0;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/
>> drivers/gpu/drm/i915/display/intel_color_pipeline.h
>> new file mode 100644
>> index 000000000000..7f1d32bc9202
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
>> @@ -0,0 +1,13 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_COLOR_PIPELINE_H__
>> +#define __INTEL_COLOR_PIPELINE_H__
>> +
>> +struct drm_plane;
>> +
>> +int intel_color_pipeline_plane_init(struct drm_plane *plane);
>> +
>> +#endif /* __INTEL_COLOR_PIPELINE_H__ */
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 3420725c4ba8..89f922d745ba 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -235,6 +235,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_cmtg.o \
>> i915-display/intel_color.o \
>> i915-display/intel_colorop.o \
>> + i915-display/intel_color_pipeline.o \
>> i915-display/intel_combo_phy.o \
>> i915-display/intel_connector.o \
>> i915-display/intel_crtc.o \
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 05/15] drm/i915/color: Add framework to program CSC
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (3 preceding siblings ...)
2025-12-01 6:46 ` [v7 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:05 ` Kandpal, Suraj
2025-12-01 15:45 ` kernel test robot
2025-12-01 6:46 ` [v7 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
` (14 subsequent siblings)
19 siblings, 2 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add framework to program CSC. It enables copying of matrix from UAPI
to intel plane state. Also add helper functions which will eventually
program values to hardware.
Add a crtc state variable to track plane color change.
v2:
- Add crtc_state->plane_color_changed
- Improve comments (Suraj)
- s/intel_plane_*_color/intel_plane_color_* (Suraj)
v3:
- align parameters with open braces (Suraj)
- Improve commit message (Suraj)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 21 ++++++++
drivers/gpu/drm/i915/display/intel_color.h | 4 +-
.../drm/i915/display/intel_display_types.h | 4 ++
drivers/gpu/drm/i915/display/intel_plane.c | 49 +++++++++++++++++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a217a67ceb43..33fe5c9b4663 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -87,6 +87,10 @@ struct intel_color_funcs {
* Read config other than LUTs and CSCs, before them. Optional.
*/
void (*get_config)(struct intel_crtc_state *crtc_state);
+
+ /* Plane CSC*/
+ void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -3963,6 +3967,23 @@ static const struct intel_color_funcs ilk_color_funcs = {
.get_config = ilk_get_config,
};
+static void
+intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+
+ if (display->funcs.color->load_plane_csc_matrix)
+ display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
+}
+
+void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.ctm)
+ intel_color_load_plane_csc_matrix(dsb, plane_state);
+}
+
void intel_color_crtc_init(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index bf7a12ce9df0..8051c827a1d8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -13,6 +13,7 @@ struct intel_crtc_state;
struct intel_crtc;
struct intel_display;
struct intel_dsb;
+struct intel_plane_state;
struct drm_property_blob;
void intel_color_init_hooks(struct intel_display *display);
@@ -40,5 +41,6 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob2,
bool is_pre_csc_lut);
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
-
+void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bb8b8466235a..6d8217497583 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,6 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
+ struct drm_property_blob *ctm;
} hw;
struct i915_vma *ggtt_vma;
@@ -1391,6 +1392,9 @@ struct intel_crtc_state {
u8 silence_period_sym_clocks;
u8 lfps_half_cycle_num_of_syms;
} alpm_state;
+
+ /* to track changes in plane color blocks */
+ bool plane_color_changed;
};
enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 7b7619d59251..328b12af4d27 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -48,6 +48,7 @@
#include "i9xx_plane_regs.h"
#include "intel_cdclk.h"
#include "intel_cursor.h"
+#include "intel_colorop.h"
#include "intel_display_rps.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
@@ -340,6 +341,52 @@ intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
*damage = drm_plane_state_src(&new_uapi_plane_state->uapi);
}
+static bool
+intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
+ struct intel_colorop *intel_colorop,
+ struct drm_property_blob *blob)
+{
+ if (intel_colorop->id == INTEL_PLANE_CB_CSC)
+ return drm_property_replace_blob(&plane_state->hw.ctm, blob);
+
+ return false;
+}
+
+static void
+intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state,
+ struct intel_crtc *crtc)
+{
+ struct drm_colorop *iter_colorop, *colorop;
+ struct drm_colorop_state *new_colorop_state;
+ struct drm_atomic_state *state = plane_state->uapi.state;
+ struct intel_colorop *intel_colorop;
+ struct drm_property_blob *blob;
+ int i = 0;
+ struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state);
+ struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
+ intel_atomic_get_new_crtc_state(intel_atomic_state, crtc) : NULL;
+ bool changed = false;
+
+ iter_colorop = plane_state->uapi.color_pipeline;
+
+ while (iter_colorop) {
+ for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
+ if (new_colorop_state->colorop == iter_colorop) {
+ blob = new_colorop_state->bypass ? NULL : new_colorop_state->data;
+ intel_colorop = to_intel_colorop(colorop);
+ changed |= intel_plane_colorop_replace_blob(plane_state,
+ intel_colorop,
+ blob);
+ }
+ }
+ iter_colorop = iter_colorop->next;
+ }
+
+ if (new_crtc_state && changed)
+ new_crtc_state->plane_color_changed = true;
+}
+
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state,
struct intel_crtc *crtc)
@@ -368,6 +415,8 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
+
+ intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);
}
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 05/15] drm/i915/color: Add framework to program CSC
2025-12-01 6:46 ` [v7 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
@ 2025-12-01 9:05 ` Kandpal, Suraj
2025-12-01 15:45 ` kernel test robot
1 sibling, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:05 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 05/15] drm/i915/color: Add framework to program CSC
>
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add framework to program CSC. It enables copying of matrix from UAPI to intel
> plane state. Also add helper functions which will eventually program values to
> hardware.
>
> Add a crtc state variable to track plane color change.
>
> v2:
> - Add crtc_state->plane_color_changed
> - Improve comments (Suraj)
> - s/intel_plane_*_color/intel_plane_color_* (Suraj)
>
> v3:
> - align parameters with open braces (Suraj)
> - Improve commit message (Suraj)
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 21 ++++++++
> drivers/gpu/drm/i915/display/intel_color.h | 4 +-
> .../drm/i915/display/intel_display_types.h | 4 ++
> drivers/gpu/drm/i915/display/intel_plane.c | 49 +++++++++++++++++++
> 4 files changed, 77 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index a217a67ceb43..33fe5c9b4663 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -87,6 +87,10 @@ struct intel_color_funcs {
> * Read config other than LUTs and CSCs, before them. Optional.
> */
> void (*get_config)(struct intel_crtc_state *crtc_state);
> +
> + /* Plane CSC*/
> + void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
> + const struct intel_plane_state
> *plane_state);
> };
>
> #define CTM_COEFF_SIGN (1ULL << 63)
> @@ -3963,6 +3967,23 @@ static const struct intel_color_funcs ilk_color_funcs
> = {
> .get_config = ilk_get_config,
> };
>
> +static void
> +intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> +
> + if (display->funcs.color->load_plane_csc_matrix)
> + display->funcs.color->load_plane_csc_matrix(dsb,
> plane_state); }
> +
> +void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> + const struct intel_plane_state
> *plane_state) {
> + if (plane_state->hw.ctm)
> + intel_color_load_plane_csc_matrix(dsb, plane_state); }
> +
> void intel_color_crtc_init(struct intel_crtc *crtc) {
> struct intel_display *display = to_intel_display(crtc); diff --git
> a/drivers/gpu/drm/i915/display/intel_color.h
> b/drivers/gpu/drm/i915/display/intel_color.h
> index bf7a12ce9df0..8051c827a1d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.h
> +++ b/drivers/gpu/drm/i915/display/intel_color.h
> @@ -13,6 +13,7 @@ struct intel_crtc_state; struct intel_crtc; struct
> intel_display; struct intel_dsb;
> +struct intel_plane_state;
> struct drm_property_blob;
>
> void intel_color_init_hooks(struct intel_display *display); @@ -40,5 +41,6 @@
> bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
> const struct drm_property_blob *blob2,
> bool is_pre_csc_lut);
> void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
> -
> +void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> + const struct intel_plane_state
> *plane_state);
> #endif /* __INTEL_COLOR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index bb8b8466235a..6d8217497583 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -646,6 +646,7 @@ struct intel_plane_state {
> enum drm_color_encoding color_encoding;
> enum drm_color_range color_range;
> enum drm_scaling_filter scaling_filter;
> + struct drm_property_blob *ctm;
> } hw;
>
> struct i915_vma *ggtt_vma;
> @@ -1391,6 +1392,9 @@ struct intel_crtc_state {
> u8 silence_period_sym_clocks;
> u8 lfps_half_cycle_num_of_syms;
> } alpm_state;
> +
> + /* to track changes in plane color blocks */
> + bool plane_color_changed;
> };
>
> enum intel_pipe_crc_source {
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> b/drivers/gpu/drm/i915/display/intel_plane.c
> index 7b7619d59251..328b12af4d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -48,6 +48,7 @@
> #include "i9xx_plane_regs.h"
> #include "intel_cdclk.h"
> #include "intel_cursor.h"
> +#include "intel_colorop.h"
> #include "intel_display_rps.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> @@ -340,6 +341,52 @@ intel_plane_copy_uapi_plane_damage(struct
> intel_plane_state *new_plane_state,
> *damage = drm_plane_state_src(&new_uapi_plane_state-
> >uapi);
> }
>
> +static bool
> +intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
> + struct intel_colorop *intel_colorop,
> + struct drm_property_blob *blob)
> +{
> + if (intel_colorop->id == INTEL_PLANE_CB_CSC)
> + return drm_property_replace_blob(&plane_state->hw.ctm,
> blob);
> +
> + return false;
> +}
> +
> +static void
> +intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state
> *plane_state,
> + const struct intel_plane_state
> *from_plane_state,
> + struct intel_crtc *crtc)
> +{
> + struct drm_colorop *iter_colorop, *colorop;
> + struct drm_colorop_state *new_colorop_state;
> + struct drm_atomic_state *state = plane_state->uapi.state;
> + struct intel_colorop *intel_colorop;
> + struct drm_property_blob *blob;
> + int i = 0;
Nit: move this below bool or just above it keep all the struct together
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> + struct intel_atomic_state *intel_atomic_state =
> to_intel_atomic_state(state);
> + struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
> + intel_atomic_get_new_crtc_state(intel_atomic_state, crtc) :
> NULL;
> + bool changed = false;
> +
> + iter_colorop = plane_state->uapi.color_pipeline;
> +
> + while (iter_colorop) {
> + for_each_new_colorop_in_state(state, colorop,
> new_colorop_state, i) {
> + if (new_colorop_state->colorop == iter_colorop) {
> + blob = new_colorop_state->bypass ? NULL :
> new_colorop_state->data;
> + intel_colorop = to_intel_colorop(colorop);
> + changed |=
> intel_plane_colorop_replace_blob(plane_state,
> +
> intel_colorop,
> +
> blob);
> + }
> + }
> + iter_colorop = iter_colorop->next;
> + }
> +
> + if (new_crtc_state && changed)
> + new_crtc_state->plane_color_changed = true; }
> +
> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
> *plane_state,
> const struct intel_plane_state
> *from_plane_state,
> struct intel_crtc *crtc)
> @@ -368,6 +415,8 @@ void intel_plane_copy_uapi_to_hw_state(struct
> intel_plane_state *plane_state,
>
> plane_state->uapi.src = drm_plane_state_src(&from_plane_state-
> >uapi);
> plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state-
> >uapi);
> +
> + intel_plane_color_copy_uapi_to_hw_state(plane_state,
> from_plane_state,
> +crtc);
> }
>
> void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7 05/15] drm/i915/color: Add framework to program CSC
2025-12-01 6:46 ` [v7 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
2025-12-01 9:05 ` Kandpal, Suraj
@ 2025-12-01 15:45 ` kernel test robot
1 sibling, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 15:45 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6 linus/master v6.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-6-uma.shankar%40intel.com
patch subject: [v7 05/15] drm/i915/color: Add framework to program CSC
config: x86_64-randconfig-012-20251201 (https://download.01.org/0day-ci/archive/20251201/202512012301.V42g2qYb-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251201/202512012301.V42g2qYb-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512012301.V42g2qYb-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_colorop.h:9,
from drivers/gpu/drm/i915/display/intel_plane.c:52:
drivers/gpu/drm/i915/display/intel_display_types.h:1993:28: error: field 'base' has incomplete type
1993 | struct drm_colorop base;
| ^~~~
drivers/gpu/drm/i915/display/intel_plane.c: In function 'intel_plane_color_copy_uapi_to_hw_state':
drivers/gpu/drm/i915/display/intel_plane.c:367:41: error: 'struct drm_plane_state' has no member named 'color_pipeline'
367 | iter_colorop = plane_state->uapi.color_pipeline;
| ^
drivers/gpu/drm/i915/display/intel_plane.c:370:17: error: implicit declaration of function 'for_each_new_colorop_in_state'; did you mean 'for_each_new_crtc_in_state'? [-Wimplicit-function-declaration]
370 | for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| for_each_new_crtc_in_state
drivers/gpu/drm/i915/display/intel_plane.c:370:84: error: expected ';' before '{' token
370 | for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
| ^~
| ;
>> drivers/gpu/drm/i915/display/intel_plane.c:360:35: error: unused variable 'blob' [-Werror=unused-variable]
360 | struct drm_property_blob *blob;
| ^~~~
>> drivers/gpu/drm/i915/display/intel_plane.c:359:31: error: unused variable 'intel_colorop' [-Werror=unused-variable]
359 | struct intel_colorop *intel_colorop;
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_plane.c: At top level:
>> drivers/gpu/drm/i915/display/intel_plane.c:341:1: error: 'intel_plane_colorop_replace_blob' defined but not used [-Werror=unused-function]
341 | intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/blob +360 drivers/gpu/drm/i915/display/intel_plane.c
339
340 static bool
> 341 intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
342 struct intel_colorop *intel_colorop,
343 struct drm_property_blob *blob)
344 {
345 if (intel_colorop->id == INTEL_PLANE_CB_CSC)
346 return drm_property_replace_blob(&plane_state->hw.ctm, blob);
347
348 return false;
349 }
350
351 static void
352 intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
353 const struct intel_plane_state *from_plane_state,
354 struct intel_crtc *crtc)
355 {
356 struct drm_colorop *iter_colorop, *colorop;
357 struct drm_colorop_state *new_colorop_state;
358 struct drm_atomic_state *state = plane_state->uapi.state;
> 359 struct intel_colorop *intel_colorop;
> 360 struct drm_property_blob *blob;
361 int i = 0;
362 struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state);
363 struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
364 intel_atomic_get_new_crtc_state(intel_atomic_state, crtc) : NULL;
365 bool changed = false;
366
367 iter_colorop = plane_state->uapi.color_pipeline;
368
369 while (iter_colorop) {
> 370 for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
371 if (new_colorop_state->colorop == iter_colorop) {
372 blob = new_colorop_state->bypass ? NULL : new_colorop_state->data;
373 intel_colorop = to_intel_colorop(colorop);
374 changed |= intel_plane_colorop_replace_blob(plane_state,
375 intel_colorop,
376 blob);
377 }
378 }
379 iter_colorop = iter_colorop->next;
380 }
381
382 if (new_crtc_state && changed)
383 new_crtc_state->plane_color_changed = true;
384 }
385
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (4 preceding siblings ...)
2025-12-01 6:46 ` [v7 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 6:46 ` [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
` (13 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
When int_bits == 0, we lose the sign bit when we do the range check
and apply the mask.
Fix this by ensuring a minimum of one integer bit, which guarantees space
for the sign bit in fully fractional representations (e.g. S0.12)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 33fe5c9b4663..81b87fed8878 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -613,6 +613,8 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
if (CTM_COEFF_NEGATIVE(coeff))
c = -c;
+ int_bits = max(int_bits, 1);
+
c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
(s64)(BIT(int_bits + frac_bits - 1) - 1));
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (5 preceding siblings ...)
2025-12-01 6:46 ` [v7 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:16 ` Kandpal, Suraj
2025-12-01 18:13 ` kernel test robot
2025-12-01 6:46 ` [v7 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
` (12 subsequent siblings)
19 siblings, 2 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add callback for setting CTM block in platforms D12 and beyond
v2:
- Add dsb support
- Pass plane_state as we are now doing a uapi to hw state copy
- Add support for 3x4 matrix
v3:
- Add relevant header file
- Fix typo (Suraj)
- Add callback to TGL+ (Suraj)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 98 ++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 81b87fed8878..2f8e985d51e5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -32,6 +32,8 @@
#include "intel_display_utils.h"
#include "intel_dsb.h"
#include "intel_vrr.h"
+#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
struct intel_color_funcs {
int (*color_check)(struct intel_atomic_state *state,
@@ -3842,6 +3844,101 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+static void
+xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_property_blob *blob = plane_state->hw.ctm;
+ struct drm_color_ctm_3x4 *ctm;
+ const u64 *input;
+ u16 coeffs[9] = {};
+ int i, j;
+
+ if (!icl_is_hdr_plane(display, plane) || !blob)
+ return;
+
+ ctm = blob->data;
+ input = ctm->matrix;
+
+ /*
+ * Convert fixed point S31.32 input to format supported by the
+ * hardware.
+ */
+ for (i = 0, j = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[j];
+
+ /*
+ * Clamp input value to min/max supported by
+ * hardware.
+ */
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[j]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+
+ /* Skip postoffs */
+ if (!((j + 2) % 4))
+ j += 2;
+ else
+ j++;
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
+ coeffs[2] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
+ coeffs[3] << 16 | coeffs[4]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[5] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
+ coeffs[6] << 16 | coeffs[7]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[8] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ /*
+ * Conversion from S31.32 to S0.12. BIT[12] is the signed bit
+ */
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 0),
+ ctm_to_twos_complement(input[3], 0, 12));
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 1),
+ ctm_to_twos_complement(input[7], 0, 12));
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 2),
+ ctm_to_twos_complement(input[11], 0, 12));
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3889,6 +3986,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
.get_config = skl_get_config,
+ .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
};
static const struct intel_color_funcs icl_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond
2025-12-01 6:46 ` [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
@ 2025-12-01 9:16 ` Kandpal, Suraj
2025-12-01 18:13 ` kernel test robot
1 sibling, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:16 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and
> beyond
>
> Add callback for setting CTM block in platforms D12 and beyond
>
> v2:
> - Add dsb support
> - Pass plane_state as we are now doing a uapi to hw state copy
> - Add support for 3x4 matrix
>
> v3:
> - Add relevant header file
> - Fix typo (Suraj)
> - Add callback to TGL+ (Suraj)
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 98 ++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 81b87fed8878..2f8e985d51e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -32,6 +32,8 @@
> #include "intel_display_utils.h"
> #include "intel_dsb.h"
> #include "intel_vrr.h"
> +#include "skl_universal_plane.h"
> +#include "skl_universal_plane_regs.h"
>
> struct intel_color_funcs {
> int (*color_check)(struct intel_atomic_state *state, @@ -3842,6
> +3844,101 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
> }
> }
>
> +static void
> +xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> + const struct drm_plane_state *state = &plane_state->uapi;
> + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> + enum plane_id plane = to_intel_plane(state->plane)->id;
Lets have a variable intel_plane rather than inlining this specially if we need it at more than one place.
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> + const struct drm_property_blob *blob = plane_state->hw.ctm;
> + struct drm_color_ctm_3x4 *ctm;
> + const u64 *input;
> + u16 coeffs[9] = {};
> + int i, j;
> +
> + if (!icl_is_hdr_plane(display, plane) || !blob)
> + return;
> +
> + ctm = blob->data;
> + input = ctm->matrix;
> +
> + /*
> + * Convert fixed point S31.32 input to format supported by the
> + * hardware.
> + */
> + for (i = 0, j = 0; i < ARRAY_SIZE(coeffs); i++) {
> + u64 abs_coeff = ((1ULL << 63) - 1) & input[j];
> +
> + /*
> + * Clamp input value to min/max supported by
> + * hardware.
> + */
> + abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
> +
> + /* sign bit */
> + if (CTM_COEFF_NEGATIVE(input[j]))
> + coeffs[i] |= 1 << 15;
> +
> + if (abs_coeff < CTM_COEFF_0_125)
> + coeffs[i] |= (3 << 12) |
> + ILK_CSC_COEFF_FP(abs_coeff, 12);
> + else if (abs_coeff < CTM_COEFF_0_25)
> + coeffs[i] |= (2 << 12) |
> + ILK_CSC_COEFF_FP(abs_coeff, 11);
> + else if (abs_coeff < CTM_COEFF_0_5)
> + coeffs[i] |= (1 << 12) |
> + ILK_CSC_COEFF_FP(abs_coeff, 10);
> + else if (abs_coeff < CTM_COEFF_1_0)
> + coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
> + else if (abs_coeff < CTM_COEFF_2_0)
> + coeffs[i] |= (7 << 12) |
> + ILK_CSC_COEFF_FP(abs_coeff, 8);
> + else
> + coeffs[i] |= (6 << 12) |
> + ILK_CSC_COEFF_FP(abs_coeff, 7);
> +
> + /* Skip postoffs */
> + if (!((j + 2) % 4))
> + j += 2;
> + else
> + j++;
> + }
> +
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
> + coeffs[0] << 16 | coeffs[1]);
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
> + coeffs[2] << 16);
> +
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
> + coeffs[3] << 16 | coeffs[4]);
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
> + coeffs[5] << 16);
> +
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
> + coeffs[6] << 16 | coeffs[7]);
> + intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
> + coeffs[8] << 16);
> +
> + intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0),
> 0);
> + intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1),
> 0);
> + intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2),
> 0);
> +
> + /*
> + * Conversion from S31.32 to S0.12. BIT[12] is the signed bit
> + */
> + intel_de_write_dsb(display, dsb,
> + PLANE_CSC_POSTOFF(pipe, plane, 0),
> + ctm_to_twos_complement(input[3], 0, 12));
> + intel_de_write_dsb(display, dsb,
> + PLANE_CSC_POSTOFF(pipe, plane, 1),
> + ctm_to_twos_complement(input[7], 0, 12));
> + intel_de_write_dsb(display, dsb,
> + PLANE_CSC_POSTOFF(pipe, plane, 2),
> + ctm_to_twos_complement(input[11], 0, 12)); }
> +
> static const struct intel_color_funcs chv_color_funcs = {
> .color_check = chv_color_check,
> .color_commit_arm = i9xx_color_commit_arm, @@ -3889,6 +3986,7
> @@ static const struct intel_color_funcs tgl_color_funcs = {
> .lut_equal = icl_lut_equal,
> .read_csc = icl_read_csc,
> .get_config = skl_get_config,
> + .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
> };
>
> static const struct intel_color_funcs icl_color_funcs = {
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond
2025-12-01 6:46 ` [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
2025-12-01 9:16 ` Kandpal, Suraj
@ 2025-12-01 18:13 ` kernel test robot
1 sibling, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 18:13 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6 linus/master v6.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-8-uma.shankar%40intel.com
patch subject: [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond
config: i386-buildonly-randconfig-006-20251201 (https://download.01.org/0day-ci/archive/20251202/202512020215.qWaNGjB2-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251202/202512020215.qWaNGjB2-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512020215.qWaNGjB2-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_color.c:31:
drivers/gpu/drm/i915/display/intel_display_types.h:1993:28: error: field 'base' has incomplete type
1993 | struct drm_colorop base;
| ^~~~
drivers/gpu/drm/i915/display/intel_color.c: In function 'xelpd_load_plane_csc_matrix':
>> drivers/gpu/drm/i915/display/intel_color.c:3865:20: error: invalid use of undefined type 'struct drm_color_ctm_3x4'
3865 | input = ctm->matrix;
| ^~
vim +3865 drivers/gpu/drm/i915/display/intel_color.c
3846
3847 static void
3848 xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
3849 const struct intel_plane_state *plane_state)
3850 {
3851 struct intel_display *display = to_intel_display(plane_state);
3852 const struct drm_plane_state *state = &plane_state->uapi;
3853 enum pipe pipe = to_intel_plane(state->plane)->pipe;
3854 enum plane_id plane = to_intel_plane(state->plane)->id;
3855 const struct drm_property_blob *blob = plane_state->hw.ctm;
3856 struct drm_color_ctm_3x4 *ctm;
3857 const u64 *input;
3858 u16 coeffs[9] = {};
3859 int i, j;
3860
3861 if (!icl_is_hdr_plane(display, plane) || !blob)
3862 return;
3863
3864 ctm = blob->data;
> 3865 input = ctm->matrix;
3866
3867 /*
3868 * Convert fixed point S31.32 input to format supported by the
3869 * hardware.
3870 */
3871 for (i = 0, j = 0; i < ARRAY_SIZE(coeffs); i++) {
3872 u64 abs_coeff = ((1ULL << 63) - 1) & input[j];
3873
3874 /*
3875 * Clamp input value to min/max supported by
3876 * hardware.
3877 */
3878 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
3879
3880 /* sign bit */
3881 if (CTM_COEFF_NEGATIVE(input[j]))
3882 coeffs[i] |= 1 << 15;
3883
3884 if (abs_coeff < CTM_COEFF_0_125)
3885 coeffs[i] |= (3 << 12) |
3886 ILK_CSC_COEFF_FP(abs_coeff, 12);
3887 else if (abs_coeff < CTM_COEFF_0_25)
3888 coeffs[i] |= (2 << 12) |
3889 ILK_CSC_COEFF_FP(abs_coeff, 11);
3890 else if (abs_coeff < CTM_COEFF_0_5)
3891 coeffs[i] |= (1 << 12) |
3892 ILK_CSC_COEFF_FP(abs_coeff, 10);
3893 else if (abs_coeff < CTM_COEFF_1_0)
3894 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
3895 else if (abs_coeff < CTM_COEFF_2_0)
3896 coeffs[i] |= (7 << 12) |
3897 ILK_CSC_COEFF_FP(abs_coeff, 8);
3898 else
3899 coeffs[i] |= (6 << 12) |
3900 ILK_CSC_COEFF_FP(abs_coeff, 7);
3901
3902 /* Skip postoffs */
3903 if (!((j + 2) % 4))
3904 j += 2;
3905 else
3906 j++;
3907 }
3908
3909 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
3910 coeffs[0] << 16 | coeffs[1]);
3911 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
3912 coeffs[2] << 16);
3913
3914 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
3915 coeffs[3] << 16 | coeffs[4]);
3916 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
3917 coeffs[5] << 16);
3918
3919 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
3920 coeffs[6] << 16 | coeffs[7]);
3921 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
3922 coeffs[8] << 16);
3923
3924 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
3925 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
3926 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
3927
3928 /*
3929 * Conversion from S31.32 to S0.12. BIT[12] is the signed bit
3930 */
3931 intel_de_write_dsb(display, dsb,
3932 PLANE_CSC_POSTOFF(pipe, plane, 0),
3933 ctm_to_twos_complement(input[3], 0, 12));
3934 intel_de_write_dsb(display, dsb,
3935 PLANE_CSC_POSTOFF(pipe, plane, 1),
3936 ctm_to_twos_complement(input[7], 0, 12));
3937 intel_de_write_dsb(display, dsb,
3938 PLANE_CSC_POSTOFF(pipe, plane, 2),
3939 ctm_to_twos_complement(input[11], 0, 12));
3940 }
3941
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 08/15] drm/i915: Add register definitions for Plane Degamma
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (6 preceding siblings ...)
2025-12-01 6:46 ` [v7 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:18 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
` (11 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add macros to define Plane Degamma registers
v2:
- Add BSpec links (Suraj)
v3:
- Add Bspec links in trailer (Suraj)
- Fix checkpatch issues (Suraj)
BSpec: 50411, 50412, 50413, 50414
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 6f815b231340..1e5d7ef37f1c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -254,6 +254,7 @@
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
@@ -290,6 +291,53 @@
_PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
_PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+#define PLANE_PAL_PREC_AUTO_INCREMENT REG_BIT(10)
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
#define _PLANE_CSC_RY_GY_1_B 0x71210
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 08/15] drm/i915: Add register definitions for Plane Degamma
2025-12-01 6:46 ` [v7 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
@ 2025-12-01 9:18 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:18 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 08/15] drm/i915: Add register definitions for Plane Degamma
>
> Add macros to define Plane Degamma registers
>
> v2:
> - Add BSpec links (Suraj)
> v3:
> - Add Bspec links in trailer (Suraj)
> - Fix checkpatch issues (Suraj)
>
> BSpec: 50411, 50412, 50413, 50414
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../i915/display/skl_universal_plane_regs.h | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 6f815b231340..1e5d7ef37f1c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -254,6 +254,7 @@
> #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23)
> /* Pre-ICL */
> #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21)
> /* ICL+ */
> #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20)
> /* ICL+ */
> +#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
> #define PLANE_COLOR_CSC_MODE_MASK
> REG_GENMASK(19, 17)
> #define PLANE_COLOR_CSC_MODE_BYPASS
> REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601
> REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> @@ -290,6 +291,53 @@
>
> _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B,
> \
>
> _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
>
> +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) *
> 4)
> +
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
> +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
> +#define PLANE_PAL_PREC_AUTO_INCREMENT REG_BIT(10)
> +
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
> +
> _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
> +
> _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
> +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
> +
> _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
> +
> +#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0
> +#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_1_B)
> +#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_2_B)
> +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
> +
> _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
> +
> +#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4
> +#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_DATA_1_A, \
> +
> _PLANE_PRE_CSC_GAMC_DATA_1_B)
> +#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe,
> _PLANE_PRE_CSC_GAMC_DATA_2_A, \
> +
> _PLANE_PRE_CSC_GAMC_DATA_2_B)
> +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
> +
> _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
> +
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
> #define _PLANE_CSC_RY_GY_1_B 0x71210
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 09/15] drm/i915: Add register definitions for Plane Post CSC
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (7 preceding siblings ...)
2025-12-01 6:46 ` [v7 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:21 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
` (10 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add macros to define Plane Post CSC registers
BSpec: 50403, 50404, 50405, 50406, 50409, 50410,
v2:
- Add Plane Post CSC Gamma Multi Segment Enable bit
- Add BSpec entries (Suraj)
v3:
- Fix checkpatch issues (Suraj)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 1e5d7ef37f1c..6fd4da9f63cf 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -254,6 +254,7 @@
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE REG_BIT(15) /* TGL+ */
#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
@@ -293,6 +294,72 @@
#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc
+#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc
+#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \
+ _PLANE_POST_CSC_GAMC_DATA_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \
+ _PLANE_POST_CSC_GAMC_DATA_2_B)
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
+
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 09/15] drm/i915: Add register definitions for Plane Post CSC
2025-12-01 6:46 ` [v7 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
@ 2025-12-01 9:21 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:21 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 09/15] drm/i915: Add register definitions for Plane Post CSC
>
> Add macros to define Plane Post CSC registers
>
> BSpec: 50403, 50404, 50405, 50406, 50409, 50410,
I think you missed my last comment this needs to be right above the Signed-off-by
>
> v2:
> - Add Plane Post CSC Gamma Multi Segment Enable bit
> - Add BSpec entries (Suraj)
> v3:
> - Fix checkpatch issues (Suraj)
>
Here
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
With that Fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../i915/display/skl_universal_plane_regs.h | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 1e5d7ef37f1c..6fd4da9f63cf 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -254,6 +254,7 @@
> #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23)
> /* Pre-ICL */
> #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21)
> /* ICL+ */
> #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20)
> /* ICL+ */
> +#define PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE
> REG_BIT(15) /* TGL+ */
> #define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
> #define PLANE_COLOR_CSC_MODE_MASK
> REG_GENMASK(19, 17)
> #define PLANE_COLOR_CSC_MODE_BYPASS
> REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> @@ -293,6 +294,72 @@
>
> #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) *
> 4)
>
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe)
> _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
> +
> _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
> +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)
> _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
> +
> _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
> +#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
> +
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
> +
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
> +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
> +
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
> +#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
> +
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe)
> _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
> +
> _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
> +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe)
> _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
> +
> _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
> +#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
> +
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
> +
> _PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
> +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
> +
> _PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
> +#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
> +
> +#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8
> +#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_INDEX_1_A, \
> +
> _PLANE_POST_CSC_GAMC_INDEX_1_B)
> +#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_INDEX_2_A, \
> +
> _PLANE_POST_CSC_GAMC_INDEX_2_B)
> +#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
> +
> +#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc
> +#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc
> +#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc
> +#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc
> +#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_DATA_1_A, \
> +
> _PLANE_POST_CSC_GAMC_DATA_1_B)
> +#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe,
> _PLANE_POST_CSC_GAMC_DATA_2_A, \
> +
> _PLANE_POST_CSC_GAMC_DATA_2_B)
> +#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i)
> _MMIO_PLANE_GAMC(plane, i,
> _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
> +
> _PLANE_POST_CSC_GAMC_DATA_2(pipe))
> +
> #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
> #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
> #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (8 preceding siblings ...)
2025-12-01 6:46 ` [v7 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:23 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
` (9 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
v2: Add dsb support
v3: Align enum names
v4: Propagate change in lut data to crtc_state
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++
.../gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_plane.c | 4 ++++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 2f8e985d51e5..4ca359d68730 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -93,6 +93,10 @@ struct intel_color_funcs {
/* Plane CSC*/
void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state);
+
+ /* Plane Pre/Post CSC */
+ void (*load_plane_luts)(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -4077,11 +4081,23 @@ intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
}
+static void
+intel_color_load_plane_luts(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+
+ if (display->funcs.color->load_plane_luts)
+ display->funcs.color->load_plane_luts(dsb, plane_state);
+}
+
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
{
if (plane_state->hw.ctm)
intel_color_load_plane_csc_matrix(dsb, plane_state);
+ if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
+ intel_color_load_plane_luts(dsb, plane_state);
}
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6d8217497583..c419a814cb34 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,7 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
- struct drm_property_blob *ctm;
+ struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
} hw;
struct i915_vma *ggtt_vma;
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 328b12af4d27..4e6ddb36b872 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -348,6 +348,10 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
{
if (intel_colorop->id == INTEL_PLANE_CB_CSC)
return drm_property_replace_blob(&plane_state->hw.ctm, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
return false;
}
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT
2025-12-01 6:46 ` [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
@ 2025-12-01 9:23 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:23 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC
> LUT
>
> Add framework that will help in loading LUT to Pre/Post CSC color blocks.
>
> v2: Add dsb support
> v3: Align enum names
> v4: Propagate change in lut data to crtc_state
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++
> .../gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_plane.c | 4 ++++
> 3 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 2f8e985d51e5..4ca359d68730 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -93,6 +93,10 @@ struct intel_color_funcs {
> /* Plane CSC*/
> void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
> const struct intel_plane_state
> *plane_state);
> +
> + /* Plane Pre/Post CSC */
> + void (*load_plane_luts)(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state);
> };
>
> #define CTM_COEFF_SIGN (1ULL << 63)
> @@ -4077,11 +4081,23 @@ intel_color_load_plane_csc_matrix(struct
> intel_dsb *dsb,
> display->funcs.color->load_plane_csc_matrix(dsb,
> plane_state); }
>
> +static void
> +intel_color_load_plane_luts(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> +
> + if (display->funcs.color->load_plane_luts)
> + display->funcs.color->load_plane_luts(dsb, plane_state); }
> +
> void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> const struct intel_plane_state
> *plane_state) {
> if (plane_state->hw.ctm)
> intel_color_load_plane_csc_matrix(dsb, plane_state);
> + if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
> + intel_color_load_plane_luts(dsb, plane_state);
> }
>
> void intel_color_crtc_init(struct intel_crtc *crtc) diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6d8217497583..c419a814cb34 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -646,7 +646,7 @@ struct intel_plane_state {
> enum drm_color_encoding color_encoding;
> enum drm_color_range color_range;
> enum drm_scaling_filter scaling_filter;
> - struct drm_property_blob *ctm;
> + struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
> } hw;
>
> struct i915_vma *ggtt_vma;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> b/drivers/gpu/drm/i915/display/intel_plane.c
> index 328b12af4d27..4e6ddb36b872 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -348,6 +348,10 @@ intel_plane_colorop_replace_blob(struct
> intel_plane_state *plane_state, {
> if (intel_colorop->id == INTEL_PLANE_CB_CSC)
> return drm_property_replace_blob(&plane_state->hw.ctm,
> blob);
> + else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
> + return drm_property_replace_blob(&plane_state-
> >hw.degamma_lut, blob);
> + else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
> + return drm_property_replace_blob(&plane_state-
> >hw.gamma_lut, blob);
>
> return false;
> }
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (9 preceding siblings ...)
2025-12-01 6:46 ` [v7 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:24 ` Kandpal, Suraj
2025-12-01 19:28 ` kernel test robot
2025-12-01 6:46 ` [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
` (8 subsequent siblings)
19 siblings, 2 replies; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add callback to program Pre-CSC LUT for TGL and beyond
v2: Add DSB support
v3: Add support for single segment 1D LUT color op
v4:
- s/drm_color_lut_32/drm_color_lut32/ (Simon)
- Change commit message (Suraj)
- Improve comments (Suraj)
- Remove multisegmented programming, to be added later
- Remove dead code for SDR planes, add when needed
BSpec: 50411, 50412, 50413, 50414
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4ca359d68730..2a114d2964fa 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
ctm_to_twos_complement(input[11], 0, 12));
}
+static void
+xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(display, plane)) {
+ lut_size = 128;
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (pre_csc_lut) {
+ for (i = 0; i < lut_size; i++) {
+ u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ /* TODO: Restrict to 0x7ffffff */
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24));
+ } while (i++ > 130);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 130);
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+ }
+}
+
+static void
+xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.degamma_lut)
+ xelpd_program_plane_pre_csc_lut(dsb, plane_state);
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3991,6 +4051,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.read_csc = icl_read_csc,
.get_config = skl_get_config,
.load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
+ .load_plane_luts = xelpd_plane_load_luts,
};
static const struct intel_color_funcs icl_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-01 6:46 ` [v7 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
@ 2025-12-01 9:24 ` Kandpal, Suraj
2025-12-02 8:24 ` Shankar, Uma
2025-12-01 19:28 ` kernel test robot
1 sibling, 1 reply; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:24 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 11/15] drm/i915/color: Program Pre-CSC registers
>
> Add callback to program Pre-CSC LUT for TGL and beyond
>
> v2: Add DSB support
> v3: Add support for single segment 1D LUT color op
> v4:
> - s/drm_color_lut_32/drm_color_lut32/ (Simon)
> - Change commit message (Suraj)
> - Improve comments (Suraj)
> - Remove multisegmented programming, to be added later
> - Remove dead code for SDR planes, add when needed
>
> BSpec: 50411, 50412, 50413, 50414
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4ca359d68730..2a114d2964fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
> ctm_to_twos_complement(input[11], 0, 12)); }
>
> +static void
> +xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> + const struct drm_plane_state *state = &plane_state->uapi;
> + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> + enum plane_id plane = to_intel_plane(state->plane)->id;
Introduce intel_plane here and use that
Regards,
Suraj Kandpal
> + const struct drm_color_lut32 *pre_csc_lut = plane_state-
> >hw.degamma_lut->data;
> + u32 i, lut_size;
> +
> + if (icl_is_hdr_plane(display, plane)) {
> + lut_size = 128;
> +
> + intel_de_write_dsb(display, dsb,
> + PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
> plane, 0),
> + PLANE_PAL_PREC_AUTO_INCREMENT);
> +
> + if (pre_csc_lut) {
> + for (i = 0; i < lut_size; i++) {
> + u32 lut_val =
> drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> +
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + lut_val);
> + }
> +
> + /* Program the max register to clamp values > 1.0. */
> + /* TODO: Restrict to 0x7ffffff */
> + do {
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + (1 << 24));
> + } while (i++ > 130);
> + } else {
> + for (i = 0; i < lut_size; i++) {
> + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> +
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
> + }
> +
> + do {
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + 1 << 24);
> + } while (i++ < 130);
> + }
> +
> + intel_de_write_dsb(display, dsb,
> PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
> + }
> +}
> +
> +static void
> +xelpd_plane_load_luts(struct intel_dsb *dsb, const struct
> +intel_plane_state *plane_state) {
> + if (plane_state->hw.degamma_lut)
> + xelpd_program_plane_pre_csc_lut(dsb, plane_state); }
> +
> static const struct intel_color_funcs chv_color_funcs = {
> .color_check = chv_color_check,
> .color_commit_arm = i9xx_color_commit_arm, @@ -3991,6 +4051,7
> @@ static const struct intel_color_funcs tgl_color_funcs = {
> .read_csc = icl_read_csc,
> .get_config = skl_get_config,
> .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
> + .load_plane_luts = xelpd_plane_load_luts,
> };
>
> static const struct intel_color_funcs icl_color_funcs = {
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* RE: [v7 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-01 9:24 ` Kandpal, Suraj
@ 2025-12-02 8:24 ` Shankar, Uma
2025-12-02 16:00 ` Kandpal, Suraj
0 siblings, 1 reply; 44+ messages in thread
From: Shankar, Uma @ 2025-12-02 8:24 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Monday, December 1, 2025 2:55 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>;
> ville.syrjala@linux.intel.com; pekka.paalanen@collabora.com;
> contact@emersion.fr; harry.wentland@amd.com; mwen@igalia.com;
> jadahl@redhat.com; sebastian.wick@redhat.com; Sharma, Swati2
> <swati2.sharma@intel.com>; alex.hung@amd.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: RE: [v7 11/15] drm/i915/color: Program Pre-CSC registers
>
> > Subject: [v7 11/15] drm/i915/color: Program Pre-CSC registers
> >
> > Add callback to program Pre-CSC LUT for TGL and beyond
> >
> > v2: Add DSB support
> > v3: Add support for single segment 1D LUT color op
> > v4:
> > - s/drm_color_lut_32/drm_color_lut32/ (Simon)
> > - Change commit message (Suraj)
> > - Improve comments (Suraj)
> > - Remove multisegmented programming, to be added later
> > - Remove dead code for SDR planes, add when needed
> >
> > BSpec: 50411, 50412, 50413, 50414
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 61
> > ++++++++++++++++++++++
> > 1 file changed, 61 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4ca359d68730..2a114d2964fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
> > ctm_to_twos_complement(input[11], 0, 12)); }
> >
> > +static void
> > +xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> > + const struct intel_plane_state *plane_state) {
> > + struct intel_display *display = to_intel_display(plane_state);
> > + const struct drm_plane_state *state = &plane_state->uapi;
> > + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> > + enum plane_id plane = to_intel_plane(state->plane)->id;
>
> Introduce intel_plane here and use that
I think its only used at 2 places, don't see any need of extra variable.
If no strong objection, I think it's ok to keep this way.
Regards,
Uma Shankar
> Regards,
> Suraj Kandpal
>
> > + const struct drm_color_lut32 *pre_csc_lut = plane_state-
> > >hw.degamma_lut->data;
> > + u32 i, lut_size;
> > +
> > + if (icl_is_hdr_plane(display, plane)) {
> > + lut_size = 128;
> > +
> > + intel_de_write_dsb(display, dsb,
> > + PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
> > plane, 0),
> > + PLANE_PAL_PREC_AUTO_INCREMENT);
> > +
> > + if (pre_csc_lut) {
> > + for (i = 0; i < lut_size; i++) {
> > + u32 lut_val =
> > drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> > +
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + lut_val);
> > + }
> > +
> > + /* Program the max register to clamp values > 1.0. */
> > + /* TODO: Restrict to 0x7ffffff */
> > + do {
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + (1 << 24));
> > + } while (i++ > 130);
> > + } else {
> > + for (i = 0; i < lut_size; i++) {
> > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> > +
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
> > + }
> > +
> > + do {
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + 1 << 24);
> > + } while (i++ < 130);
> > + }
> > +
> > + intel_de_write_dsb(display, dsb,
> > PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
> > + }
> > +}
> > +
> > +static void
> > +xelpd_plane_load_luts(struct intel_dsb *dsb, const struct
> > +intel_plane_state *plane_state) {
> > + if (plane_state->hw.degamma_lut)
> > + xelpd_program_plane_pre_csc_lut(dsb, plane_state); }
> > +
> > static const struct intel_color_funcs chv_color_funcs = {
> > .color_check = chv_color_check,
> > .color_commit_arm = i9xx_color_commit_arm, @@ -3991,6 +4051,7 @@
> > static const struct intel_color_funcs tgl_color_funcs = {
> > .read_csc = icl_read_csc,
> > .get_config = skl_get_config,
> > .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
> > + .load_plane_luts = xelpd_plane_load_luts,
> > };
> >
> > static const struct intel_color_funcs icl_color_funcs = {
> > --
> > 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* RE: [v7 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-02 8:24 ` Shankar, Uma
@ 2025-12-02 16:00 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-02 16:00 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> > Subject: RE: [v7 11/15] drm/i915/color: Program Pre-CSC registers
> >
> > > Subject: [v7 11/15] drm/i915/color: Program Pre-CSC registers
> > >
> > > Add callback to program Pre-CSC LUT for TGL and beyond
> > >
> > > v2: Add DSB support
> > > v3: Add support for single segment 1D LUT color op
> > > v4:
> > > - s/drm_color_lut_32/drm_color_lut32/ (Simon)
> > > - Change commit message (Suraj)
> > > - Improve comments (Suraj)
> > > - Remove multisegmented programming, to be added later
> > > - Remove dead code for SDR planes, add when needed
> > >
> > > BSpec: 50411, 50412, 50413, 50414
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > Signed-off-by: Chaitanya Kumar Borah
> > > <chaitanya.kumar.borah@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_color.c | 61
> > > ++++++++++++++++++++++
> > > 1 file changed, 61 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > index 4ca359d68730..2a114d2964fa 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > @@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb
> *dsb,
> > > ctm_to_twos_complement(input[11], 0, 12)); }
> > >
> > > +static void
> > > +xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> > > + const struct intel_plane_state *plane_state) {
> > > + struct intel_display *display = to_intel_display(plane_state);
> > > + const struct drm_plane_state *state = &plane_state->uapi;
> > > + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> > > + enum plane_id plane = to_intel_plane(state->plane)->id;
> >
> > Introduce intel_plane here and use that
>
> I think its only used at 2 places, don't see any need of extra variable.
> If no strong objection, I think it's ok to keep this way.
Sure Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Regards,
> Uma Shankar
>
> > Regards,
> > Suraj Kandpal
> >
> > > + const struct drm_color_lut32 *pre_csc_lut = plane_state-
> > > >hw.degamma_lut->data;
> > > + u32 i, lut_size;
> > > +
> > > + if (icl_is_hdr_plane(display, plane)) {
> > > + lut_size = 128;
> > > +
> > > + intel_de_write_dsb(display, dsb,
> > > + PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
> > > plane, 0),
> > > + PLANE_PAL_PREC_AUTO_INCREMENT);
> > > +
> > > + if (pre_csc_lut) {
> > > + for (i = 0; i < lut_size; i++) {
> > > + u32 lut_val =
> > > drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> > > +
> > > + intel_de_write_dsb(display, dsb,
> > > +
> > > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > > + lut_val);
> > > + }
> > > +
> > > + /* Program the max register to clamp values > 1.0. */
> > > + /* TODO: Restrict to 0x7ffffff */
> > > + do {
> > > + intel_de_write_dsb(display, dsb,
> > > +
> > > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > > + (1 << 24));
> > > + } while (i++ > 130);
> > > + } else {
> > > + for (i = 0; i < lut_size; i++) {
> > > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> > > +
> > > + intel_de_write_dsb(display, dsb,
> > > +
> > > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
> > > + }
> > > +
> > > + do {
> > > + intel_de_write_dsb(display, dsb,
> > > +
> > > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > > + 1 << 24);
> > > + } while (i++ < 130);
> > > + }
> > > +
> > > + intel_de_write_dsb(display, dsb,
> > > PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
> > > + }
> > > +}
> > > +
> > > +static void
> > > +xelpd_plane_load_luts(struct intel_dsb *dsb, const struct
> > > +intel_plane_state *plane_state) {
> > > + if (plane_state->hw.degamma_lut)
> > > + xelpd_program_plane_pre_csc_lut(dsb, plane_state); }
> > > +
> > > static const struct intel_color_funcs chv_color_funcs = {
> > > .color_check = chv_color_check,
> > > .color_commit_arm = i9xx_color_commit_arm, @@ -3991,6 +4051,7
> @@
> > > static const struct intel_color_funcs tgl_color_funcs = {
> > > .read_csc = icl_read_csc,
> > > .get_config = skl_get_config,
> > > .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
> > > + .load_plane_luts = xelpd_plane_load_luts,
> > > };
> > >
> > > static const struct intel_color_funcs icl_color_funcs = {
> > > --
> > > 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [v7 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-01 6:46 ` [v7 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-12-01 9:24 ` Kandpal, Suraj
@ 2025-12-01 19:28 ` kernel test robot
1 sibling, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 19:28 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6 linus/master v6.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-12-uma.shankar%40intel.com
patch subject: [v7 11/15] drm/i915/color: Program Pre-CSC registers
config: i386-buildonly-randconfig-006-20251201 (https://download.01.org/0day-ci/archive/20251202/202512020343.7KKu4M4I-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251202/202512020343.7KKu4M4I-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512020343.7KKu4M4I-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_color.c:31:
drivers/gpu/drm/i915/display/intel_display_types.h:1993:28: error: field 'base' has incomplete type
1993 | struct drm_colorop base;
| ^~~~
drivers/gpu/drm/i915/display/intel_color.c: In function 'xelpd_load_plane_csc_matrix':
drivers/gpu/drm/i915/display/intel_color.c:3869:20: error: invalid use of undefined type 'struct drm_color_ctm_3x4'
3869 | input = ctm->matrix;
| ^~
drivers/gpu/drm/i915/display/intel_color.c: In function 'xelpd_program_plane_pre_csc_lut':
>> drivers/gpu/drm/i915/display/intel_color.c:3966:47: error: implicit declaration of function 'drm_color_lut32_extract'; did you mean 'drm_color_lut_extract'? [-Wimplicit-function-declaration]
3966 | u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
| ^~~~~~~~~~~~~~~~~~~~~~~
| drm_color_lut_extract
>> drivers/gpu/drm/i915/display/intel_color.c:3966:82: error: invalid use of undefined type 'struct drm_color_lut32'
3966 | u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
| ^
>> drivers/gpu/drm/i915/display/intel_color.c:3966:85: error: invalid use of undefined type 'const struct drm_color_lut32'
3966 | u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
| ^
vim +3966 drivers/gpu/drm/i915/display/intel_color.c
3850
3851 static void
3852 xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
3853 const struct intel_plane_state *plane_state)
3854 {
3855 struct intel_display *display = to_intel_display(plane_state);
3856 const struct drm_plane_state *state = &plane_state->uapi;
3857 enum pipe pipe = to_intel_plane(state->plane)->pipe;
3858 enum plane_id plane = to_intel_plane(state->plane)->id;
3859 const struct drm_property_blob *blob = plane_state->hw.ctm;
3860 struct drm_color_ctm_3x4 *ctm;
3861 const u64 *input;
3862 u16 coeffs[9] = {};
3863 int i, j;
3864
3865 if (!icl_is_hdr_plane(display, plane) || !blob)
3866 return;
3867
3868 ctm = blob->data;
> 3869 input = ctm->matrix;
3870
3871 /*
3872 * Convert fixed point S31.32 input to format supported by the
3873 * hardware.
3874 */
3875 for (i = 0, j = 0; i < ARRAY_SIZE(coeffs); i++) {
3876 u64 abs_coeff = ((1ULL << 63) - 1) & input[j];
3877
3878 /*
3879 * Clamp input value to min/max supported by
3880 * hardware.
3881 */
3882 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
3883
3884 /* sign bit */
3885 if (CTM_COEFF_NEGATIVE(input[j]))
3886 coeffs[i] |= 1 << 15;
3887
3888 if (abs_coeff < CTM_COEFF_0_125)
3889 coeffs[i] |= (3 << 12) |
3890 ILK_CSC_COEFF_FP(abs_coeff, 12);
3891 else if (abs_coeff < CTM_COEFF_0_25)
3892 coeffs[i] |= (2 << 12) |
3893 ILK_CSC_COEFF_FP(abs_coeff, 11);
3894 else if (abs_coeff < CTM_COEFF_0_5)
3895 coeffs[i] |= (1 << 12) |
3896 ILK_CSC_COEFF_FP(abs_coeff, 10);
3897 else if (abs_coeff < CTM_COEFF_1_0)
3898 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
3899 else if (abs_coeff < CTM_COEFF_2_0)
3900 coeffs[i] |= (7 << 12) |
3901 ILK_CSC_COEFF_FP(abs_coeff, 8);
3902 else
3903 coeffs[i] |= (6 << 12) |
3904 ILK_CSC_COEFF_FP(abs_coeff, 7);
3905
3906 /* Skip postoffs */
3907 if (!((j + 2) % 4))
3908 j += 2;
3909 else
3910 j++;
3911 }
3912
3913 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
3914 coeffs[0] << 16 | coeffs[1]);
3915 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
3916 coeffs[2] << 16);
3917
3918 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
3919 coeffs[3] << 16 | coeffs[4]);
3920 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
3921 coeffs[5] << 16);
3922
3923 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
3924 coeffs[6] << 16 | coeffs[7]);
3925 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
3926 coeffs[8] << 16);
3927
3928 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
3929 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
3930 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
3931
3932 /*
3933 * Conversion from S31.32 to S0.12. BIT[12] is the signed bit
3934 */
3935 intel_de_write_dsb(display, dsb,
3936 PLANE_CSC_POSTOFF(pipe, plane, 0),
3937 ctm_to_twos_complement(input[3], 0, 12));
3938 intel_de_write_dsb(display, dsb,
3939 PLANE_CSC_POSTOFF(pipe, plane, 1),
3940 ctm_to_twos_complement(input[7], 0, 12));
3941 intel_de_write_dsb(display, dsb,
3942 PLANE_CSC_POSTOFF(pipe, plane, 2),
3943 ctm_to_twos_complement(input[11], 0, 12));
3944 }
3945
3946 static void
3947 xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
3948 const struct intel_plane_state *plane_state)
3949 {
3950 struct intel_display *display = to_intel_display(plane_state);
3951 const struct drm_plane_state *state = &plane_state->uapi;
3952 enum pipe pipe = to_intel_plane(state->plane)->pipe;
3953 enum plane_id plane = to_intel_plane(state->plane)->id;
3954 const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
3955 u32 i, lut_size;
3956
3957 if (icl_is_hdr_plane(display, plane)) {
3958 lut_size = 128;
3959
3960 intel_de_write_dsb(display, dsb,
3961 PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
3962 PLANE_PAL_PREC_AUTO_INCREMENT);
3963
3964 if (pre_csc_lut) {
3965 for (i = 0; i < lut_size; i++) {
> 3966 u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
3967
3968 intel_de_write_dsb(display, dsb,
3969 PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
3970 lut_val);
3971 }
3972
3973 /* Program the max register to clamp values > 1.0. */
3974 /* TODO: Restrict to 0x7ffffff */
3975 do {
3976 intel_de_write_dsb(display, dsb,
3977 PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
3978 (1 << 24));
3979 } while (i++ > 130);
3980 } else {
3981 for (i = 0; i < lut_size; i++) {
3982 u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
3983
3984 intel_de_write_dsb(display, dsb,
3985 PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
3986 }
3987
3988 do {
3989 intel_de_write_dsb(display, dsb,
3990 PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
3991 1 << 24);
3992 } while (i++ < 130);
3993 }
3994
3995 intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
3996 }
3997 }
3998
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (10 preceding siblings ...)
2025-12-01 6:46 ` [v7 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-02 15:32 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 13/15] drm/i915/display: Add registers for 3D LUT Uma Shankar
` (7 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Extract the LUT and program plane post csc registers.
v2: Add DSB support
v3: Add support for single segment 1D LUT
v4:
- s/drm_color_lut_32/drm_color_lut32 (Simon)
- Move declaration to beginning of the function (Suraj)
- Remove multisegmented code, add it later
- Remove dead code for SDR planes, add it later
v5:
- Fix iterator issues
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 2a114d2964fa..86d1fbc906bf 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
}
}
+static void
+xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;
+ u32 i, j, lut_size, lut_val;
+
+ if (icl_is_hdr_plane(display, plane)) {
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+ /* TODO: Add macro */
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+ if (post_csc_lut) {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ lut_val = drm_color_lut32_extract(post_csc_lut[j++].green, 24);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Segment 2 */
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24));
+ } while (++j < 34);
+ } else {
+ /*TODO: Add for segment 0 */
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 34);
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);
+ }
+}
+
static void
xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)
{
if (plane_state->hw.degamma_lut)
xelpd_program_plane_pre_csc_lut(dsb, plane_state);
+
+ if (plane_state->hw.gamma_lut)
+ xelpd_program_plane_post_csc_lut(dsb, plane_state);
}
static const struct intel_color_funcs chv_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers
2025-12-01 6:46 ` [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
@ 2025-12-02 15:32 ` Kandpal, Suraj
2025-12-02 16:10 ` Kandpal, Suraj
0 siblings, 1 reply; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-02 15:32 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers
This needs to be i915/color:
>
> Extract the LUT and program plane post csc registers.
>
> v2: Add DSB support
> v3: Add support for single segment 1D LUT
> v4:
> - s/drm_color_lut_32/drm_color_lut32 (Simon)
> - Move declaration to beginning of the function (Suraj)
> - Remove multisegmented code, add it later
> - Remove dead code for SDR planes, add it later
> v5:
> - Fix iterator issues
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 59 ++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 2a114d2964fa..86d1fbc906bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct
> intel_dsb *dsb,
> }
> }
>
> +static void
> +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> + const struct drm_plane_state *state = &plane_state->uapi;
> + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> + enum plane_id plane = to_intel_plane(state->plane)->id;
> + const struct drm_color_lut32 *post_csc_lut = plane_state-
> >hw.gamma_lut->data;
> + u32 i, j, lut_size, lut_val;
j is un-uninitialized here and it remains un-initialized even when first used can cause unforeseen errors
Regards,
Suraj Kandpal
> +
> + if (icl_is_hdr_plane(display, plane)) {
> + intel_de_write_dsb(display, dsb,
> PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
> + PLANE_PAL_PREC_AUTO_INCREMENT);
> + /* TODO: Add macro */
> + intel_de_write_dsb(display, dsb,
> PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
> + PLANE_PAL_PREC_AUTO_INCREMENT);
> + if (post_csc_lut) {
> + lut_size = 32;
> + for (i = 0; i < lut_size; i++) {
> + lut_val =
> drm_color_lut32_extract(post_csc_lut[j++].green, 24);
> +
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + lut_val);
> + }
> +
> + /* Segment 2 */
> + do {
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + (1 << 24));
> + } while (++j < 34);
> + } else {
> + /*TODO: Add for segment 0 */
> + lut_size = 32;
> + for (i = 0; i < lut_size; i++) {
> + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> +
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
> + }
> +
> + do {
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> + 1 << 24);
> + } while (i++ < 34);
> + }
> +
> + intel_de_write_dsb(display, dsb,
> PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
> + intel_de_write_dsb(display, dsb,
> +
> PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);
> + }
> +}
> +
> static void
> xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state
> *plane_state) {
> if (plane_state->hw.degamma_lut)
> xelpd_program_plane_pre_csc_lut(dsb, plane_state);
> +
> + if (plane_state->hw.gamma_lut)
> + xelpd_program_plane_post_csc_lut(dsb, plane_state);
> }
>
> static const struct intel_color_funcs chv_color_funcs = {
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread* RE: [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers
2025-12-02 15:32 ` Kandpal, Suraj
@ 2025-12-02 16:10 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-02 16:10 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> > Subject: [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers
>
> This needs to be i915/color:
>
> >
> > Extract the LUT and program plane post csc registers.
> >
> > v2: Add DSB support
> > v3: Add support for single segment 1D LUT
> > v4:
> > - s/drm_color_lut_32/drm_color_lut32 (Simon)
> > - Move declaration to beginning of the function (Suraj)
> > - Remove multisegmented code, add it later
> > - Remove dead code for SDR planes, add it later
> > v5:
> > - Fix iterator issues
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 59 ++++++++++++++++++++++
> > 1 file changed, 59 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 2a114d2964fa..86d1fbc906bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct
> > intel_dsb *dsb,
> > }
> > }
> >
> > +static void
> > +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
> > + const struct intel_plane_state *plane_state) {
> > + struct intel_display *display = to_intel_display(plane_state);
> > + const struct drm_plane_state *state = &plane_state->uapi;
> > + enum pipe pipe = to_intel_plane(state->plane)->pipe;
> > + enum plane_id plane = to_intel_plane(state->plane)->id;
> > + const struct drm_color_lut32 *post_csc_lut = plane_state-
> > >hw.gamma_lut->data;
> > + u32 i, j, lut_size, lut_val;
>
> j is un-uninitialized here and it remains un-initialized even when first used can
> cause unforeseen errors
I meant uninitialized here 😃, with the above comments addressed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Regards,
> Suraj Kandpal
>
> > +
> > + if (icl_is_hdr_plane(display, plane)) {
> > + intel_de_write_dsb(display, dsb,
> > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
> > + PLANE_PAL_PREC_AUTO_INCREMENT);
> > + /* TODO: Add macro */
> > + intel_de_write_dsb(display, dsb,
> > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
> > + PLANE_PAL_PREC_AUTO_INCREMENT);
> > + if (post_csc_lut) {
> > + lut_size = 32;
> > + for (i = 0; i < lut_size; i++) {
> > + lut_val =
> > drm_color_lut32_extract(post_csc_lut[j++].green, 24);
> > +
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + lut_val);
> > + }
> > +
> > + /* Segment 2 */
> > + do {
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + (1 << 24));
> > + } while (++j < 34);
> > + } else {
> > + /*TODO: Add for segment 0 */
> > + lut_size = 32;
> > + for (i = 0; i < lut_size; i++) {
> > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> > +
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
> > + }
> > +
> > + do {
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > + 1 << 24);
> > + } while (i++ < 34);
> > + }
> > +
> > + intel_de_write_dsb(display, dsb,
> > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
> > + intel_de_write_dsb(display, dsb,
> > +
> > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);
> > + }
> > +}
> > +
> > static void
> > xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state
> > *plane_state) {
> > if (plane_state->hw.degamma_lut)
> > xelpd_program_plane_pre_csc_lut(dsb, plane_state);
> > +
> > + if (plane_state->hw.gamma_lut)
> > + xelpd_program_plane_post_csc_lut(dsb, plane_state);
> > }
> >
> > static const struct intel_color_funcs chv_color_funcs = {
> > --
> > 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 13/15] drm/i915/display: Add registers for 3D LUT
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (11 preceding siblings ...)
2025-12-01 6:46 ` [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 9:26 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
` (6 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add registers needed to program 3D LUT
v2:
- Follow convention documented in i915_reg.h (Jani)
- Removing space in trailer (Suraj)
- Move registers to intel_color_regs.h
BSpec: 69378, 69379, 69380
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_color_regs.h | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index 8eb643cfead7..c370b6029369 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -316,4 +316,33 @@
#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
+/* 3D LUT */
+#define _LUT_3D_CTL_A 0x490A4
+#define _LUT_3D_CTL_B 0x491A4
+#define LUT_3D_CTL(pipe) _MMIO_PIPE(pipe, _LUT_3D_CTL_A, _LUT_3D_CTL_B)
+#define LUT_3D_ENABLE REG_BIT(31)
+#define LUT_3D_READY REG_BIT(30)
+#define LUT_3D_BINDING_MASK REG_GENMASK(23, 22)
+#define LUT_3D_BIND_PIPE REG_FIELD_PREP(LUT_3D_BINDING_MASK, 0)
+#define LUT_3D_BIND_PLANE_1 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 1)
+#define LUT_3D_BIND_PLANE_2 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 2)
+#define LUT_3D_BIND_PLANE_3 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 3)
+
+#define _LUT_3D_INDEX_A 0x490A8
+#define _LUT_3D_INDEX_B 0x491A8
+#define LUT_3D_INDEX(pipe) _MMIO_PIPE(pipe, _LUT_3D_INDEX_A, _LUT_3D_INDEX_B)
+#define LUT_3D_AUTO_INCREMENT REG_BIT(13)
+#define LUT_3D_INDEX_VALUE_MASK REG_GENMASK(12, 0)
+#define LUT_3D_INDEX_VALUE(x) REG_FIELD_PREP(LUT_3D_INDEX_VALUE_MASK, (x))
+
+#define _LUT_3D_DATA_A 0x490AC
+#define _LUT_3D_DATA_B 0x491AC
+#define LUT_3D_DATA(pipe) _MMIO_PIPE(pipe, _LUT_3D_DATA_A, _LUT_3D_DATA_B)
+#define LUT_3D_DATA_RED_MASK REG_GENMASK(29, 20)
+#define LUT_3D_DATA_GREEN_MASK REG_GENMASK(19, 10)
+#define LUT_3D_DATA_BLUE_MASK REG_GENMASK(9, 0)
+#define LUT_3D_DATA_RED(x) REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, (x))
+#define LUT_3D_DATA_GREEN(x) REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, (x))
+#define LUT_3D_DATA_BLUE(x) REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, (x))
+
#endif /* __INTEL_COLOR_REGS_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 13/15] drm/i915/display: Add registers for 3D LUT
2025-12-01 6:46 ` [v7 13/15] drm/i915/display: Add registers for 3D LUT Uma Shankar
@ 2025-12-01 9:26 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-01 9:26 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 13/15] drm/i915/display: Add registers for 3D LUT
This needs to be /color
Other than that
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add registers needed to program 3D LUT
>
> v2:
> - Follow convention documented in i915_reg.h (Jani)
> - Removing space in trailer (Suraj)
> - Move registers to intel_color_regs.h
>
> BSpec: 69378, 69379, 69380
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> .../gpu/drm/i915/display/intel_color_regs.h | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h
> b/drivers/gpu/drm/i915/display/intel_color_regs.h
> index 8eb643cfead7..c370b6029369 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
> @@ -316,4 +316,33 @@
> #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
> #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe,
> _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
>
> +/* 3D LUT */
> +#define _LUT_3D_CTL_A 0x490A4
> +#define _LUT_3D_CTL_B 0x491A4
> +#define LUT_3D_CTL(pipe) _MMIO_PIPE(pipe, _LUT_3D_CTL_A,
> _LUT_3D_CTL_B)
> +#define LUT_3D_ENABLE REG_BIT(31)
> +#define LUT_3D_READY REG_BIT(30)
> +#define LUT_3D_BINDING_MASK REG_GENMASK(23, 22)
> +#define LUT_3D_BIND_PIPE
> REG_FIELD_PREP(LUT_3D_BINDING_MASK, 0)
> +#define LUT_3D_BIND_PLANE_1
> REG_FIELD_PREP(LUT_3D_BINDING_MASK, 1)
> +#define LUT_3D_BIND_PLANE_2
> REG_FIELD_PREP(LUT_3D_BINDING_MASK, 2)
> +#define LUT_3D_BIND_PLANE_3
> REG_FIELD_PREP(LUT_3D_BINDING_MASK, 3)
> +
> +#define _LUT_3D_INDEX_A 0x490A8
> +#define _LUT_3D_INDEX_B 0x491A8
> +#define LUT_3D_INDEX(pipe) _MMIO_PIPE(pipe, _LUT_3D_INDEX_A,
> _LUT_3D_INDEX_B)
> +#define LUT_3D_AUTO_INCREMENT REG_BIT(13)
> +#define LUT_3D_INDEX_VALUE_MASK REG_GENMASK(12, 0)
> +#define LUT_3D_INDEX_VALUE(x)
> REG_FIELD_PREP(LUT_3D_INDEX_VALUE_MASK, (x))
> +
> +#define _LUT_3D_DATA_A 0x490AC
> +#define _LUT_3D_DATA_B 0x491AC
> +#define LUT_3D_DATA(pipe) _MMIO_PIPE(pipe, _LUT_3D_DATA_A,
> _LUT_3D_DATA_B)
> +#define LUT_3D_DATA_RED_MASK REG_GENMASK(29, 20)
> +#define LUT_3D_DATA_GREEN_MASK REG_GENMASK(19, 10)
> +#define LUT_3D_DATA_BLUE_MASK REG_GENMASK(9, 0)
> +#define LUT_3D_DATA_RED(x)
> REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, (x))
> +#define LUT_3D_DATA_GREEN(x)
> REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, (x))
> +#define LUT_3D_DATA_BLUE(x)
> REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, (x))
> +
> #endif /* __INTEL_COLOR_REGS_H__ */
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (12 preceding siblings ...)
2025-12-01 6:46 ` [v7 13/15] drm/i915/display: Add registers for 3D LUT Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-02 15:42 ` Kandpal, Suraj
2025-12-01 6:46 ` [v7 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
` (5 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add helpers to program the 3D LUT registers and arm them.
LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
the LUT buffer is loaded into it's internal working RAM.
So by the time we try to load/commit new values, we expect
it to be cleared off. If not, log an error and return
without writing new values. Do it only when while writing
with MMIO. There is no way to read register within DSB
execution.
v2:
- Add information regarding LUT_3D_READY to commit message (Jani)
- Log error instead of a drm_warn and return without committing changes
if 3DLUT HW is not ready to accept new values.
- Refactor intel_color_crtc_has_3dlut()
Also remove Gen10 check (Suraj)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 79 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_color.h | 4 +
.../drm/i915/display/intel_color_pipeline.c | 25 +++++-
.../drm/i915/display/intel_color_pipeline.h | 3 +-
.../drm/i915/display/intel_display_limits.h | 1 +
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_plane.c | 2 +
7 files changed, 111 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 86d1fbc906bf..70e6effba9b3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4062,6 +4062,53 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
xelpd_program_plane_post_csc_lut(dsb, plane_state);
}
+static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
+{
+ return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
+ REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
+ REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
+}
+
+static void glk_load_lut_3d(struct intel_dsb *dsb,
+ struct intel_crtc *crtc,
+ const struct drm_property_blob *blob)
+{
+ struct intel_display *display = to_intel_display(crtc->base.dev);
+ const struct drm_color_lut32 *lut = blob->data;
+ int i, lut_size = drm_color_lut32_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+ drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
+ crtc->base.base.id, crtc->base.name);
+ return;
+ }
+
+ intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), LUT_3D_AUTO_INCREMENT);
+ for (i = 0; i < lut_size; i++)
+ intel_de_write_dsb(display, dsb, LUT_3D_DATA(pipe), glk_3dlut_10(&lut[i]));
+ intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);
+}
+
+static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bool enable)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 val;
+
+ if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+ drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not committing change\n",
+ crtc->base.base.id, crtc->base.name);
+ return;
+ }
+
+ if (enable)
+ val = LUT_3D_ENABLE | LUT_3D_READY | LUT_3D_BIND_PLANE_1;
+ else
+ val = 0;
+ intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -4191,6 +4238,16 @@ static const struct intel_color_funcs ilk_color_funcs = {
.get_config = ilk_get_config,
};
+void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
+
+ if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
+ glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
+}
+
static void
intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
@@ -4211,6 +4268,26 @@ intel_color_load_plane_luts(struct intel_dsb *dsb,
display->funcs.color->load_plane_luts(dsb, plane_state);
}
+bool
+intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe)
+{
+ if (DISPLAY_VER(display) >= 12)
+ return pipe == PIPE_A || pipe == PIPE_B;
+ else
+ return false;
+}
+
+static void
+intel_color_load_3dlut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
+
+ if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
+ glk_load_lut_3d(dsb, crtc, plane_state->hw.lut_3d);
+}
+
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
{
@@ -4218,6 +4295,8 @@ void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
intel_color_load_plane_csc_matrix(dsb, plane_state);
if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
intel_color_load_plane_luts(dsb, plane_state);
+ if (plane_state->hw.lut_3d)
+ intel_color_load_3dlut(dsb, plane_state);
}
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 8051c827a1d8..c21b9bdf7bb8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -15,6 +15,7 @@ struct intel_display;
struct intel_dsb;
struct intel_plane_state;
struct drm_property_blob;
+enum pipe;
void intel_color_init_hooks(struct intel_display *display);
int intel_color_init(struct intel_display *display);
@@ -43,4 +44,7 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state);
+void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
+bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
index 1415f94dd3e3..8214a00e34cf 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2025 Intel Corporation
*/
+#include "intel_color.h"
#include "intel_colorop.h"
#include "intel_color_pipeline.h"
#include "intel_de.h"
@@ -13,10 +14,12 @@
#define PLANE_GAMMA_SIZE 32
static
-int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
+ enum pipe pipe)
{
struct intel_colorop *colorop;
struct drm_device *dev = plane->dev;
+ struct intel_display *display = to_intel_display(dev);
int ret;
struct drm_colorop *prev_op;
@@ -36,6 +39,22 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
/* TODO: handle failures and clean up */
prev_op = &colorop->base;
+ if (DISPLAY_VER(display) >= 35 &&
+ intel_color_crtc_has_3dlut(display, pipe) &&
+ plane->type == DRM_PLANE_TYPE_PRIMARY) {
+ colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
+
+ ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
+ DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+ true);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+
+ prev_op = &colorop->base;
+ }
+
colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
DRM_COLOROP_FLAG_ALLOW_BYPASS);
@@ -58,7 +77,7 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
return 0;
}
-int intel_color_pipeline_plane_init(struct drm_plane *plane)
+int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
{
struct drm_device *dev = plane->dev;
struct intel_display *display = to_intel_display(dev);
@@ -77,7 +96,7 @@ int intel_color_pipeline_plane_init(struct drm_plane *plane)
len++;
/* Add pipeline consisting of transfer functions */
- ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
+ ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
if (ret)
return ret;
len++;
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
index 7f1d32bc9202..a457d306da7f 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.h
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
@@ -7,7 +7,8 @@
#define __INTEL_COLOR_PIPELINE_H__
struct drm_plane;
+enum pipe;
-int intel_color_pipeline_plane_init(struct drm_plane *plane);
+int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe);
#endif /* __INTEL_COLOR_PIPELINE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 55fd574ba313..cb3c9c665c44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -142,6 +142,7 @@ enum intel_color_block {
INTEL_PLANE_CB_PRE_CSC_LUT,
INTEL_PLANE_CB_CSC,
INTEL_PLANE_CB_POST_CSC_LUT,
+ INTEL_PLANE_CB_3DLUT,
INTEL_CB_MAX
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c419a814cb34..06bf8f7c0989 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,7 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
- struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
+ struct drm_property_blob *ctm, *degamma_lut, *gamma_lut, *lut_3d;
} hw;
struct i915_vma *ggtt_vma;
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 4e6ddb36b872..d9db3742b8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -352,6 +352,8 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
+ return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
return false;
}
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-01 6:46 ` [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
@ 2025-12-02 15:42 ` Kandpal, Suraj
0 siblings, 0 replies; 44+ messages in thread
From: Kandpal, Suraj @ 2025-12-02 15:42 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, Sharma, Swati2, alex.hung@amd.com,
Nikula, Jani
> Subject: [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline
>
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add helpers to program the 3D LUT registers and arm them.
>
> LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once the LUT buffer is
> loaded into it's internal working RAM.
> So by the time we try to load/commit new values, we expect it to be cleared
> off. If not, log an error and return without writing new values. Do it only when
> while writing with MMIO.
This should be either "while writing MMIO" or "when writing MMIO"
> There is no way to read register within DSB
> execution.
>
> v2:
> - Add information regarding LUT_3D_READY to commit message (Jani)
> - Log error instead of a drm_warn and return without committing changes
> if 3DLUT HW is not ready to accept new values.
> - Refactor intel_color_crtc_has_3dlut()
> Also remove Gen10 check (Suraj)
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 79 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_color.h | 4 +
> .../drm/i915/display/intel_color_pipeline.c | 25 +++++-
> .../drm/i915/display/intel_color_pipeline.h | 3 +-
> .../drm/i915/display/intel_display_limits.h | 1 +
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_plane.c | 2 +
> 7 files changed, 111 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 86d1fbc906bf..70e6effba9b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4062,6 +4062,53 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const
> struct intel_plane_state *pla
> xelpd_program_plane_post_csc_lut(dsb, plane_state); }
>
> +static u32 glk_3dlut_10(const struct drm_color_lut32 *color) {
> + return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK,
> drm_color_lut32_extract(color->red, 10)) |
> + REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK,
> drm_color_lut32_extract(color->green, 10)) |
> + REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK,
> +drm_color_lut32_extract(color->blue, 10)); }
> +
> +static void glk_load_lut_3d(struct intel_dsb *dsb,
> + struct intel_crtc *crtc,
> + const struct drm_property_blob *blob) {
> + struct intel_display *display = to_intel_display(crtc->base.dev);
> + const struct drm_color_lut32 *lut = blob->data;
> + int i, lut_size = drm_color_lut32_size(blob);
> + enum pipe pipe = crtc->pipe;
> +
> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) &
> LUT_3D_READY) {
> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not
> loading LUTs\n",
> + crtc->base.base.id, crtc->base.name);
> + return;
> + }
> +
> + intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe),
> LUT_3D_AUTO_INCREMENT);
> + for (i = 0; i < lut_size; i++)
> + intel_de_write_dsb(display, dsb, LUT_3D_DATA(pipe),
> glk_3dlut_10(&lut[i]));
> + intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0); }
> +
> +static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc
> +*crtc, bool enable) {
> + struct intel_display *display = to_intel_display(crtc);
> + enum pipe pipe = crtc->pipe;
> + u32 val;
> +
> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) &
> LUT_3D_READY) {
> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not
> committing change\n",
> + crtc->base.base.id, crtc->base.name);
> + return;
> + }
> +
> + if (enable)
> + val = LUT_3D_ENABLE | LUT_3D_READY |
> LUT_3D_BIND_PLANE_1;
> + else
> + val = 0;
If you initialize the val to 0 when you declare it, the else block can be avoided.
> + intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val); }
> +
> static const struct intel_color_funcs chv_color_funcs = {
> .color_check = chv_color_check,
> .color_commit_arm = i9xx_color_commit_arm, @@ -4191,6 +4238,16
> @@ static const struct intel_color_funcs ilk_color_funcs = {
> .get_config = ilk_get_config,
> };
>
> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> +
> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d); }
> +
> static void
> intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
> const struct intel_plane_state *plane_state)
> @@ -4211,6 +4268,26 @@ intel_color_load_plane_luts(struct intel_dsb *dsb,
> display->funcs.color->load_plane_luts(dsb, plane_state); }
>
> +bool
> +intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe
> +pipe) {
> + if (DISPLAY_VER(display) >= 12)
> + return pipe == PIPE_A || pipe == PIPE_B;
> + else
> + return false;
> +}
> +
> +static void
> +intel_color_load_3dlut(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state) {
> + struct intel_display *display = to_intel_display(plane_state);
> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> +
> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> + glk_load_lut_3d(dsb, crtc, plane_state->hw.lut_3d); }
> +
> void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> const struct intel_plane_state
> *plane_state) { @@ -4218,6 +4295,8 @@ void
> intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> intel_color_load_plane_csc_matrix(dsb, plane_state);
> if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
> intel_color_load_plane_luts(dsb, plane_state);
> + if (plane_state->hw.lut_3d)
> + intel_color_load_3dlut(dsb, plane_state);
> }
>
> void intel_color_crtc_init(struct intel_crtc *crtc) diff --git
> a/drivers/gpu/drm/i915/display/intel_color.h
> b/drivers/gpu/drm/i915/display/intel_color.h
> index 8051c827a1d8..c21b9bdf7bb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.h
> +++ b/drivers/gpu/drm/i915/display/intel_color.h
> @@ -15,6 +15,7 @@ struct intel_display;
> struct intel_dsb;
> struct intel_plane_state;
> struct drm_property_blob;
> +enum pipe;
>
> void intel_color_init_hooks(struct intel_display *display); int
> intel_color_init(struct intel_display *display); @@ -43,4 +44,7 @@ bool
> intel_color_lut_equal(const struct intel_crtc_state *crtc_state, void
> intel_color_assert_luts(const struct intel_crtc_state *crtc_state); void
> intel_color_plane_program_pipeline(struct intel_dsb *dsb,
> const struct intel_plane_state
> *plane_state);
> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state);
> bool
> +intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe
> +pipe);
> #endif /* __INTEL_COLOR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 1415f94dd3e3..8214a00e34cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -2,6 +2,7 @@
> /*
> * Copyright © 2025 Intel Corporation
> */
> +#include "intel_color.h"
> #include "intel_colorop.h"
> #include "intel_color_pipeline.h"
> #include "intel_de.h"
> @@ -13,10 +14,12 @@
> #define PLANE_GAMMA_SIZE 32
>
> static
> -int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct
> drm_prop_enum_list *list)
> +int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct
> drm_prop_enum_list *list,
> + enum pipe pipe)
> {
> struct intel_colorop *colorop;
> struct drm_device *dev = plane->dev;
> + struct intel_display *display = to_intel_display(dev);
This needs to be declared at the first line when possible or at least at the next topmost line.
With all the above fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> int ret;
> struct drm_colorop *prev_op;
>
> @@ -36,6 +39,22 @@ int _intel_color_pipeline_plane_init(struct drm_plane
> *plane, struct drm_prop_en
> /* TODO: handle failures and clean up */
> prev_op = &colorop->base;
>
> + if (DISPLAY_VER(display) >= 35 &&
> + intel_color_crtc_has_3dlut(display, pipe) &&
> + plane->type == DRM_PLANE_TYPE_PRIMARY) {
> + colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
> +
> + ret = drm_plane_colorop_3dlut_init(dev, &colorop->base,
> plane, 17,
> +
> DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
> + true);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> +
> + prev_op = &colorop->base;
> + }
> +
> colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
>
> DRM_COLOROP_FLAG_ALLOW_BYPASS); @@ -58,7 +77,7 @@ int
> _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
> return 0;
> }
>
> -int intel_color_pipeline_plane_init(struct drm_plane *plane)
> +int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe
> +pipe)
> {
> struct drm_device *dev = plane->dev;
> struct intel_display *display = to_intel_display(dev); @@ -77,7 +96,7
> @@ int intel_color_pipeline_plane_init(struct drm_plane *plane)
> len++;
>
> /* Add pipeline consisting of transfer functions */
> - ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
> + ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
> if (ret)
> return ret;
> len++;
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> index 7f1d32bc9202..a457d306da7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
> @@ -7,7 +7,8 @@
> #define __INTEL_COLOR_PIPELINE_H__
>
> struct drm_plane;
> +enum pipe;
>
> -int intel_color_pipeline_plane_init(struct drm_plane *plane);
> +int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe
> +pipe);
>
> #endif /* __INTEL_COLOR_PIPELINE_H__ */ diff --git
> a/drivers/gpu/drm/i915/display/intel_display_limits.h
> b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index 55fd574ba313..cb3c9c665c44 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -142,6 +142,7 @@ enum intel_color_block {
> INTEL_PLANE_CB_PRE_CSC_LUT,
> INTEL_PLANE_CB_CSC,
> INTEL_PLANE_CB_POST_CSC_LUT,
> + INTEL_PLANE_CB_3DLUT,
>
> INTEL_CB_MAX
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c419a814cb34..06bf8f7c0989 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -646,7 +646,7 @@ struct intel_plane_state {
> enum drm_color_encoding color_encoding;
> enum drm_color_range color_range;
> enum drm_scaling_filter scaling_filter;
> - struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
> + struct drm_property_blob *ctm, *degamma_lut, *gamma_lut,
> *lut_3d;
> } hw;
>
> struct i915_vma *ggtt_vma;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> b/drivers/gpu/drm/i915/display/intel_plane.c
> index 4e6ddb36b872..d9db3742b8c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -352,6 +352,8 @@ intel_plane_colorop_replace_blob(struct
> intel_plane_state *plane_state,
> return drm_property_replace_blob(&plane_state-
> >hw.degamma_lut, blob);
> else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
> return drm_property_replace_blob(&plane_state-
> >hw.gamma_lut, blob);
> + else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
> + return drm_property_replace_blob(&plane_state->hw.lut_3d,
> blob);
>
> return false;
> }
> --
> 2.50.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [v7 15/15] drm/i915/color: Enable Plane Color Pipelines
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (13 preceding siblings ...)
2025-12-01 6:46 ` [v7 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
@ 2025-12-01 6:46 ` Uma Shankar
2025-12-01 21:14 ` kernel test robot
2025-12-01 6:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev6) Patchwork
` (4 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Uma Shankar @ 2025-12-01 6:46 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
v3: s/drm_color_lut_32/drm_color_lut32 (Simon)
v4: - Fix dsb programming
- Remove multi-segment LUT, they will be added in later patches
- Add pipeline only to TGL+
- Code Refactor
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
.../drm/i915/display/skl_universal_plane.c | 21 +++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e5ce47efc809..9c77b4416324 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7289,6 +7289,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;
if (!new_crtc_state->use_flipq &&
!new_crtc_state->use_dsb &&
@@ -7299,10 +7300,12 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
* Rough estimate:
* ~64 registers per each plane * 8 planes = 512
* Double that for pipe stuff and other overhead.
+ * ~4913 registers for 3DLUT
+ * ~200 color registers * 3 HDR planes
*/
new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
new_crtc_state->use_dsb ||
- new_crtc_state->use_flipq ? 1024 : 16);
+ new_crtc_state->use_flipq ? size : 16);
if (!new_crtc_state->dsb_commit) {
new_crtc_state->use_flipq = false;
new_crtc_state->use_dsb = false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 921b2f73d27a..495176aee4bb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -11,6 +11,8 @@
#include "pxp/intel_pxp.h"
#include "intel_bo.h"
+#include "intel_color.h"
+#include "intel_color_pipeline.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
@@ -1275,6 +1277,18 @@ static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)
if (plane_state->force_black)
plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ if (plane_state->hw.degamma_lut)
+ plane_color_ctl |= PLANE_COLOR_PRE_CSC_GAMMA_ENABLE;
+
+ if (plane_state->hw.ctm)
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+
+ if (plane_state->hw.gamma_lut) {
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)
+ plane_color_ctl |= PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE;
+ }
+
return plane_color_ctl;
}
@@ -1556,6 +1570,8 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
+ intel_color_plane_program_pipeline(dsb, plane_state);
+
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
crtc_x = 0;
@@ -1657,6 +1673,8 @@ icl_plane_update_arm(struct intel_dsb *dsb,
icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
+ intel_color_plane_commit_arm(dsb, plane_state);
+
/*
* In order to have FBC for fp16 formats pixel normalizer block must be
* active. Check if pixel normalizer block need to be enabled for FBC.
@@ -3001,6 +3019,9 @@ skl_universal_plane_create(struct intel_display *display,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ if (DISPLAY_VER(display) >= 12)
+ intel_color_pipeline_plane_init(&plane->base, pipe);
+
drm_plane_create_alpha_property(&plane->base);
drm_plane_create_blend_mode_property(&plane->base,
BIT(DRM_MODE_BLEND_PIXEL_NONE) |
--
2.50.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [v7 15/15] drm/i915/color: Enable Plane Color Pipelines
2025-12-01 6:46 ` [v7 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
@ 2025-12-01 21:14 ` kernel test robot
0 siblings, 0 replies; 44+ messages in thread
From: kernel test robot @ 2025-12-01 21:14 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: oe-kbuild-all, chaitanya.kumar.borah, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal, Uma Shankar
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20251201]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.18 v6.18-rc7 v6.18-rc6 linus/master v6.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Uma-Shankar/drm-i915-display-Add-identifiers-for-driver-specific-blocks/20251201-150245
base: next-20251201
patch link: https://lore.kernel.org/r/20251201064655.3579280-16-uma.shankar%40intel.com
patch subject: [v7 15/15] drm/i915/color: Enable Plane Color Pipelines
config: i386-buildonly-randconfig-006-20251201 (https://download.01.org/0day-ci/archive/20251202/202512020555.0E687sGd-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251202/202512020555.0E687sGd-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512020555.0E687sGd-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/skl_universal_plane.c:19:
drivers/gpu/drm/i915/display/intel_display_types.h:1993:28: error: field 'base' has incomplete type
1993 | struct drm_colorop base;
| ^~~~
drivers/gpu/drm/i915/display/skl_universal_plane.c: In function 'glk_plane_color_ctl':
>> drivers/gpu/drm/i915/display/skl_universal_plane.c:1288:21: error: implicit declaration of function 'drm_color_lut32_size'; did you mean 'drm_color_lut_size'? [-Wimplicit-function-declaration]
1288 | if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)
| ^~~~~~~~~~~~~~~~~~~~
| drm_color_lut_size
vim +1288 drivers/gpu/drm/i915/display/skl_universal_plane.c
1245
1246 static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)
1247 {
1248 struct intel_display *display = to_intel_display(plane_state);
1249 const struct drm_framebuffer *fb = plane_state->hw.fb;
1250 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1251 u32 plane_color_ctl = 0;
1252
1253 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
1254 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
1255
1256 if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) {
1257 switch (plane_state->hw.color_encoding) {
1258 case DRM_COLOR_YCBCR_BT709:
1259 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
1260 break;
1261 case DRM_COLOR_YCBCR_BT2020:
1262 plane_color_ctl |=
1263 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
1264 break;
1265 default:
1266 plane_color_ctl |=
1267 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
1268 }
1269 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1270 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
1271 } else if (fb->format->is_yuv) {
1272 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
1273 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1274 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
1275 }
1276
1277 if (plane_state->force_black)
1278 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
1279
1280 if (plane_state->hw.degamma_lut)
1281 plane_color_ctl |= PLANE_COLOR_PRE_CSC_GAMMA_ENABLE;
1282
1283 if (plane_state->hw.ctm)
1284 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
1285
1286 if (plane_state->hw.gamma_lut) {
1287 plane_color_ctl &= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
> 1288 if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)
1289 plane_color_ctl |= PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE;
1290 }
1291
1292 return plane_color_ctl;
1293 }
1294
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 44+ messages in thread
* ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev6)
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (14 preceding siblings ...)
2025-12-01 6:46 ` [v7 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
@ 2025-12-01 6:47 ` Patchwork
2025-12-01 6:48 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2025-12-01 6:47 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev6)
URL : https://patchwork.freedesktop.org/series/141788/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d8f5267dc37e79d7f45b81ec2495dcfb6e8d7f14
Author: Uma Shankar <uma.shankar@intel.com>
Date: Mon Dec 1 12:16:55 2025 +0530
drm/i915/color: Enable Plane Color Pipelines
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
v3: s/drm_color_lut_32/drm_color_lut32 (Simon)
v4: - Fix dsb programming
- Remove multi-segment LUT, they will be added in later patches
- Add pipeline only to TGL+
- Code Refactor
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 9fcf9189976d387cb9199155c35dd6c826268c52 drm-intel
dbb6832c746b drm/i915/display: Add identifiers for driver specific blocks
c70350e10b61 drm/i915: Add intel_color_op
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
2cedffcb569b drm/i915/color: Add helper to create intel colorop
f93d30ada8a3 drm/i915/color: Create a transfer function color pipeline
-:41: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 124 lines checked
f70a9facffd9 drm/i915/color: Add framework to program CSC
b43480bd87b5 drm/i915/color: Preserve sign bit when int_bits is Zero
753d3e1473a5 drm/i915/color: Add plane CTM callback for D12 and beyond
0bc27935d927 drm/i915: Add register definitions for Plane Degamma
-:40: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:300:
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
-:42: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:302:
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
-:44: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
-:45: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
-:52: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:312:
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
-:54: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:314:
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
-:56: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
-:57: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:317:
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
-:67: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#67: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
-:68: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#68: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:328:
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
-:78: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
-:78: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#78: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
-:79: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#79: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:339:
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
total: 0 errors, 12 warnings, 4 checks, 60 lines checked
688047b90591 drm/i915: Add register definitions for Plane Post CSC
-:39: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:301:
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
-:40: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:302:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
-:41: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:303:
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
-:42: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
-:43: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#43: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
-:44: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:306:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
-:50: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:312:
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
-:51: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:313:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
-:52: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:314:
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
-:53: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:315:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
-:54: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
-:55: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:317:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
-:61: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:323:
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
-:63: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#63: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:325:
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
-:65: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#65: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
-:66: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:328:
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
-:72: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:334:
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
-:74: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:336:
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
-:76: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
-:76: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#76: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
-:77: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:339:
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
-:83: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#83: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:345:
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \
-:85: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:347:
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \
-:87: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:349:
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
-:87: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#87: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:349:
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
-:88: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:350:
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
-:98: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:360:
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
-:98: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#98: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:360:
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
-:99: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#99: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:361:
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
total: 0 errors, 26 warnings, 6 checks, 79 lines checked
b4120f4d09db drm/i915/color: Add framework to program PRE/POST CSC LUT
1639b52e7a7c drm/i915/color: Program Pre-CSC registers
59c545469b16 drm/i915/xelpd: Program Plane Post CSC Registers
2f5cdc667ac3 drm/i915/display: Add registers for 3D LUT
7fcdd42d1f14 drm/i915/color: Add 3D LUT to color pipeline
d8f5267dc37e drm/i915/color: Enable Plane Color Pipelines
^ permalink raw reply [flat|nested] 44+ messages in thread* ✓ CI.KUnit: success for Plane Color Pipeline support for Intel platforms (rev6)
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (15 preceding siblings ...)
2025-12-01 6:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev6) Patchwork
@ 2025-12-01 6:48 ` Patchwork
2025-12-01 7:03 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2025-12-01 6:48 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev6)
URL : https://patchwork.freedesktop.org/series/141788/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:47:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:47:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:47:55] Starting KUnit Kernel (1/1)...
[06:47:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:47:55] ================== guc_buf (11 subtests) ===================
[06:47:55] [PASSED] test_smallest
[06:47:55] [PASSED] test_largest
[06:47:55] [PASSED] test_granular
[06:47:55] [PASSED] test_unique
[06:47:55] [PASSED] test_overlap
[06:47:55] [PASSED] test_reusable
[06:47:55] [PASSED] test_too_big
[06:47:55] [PASSED] test_flush
[06:47:55] [PASSED] test_lookup
[06:47:55] [PASSED] test_data
[06:47:55] [PASSED] test_class
[06:47:55] ===================== [PASSED] guc_buf =====================
[06:47:55] =================== guc_dbm (7 subtests) ===================
[06:47:55] [PASSED] test_empty
[06:47:55] [PASSED] test_default
[06:47:55] ======================== test_size ========================
[06:47:55] [PASSED] 4
[06:47:55] [PASSED] 8
[06:47:55] [PASSED] 32
[06:47:55] [PASSED] 256
[06:47:55] ==================== [PASSED] test_size ====================
[06:47:55] ======================= test_reuse ========================
[06:47:55] [PASSED] 4
[06:47:55] [PASSED] 8
[06:47:55] [PASSED] 32
[06:47:55] [PASSED] 256
[06:47:55] =================== [PASSED] test_reuse ====================
[06:47:55] =================== test_range_overlap ====================
[06:47:55] [PASSED] 4
[06:47:55] [PASSED] 8
[06:47:55] [PASSED] 32
[06:47:55] [PASSED] 256
[06:47:55] =============== [PASSED] test_range_overlap ================
[06:47:55] =================== test_range_compact ====================
[06:47:55] [PASSED] 4
[06:47:55] [PASSED] 8
[06:47:55] [PASSED] 32
[06:47:55] [PASSED] 256
[06:47:55] =============== [PASSED] test_range_compact ================
[06:47:55] ==================== test_range_spare =====================
[06:47:55] [PASSED] 4
[06:47:55] [PASSED] 8
[06:47:55] [PASSED] 32
[06:47:55] [PASSED] 256
[06:47:55] ================ [PASSED] test_range_spare =================
[06:47:55] ===================== [PASSED] guc_dbm =====================
[06:47:55] =================== guc_idm (6 subtests) ===================
[06:47:55] [PASSED] bad_init
[06:47:55] [PASSED] no_init
[06:47:55] [PASSED] init_fini
[06:47:55] [PASSED] check_used
[06:47:55] [PASSED] check_quota
[06:47:55] [PASSED] check_all
[06:47:55] ===================== [PASSED] guc_idm =====================
[06:47:55] ================== no_relay (3 subtests) ===================
[06:47:55] [PASSED] xe_drops_guc2pf_if_not_ready
[06:47:55] [PASSED] xe_drops_guc2vf_if_not_ready
[06:47:55] [PASSED] xe_rejects_send_if_not_ready
[06:47:55] ==================== [PASSED] no_relay =====================
[06:47:55] ================== pf_relay (14 subtests) ==================
[06:47:55] [PASSED] pf_rejects_guc2pf_too_short
[06:47:55] [PASSED] pf_rejects_guc2pf_too_long
[06:47:55] [PASSED] pf_rejects_guc2pf_no_payload
[06:47:55] [PASSED] pf_fails_no_payload
[06:47:55] [PASSED] pf_fails_bad_origin
[06:47:55] [PASSED] pf_fails_bad_type
[06:47:55] [PASSED] pf_txn_reports_error
[06:47:55] [PASSED] pf_txn_sends_pf2guc
[06:47:55] [PASSED] pf_sends_pf2guc
[06:47:55] [SKIPPED] pf_loopback_nop
[06:47:55] [SKIPPED] pf_loopback_echo
[06:47:55] [SKIPPED] pf_loopback_fail
[06:47:55] [SKIPPED] pf_loopback_busy
[06:47:55] [SKIPPED] pf_loopback_retry
[06:47:55] ==================== [PASSED] pf_relay =====================
[06:47:55] ================== vf_relay (3 subtests) ===================
[06:47:55] [PASSED] vf_rejects_guc2vf_too_short
[06:47:55] [PASSED] vf_rejects_guc2vf_too_long
[06:47:55] [PASSED] vf_rejects_guc2vf_no_payload
[06:47:55] ==================== [PASSED] vf_relay =====================
[06:47:55] ================ pf_gt_config (6 subtests) =================
[06:47:55] [PASSED] fair_contexts_1vf
[06:47:55] [PASSED] fair_doorbells_1vf
[06:47:55] [PASSED] fair_ggtt_1vf
[06:47:55] ====================== fair_contexts ======================
[06:47:55] [PASSED] 1 VF
[06:47:55] [PASSED] 2 VFs
[06:47:55] [PASSED] 3 VFs
[06:47:55] [PASSED] 4 VFs
[06:47:55] [PASSED] 5 VFs
[06:47:55] [PASSED] 6 VFs
[06:47:55] [PASSED] 7 VFs
[06:47:55] [PASSED] 8 VFs
[06:47:55] [PASSED] 9 VFs
[06:47:55] [PASSED] 10 VFs
[06:47:55] [PASSED] 11 VFs
[06:47:55] [PASSED] 12 VFs
[06:47:55] [PASSED] 13 VFs
[06:47:55] [PASSED] 14 VFs
[06:47:55] [PASSED] 15 VFs
[06:47:55] [PASSED] 16 VFs
[06:47:55] [PASSED] 17 VFs
[06:47:55] [PASSED] 18 VFs
[06:47:55] [PASSED] 19 VFs
[06:47:55] [PASSED] 20 VFs
[06:47:55] [PASSED] 21 VFs
[06:47:55] [PASSED] 22 VFs
[06:47:55] [PASSED] 23 VFs
[06:47:55] [PASSED] 24 VFs
[06:47:55] [PASSED] 25 VFs
[06:47:55] [PASSED] 26 VFs
[06:47:55] [PASSED] 27 VFs
[06:47:55] [PASSED] 28 VFs
[06:47:55] [PASSED] 29 VFs
[06:47:55] [PASSED] 30 VFs
[06:47:55] [PASSED] 31 VFs
[06:47:55] [PASSED] 32 VFs
[06:47:55] [PASSED] 33 VFs
[06:47:55] [PASSED] 34 VFs
[06:47:55] [PASSED] 35 VFs
[06:47:55] [PASSED] 36 VFs
[06:47:55] [PASSED] 37 VFs
[06:47:55] [PASSED] 38 VFs
[06:47:55] [PASSED] 39 VFs
[06:47:55] [PASSED] 40 VFs
[06:47:55] [PASSED] 41 VFs
[06:47:55] [PASSED] 42 VFs
[06:47:55] [PASSED] 43 VFs
[06:47:55] [PASSED] 44 VFs
[06:47:55] [PASSED] 45 VFs
[06:47:55] [PASSED] 46 VFs
[06:47:55] [PASSED] 47 VFs
[06:47:55] [PASSED] 48 VFs
[06:47:55] [PASSED] 49 VFs
[06:47:55] [PASSED] 50 VFs
[06:47:55] [PASSED] 51 VFs
[06:47:55] [PASSED] 52 VFs
[06:47:55] [PASSED] 53 VFs
[06:47:55] [PASSED] 54 VFs
[06:47:55] [PASSED] 55 VFs
[06:47:55] [PASSED] 56 VFs
[06:47:55] [PASSED] 57 VFs
[06:47:55] [PASSED] 58 VFs
[06:47:55] [PASSED] 59 VFs
[06:47:55] [PASSED] 60 VFs
[06:47:55] [PASSED] 61 VFs
[06:47:55] [PASSED] 62 VFs
[06:47:55] [PASSED] 63 VFs
[06:47:55] ================== [PASSED] fair_contexts ==================
[06:47:55] ===================== fair_doorbells ======================
[06:47:55] [PASSED] 1 VF
[06:47:55] [PASSED] 2 VFs
[06:47:55] [PASSED] 3 VFs
[06:47:55] [PASSED] 4 VFs
[06:47:55] [PASSED] 5 VFs
[06:47:55] [PASSED] 6 VFs
[06:47:55] [PASSED] 7 VFs
[06:47:55] [PASSED] 8 VFs
[06:47:55] [PASSED] 9 VFs
[06:47:55] [PASSED] 10 VFs
[06:47:55] [PASSED] 11 VFs
[06:47:55] [PASSED] 12 VFs
[06:47:55] [PASSED] 13 VFs
[06:47:55] [PASSED] 14 VFs
[06:47:55] [PASSED] 15 VFs
[06:47:55] [PASSED] 16 VFs
[06:47:55] [PASSED] 17 VFs
[06:47:55] [PASSED] 18 VFs
[06:47:55] [PASSED] 19 VFs
[06:47:55] [PASSED] 20 VFs
[06:47:55] [PASSED] 21 VFs
[06:47:55] [PASSED] 22 VFs
[06:47:55] [PASSED] 23 VFs
[06:47:55] [PASSED] 24 VFs
[06:47:55] [PASSED] 25 VFs
[06:47:55] [PASSED] 26 VFs
[06:47:55] [PASSED] 27 VFs
[06:47:55] [PASSED] 28 VFs
[06:47:55] [PASSED] 29 VFs
[06:47:55] [PASSED] 30 VFs
[06:47:55] [PASSED] 31 VFs
[06:47:55] [PASSED] 32 VFs
[06:47:55] [PASSED] 33 VFs
[06:47:55] [PASSED] 34 VFs
[06:47:55] [PASSED] 35 VFs
[06:47:55] [PASSED] 36 VFs
[06:47:55] [PASSED] 37 VFs
[06:47:55] [PASSED] 38 VFs
[06:47:55] [PASSED] 39 VFs
[06:47:55] [PASSED] 40 VFs
[06:47:55] [PASSED] 41 VFs
[06:47:56] [PASSED] 42 VFs
[06:47:56] [PASSED] 43 VFs
[06:47:56] [PASSED] 44 VFs
[06:47:56] [PASSED] 45 VFs
[06:47:56] [PASSED] 46 VFs
[06:47:56] [PASSED] 47 VFs
[06:47:56] [PASSED] 48 VFs
[06:47:56] [PASSED] 49 VFs
[06:47:56] [PASSED] 50 VFs
[06:47:56] [PASSED] 51 VFs
[06:47:56] [PASSED] 52 VFs
[06:47:56] [PASSED] 53 VFs
[06:47:56] [PASSED] 54 VFs
[06:47:56] [PASSED] 55 VFs
[06:47:56] [PASSED] 56 VFs
[06:47:56] [PASSED] 57 VFs
[06:47:56] [PASSED] 58 VFs
[06:47:56] [PASSED] 59 VFs
[06:47:56] [PASSED] 60 VFs
[06:47:56] [PASSED] 61 VFs
[06:47:56] [PASSED] 62 VFs
[06:47:56] [PASSED] 63 VFs
[06:47:56] ================= [PASSED] fair_doorbells ==================
[06:47:56] ======================== fair_ggtt ========================
[06:47:56] [PASSED] 1 VF
[06:47:56] [PASSED] 2 VFs
[06:47:56] [PASSED] 3 VFs
[06:47:56] [PASSED] 4 VFs
[06:47:56] [PASSED] 5 VFs
[06:47:56] [PASSED] 6 VFs
[06:47:56] [PASSED] 7 VFs
[06:47:56] [PASSED] 8 VFs
[06:47:56] [PASSED] 9 VFs
[06:47:56] [PASSED] 10 VFs
[06:47:56] [PASSED] 11 VFs
[06:47:56] [PASSED] 12 VFs
[06:47:56] [PASSED] 13 VFs
[06:47:56] [PASSED] 14 VFs
[06:47:56] [PASSED] 15 VFs
[06:47:56] [PASSED] 16 VFs
[06:47:56] [PASSED] 17 VFs
[06:47:56] [PASSED] 18 VFs
[06:47:56] [PASSED] 19 VFs
[06:47:56] [PASSED] 20 VFs
[06:47:56] [PASSED] 21 VFs
[06:47:56] [PASSED] 22 VFs
[06:47:56] [PASSED] 23 VFs
[06:47:56] [PASSED] 24 VFs
[06:47:56] [PASSED] 25 VFs
[06:47:56] [PASSED] 26 VFs
[06:47:56] [PASSED] 27 VFs
[06:47:56] [PASSED] 28 VFs
[06:47:56] [PASSED] 29 VFs
[06:47:56] [PASSED] 30 VFs
[06:47:56] [PASSED] 31 VFs
[06:47:56] [PASSED] 32 VFs
[06:47:56] [PASSED] 33 VFs
[06:47:56] [PASSED] 34 VFs
[06:47:56] [PASSED] 35 VFs
[06:47:56] [PASSED] 36 VFs
[06:47:56] [PASSED] 37 VFs
[06:47:56] [PASSED] 38 VFs
[06:47:56] [PASSED] 39 VFs
[06:47:56] [PASSED] 40 VFs
[06:47:56] [PASSED] 41 VFs
[06:47:56] [PASSED] 42 VFs
[06:47:56] [PASSED] 43 VFs
[06:47:56] [PASSED] 44 VFs
[06:47:56] [PASSED] 45 VFs
[06:47:56] [PASSED] 46 VFs
[06:47:56] [PASSED] 47 VFs
[06:47:56] [PASSED] 48 VFs
[06:47:56] [PASSED] 49 VFs
[06:47:56] [PASSED] 50 VFs
[06:47:56] [PASSED] 51 VFs
[06:47:56] [PASSED] 52 VFs
[06:47:56] [PASSED] 53 VFs
[06:47:56] [PASSED] 54 VFs
[06:47:56] [PASSED] 55 VFs
[06:47:56] [PASSED] 56 VFs
[06:47:56] [PASSED] 57 VFs
[06:47:56] [PASSED] 58 VFs
[06:47:56] [PASSED] 59 VFs
[06:47:56] [PASSED] 60 VFs
[06:47:56] [PASSED] 61 VFs
[06:47:56] [PASSED] 62 VFs
[06:47:56] [PASSED] 63 VFs
[06:47:56] ==================== [PASSED] fair_ggtt ====================
[06:47:56] ================== [PASSED] pf_gt_config ===================
[06:47:56] ===================== lmtt (1 subtest) =====================
[06:47:56] ======================== test_ops =========================
[06:47:56] [PASSED] 2-level
[06:47:56] [PASSED] multi-level
[06:47:56] ==================== [PASSED] test_ops =====================
[06:47:56] ====================== [PASSED] lmtt =======================
[06:47:56] ================= pf_service (11 subtests) =================
[06:47:56] [PASSED] pf_negotiate_any
[06:47:56] [PASSED] pf_negotiate_base_match
[06:47:56] [PASSED] pf_negotiate_base_newer
[06:47:56] [PASSED] pf_negotiate_base_next
[06:47:56] [SKIPPED] pf_negotiate_base_older
[06:47:56] [PASSED] pf_negotiate_base_prev
[06:47:56] [PASSED] pf_negotiate_latest_match
[06:47:56] [PASSED] pf_negotiate_latest_newer
[06:47:56] [PASSED] pf_negotiate_latest_next
[06:47:56] [SKIPPED] pf_negotiate_latest_older
[06:47:56] [SKIPPED] pf_negotiate_latest_prev
[06:47:56] =================== [PASSED] pf_service ====================
[06:47:56] ================= xe_guc_g2g (2 subtests) ==================
[06:47:56] ============== xe_live_guc_g2g_kunit_default ==============
[06:47:56] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:47:56] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:47:56] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:47:56] =================== [SKIPPED] xe_guc_g2g ===================
[06:47:56] =================== xe_mocs (2 subtests) ===================
[06:47:56] ================ xe_live_mocs_kernel_kunit ================
[06:47:56] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:47:56] ================ xe_live_mocs_reset_kunit =================
[06:47:56] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:47:56] ==================== [SKIPPED] xe_mocs =====================
[06:47:56] ================= xe_migrate (2 subtests) ==================
[06:47:56] ================= xe_migrate_sanity_kunit =================
[06:47:56] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:47:56] ================== xe_validate_ccs_kunit ==================
[06:47:56] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:47:56] =================== [SKIPPED] xe_migrate ===================
[06:47:56] ================== xe_dma_buf (1 subtest) ==================
[06:47:56] ==================== xe_dma_buf_kunit =====================
[06:47:56] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:47:56] =================== [SKIPPED] xe_dma_buf ===================
[06:47:56] ================= xe_bo_shrink (1 subtest) =================
[06:47:56] =================== xe_bo_shrink_kunit ====================
[06:47:56] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:47:56] ================== [SKIPPED] xe_bo_shrink ==================
[06:47:56] ==================== xe_bo (2 subtests) ====================
[06:47:56] ================== xe_ccs_migrate_kunit ===================
[06:47:56] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:47:56] ==================== xe_bo_evict_kunit ====================
[06:47:56] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:47:56] ===================== [SKIPPED] xe_bo ======================
[06:47:56] ==================== args (11 subtests) ====================
[06:47:56] [PASSED] count_args_test
[06:47:56] [PASSED] call_args_example
[06:47:56] [PASSED] call_args_test
[06:47:56] [PASSED] drop_first_arg_example
[06:47:56] [PASSED] drop_first_arg_test
[06:47:56] [PASSED] first_arg_example
[06:47:56] [PASSED] first_arg_test
[06:47:56] [PASSED] last_arg_example
[06:47:56] [PASSED] last_arg_test
[06:47:56] [PASSED] pick_arg_example
[06:47:56] [PASSED] sep_comma_example
[06:47:56] ====================== [PASSED] args =======================
[06:47:56] =================== xe_pci (3 subtests) ====================
[06:47:56] ==================== check_graphics_ip ====================
[06:47:56] [PASSED] 12.00 Xe_LP
[06:47:56] [PASSED] 12.10 Xe_LP+
[06:47:56] [PASSED] 12.55 Xe_HPG
[06:47:56] [PASSED] 12.60 Xe_HPC
[06:47:56] [PASSED] 12.70 Xe_LPG
[06:47:56] [PASSED] 12.71 Xe_LPG
[06:47:56] [PASSED] 12.74 Xe_LPG+
[06:47:56] [PASSED] 20.01 Xe2_HPG
[06:47:56] [PASSED] 20.02 Xe2_HPG
[06:47:56] [PASSED] 20.04 Xe2_LPG
[06:47:56] [PASSED] 30.00 Xe3_LPG
[06:47:56] [PASSED] 30.01 Xe3_LPG
[06:47:56] [PASSED] 30.03 Xe3_LPG
[06:47:56] [PASSED] 30.04 Xe3_LPG
[06:47:56] [PASSED] 30.05 Xe3_LPG
[06:47:56] [PASSED] 35.11 Xe3p_XPC
[06:47:56] ================ [PASSED] check_graphics_ip ================
[06:47:56] ===================== check_media_ip ======================
[06:47:56] [PASSED] 12.00 Xe_M
[06:47:56] [PASSED] 12.55 Xe_HPM
[06:47:56] [PASSED] 13.00 Xe_LPM+
[06:47:56] [PASSED] 13.01 Xe2_HPM
[06:47:56] [PASSED] 20.00 Xe2_LPM
[06:47:56] [PASSED] 30.00 Xe3_LPM
[06:47:56] [PASSED] 30.02 Xe3_LPM
[06:47:56] [PASSED] 35.00 Xe3p_LPM
[06:47:56] [PASSED] 35.03 Xe3p_HPM
[06:47:56] ================= [PASSED] check_media_ip ==================
[06:47:56] =================== check_platform_desc ===================
[06:47:56] [PASSED] 0x9A60 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A68 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A70 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A40 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A49 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A59 (TIGERLAKE)
[06:47:56] [PASSED] 0x9A78 (TIGERLAKE)
[06:47:56] [PASSED] 0x9AC0 (TIGERLAKE)
[06:47:56] [PASSED] 0x9AC9 (TIGERLAKE)
[06:47:56] [PASSED] 0x9AD9 (TIGERLAKE)
[06:47:56] [PASSED] 0x9AF8 (TIGERLAKE)
[06:47:56] [PASSED] 0x4C80 (ROCKETLAKE)
[06:47:56] [PASSED] 0x4C8A (ROCKETLAKE)
[06:47:56] [PASSED] 0x4C8B (ROCKETLAKE)
[06:47:56] [PASSED] 0x4C8C (ROCKETLAKE)
[06:47:56] [PASSED] 0x4C90 (ROCKETLAKE)
[06:47:56] [PASSED] 0x4C9A (ROCKETLAKE)
[06:47:56] [PASSED] 0x4680 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4682 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4688 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x468A (ALDERLAKE_S)
[06:47:56] [PASSED] 0x468B (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4690 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4692 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4693 (ALDERLAKE_S)
[06:47:56] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46AA (ALDERLAKE_P)
[06:47:56] [PASSED] 0x462A (ALDERLAKE_P)
[06:47:56] [PASSED] 0x4626 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x4628 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[06:47:56] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:47:56] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:47:56] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:47:56] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:47:56] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:47:56] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:47:56] [PASSED] 0xA721 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA720 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:47:56] [PASSED] 0xA780 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA781 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA782 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA783 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA788 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA789 (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA78A (ALDERLAKE_S)
[06:47:56] [PASSED] 0xA78B (ALDERLAKE_S)
[06:47:56] [PASSED] 0x4905 (DG1)
[06:47:56] [PASSED] 0x4906 (DG1)
[06:47:56] [PASSED] 0x4907 (DG1)
[06:47:56] [PASSED] 0x4908 (DG1)
[06:47:56] [PASSED] 0x4909 (DG1)
[06:47:56] [PASSED] 0x56C0 (DG2)
[06:47:56] [PASSED] 0x56C2 (DG2)
[06:47:56] [PASSED] 0x56C1 (DG2)
[06:47:56] [PASSED] 0x7D51 (METEORLAKE)
[06:47:56] [PASSED] 0x7DD1 (METEORLAKE)
[06:47:56] [PASSED] 0x7D41 (METEORLAKE)
[06:47:56] [PASSED] 0x7D67 (METEORLAKE)
[06:47:56] [PASSED] 0xB640 (METEORLAKE)
[06:47:56] [PASSED] 0x56A0 (DG2)
[06:47:56] [PASSED] 0x56A1 (DG2)
[06:47:56] [PASSED] 0x56A2 (DG2)
[06:47:56] [PASSED] 0x56BE (DG2)
[06:47:56] [PASSED] 0x56BF (DG2)
[06:47:56] [PASSED] 0x5690 (DG2)
[06:47:56] [PASSED] 0x5691 (DG2)
[06:47:56] [PASSED] 0x5692 (DG2)
[06:47:56] [PASSED] 0x56A5 (DG2)
[06:47:56] [PASSED] 0x56A6 (DG2)
[06:47:56] [PASSED] 0x56B0 (DG2)
[06:47:56] [PASSED] 0x56B1 (DG2)
[06:47:56] [PASSED] 0x56BA (DG2)
[06:47:56] [PASSED] 0x56BB (DG2)
[06:47:56] [PASSED] 0x56BC (DG2)
[06:47:56] [PASSED] 0x56BD (DG2)
[06:47:56] [PASSED] 0x5693 (DG2)
[06:47:56] [PASSED] 0x5694 (DG2)
[06:47:56] [PASSED] 0x5695 (DG2)
[06:47:56] [PASSED] 0x56A3 (DG2)
[06:47:56] [PASSED] 0x56A4 (DG2)
[06:47:56] [PASSED] 0x56B2 (DG2)
[06:47:56] [PASSED] 0x56B3 (DG2)
[06:47:56] [PASSED] 0x5696 (DG2)
[06:47:56] [PASSED] 0x5697 (DG2)
[06:47:56] [PASSED] 0xB69 (PVC)
[06:47:56] [PASSED] 0xB6E (PVC)
[06:47:56] [PASSED] 0xBD4 (PVC)
[06:47:56] [PASSED] 0xBD5 (PVC)
[06:47:56] [PASSED] 0xBD6 (PVC)
[06:47:56] [PASSED] 0xBD7 (PVC)
[06:47:56] [PASSED] 0xBD8 (PVC)
[06:47:56] [PASSED] 0xBD9 (PVC)
[06:47:56] [PASSED] 0xBDA (PVC)
[06:47:56] [PASSED] 0xBDB (PVC)
[06:47:56] [PASSED] 0xBE0 (PVC)
[06:47:56] [PASSED] 0xBE1 (PVC)
[06:47:56] [PASSED] 0xBE5 (PVC)
[06:47:56] [PASSED] 0x7D40 (METEORLAKE)
[06:47:56] [PASSED] 0x7D45 (METEORLAKE)
[06:47:56] [PASSED] 0x7D55 (METEORLAKE)
[06:47:56] [PASSED] 0x7D60 (METEORLAKE)
[06:47:56] [PASSED] 0x7DD5 (METEORLAKE)
[06:47:56] [PASSED] 0x6420 (LUNARLAKE)
[06:47:56] [PASSED] 0x64A0 (LUNARLAKE)
[06:47:56] [PASSED] 0x64B0 (LUNARLAKE)
[06:47:56] [PASSED] 0xE202 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE209 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE20B (BATTLEMAGE)
[06:47:56] [PASSED] 0xE20C (BATTLEMAGE)
[06:47:56] [PASSED] 0xE20D (BATTLEMAGE)
[06:47:56] [PASSED] 0xE210 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE211 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE212 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE216 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE220 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE221 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE222 (BATTLEMAGE)
[06:47:56] [PASSED] 0xE223 (BATTLEMAGE)
[06:47:56] [PASSED] 0xB080 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB081 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB082 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB083 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB084 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB085 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB086 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB087 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB08F (PANTHERLAKE)
[06:47:56] [PASSED] 0xB090 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:47:56] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:47:56] [PASSED] 0xD740 (NOVALAKE_S)
[06:47:56] [PASSED] 0xD741 (NOVALAKE_S)
[06:47:56] [PASSED] 0xD742 (NOVALAKE_S)
[06:47:56] [PASSED] 0xD743 (NOVALAKE_S)
[06:47:56] [PASSED] 0xD744 (NOVALAKE_S)
[06:47:56] [PASSED] 0xD745 (NOVALAKE_S)
[06:47:56] [PASSED] 0x674C (CRESCENTISLAND)
[06:47:56] [PASSED] 0xFD80 (PANTHERLAKE)
[06:47:56] [PASSED] 0xFD81 (PANTHERLAKE)
[06:47:56] =============== [PASSED] check_platform_desc ===============
[06:47:56] ===================== [PASSED] xe_pci ======================
[06:47:56] =================== xe_rtp (2 subtests) ====================
[06:47:56] =============== xe_rtp_process_to_sr_tests ================
[06:47:56] [PASSED] coalesce-same-reg
[06:47:56] [PASSED] no-match-no-add
[06:47:56] [PASSED] match-or
[06:47:56] [PASSED] match-or-xfail
[06:47:56] [PASSED] no-match-no-add-multiple-rules
[06:47:56] [PASSED] two-regs-two-entries
[06:47:56] [PASSED] clr-one-set-other
[06:47:56] [PASSED] set-field
[06:47:56] [PASSED] conflict-duplicate
[06:47:56] [PASSED] conflict-not-disjoint
[06:47:56] [PASSED] conflict-reg-type
[06:47:56] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:47:56] ================== xe_rtp_process_tests ===================
[06:47:56] [PASSED] active1
[06:47:56] [PASSED] active2
[06:47:56] [PASSED] active-inactive
[06:47:56] [PASSED] inactive-active
[06:47:56] [PASSED] inactive-1st_or_active-inactive
[06:47:56] [PASSED] inactive-2nd_or_active-inactive
[06:47:56] [PASSED] inactive-last_or_active-inactive
[06:47:56] [PASSED] inactive-no_or_active-inactive
[06:47:56] ============== [PASSED] xe_rtp_process_tests ===============
[06:47:56] ===================== [PASSED] xe_rtp ======================
[06:47:56] ==================== xe_wa (1 subtest) =====================
[06:47:56] ======================== xe_wa_gt =========================
[06:47:56] [PASSED] TIGERLAKE B0
[06:47:56] [PASSED] DG1 A0
[06:47:56] [PASSED] DG1 B0
[06:47:56] [PASSED] ALDERLAKE_S A0
[06:47:56] [PASSED] ALDERLAKE_S B0
[06:47:56] [PASSED] ALDERLAKE_S C0
[06:47:56] [PASSED] ALDERLAKE_S D0
[06:47:56] [PASSED] ALDERLAKE_P A0
[06:47:56] [PASSED] ALDERLAKE_P B0
[06:47:56] [PASSED] ALDERLAKE_P C0
[06:47:56] [PASSED] ALDERLAKE_S RPLS D0
[06:47:56] [PASSED] ALDERLAKE_P RPLU E0
[06:47:56] [PASSED] DG2 G10 C0
[06:47:56] [PASSED] DG2 G11 B1
[06:47:56] [PASSED] DG2 G12 A1
[06:47:56] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:47:56] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:47:56] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:47:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:47:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:47:56] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:47:56] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:47:56] ==================== [PASSED] xe_wa_gt =====================
[06:47:56] ====================== [PASSED] xe_wa ======================
[06:47:56] ============================================================
[06:47:56] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[06:47:56] Elapsed time: 35.603s total, 4.157s configuring, 30.928s building, 0.463s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:47:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:47:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:48:23] Starting KUnit Kernel (1/1)...
[06:48:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:48:23] ============ drm_test_pick_cmdline (2 subtests) ============
[06:48:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:48:23] =============== drm_test_pick_cmdline_named ===============
[06:48:23] [PASSED] NTSC
[06:48:23] [PASSED] NTSC-J
[06:48:23] [PASSED] PAL
[06:48:23] [PASSED] PAL-M
[06:48:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:48:23] ============== [PASSED] drm_test_pick_cmdline ==============
[06:48:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:48:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:48:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:48:23] =========== drm_validate_clone_mode (2 subtests) ===========
[06:48:23] ============== drm_test_check_in_clone_mode ===============
[06:48:23] [PASSED] in_clone_mode
[06:48:23] [PASSED] not_in_clone_mode
[06:48:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:48:23] =============== drm_test_check_valid_clones ===============
[06:48:23] [PASSED] not_in_clone_mode
[06:48:23] [PASSED] valid_clone
[06:48:23] [PASSED] invalid_clone
[06:48:23] =========== [PASSED] drm_test_check_valid_clones ===========
[06:48:23] ============= [PASSED] drm_validate_clone_mode =============
[06:48:23] ============= drm_validate_modeset (1 subtest) =============
[06:48:23] [PASSED] drm_test_check_connector_changed_modeset
[06:48:23] ============== [PASSED] drm_validate_modeset ===============
[06:48:23] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:48:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:48:23] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:48:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:48:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:48:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:48:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:48:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:48:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:48:23] ============== drm_bridge_alloc (2 subtests) ===============
[06:48:23] [PASSED] drm_test_drm_bridge_alloc_basic
[06:48:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:48:23] ================ [PASSED] drm_bridge_alloc =================
[06:48:23] ================== drm_buddy (8 subtests) ==================
[06:48:23] [PASSED] drm_test_buddy_alloc_limit
[06:48:23] [PASSED] drm_test_buddy_alloc_optimistic
[06:48:23] [PASSED] drm_test_buddy_alloc_pessimistic
[06:48:23] [PASSED] drm_test_buddy_alloc_pathological
[06:48:23] [PASSED] drm_test_buddy_alloc_contiguous
[06:48:23] [PASSED] drm_test_buddy_alloc_clear
[06:48:23] [PASSED] drm_test_buddy_alloc_range_bias
[06:48:23] [PASSED] drm_test_buddy_fragmentation_performance
[06:48:23] ==================== [PASSED] drm_buddy ====================
[06:48:23] ============= drm_cmdline_parser (40 subtests) =============
[06:48:23] [PASSED] drm_test_cmdline_force_d_only
[06:48:23] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:48:23] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:48:23] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:48:23] [PASSED] drm_test_cmdline_force_e_only
[06:48:23] [PASSED] drm_test_cmdline_res
[06:48:23] [PASSED] drm_test_cmdline_res_vesa
[06:48:23] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:48:23] [PASSED] drm_test_cmdline_res_rblank
[06:48:23] [PASSED] drm_test_cmdline_res_bpp
[06:48:23] [PASSED] drm_test_cmdline_res_refresh
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:48:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:48:23] [PASSED] drm_test_cmdline_res_margins_force_on
[06:48:23] [PASSED] drm_test_cmdline_res_vesa_margins
[06:48:23] [PASSED] drm_test_cmdline_name
[06:48:23] [PASSED] drm_test_cmdline_name_bpp
[06:48:23] [PASSED] drm_test_cmdline_name_option
[06:48:23] [PASSED] drm_test_cmdline_name_bpp_option
[06:48:23] [PASSED] drm_test_cmdline_rotate_0
[06:48:23] [PASSED] drm_test_cmdline_rotate_90
[06:48:23] [PASSED] drm_test_cmdline_rotate_180
[06:48:23] [PASSED] drm_test_cmdline_rotate_270
[06:48:23] [PASSED] drm_test_cmdline_hmirror
[06:48:23] [PASSED] drm_test_cmdline_vmirror
[06:48:23] [PASSED] drm_test_cmdline_margin_options
[06:48:23] [PASSED] drm_test_cmdline_multiple_options
[06:48:23] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:48:23] [PASSED] drm_test_cmdline_extra_and_option
[06:48:23] [PASSED] drm_test_cmdline_freestanding_options
[06:48:23] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:48:23] [PASSED] drm_test_cmdline_panel_orientation
[06:48:23] ================ drm_test_cmdline_invalid =================
[06:48:23] [PASSED] margin_only
[06:48:23] [PASSED] interlace_only
[06:48:23] [PASSED] res_missing_x
[06:48:23] [PASSED] res_missing_y
[06:48:23] [PASSED] res_bad_y
[06:48:23] [PASSED] res_missing_y_bpp
[06:48:23] [PASSED] res_bad_bpp
[06:48:23] [PASSED] res_bad_refresh
[06:48:23] [PASSED] res_bpp_refresh_force_on_off
[06:48:23] [PASSED] res_invalid_mode
[06:48:23] [PASSED] res_bpp_wrong_place_mode
[06:48:23] [PASSED] name_bpp_refresh
[06:48:23] [PASSED] name_refresh
[06:48:23] [PASSED] name_refresh_wrong_mode
[06:48:23] [PASSED] name_refresh_invalid_mode
[06:48:23] [PASSED] rotate_multiple
[06:48:23] [PASSED] rotate_invalid_val
[06:48:23] [PASSED] rotate_truncated
[06:48:23] [PASSED] invalid_option
[06:48:23] [PASSED] invalid_tv_option
[06:48:23] [PASSED] truncated_tv_option
[06:48:23] ============ [PASSED] drm_test_cmdline_invalid =============
[06:48:23] =============== drm_test_cmdline_tv_options ===============
[06:48:23] [PASSED] NTSC
[06:48:23] [PASSED] NTSC_443
[06:48:23] [PASSED] NTSC_J
[06:48:23] [PASSED] PAL
[06:48:23] [PASSED] PAL_M
[06:48:23] [PASSED] PAL_N
[06:48:23] [PASSED] SECAM
[06:48:23] [PASSED] MONO_525
[06:48:23] [PASSED] MONO_625
[06:48:23] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:48:23] =============== [PASSED] drm_cmdline_parser ================
[06:48:23] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:48:23] [PASSED] drm_test_connector_hdmi_init_valid
[06:48:23] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:48:23] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:48:23] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:48:23] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:48:23] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:48:23] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:48:23] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:48:23] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:48:23] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:48:23] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:48:23] [PASSED] supported_formats=0x3 yuv420_allowed=1
[06:48:23] [PASSED] supported_formats=0x3 yuv420_allowed=0
[06:48:23] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:48:23] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:48:23] [PASSED] drm_test_connector_hdmi_init_null_product
[06:48:23] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:48:23] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:48:23] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:48:23] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:48:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:48:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:48:23] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:48:23] ========= drm_test_connector_hdmi_init_type_valid =========
[06:48:23] [PASSED] HDMI-A
[06:48:23] [PASSED] HDMI-B
[06:48:23] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:48:23] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:48:23] [PASSED] Unknown
[06:48:23] [PASSED] VGA
[06:48:23] [PASSED] DVI-I
[06:48:23] [PASSED] DVI-D
[06:48:23] [PASSED] DVI-A
[06:48:23] [PASSED] Composite
[06:48:23] [PASSED] SVIDEO
[06:48:23] [PASSED] LVDS
[06:48:23] [PASSED] Component
[06:48:23] [PASSED] DIN
[06:48:23] [PASSED] DP
[06:48:23] [PASSED] TV
[06:48:23] [PASSED] eDP
[06:48:23] [PASSED] Virtual
[06:48:23] [PASSED] DSI
[06:48:23] [PASSED] DPI
[06:48:23] [PASSED] Writeback
[06:48:23] [PASSED] SPI
[06:48:23] [PASSED] USB
[06:48:23] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:48:23] ============ [PASSED] drmm_connector_hdmi_init =============
[06:48:23] ============= drmm_connector_init (3 subtests) =============
[06:48:23] [PASSED] drm_test_drmm_connector_init
[06:48:23] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:48:23] ========= drm_test_drmm_connector_init_type_valid =========
[06:48:23] [PASSED] Unknown
[06:48:23] [PASSED] VGA
[06:48:23] [PASSED] DVI-I
[06:48:23] [PASSED] DVI-D
[06:48:23] [PASSED] DVI-A
[06:48:23] [PASSED] Composite
[06:48:23] [PASSED] SVIDEO
[06:48:23] [PASSED] LVDS
[06:48:23] [PASSED] Component
[06:48:23] [PASSED] DIN
[06:48:23] [PASSED] DP
[06:48:23] [PASSED] HDMI-A
[06:48:23] [PASSED] HDMI-B
[06:48:23] [PASSED] TV
[06:48:23] [PASSED] eDP
[06:48:23] [PASSED] Virtual
[06:48:23] [PASSED] DSI
[06:48:23] [PASSED] DPI
[06:48:23] [PASSED] Writeback
[06:48:23] [PASSED] SPI
[06:48:23] [PASSED] USB
[06:48:23] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:48:23] =============== [PASSED] drmm_connector_init ===============
[06:48:23] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_init
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:48:23] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:48:23] [PASSED] Unknown
[06:48:23] [PASSED] VGA
[06:48:23] [PASSED] DVI-I
[06:48:23] [PASSED] DVI-D
[06:48:23] [PASSED] DVI-A
[06:48:23] [PASSED] Composite
[06:48:23] [PASSED] SVIDEO
[06:48:23] [PASSED] LVDS
[06:48:23] [PASSED] Component
[06:48:23] [PASSED] DIN
[06:48:23] [PASSED] DP
[06:48:23] [PASSED] HDMI-A
[06:48:23] [PASSED] HDMI-B
[06:48:23] [PASSED] TV
[06:48:23] [PASSED] eDP
[06:48:23] [PASSED] Virtual
[06:48:23] [PASSED] DSI
[06:48:23] [PASSED] DPI
[06:48:23] [PASSED] Writeback
[06:48:23] [PASSED] SPI
[06:48:23] [PASSED] USB
[06:48:23] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:48:23] ======== drm_test_drm_connector_dynamic_init_name =========
[06:48:23] [PASSED] Unknown
[06:48:23] [PASSED] VGA
[06:48:23] [PASSED] DVI-I
[06:48:23] [PASSED] DVI-D
[06:48:23] [PASSED] DVI-A
[06:48:23] [PASSED] Composite
[06:48:23] [PASSED] SVIDEO
[06:48:23] [PASSED] LVDS
[06:48:23] [PASSED] Component
[06:48:23] [PASSED] DIN
[06:48:23] [PASSED] DP
[06:48:23] [PASSED] HDMI-A
[06:48:23] [PASSED] HDMI-B
[06:48:23] [PASSED] TV
[06:48:23] [PASSED] eDP
[06:48:23] [PASSED] Virtual
[06:48:23] [PASSED] DSI
[06:48:23] [PASSED] DPI
[06:48:23] [PASSED] Writeback
[06:48:23] [PASSED] SPI
[06:48:23] [PASSED] USB
[06:48:23] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:48:23] =========== [PASSED] drm_connector_dynamic_init ============
[06:48:23] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:48:23] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:48:23] ======= drm_connector_dynamic_register (7 subtests) ========
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:48:23] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:48:23] ========= [PASSED] drm_connector_dynamic_register ==========
[06:48:23] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:48:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:48:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:48:23] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:48:23] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:48:23] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:48:23] [PASSED] NTSC
[06:48:23] [PASSED] NTSC-443
[06:48:23] [PASSED] NTSC-J
[06:48:23] [PASSED] PAL
[06:48:23] [PASSED] PAL-M
[06:48:23] [PASSED] PAL-N
[06:48:23] [PASSED] SECAM
[06:48:23] [PASSED] Mono
[06:48:23] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:48:23] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:48:23] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:48:23] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:48:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:48:23] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:48:23] [PASSED] VIC 96
[06:48:23] [PASSED] VIC 97
[06:48:23] [PASSED] VIC 101
[06:48:23] [PASSED] VIC 102
[06:48:23] [PASSED] VIC 106
[06:48:23] [PASSED] VIC 107
[06:48:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:48:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:48:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:48:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:48:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:48:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:48:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:48:23] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:48:23] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:48:23] [PASSED] Automatic
[06:48:23] [PASSED] Full
[06:48:23] [PASSED] Limited 16:235
[06:48:23] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:48:23] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:48:23] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:48:23] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:48:23] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:48:23] [PASSED] RGB
[06:48:23] [PASSED] YUV 4:2:0
[06:48:23] [PASSED] YUV 4:2:2
[06:48:23] [PASSED] YUV 4:4:4
[06:48:23] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:48:23] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:48:23] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:48:23] ============= drm_damage_helper (21 subtests) ==============
[06:48:23] [PASSED] drm_test_damage_iter_no_damage
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:48:23] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:48:23] [PASSED] drm_test_damage_iter_simple_damage
[06:48:23] [PASSED] drm_test_damage_iter_single_damage
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:48:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:48:23] [PASSED] drm_test_damage_iter_damage
[06:48:23] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:48:23] [PASSED] drm_test_damage_iter_damage_one_outside
[06:48:23] [PASSED] drm_test_damage_iter_damage_src_moved
[06:48:23] [PASSED] drm_test_damage_iter_damage_not_visible
[06:48:23] ================ [PASSED] drm_damage_helper ================
[06:48:23] ============== drm_dp_mst_helper (3 subtests) ==============
[06:48:23] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:48:23] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:48:23] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:48:23] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:48:23] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:48:23] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:48:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:48:23] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:48:23] [PASSED] Link rate 2000000 lane count 4
[06:48:23] [PASSED] Link rate 2000000 lane count 2
[06:48:23] [PASSED] Link rate 2000000 lane count 1
[06:48:23] [PASSED] Link rate 1350000 lane count 4
[06:48:23] [PASSED] Link rate 1350000 lane count 2
[06:48:23] [PASSED] Link rate 1350000 lane count 1
[06:48:23] [PASSED] Link rate 1000000 lane count 4
[06:48:23] [PASSED] Link rate 1000000 lane count 2
[06:48:23] [PASSED] Link rate 1000000 lane count 1
[06:48:23] [PASSED] Link rate 810000 lane count 4
[06:48:23] [PASSED] Link rate 810000 lane count 2
[06:48:23] [PASSED] Link rate 810000 lane count 1
[06:48:23] [PASSED] Link rate 540000 lane count 4
[06:48:23] [PASSED] Link rate 540000 lane count 2
[06:48:23] [PASSED] Link rate 540000 lane count 1
[06:48:23] [PASSED] Link rate 270000 lane count 4
[06:48:23] [PASSED] Link rate 270000 lane count 2
[06:48:23] [PASSED] Link rate 270000 lane count 1
[06:48:23] [PASSED] Link rate 162000 lane count 4
[06:48:23] [PASSED] Link rate 162000 lane count 2
[06:48:23] [PASSED] Link rate 162000 lane count 1
[06:48:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:48:23] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:48:23] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:48:23] [PASSED] DP_POWER_UP_PHY with port number
[06:48:23] [PASSED] DP_POWER_DOWN_PHY with port number
[06:48:23] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:48:23] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:48:23] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:48:23] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:48:23] [PASSED] DP_QUERY_PAYLOAD with port number
[06:48:23] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:48:23] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:48:23] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:48:23] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:48:23] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:48:23] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:48:23] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:48:23] [PASSED] DP_REMOTE_I2C_READ with port number
[06:48:23] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:48:23] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:48:23] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:48:23] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:48:23] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:48:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:48:23] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:48:23] ================ [PASSED] drm_dp_mst_helper ================
[06:48:23] ================== drm_exec (7 subtests) ===================
[06:48:23] [PASSED] sanitycheck
[06:48:23] [PASSED] test_lock
[06:48:23] [PASSED] test_lock_unlock
[06:48:23] [PASSED] test_duplicates
[06:48:23] [PASSED] test_prepare
[06:48:23] [PASSED] test_prepare_array
[06:48:23] [PASSED] test_multiple_loops
[06:48:23] ==================== [PASSED] drm_exec =====================
[06:48:23] =========== drm_format_helper_test (17 subtests) ===========
[06:48:23] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:48:23] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:48:23] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:48:23] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:48:23] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:48:23] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:48:23] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:48:23] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:48:23] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:48:23] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:48:23] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:48:23] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:48:23] ==================== drm_test_fb_swab =====================
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ================ [PASSED] drm_test_fb_swab =================
[06:48:23] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:48:23] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:48:23] [PASSED] single_pixel_source_buffer
[06:48:23] [PASSED] single_pixel_clip_rectangle
[06:48:23] [PASSED] well_known_colors
[06:48:23] [PASSED] destination_pitch
[06:48:23] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:48:23] ================= drm_test_fb_clip_offset =================
[06:48:23] [PASSED] pass through
[06:48:23] [PASSED] horizontal offset
[06:48:23] [PASSED] vertical offset
[06:48:23] [PASSED] horizontal and vertical offset
[06:48:23] [PASSED] horizontal offset (custom pitch)
[06:48:23] [PASSED] vertical offset (custom pitch)
[06:48:23] [PASSED] horizontal and vertical offset (custom pitch)
[06:48:23] ============= [PASSED] drm_test_fb_clip_offset =============
[06:48:23] =================== drm_test_fb_memcpy ====================
[06:48:23] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:48:23] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:48:23] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:48:23] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:48:23] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:48:23] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:48:23] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:48:23] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:48:23] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:48:23] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:48:23] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:48:23] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:48:23] =============== [PASSED] drm_test_fb_memcpy ================
[06:48:23] ============= [PASSED] drm_format_helper_test ==============
[06:48:23] ================= drm_format (18 subtests) =================
[06:48:23] [PASSED] drm_test_format_block_width_invalid
[06:48:23] [PASSED] drm_test_format_block_width_one_plane
[06:48:23] [PASSED] drm_test_format_block_width_two_plane
[06:48:23] [PASSED] drm_test_format_block_width_three_plane
[06:48:23] [PASSED] drm_test_format_block_width_tiled
[06:48:23] [PASSED] drm_test_format_block_height_invalid
[06:48:23] [PASSED] drm_test_format_block_height_one_plane
[06:48:23] [PASSED] drm_test_format_block_height_two_plane
[06:48:23] [PASSED] drm_test_format_block_height_three_plane
[06:48:23] [PASSED] drm_test_format_block_height_tiled
[06:48:23] [PASSED] drm_test_format_min_pitch_invalid
[06:48:23] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:48:23] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:48:23] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:48:23] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:48:23] [PASSED] drm_test_format_min_pitch_two_plane
[06:48:23] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:48:23] [PASSED] drm_test_format_min_pitch_tiled
[06:48:23] =================== [PASSED] drm_format ====================
[06:48:23] ============== drm_framebuffer (10 subtests) ===============
[06:48:23] ========== drm_test_framebuffer_check_src_coords ==========
[06:48:23] [PASSED] Success: source fits into fb
[06:48:23] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:48:23] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:48:23] [PASSED] Fail: overflowing fb with source width
[06:48:23] [PASSED] Fail: overflowing fb with source height
[06:48:23] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:48:23] [PASSED] drm_test_framebuffer_cleanup
[06:48:23] =============== drm_test_framebuffer_create ===============
[06:48:23] [PASSED] ABGR8888 normal sizes
[06:48:23] [PASSED] ABGR8888 max sizes
[06:48:23] [PASSED] ABGR8888 pitch greater than min required
[06:48:23] [PASSED] ABGR8888 pitch less than min required
[06:48:23] [PASSED] ABGR8888 Invalid width
[06:48:23] [PASSED] ABGR8888 Invalid buffer handle
[06:48:23] [PASSED] No pixel format
[06:48:23] [PASSED] ABGR8888 Width 0
[06:48:23] [PASSED] ABGR8888 Height 0
[06:48:23] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:48:23] [PASSED] ABGR8888 Large buffer offset
[06:48:23] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:48:23] [PASSED] ABGR8888 Invalid flag
[06:48:23] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:48:23] [PASSED] ABGR8888 Valid buffer modifier
[06:48:23] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:48:23] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] NV12 Normal sizes
[06:48:23] [PASSED] NV12 Max sizes
[06:48:23] [PASSED] NV12 Invalid pitch
[06:48:23] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:48:23] [PASSED] NV12 different modifier per-plane
[06:48:23] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:48:23] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] NV12 Modifier for inexistent plane
[06:48:23] [PASSED] NV12 Handle for inexistent plane
[06:48:23] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:48:23] [PASSED] YVU420 Normal sizes
[06:48:23] [PASSED] YVU420 Max sizes
[06:48:23] [PASSED] YVU420 Invalid pitch
[06:48:23] [PASSED] YVU420 Different pitches
[06:48:23] [PASSED] YVU420 Different buffer offsets/pitches
[06:48:23] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:48:23] [PASSED] YVU420 Valid modifier
[06:48:23] [PASSED] YVU420 Different modifiers per plane
[06:48:23] [PASSED] YVU420 Modifier for inexistent plane
[06:48:23] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:48:23] [PASSED] X0L2 Normal sizes
[06:48:23] [PASSED] X0L2 Max sizes
[06:48:23] [PASSED] X0L2 Invalid pitch
[06:48:23] [PASSED] X0L2 Pitch greater than minimum required
[06:48:23] [PASSED] X0L2 Handle for inexistent plane
[06:48:23] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:48:23] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:48:23] [PASSED] X0L2 Valid modifier
[06:48:23] [PASSED] X0L2 Modifier for inexistent plane
[06:48:23] =========== [PASSED] drm_test_framebuffer_create ===========
[06:48:23] [PASSED] drm_test_framebuffer_free
[06:48:23] [PASSED] drm_test_framebuffer_init
[06:48:23] [PASSED] drm_test_framebuffer_init_bad_format
[06:48:23] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:48:23] [PASSED] drm_test_framebuffer_lookup
[06:48:23] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:48:23] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:48:23] ================= [PASSED] drm_framebuffer =================
[06:48:23] ================ drm_gem_shmem (8 subtests) ================
[06:48:23] [PASSED] drm_gem_shmem_test_obj_create
[06:48:23] [PASSED] drm_gem_shmem_test_obj_create_private
[06:48:23] [PASSED] drm_gem_shmem_test_pin_pages
[06:48:23] [PASSED] drm_gem_shmem_test_vmap
[06:48:23] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:48:23] [PASSED] drm_gem_shmem_test_get_sg_table
[06:48:23] [PASSED] drm_gem_shmem_test_madvise
[06:48:23] [PASSED] drm_gem_shmem_test_purge
[06:48:23] ================== [PASSED] drm_gem_shmem ==================
[06:48:23] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:48:23] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:48:23] [PASSED] Automatic
[06:48:23] [PASSED] Full
[06:48:23] [PASSED] Limited 16:235
[06:48:23] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:48:23] [PASSED] drm_test_check_disable_connector
[06:48:23] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:48:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:48:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:48:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:48:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:48:23] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:48:23] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:48:23] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:48:23] [PASSED] drm_test_check_output_bpc_dvi
[06:48:23] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:48:23] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:48:23] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:48:23] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:48:23] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:48:23] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:48:23] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:48:23] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:48:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:48:23] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:48:23] [PASSED] drm_test_check_broadcast_rgb_value
[06:48:23] [PASSED] drm_test_check_bpc_8_value
[06:48:23] [PASSED] drm_test_check_bpc_10_value
[06:48:23] [PASSED] drm_test_check_bpc_12_value
[06:48:23] [PASSED] drm_test_check_format_value
[06:48:23] [PASSED] drm_test_check_tmds_char_value
[06:48:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:48:23] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:48:23] [PASSED] drm_test_check_mode_valid
[06:48:23] [PASSED] drm_test_check_mode_valid_reject
[06:48:23] [PASSED] drm_test_check_mode_valid_reject_rate
[06:48:23] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:48:23] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:48:23] ================= drm_managed (2 subtests) =================
[06:48:23] [PASSED] drm_test_managed_release_action
[06:48:23] [PASSED] drm_test_managed_run_action
[06:48:23] =================== [PASSED] drm_managed ===================
[06:48:23] =================== drm_mm (6 subtests) ====================
[06:48:23] [PASSED] drm_test_mm_init
[06:48:23] [PASSED] drm_test_mm_debug
[06:48:23] [PASSED] drm_test_mm_align32
[06:48:23] [PASSED] drm_test_mm_align64
[06:48:23] [PASSED] drm_test_mm_lowest
[06:48:23] [PASSED] drm_test_mm_highest
[06:48:23] ===================== [PASSED] drm_mm ======================
[06:48:23] ============= drm_modes_analog_tv (5 subtests) =============
[06:48:23] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:48:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:48:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:48:23] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:48:23] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:48:23] =============== [PASSED] drm_modes_analog_tv ===============
[06:48:23] ============== drm_plane_helper (2 subtests) ===============
[06:48:23] =============== drm_test_check_plane_state ================
[06:48:23] [PASSED] clipping_simple
[06:48:23] [PASSED] clipping_rotate_reflect
[06:48:23] [PASSED] positioning_simple
[06:48:23] [PASSED] upscaling
[06:48:23] [PASSED] downscaling
[06:48:23] [PASSED] rounding1
[06:48:23] [PASSED] rounding2
[06:48:23] [PASSED] rounding3
[06:48:23] [PASSED] rounding4
[06:48:23] =========== [PASSED] drm_test_check_plane_state ============
[06:48:23] =========== drm_test_check_invalid_plane_state ============
[06:48:23] [PASSED] positioning_invalid
[06:48:23] [PASSED] upscaling_invalid
[06:48:23] [PASSED] downscaling_invalid
[06:48:23] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:48:23] ================ [PASSED] drm_plane_helper =================
[06:48:23] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:48:23] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:48:23] [PASSED] None
[06:48:23] [PASSED] PAL
[06:48:23] [PASSED] NTSC
[06:48:23] [PASSED] Both, NTSC Default
[06:48:23] [PASSED] Both, PAL Default
[06:48:23] [PASSED] Both, NTSC Default, with PAL on command-line
[06:48:23] [PASSED] Both, PAL Default, with NTSC on command-line
[06:48:23] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:48:23] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:48:23] ================== drm_rect (9 subtests) ===================
[06:48:23] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:48:23] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:48:23] [PASSED] drm_test_rect_clip_scaled_clipped
[06:48:23] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:48:23] ================= drm_test_rect_intersect =================
[06:48:23] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:48:23] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:48:23] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:48:23] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:48:23] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:48:23] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:48:23] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:48:23] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:48:23] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:48:23] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:48:23] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:48:23] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:48:23] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:48:23] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:48:23] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:48:23] ============= [PASSED] drm_test_rect_intersect =============
[06:48:23] ================ drm_test_rect_calc_hscale ================
[06:48:23] [PASSED] normal use
[06:48:23] [PASSED] out of max range
[06:48:23] [PASSED] out of min range
[06:48:23] [PASSED] zero dst
[06:48:23] [PASSED] negative src
[06:48:23] [PASSED] negative dst
[06:48:23] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:48:23] ================ drm_test_rect_calc_vscale ================
[06:48:23] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[06:48:23] [PASSED] out of max range
[06:48:23] [PASSED] out of min range
[06:48:23] [PASSED] zero dst
[06:48:23] [PASSED] negative src
[06:48:23] [PASSED] negative dst
[06:48:23] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:48:23] ================== drm_test_rect_rotate ===================
[06:48:23] [PASSED] reflect-x
[06:48:23] [PASSED] reflect-y
[06:48:23] [PASSED] rotate-0
[06:48:23] [PASSED] rotate-90
[06:48:23] [PASSED] rotate-180
[06:48:23] [PASSED] rotate-270
[06:48:23] ============== [PASSED] drm_test_rect_rotate ===============
[06:48:23] ================ drm_test_rect_rotate_inv =================
[06:48:23] [PASSED] reflect-x
[06:48:23] [PASSED] reflect-y
[06:48:23] [PASSED] rotate-0
[06:48:23] [PASSED] rotate-90
[06:48:23] [PASSED] rotate-180
[06:48:23] [PASSED] rotate-270
[06:48:23] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:48:23] ==================== [PASSED] drm_rect =====================
[06:48:23] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:48:23] ============ drm_test_sysfb_build_fourcc_list =============
[06:48:23] [PASSED] no native formats
[06:48:23] [PASSED] XRGB8888 as native format
[06:48:23] [PASSED] remove duplicates
[06:48:23] [PASSED] convert alpha formats
[06:48:23] [PASSED] random formats
[06:48:23] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:48:23] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:48:23] ================== drm_fixp (2 subtests) ===================
[06:48:23] [PASSED] drm_test_int2fixp
[06:48:23] [PASSED] drm_test_sm2fixp
[06:48:23] ==================== [PASSED] drm_fixp =====================
[06:48:23] ============================================================
[06:48:23] Testing complete. Ran 624 tests: passed: 624
[06:48:23] Elapsed time: 27.291s total, 1.665s configuring, 25.202s building, 0.393s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:48:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:48:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:48:34] Starting KUnit Kernel (1/1)...
[06:48:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:48:34] ================= ttm_device (5 subtests) ==================
[06:48:34] [PASSED] ttm_device_init_basic
[06:48:34] [PASSED] ttm_device_init_multiple
[06:48:34] [PASSED] ttm_device_fini_basic
[06:48:34] [PASSED] ttm_device_init_no_vma_man
[06:48:34] ================== ttm_device_init_pools ==================
[06:48:34] [PASSED] No DMA allocations, no DMA32 required
[06:48:34] [PASSED] DMA allocations, DMA32 required
[06:48:34] [PASSED] No DMA allocations, DMA32 required
[06:48:34] [PASSED] DMA allocations, no DMA32 required
[06:48:34] ============== [PASSED] ttm_device_init_pools ==============
[06:48:34] =================== [PASSED] ttm_device ====================
[06:48:34] ================== ttm_pool (8 subtests) ===================
[06:48:34] ================== ttm_pool_alloc_basic ===================
[06:48:34] [PASSED] One page
[06:48:34] [PASSED] More than one page
[06:48:34] [PASSED] Above the allocation limit
[06:48:34] [PASSED] One page, with coherent DMA mappings enabled
[06:48:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:48:34] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:48:34] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:48:34] [PASSED] One page
[06:48:34] [PASSED] More than one page
[06:48:34] [PASSED] Above the allocation limit
[06:48:34] [PASSED] One page, with coherent DMA mappings enabled
[06:48:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:48:34] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:48:34] [PASSED] ttm_pool_alloc_order_caching_match
[06:48:34] [PASSED] ttm_pool_alloc_caching_mismatch
[06:48:34] [PASSED] ttm_pool_alloc_order_mismatch
[06:48:34] [PASSED] ttm_pool_free_dma_alloc
[06:48:34] [PASSED] ttm_pool_free_no_dma_alloc
[06:48:34] [PASSED] ttm_pool_fini_basic
[06:48:34] ==================== [PASSED] ttm_pool =====================
[06:48:34] ================ ttm_resource (8 subtests) =================
[06:48:34] ================= ttm_resource_init_basic =================
[06:48:34] [PASSED] Init resource in TTM_PL_SYSTEM
[06:48:34] [PASSED] Init resource in TTM_PL_VRAM
[06:48:34] [PASSED] Init resource in a private placement
[06:48:34] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:48:34] ============= [PASSED] ttm_resource_init_basic =============
[06:48:34] [PASSED] ttm_resource_init_pinned
[06:48:34] [PASSED] ttm_resource_fini_basic
[06:48:34] [PASSED] ttm_resource_manager_init_basic
[06:48:34] [PASSED] ttm_resource_manager_usage_basic
[06:48:34] [PASSED] ttm_resource_manager_set_used_basic
[06:48:34] [PASSED] ttm_sys_man_alloc_basic
[06:48:34] [PASSED] ttm_sys_man_free_basic
[06:48:34] ================== [PASSED] ttm_resource ===================
[06:48:34] =================== ttm_tt (15 subtests) ===================
[06:48:34] ==================== ttm_tt_init_basic ====================
[06:48:34] [PASSED] Page-aligned size
[06:48:34] [PASSED] Extra pages requested
[06:48:34] ================ [PASSED] ttm_tt_init_basic ================
[06:48:34] [PASSED] ttm_tt_init_misaligned
[06:48:34] [PASSED] ttm_tt_fini_basic
[06:48:34] [PASSED] ttm_tt_fini_sg
[06:48:34] [PASSED] ttm_tt_fini_shmem
[06:48:34] [PASSED] ttm_tt_create_basic
[06:48:34] [PASSED] ttm_tt_create_invalid_bo_type
[06:48:34] [PASSED] ttm_tt_create_ttm_exists
[06:48:34] [PASSED] ttm_tt_create_failed
[06:48:34] [PASSED] ttm_tt_destroy_basic
[06:48:34] [PASSED] ttm_tt_populate_null_ttm
[06:48:34] [PASSED] ttm_tt_populate_populated_ttm
[06:48:34] [PASSED] ttm_tt_unpopulate_basic
[06:48:34] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:48:34] [PASSED] ttm_tt_swapin_basic
[06:48:34] ===================== [PASSED] ttm_tt ======================
[06:48:34] =================== ttm_bo (14 subtests) ===================
[06:48:34] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:48:34] [PASSED] Cannot be interrupted and sleeps
[06:48:34] [PASSED] Cannot be interrupted, locks straight away
[06:48:34] [PASSED] Can be interrupted, sleeps
[06:48:34] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:48:34] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:48:34] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:48:34] [PASSED] ttm_bo_reserve_double_resv
[06:48:34] [PASSED] ttm_bo_reserve_interrupted
[06:48:34] [PASSED] ttm_bo_reserve_deadlock
[06:48:34] [PASSED] ttm_bo_unreserve_basic
[06:48:34] [PASSED] ttm_bo_unreserve_pinned
[06:48:34] [PASSED] ttm_bo_unreserve_bulk
[06:48:34] [PASSED] ttm_bo_fini_basic
[06:48:34] [PASSED] ttm_bo_fini_shared_resv
[06:48:34] [PASSED] ttm_bo_pin_basic
[06:48:34] [PASSED] ttm_bo_pin_unpin_resource
[06:48:34] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:48:34] ===================== [PASSED] ttm_bo ======================
[06:48:34] ============== ttm_bo_validate (21 subtests) ===============
[06:48:34] ============== ttm_bo_init_reserved_sys_man ===============
[06:48:34] [PASSED] Buffer object for userspace
[06:48:34] [PASSED] Kernel buffer object
[06:48:34] [PASSED] Shared buffer object
[06:48:34] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:48:34] ============== ttm_bo_init_reserved_mock_man ==============
[06:48:34] [PASSED] Buffer object for userspace
[06:48:34] [PASSED] Kernel buffer object
[06:48:34] [PASSED] Shared buffer object
[06:48:34] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:48:34] [PASSED] ttm_bo_init_reserved_resv
[06:48:34] ================== ttm_bo_validate_basic ==================
[06:48:34] [PASSED] Buffer object for userspace
[06:48:34] [PASSED] Kernel buffer object
[06:48:34] [PASSED] Shared buffer object
[06:48:34] ============== [PASSED] ttm_bo_validate_basic ==============
[06:48:34] [PASSED] ttm_bo_validate_invalid_placement
[06:48:34] ============= ttm_bo_validate_same_placement ==============
[06:48:34] [PASSED] System manager
[06:48:34] [PASSED] VRAM manager
[06:48:34] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:48:34] [PASSED] ttm_bo_validate_failed_alloc
[06:48:34] [PASSED] ttm_bo_validate_pinned
[06:48:34] [PASSED] ttm_bo_validate_busy_placement
[06:48:34] ================ ttm_bo_validate_multihop =================
[06:48:34] [PASSED] Buffer object for userspace
[06:48:34] [PASSED] Kernel buffer object
[06:48:34] [PASSED] Shared buffer object
[06:48:34] ============ [PASSED] ttm_bo_validate_multihop =============
[06:48:34] ========== ttm_bo_validate_no_placement_signaled ==========
[06:48:34] [PASSED] Buffer object in system domain, no page vector
[06:48:34] [PASSED] Buffer object in system domain with an existing page vector
[06:48:34] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:48:34] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:48:34] [PASSED] Buffer object for userspace
[06:48:34] [PASSED] Kernel buffer object
[06:48:34] [PASSED] Shared buffer object
[06:48:34] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:48:34] [PASSED] ttm_bo_validate_move_fence_signaled
[06:48:34] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:48:34] [PASSED] Waits for GPU
[06:48:34] [PASSED] Tries to lock straight away
[06:48:34] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:48:34] [PASSED] ttm_bo_validate_happy_evict
[06:48:34] [PASSED] ttm_bo_validate_all_pinned_evict
[06:48:34] [PASSED] ttm_bo_validate_allowed_only_evict
[06:48:34] [PASSED] ttm_bo_validate_deleted_evict
[06:48:34] [PASSED] ttm_bo_validate_busy_domain_evict
[06:48:34] [PASSED] ttm_bo_validate_evict_gutting
[06:48:34] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:48:34] ================= [PASSED] ttm_bo_validate =================
[06:48:34] ============================================================
[06:48:34] Testing complete. Ran 101 tests: passed: 101
[06:48:34] Elapsed time: 11.277s total, 1.696s configuring, 9.366s building, 0.186s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ CI.checksparse: warning for Plane Color Pipeline support for Intel platforms (rev6)
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (16 preceding siblings ...)
2025-12-01 6:48 ` ✓ CI.KUnit: success " Patchwork
@ 2025-12-01 7:03 ` Patchwork
2025-12-01 7:50 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-01 8:41 ` ✗ Xe.CI.Full: failure " Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2025-12-01 7:03 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev6)
URL : https://patchwork.freedesktop.org/series/141788/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 9fcf9189976d387cb9199155c35dd6c826268c52
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2081:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2094:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2094:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2094:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 44+ messages in thread* ✓ Xe.CI.BAT: success for Plane Color Pipeline support for Intel platforms (rev6)
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (17 preceding siblings ...)
2025-12-01 7:03 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-12-01 7:50 ` Patchwork
2025-12-01 8:41 ` ✗ Xe.CI.Full: failure " Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2025-12-01 7:50 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1872 bytes --]
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev6)
URL : https://patchwork.freedesktop.org/series/141788/
State : success
== Summary ==
CI Bug Log - changes from xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52_BAT -> xe-pw-141788v6_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-141788v6_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_waitfence@abstime:
- bat-dg2-oem2: [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/bat-dg2-oem2/igt@xe_waitfence@abstime.html
#### Possible fixes ####
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [FAIL][3] ([Intel XE#6519]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/bat-dg2-oem2/igt@xe_waitfence@engine.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/bat-dg2-oem2/igt@xe_waitfence@engine.html
[Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
Build changes
-------------
* Linux: xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52 -> xe-pw-141788v6
IGT_8645: 8645
xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52: 9fcf9189976d387cb9199155c35dd6c826268c52
xe-pw-141788v6: 141788v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/index.html
[-- Attachment #2: Type: text/html, Size: 2459 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Xe.CI.Full: failure for Plane Color Pipeline support for Intel platforms (rev6)
2025-12-01 6:46 [v7 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (18 preceding siblings ...)
2025-12-01 7:50 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-12-01 8:41 ` Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2025-12-01 8:41 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 57137 bytes --]
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev6)
URL : https://patchwork.freedesktop.org/series/141788/
State : failure
== Summary ==
CI Bug Log - changes from xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52_FULL -> xe-pw-141788v6_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-141788v6_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-141788v6_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-141788v6_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_edge_walk@256x256-top-edge:
- shard-bmg: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_cursor_edge_walk@256x256-top-edge.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-edge.html
* igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-hdmi-a-3.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-new-prefetch:
- shard-bmg: NOTRUN -> [SKIP][4] +35 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-new-prefetch.html
* igt@xe_exec_threads@threads-hang-fd-userptr:
- shard-bmg: [PASS][5] -> [SKIP][6] +4 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_exec_threads@threads-hang-fd-userptr.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_exec_threads@threads-hang-fd-userptr.html
* igt@xe_noexec_ping_pong@basic:
- shard-bmg: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_noexec_ping_pong@basic.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_noexec_ping_pong@basic.html
#### Warnings ####
* igt@kms_content_protection@dp-mst-suspend-resume:
- shard-bmg: [SKIP][9] ([Intel XE#6692]) -> [SKIP][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_content_protection@dp-mst-suspend-resume.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_content_protection@dp-mst-suspend-resume.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][11] ([Intel XE#4141]) -> [SKIP][12] +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][13] ([Intel XE#2311]) -> [SKIP][14]
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-bmg: [SKIP][15] ([Intel XE#2313]) -> [SKIP][16] +2 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@xe_eudebug@discovery-race-vmbind:
- shard-bmg: [SKIP][17] ([Intel XE#4837]) -> [SKIP][18]
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_eudebug@discovery-race-vmbind.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_eudebug@discovery-race-vmbind.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-bmg: [ABORT][19] ([Intel XE#6675]) -> [SKIP][20]
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_pm@s3-vm-bind-unbind-all.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-bmg: [SKIP][21] ([Intel XE#944]) -> [SKIP][22]
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_query@multigpu-query-invalid-extension.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_query@multigpu-query-invalid-extension.html
New tests
---------
New tests have been introduced between xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52_FULL and xe-pw-141788v6_FULL:
### New IGT tests (26) ###
* igt@kms_color@deep-color@pipe-a-dp-2-ctm:
- Statuses : 1 pass(s)
- Exec time: [4.76] s
* igt@kms_color@deep-color@pipe-a-dp-2-degamma:
- Statuses : 1 pass(s)
- Exec time: [4.73] s
* igt@kms_color@deep-color@pipe-a-dp-2-gamma:
- Statuses : 1 pass(s)
- Exec time: [4.73] s
* igt@kms_color@deep-color@pipe-b-dp-2-ctm:
- Statuses : 1 pass(s)
- Exec time: [4.76] s
* igt@kms_color@deep-color@pipe-b-dp-2-degamma:
- Statuses : 1 pass(s)
- Exec time: [4.75] s
* igt@kms_color@deep-color@pipe-b-dp-2-gamma:
- Statuses : 1 pass(s)
- Exec time: [4.75] s
* igt@kms_color@deep-color@pipe-c-dp-2-ctm:
- Statuses : 1 pass(s)
- Exec time: [4.73] s
* igt@kms_color@deep-color@pipe-c-dp-2-degamma:
- Statuses : 1 pass(s)
- Exec time: [4.75] s
* igt@kms_color@deep-color@pipe-c-dp-2-gamma:
- Statuses : 1 pass(s)
- Exec time: [4.75] s
* igt@kms_color@deep-color@pipe-d-dp-2-ctm:
- Statuses : 1 pass(s)
- Exec time: [4.74] s
* igt@kms_color@deep-color@pipe-d-dp-2-degamma:
- Statuses : 1 pass(s)
- Exec time: [4.74] s
* igt@kms_color@deep-color@pipe-d-dp-2-gamma:
- Statuses : 1 pass(s)
- Exec time: [4.75] s
* igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [2.69] s
* igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [2.50] s
* igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.75] s
* igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.73] s
* igt@kms_pm_rpm@legacy-planes-dpms@plane-123:
- Statuses : 1 pass(s)
- Exec time: [7.87] s
* igt@kms_pm_rpm@legacy-planes-dpms@plane-133:
- Statuses : 1 pass(s)
- Exec time: [7.87] s
* igt@kms_pm_rpm@legacy-planes@plane-123:
- Statuses : 4 pass(s)
- Exec time: [2.63, 12.72] s
* igt@kms_pm_rpm@legacy-planes@plane-133:
- Statuses : 4 pass(s)
- Exec time: [2.58, 12.71] s
* igt@kms_pm_rpm@universal-planes-dpms@plane-123:
- Statuses : 3 pass(s)
- Exec time: [4.42, 12.03] s
* igt@kms_pm_rpm@universal-planes-dpms@plane-133:
- Statuses : 3 pass(s)
- Exec time: [5.83, 12.03] s
* igt@kms_pm_rpm@universal-planes-dpms@plane-143:
- Statuses : 3 pass(s)
- Exec time: [4.50, 12.02] s
* igt@kms_pm_rpm@universal-planes@plane-123:
- Statuses : 1 pass(s)
- Exec time: [12.84] s
* igt@kms_pm_rpm@universal-planes@plane-133:
- Statuses : 1 pass(s)
- Exec time: [12.84] s
* igt@kms_pm_rpm@universal-planes@plane-143:
- Statuses : 1 pass(s)
- Exec time: [12.12] s
Known issues
------------
Here are the changes found in xe-pw-141788v6_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [DMESG-WARN][23] ([Intel XE#4543]) +2 other tests dmesg-warn
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic:
- shard-adlp: [PASS][24] -> [DMESG-WARN][25] ([Intel XE#2953] / [Intel XE#4173])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-9/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-8/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1407]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: NOTRUN -> [SKIP][27] ([Intel XE#1124]) +6 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][28] ([Intel XE#316]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_bw@linear-tiling-3-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][29] ([Intel XE#367])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#1512])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#2887]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][32] ([Intel XE#787]) +8 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][33] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#3442])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#3432])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_cdclk@mode-transition:
- shard-adlp: NOTRUN -> [SKIP][36] ([Intel XE#4417] / [Intel XE#455])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#4417]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_cdclk@mode-transition@pipe-a-hdmi-a-1.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-adlp: NOTRUN -> [SKIP][38] ([Intel XE#306])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@ctm-max:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#306])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
- shard-adlp: NOTRUN -> [SKIP][40] ([Intel XE#373]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#373])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#6704]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc.html
* igt@kms_colorop@plane-xr24-xr24-pq_125_eotf-pq_125_inv_eotf-pq_125_eotf:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#6704]) +2 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-1/igt@kms_colorop@plane-xr24-xr24-pq_125_eotf-pq_125_inv_eotf-pq_125_eotf.html
* igt@kms_content_protection@atomic@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][44] ([Intel XE#1178])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_content_protection@atomic@pipe-a-dp-2.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-adlp: NOTRUN -> [SKIP][45] ([Intel XE#307])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#1424])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#309]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-bmg: [PASS][48] -> [SKIP][49] ([Intel XE#2291]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#309])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-adlp: NOTRUN -> [SKIP][51] ([Intel XE#455]) +3 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-adlp: NOTRUN -> [SKIP][52] ([Intel XE#3009])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-2/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#2244])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_feature_discovery@display-2x:
- shard-adlp: NOTRUN -> [SKIP][54] ([Intel XE#702])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#1421])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-adlp: NOTRUN -> [SKIP][56] ([Intel XE#310]) +4 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [PASS][57] -> [SKIP][58] ([Intel XE#2316]) +7 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@blocking-wf_vblank@b-dp2:
- shard-bmg: [PASS][59] -> [FAIL][60] ([Intel XE#5338] / [Intel XE#6266])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-8/igt@kms_flip@blocking-wf_vblank@b-dp2.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-4/igt@kms_flip@blocking-wf_vblank@b-dp2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-lnl: [PASS][61] -> [FAIL][62] ([Intel XE#5337] / [Intel XE#6266]) +1 other test fail
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-3/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-4/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#1397] / [Intel XE#1745])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#1397])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#1401] / [Intel XE#1745])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1401])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#651])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][68] ([Intel XE#656]) +12 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#651])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#651]) +5 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-adlp: NOTRUN -> [SKIP][71] ([Intel XE#653]) +4 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][72] ([Intel XE#656]) +2 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-bmg: [PASS][73] -> [ABORT][74] ([Intel XE#6662]) +1 other test abort
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-4/igt@kms_hdr@bpc-switch-dpms.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-lnl: [PASS][75] -> [ABORT][76] ([Intel XE#6675]) +1 other test abort
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-7/igt@kms_hdr@bpc-switch-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [ABORT][77] ([Intel XE#6675]) +1 other test abort
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3.html
* igt@kms_hdr@brightness-with-hdr:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#3374] / [Intel XE#3544])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-toggle-suspend:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#1503])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-adlp: NOTRUN -> [SKIP][80] ([Intel XE#2925] / [Intel XE#2927])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#2925])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-adlp: NOTRUN -> [SKIP][82] ([Intel XE#4596])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@tiling-4:
- shard-adlp: NOTRUN -> [SKIP][83] ([Intel XE#5020])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_plane_multiple@tiling-4.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-adlp: NOTRUN -> [SKIP][84] ([Intel XE#836])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-2/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#1406] / [Intel XE#2893])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
- shard-adlp: NOTRUN -> [SKIP][86] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-lnl: NOTRUN -> [SKIP][87] ([Intel XE#1128] / [Intel XE#1406])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-lnl: NOTRUN -> [SKIP][88] ([Intel XE#1406])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@psr-sprite-plane-onoff:
- shard-adlp: NOTRUN -> [SKIP][89] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +6 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-lnl: NOTRUN -> [SKIP][90] ([Intel XE#3414] / [Intel XE#3904])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-lnl: [PASS][91] -> [FAIL][92] ([Intel XE#6361]) +2 other tests fail
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-8/igt@kms_setmode@basic@pipe-b-edp-1.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@kms_tv_load_detect@load-detect:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#330])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [PASS][94] -> [SKIP][95] ([Intel XE#1499])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-7/igt@kms_vrr@negative-basic.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@kms_vrr@negative-basic.html
* igt@xe_ccs@large-ctrl-surf-copy:
- shard-adlp: NOTRUN -> [SKIP][96] ([Intel XE#3576] / [Intel XE#5610])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_ccs@large-ctrl-surf-copy.html
* igt@xe_compute_preempt@compute-preempt-many-vram:
- shard-lnl: NOTRUN -> [SKIP][97] ([Intel XE#5191])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@xe_compute_preempt@compute-preempt-many-vram.html
* igt@xe_copy_basic@mem-set-linear-0x3fff:
- shard-adlp: NOTRUN -> [SKIP][98] ([Intel XE#1126]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_copy_basic@mem-set-linear-0x3fff.html
* igt@xe_eu_stall@unprivileged-access:
- shard-adlp: NOTRUN -> [SKIP][99] ([Intel XE#5626])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_eu_stall@unprivileged-access.html
* igt@xe_eudebug@basic-read-event:
- shard-adlp: NOTRUN -> [SKIP][100] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@xe_eudebug@basic-read-event.html
* igt@xe_eudebug_online@pagefault-read:
- shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#4837]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@xe_eudebug_online@pagefault-read.html
* igt@xe_evict@evict-beng-large-multi-vm-cm:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#688])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@xe_evict@evict-beng-large-multi-vm-cm.html
* igt@xe_evict@evict-beng-threads-small:
- shard-adlp: NOTRUN -> [SKIP][103] ([Intel XE#261])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_evict@evict-beng-threads-small.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [PASS][104] -> [INCOMPLETE][105] ([Intel XE#6321] / [Intel XE#6606])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_evict@evict-small-cm:
- shard-adlp: NOTRUN -> [SKIP][106] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +1 other test skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@xe_evict@evict-small-cm.html
* igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd:
- shard-adlp: NOTRUN -> [SKIP][107] ([Intel XE#688])
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][108] ([Intel XE#1392]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
- shard-adlp: NOTRUN -> [SKIP][109] ([Intel XE#1392] / [Intel XE#5575]) +5 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
- shard-adlp: NOTRUN -> [SKIP][110] ([Intel XE#288] / [Intel XE#5561]) +12 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html
* igt@xe_exec_reset@cm-close-fd:
- shard-adlp: [PASS][111] -> [DMESG-WARN][112] ([Intel XE#3868])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-1/igt@xe_exec_reset@cm-close-fd.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-3/igt@xe_exec_reset@cm-close-fd.html
* igt@xe_exec_system_allocator@once-mmap-new-nomemset:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#6703])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_exec_system_allocator@once-mmap-new-nomemset.html
* igt@xe_exec_system_allocator@process-many-large-mmap-remap-ro-dontunmap-eocheck:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#4915]) +113 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_exec_system_allocator@process-many-large-mmap-remap-ro-dontunmap-eocheck.html
* igt@xe_exec_system_allocator@process-many-mmap-file-mlock-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#4915]) +2 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-434/igt@xe_exec_system_allocator@process-many-mmap-file-mlock-nomemset.html
* igt@xe_exec_system_allocator@process-many-stride-mmap-shared-remap-dontunmap:
- shard-bmg: [PASS][116] -> [SKIP][117] ([Intel XE#6557])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@xe_exec_system_allocator@process-many-stride-mmap-shared-remap-dontunmap.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_exec_system_allocator@process-many-stride-mmap-shared-remap-dontunmap.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#4943]) +2 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-busy:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#6557]) +3 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-busy.html
* igt@xe_oa@rc6-disable:
- shard-adlp: NOTRUN -> [SKIP][120] ([Intel XE#3573]) +3 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_oa@rc6-disable.html
* igt@xe_pm@s2idle-basic:
- shard-dg2-set2: NOTRUN -> [ABORT][121] ([Intel XE#6675])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-434/igt@xe_pm@s2idle-basic.html
* igt@xe_pm@s2idle-basic-exec:
- shard-adlp: [PASS][122] -> [ABORT][123] ([Intel XE#6675]) +4 other tests abort
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-2/igt@xe_pm@s2idle-basic-exec.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_pm@s2idle-basic-exec.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-lnl: NOTRUN -> [SKIP][124] ([Intel XE#2284] / [Intel XE#366])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [PASS][125] -> [ABORT][126] ([Intel XE#6675])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-dg2-432/igt@xe_pm@s3-vm-bind-unbind-all.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-464/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pm@s4-multiple-execs:
- shard-bmg: [PASS][127] -> [ABORT][128] ([Intel XE#6675])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@xe_pm@s4-multiple-execs.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@xe_pm@s4-multiple-execs.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-adlp: NOTRUN -> [ABORT][129] ([Intel XE#6675])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-1/igt@xe_pm@s4-vm-bind-prefetch.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-lnl: NOTRUN -> [ABORT][130] ([Intel XE#6675])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-7/igt@xe_pm@s4-vm-bind-unbind-all.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0:
- shard-lnl: [PASS][131] -> [FAIL][132] ([Intel XE#6251])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-adlp: NOTRUN -> [SKIP][133] ([Intel XE#944]) +1 other test skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-6/igt@xe_query@multigpu-query-invalid-size.html
* igt@xe_sriov_vram@vf-access-after-resize-down:
- shard-adlp: NOTRUN -> [SKIP][134] ([Intel XE#6376])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-2/igt@xe_sriov_vram@vf-access-after-resize-down.html
#### Possible fixes ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-adlp: [FAIL][135] ([Intel XE#1231]) -> [PASS][136] +1 other test pass
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: [SKIP][137] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][139] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][140] +1 other test pass
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-bmg: [SKIP][141] ([Intel XE#2291]) -> [PASS][142] +1 other test pass
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-6/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-bmg: [SKIP][143] ([Intel XE#2316]) -> [PASS][144] +2 other tests pass
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_flip@2x-plain-flip-interruptible.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_force_connector_basic@force-connector-state:
- shard-adlp: [DMESG-WARN][145] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-9/igt@kms_force_connector_basic@force-connector-state.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-8/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_setmode@basic@pipe-a-dp-4:
- shard-dg2-set2: [FAIL][147] ([Intel XE#6361]) -> [PASS][148] +1 other test pass
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-dg2-432/igt@kms_setmode@basic@pipe-a-dp-4.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-432/igt@kms_setmode@basic@pipe-a-dp-4.html
* igt@xe_pm@s2idle-exec-after:
- shard-lnl: [ABORT][149] ([Intel XE#6675]) -> [PASS][150] +1 other test pass
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-2/igt@xe_pm@s2idle-exec-after.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@xe_pm@s2idle-exec-after.html
* igt@xe_pm@s3-multiple-execs:
- shard-adlp: [ABORT][151] ([Intel XE#6675]) -> [PASS][152] +4 other tests pass
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-adlp-2/igt@xe_pm@s3-multiple-execs.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-adlp-9/igt@xe_pm@s3-multiple-execs.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
- shard-lnl: [FAIL][153] ([Intel XE#6251]) -> [PASS][154] +1 other test pass
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
#### Warnings ####
* igt@kms_content_protection@atomic:
- shard-bmg: [SKIP][155] ([Intel XE#2341]) -> [FAIL][156] ([Intel XE#1178])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_content_protection@atomic.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-bmg: [FAIL][157] ([Intel XE#1178]) -> [SKIP][158] ([Intel XE#2341])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_content_protection@legacy.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_content_protection@legacy.html
* igt@kms_flip@blocking-wf_vblank:
- shard-bmg: [FAIL][159] ([Intel XE#5338] / [Intel XE#6266]) -> [FAIL][160] ([Intel XE#3098] / [Intel XE#5338] / [Intel XE#6266])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-8/igt@kms_flip@blocking-wf_vblank.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-4/igt@kms_flip@blocking-wf_vblank.html
* igt@kms_flip@blocking-wf_vblank@a-dp2:
- shard-bmg: [FAIL][161] ([Intel XE#5338] / [Intel XE#6266]) -> [FAIL][162] ([Intel XE#3098])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-8/igt@kms_flip@blocking-wf_vblank@a-dp2.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-4/igt@kms_flip@blocking-wf_vblank@a-dp2.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: [SKIP][163] ([Intel XE#2312]) -> [SKIP][164] ([Intel XE#2311]) +8 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][165] ([Intel XE#2312]) -> [SKIP][166] ([Intel XE#4141]) +2 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][167] ([Intel XE#4141]) -> [SKIP][168] ([Intel XE#2312]) +3 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][169] ([Intel XE#2311]) -> [SKIP][170] ([Intel XE#2312]) +11 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][171] ([Intel XE#2313]) -> [SKIP][172] ([Intel XE#2312]) +7 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-bmg: [SKIP][173] ([Intel XE#2313]) -> [SKIP][174] ([Intel XE#6557])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][175] ([Intel XE#2312]) -> [SKIP][176] ([Intel XE#2313]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][177] ([Intel XE#3544]) -> [SKIP][178] ([Intel XE#3374] / [Intel XE#3544])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: [SKIP][179] ([Intel XE#4596]) -> [SKIP][180] ([Intel XE#5021])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_psr@fbc-pr-basic:
- shard-bmg: [SKIP][181] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][182] ([Intel XE#1406])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-3/igt@kms_psr@fbc-pr-basic.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-2/igt@kms_psr@fbc-pr-basic.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][183] ([Intel XE#2509]) -> [SKIP][184] ([Intel XE#2426])
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2-set2: [SKIP][185] ([Intel XE#362]) -> [SKIP][186] ([Intel XE#1500])
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
[Intel XE#5337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5337
[Intel XE#5338]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5338
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5610
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6606]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6606
[Intel XE#6662]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6662
[Intel XE#6675]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6675
[Intel XE#6692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6692
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6704]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6704
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52 -> xe-pw-141788v6
IGT_8645: 8645
xe-4170-9fcf9189976d387cb9199155c35dd6c826268c52: 9fcf9189976d387cb9199155c35dd6c826268c52
xe-pw-141788v6: 141788v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141788v6/index.html
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