[PATCH v2 00/15] drm/i915/pll: Verify pll dividers and remove redundant .clock member

[PATCH v2 00/15] drm/i915/pll: Verify pll dividers and remove redundant .clock member

[Mika Kahola]

Fix the issues in v1 after further testing, review and issues existing
in the current code revealed by the self-tests added by the patchset
and as such gives a background/rationale for adding all the self-test
infra in the patchset (see last 3 items below).

* Fix determining the encoder mode from the crtc_state vs.
   the intel_encoder_is_dp/hdmi() helpers
* Fix termination of PLL parameter list in the PLL tables
* Move changes in the patchset to the patch they logically belong
* Use a stricter +-1kHz allowance for a difference between the
   computed and requested PLL clock rate
* Drop fixed non-FRL HDMI PLL parameter entries, due to a mismatch
   between the fixed PLL dividers and clock rate for these
* Fix 10x-off FRL HDMI clock rates
* Fix DP2.0 10G and 20G and HDMI FRL clock rate determination
   during PLL enabling

https://lore.kernel.org/intel-gfx/20251216083759.383163-1-mika.kahola@intel.com/

Cc: Imre Deak <imre.deak@intel.com>

Mika Kahola (15):
  drm/i915/c10: Move C10 port clock calculation
  drm/i915/c20: Move C20 port clock calculation
  drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider
    calculation
  drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation
  drm/i915/cx0: Drop encoder from port clock calculation
  drm/i915/cx0: Create macro around pll tables
  drm/i915/lt_phy: Create macro for lt phy pll state
  drm/i915/display: Add helper function for fuzzy clock check
  drm/i915/cx0: Fix HDMI FRL clock rates
  drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during
    programming
  drm/i915/cx0: Verify C10/C20 pll dividers
  drm/i915/lt_phy: Add verification for lt phy pll dividers
  drm/i915/cx0: Drop C20 25.175 MHz rate
  drm/i915/lt_phy: Drop 27.2 MHz rate
  drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 731 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   4 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  11 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 -
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  18 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 242 +++---
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   5 +-
 .../drm/i915/display/intel_snps_hdmi_pll.c    |   2 -
 10 files changed, 549 insertions(+), 472 deletions(-)

-- 
2.34.1

[PATCH v2 01/15] drm/i915/c10: Move C10 port clock calculation

[Mika Kahola]

Prepare removal of .clock member from pll state
structures by moving intel_c10pll_calc_port_clock()
function.

No functional changes.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 54 ++++++++++----------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f6d69627154e..5fb39c114078 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2103,6 +2103,33 @@ static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state)
 	return c20pll_state_is_dp(&pll_state->c20);
 }
 
+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+					const struct intel_c10pll_state *pll_state)
+{
+	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
+	int tmpclk = 0;
+
+	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
+		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
+	}
+
+	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+		      pll_state->pll[2]) / 2 + 16;
+
+	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+
+	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+				     10 << (tx_clk_div + 16));
+	tmpclk *= (hdmi_div ? 2 : 1);
+
+	return tmpclk;
+}
+
 /*
  * TODO: Convert the following to align with intel_c20pll_find_table() and
  * intel_c20pll_calc_state_from_table().
@@ -2166,33 +2193,6 @@ static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state)
-{
-	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
-	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
-	int tmpclk = 0;
-
-	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
-		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
-		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
-		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
-	}
-
-	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
-		      pll_state->pll[2]) / 2 + 16;
-
-	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
-	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
-
-	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
-				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
-				     10 << (tx_clk_div + 16));
-	tmpclk *= (hdmi_div ? 2 : 1);
-
-	return tmpclk;
-}
-
 static int readout_enabled_lane_count(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
-- 
2.34.1

[PATCH v2 02/15] drm/i915/c20: Move C20 port clock calculation

[Mika Kahola]

Prepare removal of .clock member from the pll state
structure by moving intel_c20pll_calc_port_clock()
function.

No functional change.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 100 +++++++++----------
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5fb39c114078..1deb865618b7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2130,6 +2130,56 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 	return tmpclk;
 }
 
+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
+{
+	return state->tx[0] & C20_PHY_USE_MPLLB;
+}
+
+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+					const struct intel_c20pll_state *pll_state)
+{
+	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+	unsigned int multiplier, refclk = 38400;
+	unsigned int tx_clk_div;
+	unsigned int ref_clk_mpllb_div;
+	unsigned int fb_clk_div4_en;
+	unsigned int ref, vco;
+	unsigned int tx_rate_mult;
+	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+	if (intel_c20phy_use_mpllb(pll_state)) {
+		tx_rate_mult = 1;
+		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+		frac_quot = pll_state->mpllb[8];
+		frac_rem =  pll_state->mpllb[9];
+		frac_den =  pll_state->mpllb[7];
+		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+		tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
+		fb_clk_div4_en = 0;
+	} else {
+		tx_rate_mult = 2;
+		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+		frac_quot = pll_state->mplla[8];
+		frac_rem =  pll_state->mplla[9];
+		frac_den =  pll_state->mplla[7];
+		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+		tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
+		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
+	}
+
+	if (frac_en)
+		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+	else
+		frac = 0;
+
+	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
+	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
+
+	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
 /*
  * TODO: Convert the following to align with intel_c20pll_find_table() and
  * intel_c20pll_calc_state_from_table().
@@ -2702,56 +2752,6 @@ int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
 }
 
-static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
-{
-	return state->tx[0] & C20_PHY_USE_MPLLB;
-}
-
-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c20pll_state *pll_state)
-{
-	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
-	unsigned int multiplier, refclk = 38400;
-	unsigned int tx_clk_div;
-	unsigned int ref_clk_mpllb_div;
-	unsigned int fb_clk_div4_en;
-	unsigned int ref, vco;
-	unsigned int tx_rate_mult;
-	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
-
-	if (intel_c20phy_use_mpllb(pll_state)) {
-		tx_rate_mult = 1;
-		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
-		frac_quot = pll_state->mpllb[8];
-		frac_rem =  pll_state->mpllb[9];
-		frac_den =  pll_state->mpllb[7];
-		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
-		tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
-		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
-		fb_clk_div4_en = 0;
-	} else {
-		tx_rate_mult = 2;
-		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
-		frac_quot = pll_state->mplla[8];
-		frac_rem =  pll_state->mplla[9];
-		frac_den =  pll_state->mplla[7];
-		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
-		tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
-		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
-		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
-	}
-
-	if (frac_en)
-		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
-	else
-		frac = 0;
-
-	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
-	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
-
-	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
-}
-
 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
 {
-- 
2.34.1

[PATCH v2 03/15] drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculation

[Mika Kahola]

Drop crtc_state from hdmi tmds calculation and replace with the
parameters that are only required. Follow-up changes will call
these functions without a crtc_state available.

v2: Keep required crtc_state param for intel_c20_pll_tables_get()
    and other functions calling this one.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1deb865618b7..664c48dc0ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2414,9 +2414,8 @@ static bool is_arrowlake_s_by_host_bridge(void)
 	return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
 }
 
-static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_state)
+static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	u16 tx_misc;
 	u16 tx_dcc_cal_dac_ctrl_range = 8;
 	u16 tx_term_ctrl = 2;
@@ -2438,7 +2437,8 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_stat
 		C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl));
 }
 
-static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_state,
+static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display,
+					   int port_clock,
 					   struct intel_c20pll_state *pll_state)
 {
 	u64 datarate;
@@ -2452,10 +2452,10 @@ static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_s
 	u8  mpllb_ana_freq_vco;
 	u8  mpll_div_multiplier;
 
-	if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000)
+	if (port_clock < 25175 || port_clock > 600000)
 		return -EINVAL;
 
-	datarate = ((u64)crtc_state->port_clock * 1000) * 10;
+	datarate = ((u64)port_clock * 1000) * 10;
 	mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
 	vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
 	vco_freq = (datarate << vco_freq_shift) >> 8;
@@ -2477,9 +2477,9 @@ static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_s
 	else
 		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
 
-	pll_state->clock	= crtc_state->port_clock;
+	pll_state->clock	= port_clock;
 	pll_state->tx[0]	= 0xbe88;
-	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(crtc_state);
+	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(display);
 	pll_state->tx[2]	= 0x0000;
 	pll_state->cmn[0]	= 0x0500;
 	pll_state->cmn[1]	= 0x0005;
@@ -2724,7 +2724,8 @@ static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (!is_dp)
 		/* TODO: Update SSC state for HDMI as well */
-		err = intel_c20_compute_hdmi_tmds_pll(crtc_state, &hw_state->cx0pll.c20);
+		err = intel_c20_compute_hdmi_tmds_pll(display, crtc_state->port_clock,
+						      &hw_state->cx0pll.c20);
 
 	if (err)
 		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
-- 
2.34.1

[PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation

[Mika Kahola]

Drop crtc_state from intel_lt_phy_calc_port_clock() function call
and replace it with pll state instead. Follow-up changes will
call these functions without a crtc_state available.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c    |  4 +++-
 drivers/gpu/drm/i915/display/intel_dpll.c   |  3 ++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 19 ++++++++-----------
 drivers/gpu/drm/i915/display/intel_lt_phy.h |  4 ++--
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cb91d07cdaa6..d8739e2bb004 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4247,13 +4247,15 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
 				   struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
+
 	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
 
 	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
 		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
 	else
 		crtc_state->port_clock =
-			intel_lt_phy_calc_port_clock(encoder, crtc_state);
+			intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a4f372c9e6fc..1b5b18fa0a36 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1219,6 +1219,7 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
+	struct intel_display *display = to_intel_display(encoder);
 	int ret;
 
 	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
@@ -1227,7 +1228,7 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 
 	/* TODO: Do the readback via intel_compute_shared_dplls() */
 	crtc_state->port_clock =
-			intel_lt_phy_calc_port_clock(encoder, crtc_state);
+			intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
 
 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 939c8975fd4c..74b0bc90c959 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1679,7 +1679,8 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 }
 
 static int
-intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
+intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display,
+				  const struct intel_lt_phy_pll_state *lt_state)
 {
 #define REGVAL(i) (				\
 	(lt_state->data[i][3])		|	\
@@ -1688,9 +1689,6 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
 	(lt_state->data[i][0] << 24)		\
 )
 
-	struct intel_display *display = to_intel_display(crtc_state);
-	const struct intel_lt_phy_pll_state *lt_state =
-		&crtc_state->dpll_hw_state.ltpll;
 	int clk = 0;
 	u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
 	u64 temp0, temp1;
@@ -1748,12 +1746,10 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
 }
 
 int
-intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
-			     const struct intel_crtc_state *crtc_state)
+intel_lt_phy_calc_port_clock(struct intel_display *display,
+			     const struct intel_lt_phy_pll_state *lt_state)
 {
 	int clk;
-	const struct intel_lt_phy_pll_state *lt_state =
-		&crtc_state->dpll_hw_state.ltpll;
 	u8 mode, rate;
 
 	mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
@@ -1769,7 +1765,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
 				      lt_state->config[0]);
 		clk = intel_lt_phy_get_dp_clock(rate);
 	} else {
-		clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
+		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
 	}
 
 	return clk;
@@ -2220,6 +2216,7 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state,
 				       struct intel_lt_phy_pll_state *pll_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	u8 owned_lane_mask;
 	u8 lane;
 	struct ref_tracker *wakeref;
@@ -2245,7 +2242,7 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	}
 
 	pll_state->clock =
-		intel_lt_phy_calc_port_clock(encoder, crtc_state);
+		intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
@@ -2275,7 +2272,7 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 
 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
 	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
-	clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state);
+	clock = intel_lt_phy_calc_port_clock(display, &new_crtc_state->dpll_hw_state.ltpll);
 
 	dig_port = enc_to_dig_port(encoder);
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 7659c92b6c3c..c4999a55473e 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -21,8 +21,8 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder);
-int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *crtc_state);
+int intel_lt_phy_calc_port_clock(struct intel_display *display,
+				 const struct intel_lt_phy_pll_state *lt_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state);
 void intel_lt_phy_dump_hw_state(struct intel_display *display,
-- 
2.34.1

[PATCH v2 05/15] drm/i915/cx0: Drop encoder from port clock calculation

[Mika Kahola]

For C10 and C20 we have unused encoder parameter passed
to port clock calculation function. Remove encoder from
passing it to port clock calculation function.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 664c48dc0ce3..b7ac89e32586 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2103,8 +2103,7 @@ static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state)
 	return c20pll_state_is_dp(&pll_state->c20);
 }
 
-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state)
+static int intel_c10pll_calc_port_clock(const struct intel_c10pll_state *pll_state)
 {
 	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
 	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
@@ -2135,8 +2134,7 @@ static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
 	return state->tx[0] & C20_PHY_USE_MPLLB;
 }
 
-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c20pll_state *pll_state)
+static int intel_c20pll_calc_port_clock(const struct intel_c20pll_state *pll_state)
 {
 	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
 	unsigned int multiplier, refclk = 38400;
@@ -2325,7 +2323,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
-	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
+	pll_state->clock = intel_c10pll_calc_port_clock(pll_state);
 
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
 
@@ -2821,7 +2819,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 		}
 	}
 
-	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
+	pll_state->clock = intel_c20pll_calc_port_clock(pll_state);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
@@ -3713,9 +3711,9 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_cx0pll_state *pll_state)
 {
 	if (intel_encoder_is_c10phy(encoder))
-		return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);
+		return intel_c10pll_calc_port_clock(&pll_state->c10);
 
-	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
+	return intel_c20pll_calc_port_clock(&pll_state->c20);
 }
 
 /*
-- 
2.34.1

[PATCH v2 06/15] drm/i915/cx0: Create macro around pll tables

[Mika Kahola]

Create macro for storing pll dividers with table name
and clock rate.

v2: Preserve the terminating {} in each PLL table.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 301 ++++++++++---------
 1 file changed, 167 insertions(+), 134 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b7ac89e32586..ab402bd8a125 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -780,25 +780,58 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
 	.pll[19] = 0x23,
 };
 
-static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = {
-	&mtl_c10_dp_rbr,
-	&mtl_c10_dp_hbr1,
-	&mtl_c10_dp_hbr2,
-	&mtl_c10_dp_hbr3,
-	NULL,
-};
-
-static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
-	&mtl_c10_dp_rbr,
-	&mtl_c10_edp_r216,
-	&mtl_c10_edp_r243,
-	&mtl_c10_dp_hbr1,
-	&mtl_c10_edp_r324,
-	&mtl_c10_edp_r432,
-	&mtl_c10_dp_hbr2,
-	&mtl_c10_edp_r675,
-	&mtl_c10_dp_hbr3,
-	NULL,
+struct intel_cx0pll_params {
+	const char *name;
+	bool is_c10;
+	bool is_hdmi;
+	int clock_rate;
+	union {
+		const struct intel_c10pll_state *c10;
+		const struct intel_c20pll_state *c20;
+	};
+};
+
+#define __C10PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \
+	.name = __stringify(__state), \
+	.is_c10 = true, \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.c10 = &__state, \
+}
+
+#define __C20PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
+	.name = __stringify(__state), \
+	.is_c10 = false, \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.c20 = &__state, \
+}
+
+#define C10PLL_HDMI_PARAMS(__clock_rate, __state)       __C10PLL_PARAMS(true, __clock_rate, __state)
+#define C10PLL_DP_PARAMS(__clock_rate, __state)         __C10PLL_PARAMS(false, __clock_rate, __state)
+
+#define C20PLL_HDMI_PARAMS(__clock_rate, __state)       __C20PLL_PARAMS(true, __clock_rate, __state)
+#define C20PLL_DP_PARAMS(__clock_rate, __state)         __C20PLL_PARAMS(false, __clock_rate, __state)
+
+static const struct intel_cx0pll_params mtl_c10_dp_tables[] = {
+	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
+	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
+	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
+	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
+	{}
+};
+
+static const struct intel_cx0pll_params mtl_c10_edp_tables[] = {
+	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
+	C10PLL_DP_PARAMS(216000, mtl_c10_edp_r216),
+	C10PLL_DP_PARAMS(243000, mtl_c10_edp_r243),
+	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
+	C10PLL_DP_PARAMS(324000, mtl_c10_edp_r324),
+	C10PLL_DP_PARAMS(432000, mtl_c10_edp_r432),
+	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
+	C10PLL_DP_PARAMS(675000, mtl_c10_edp_r675),
+	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
+	{}
 };
 
 /* C20 basic DP 1.4 tables */
@@ -976,15 +1009,15 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
 		},
 };
 
-static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
-	&mtl_c20_dp_rbr,
-	&mtl_c20_dp_hbr1,
-	&mtl_c20_dp_hbr2,
-	&mtl_c20_dp_hbr3,
-	&mtl_c20_dp_uhbr10,
-	&mtl_c20_dp_uhbr13_5,
-	&mtl_c20_dp_uhbr20,
-	NULL,
+static const struct intel_cx0pll_params mtl_c20_dp_tables[] = {
+	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
+	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
+	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
+	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
+	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
+	C20PLL_DP_PARAMS(1350000, mtl_c20_dp_uhbr13_5),
+	C20PLL_DP_PARAMS(2000000, mtl_c20_dp_uhbr20),
+	{}
 };
 
 /*
@@ -1116,17 +1149,17 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
 		  },
 };
 
-static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
-	&mtl_c20_dp_rbr,
-	&xe2hpd_c20_edp_r216,
-	&xe2hpd_c20_edp_r243,
-	&mtl_c20_dp_hbr1,
-	&xe2hpd_c20_edp_r324,
-	&xe2hpd_c20_edp_r432,
-	&mtl_c20_dp_hbr2,
-	&xe2hpd_c20_edp_r675,
-	&mtl_c20_dp_hbr3,
-	NULL,
+static const struct intel_cx0pll_params xe2hpd_c20_edp_tables[] = {
+	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
+	C20PLL_DP_PARAMS(216000, xe2hpd_c20_edp_r216),
+	C20PLL_DP_PARAMS(243000, xe2hpd_c20_edp_r243),
+	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
+	C20PLL_DP_PARAMS(324000, xe2hpd_c20_edp_r324),
+	C20PLL_DP_PARAMS(432000, xe2hpd_c20_edp_r432),
+	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
+	C20PLL_DP_PARAMS(675000, xe2hpd_c20_edp_r675),
+	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
+	{}
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
@@ -1154,30 +1187,30 @@ static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
 		},
 };
 
-static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
-	&mtl_c20_dp_rbr,
-	&mtl_c20_dp_hbr1,
-	&mtl_c20_dp_hbr2,
-	&mtl_c20_dp_hbr3,
-	&mtl_c20_dp_uhbr10,
-	&xe2hpd_c20_dp_uhbr13_5,
-	NULL,
+static const struct intel_cx0pll_params xe2hpd_c20_dp_tables[] = {
+	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
+	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
+	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
+	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
+	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
+	C20PLL_DP_PARAMS(1350000, xe2hpd_c20_dp_uhbr13_5),
+	{}
 };
 
-static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
-	&mtl_c20_dp_rbr,
-	&xe2hpd_c20_edp_r216,
-	&xe2hpd_c20_edp_r243,
-	&mtl_c20_dp_hbr1,
-	&xe2hpd_c20_edp_r324,
-	&xe2hpd_c20_edp_r432,
-	&mtl_c20_dp_hbr2,
-	&xe2hpd_c20_edp_r675,
-	&mtl_c20_dp_hbr3,
-	&mtl_c20_dp_uhbr10,
-	&xe2hpd_c20_dp_uhbr13_5,
-	&mtl_c20_dp_uhbr20,
-	NULL,
+static const struct intel_cx0pll_params xe3lpd_c20_dp_edp_tables[] = {
+	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
+	C20PLL_DP_PARAMS(216000, xe2hpd_c20_edp_r216),
+	C20PLL_DP_PARAMS(243000, xe2hpd_c20_edp_r243),
+	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
+	C20PLL_DP_PARAMS(324000, xe2hpd_c20_edp_r324),
+	C20PLL_DP_PARAMS(432000, xe2hpd_c20_edp_r432),
+	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
+	C20PLL_DP_PARAMS(675000, xe2hpd_c20_edp_r675),
+	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
+	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
+	C20PLL_DP_PARAMS(1350000, xe2hpd_c20_dp_uhbr13_5),
+	C20PLL_DP_PARAMS(2000000, mtl_c20_dp_uhbr20),
+	{}
 };
 
 /*
@@ -1715,53 +1748,53 @@ static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
 	.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
 };
 
-static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
-	&mtl_c10_hdmi_25_2, /* Consolidated Table */
-	&mtl_c10_hdmi_27_0, /* Consolidated Table */
-	&mtl_c10_hdmi_27027,
-	&mtl_c10_hdmi_28320,
-	&mtl_c10_hdmi_30240,
-	&mtl_c10_hdmi_31500,
-	&mtl_c10_hdmi_36000,
-	&mtl_c10_hdmi_40000,
-	&mtl_c10_hdmi_49500,
-	&mtl_c10_hdmi_50000,
-	&mtl_c10_hdmi_57284,
-	&mtl_c10_hdmi_58000,
-	&mtl_c10_hdmi_65000,
-	&mtl_c10_hdmi_71000,
-	&mtl_c10_hdmi_74176,
-	&mtl_c10_hdmi_74_25, /* Consolidated Table */
-	&mtl_c10_hdmi_75000,
-	&mtl_c10_hdmi_78750,
-	&mtl_c10_hdmi_85500,
-	&mtl_c10_hdmi_88750,
-	&mtl_c10_hdmi_106500,
-	&mtl_c10_hdmi_108000,
-	&mtl_c10_hdmi_115500,
-	&mtl_c10_hdmi_119000,
-	&mtl_c10_hdmi_135000,
-	&mtl_c10_hdmi_138500,
-	&mtl_c10_hdmi_147160,
-	&mtl_c10_hdmi_148352,
-	&mtl_c10_hdmi_148_5, /* Consolidated Table */
-	&mtl_c10_hdmi_154000,
-	&mtl_c10_hdmi_162000,
-	&mtl_c10_hdmi_167000,
-	&mtl_c10_hdmi_197802,
-	&mtl_c10_hdmi_198000,
-	&mtl_c10_hdmi_209800,
-	&mtl_c10_hdmi_241500,
-	&mtl_c10_hdmi_262750,
-	&mtl_c10_hdmi_268500,
-	&mtl_c10_hdmi_296703,
-	&mtl_c10_hdmi_297000,
-	&mtl_c10_hdmi_319750,
-	&mtl_c10_hdmi_497750,
-	&mtl_c10_hdmi_592000,
-	&mtl_c10_hdmi_593407,
-	&mtl_c10_hdmi_594, /* Consolidated Table */
-	NULL,
+static const struct intel_cx0pll_params mtl_c10_hdmi_tables[] = {
+	C10PLL_HDMI_PARAMS(25200, mtl_c10_hdmi_25_2), /* Consolidated Table */
+	C10PLL_HDMI_PARAMS(27000, mtl_c10_hdmi_27_0), /* Consolidated Table */
+	C10PLL_HDMI_PARAMS(27027, mtl_c10_hdmi_27027),
+	C10PLL_HDMI_PARAMS(28320, mtl_c10_hdmi_28320),
+	C10PLL_HDMI_PARAMS(30240, mtl_c10_hdmi_30240),
+	C10PLL_HDMI_PARAMS(31500, mtl_c10_hdmi_31500),
+	C10PLL_HDMI_PARAMS(36000, mtl_c10_hdmi_36000),
+	C10PLL_HDMI_PARAMS(40000, mtl_c10_hdmi_40000),
+	C10PLL_HDMI_PARAMS(49500, mtl_c10_hdmi_49500),
+	C10PLL_HDMI_PARAMS(50000, mtl_c10_hdmi_50000),
+	C10PLL_HDMI_PARAMS(57284, mtl_c10_hdmi_57284),
+	C10PLL_HDMI_PARAMS(58000, mtl_c10_hdmi_58000),
+	C10PLL_HDMI_PARAMS(65000, mtl_c10_hdmi_65000),
+	C10PLL_HDMI_PARAMS(71000, mtl_c10_hdmi_71000),
+	C10PLL_HDMI_PARAMS(74176, mtl_c10_hdmi_74176),
+	C10PLL_HDMI_PARAMS(74250, mtl_c10_hdmi_74_25), /* Consolidated Table */
+	C10PLL_HDMI_PARAMS(75000, mtl_c10_hdmi_75000),
+	C10PLL_HDMI_PARAMS(78750, mtl_c10_hdmi_78750),
+	C10PLL_HDMI_PARAMS(85500, mtl_c10_hdmi_85500),
+	C10PLL_HDMI_PARAMS(88750, mtl_c10_hdmi_88750),
+	C10PLL_HDMI_PARAMS(106500, mtl_c10_hdmi_106500),
+	C10PLL_HDMI_PARAMS(108000, mtl_c10_hdmi_108000),
+	C10PLL_HDMI_PARAMS(115500, mtl_c10_hdmi_115500),
+	C10PLL_HDMI_PARAMS(119000, mtl_c10_hdmi_119000),
+	C10PLL_HDMI_PARAMS(135000, mtl_c10_hdmi_135000),
+	C10PLL_HDMI_PARAMS(138500, mtl_c10_hdmi_138500),
+	C10PLL_HDMI_PARAMS(147160, mtl_c10_hdmi_147160),
+	C10PLL_HDMI_PARAMS(148352, mtl_c10_hdmi_148352),
+	C10PLL_HDMI_PARAMS(148500, mtl_c10_hdmi_148_5), /* Consolidated Table */
+	C10PLL_HDMI_PARAMS(154000, mtl_c10_hdmi_154000),
+	C10PLL_HDMI_PARAMS(162000, mtl_c10_hdmi_162000),
+	C10PLL_HDMI_PARAMS(167000, mtl_c10_hdmi_167000),
+	C10PLL_HDMI_PARAMS(197802, mtl_c10_hdmi_197802),
+	C10PLL_HDMI_PARAMS(198000, mtl_c10_hdmi_198000),
+	C10PLL_HDMI_PARAMS(209800, mtl_c10_hdmi_209800),
+	C10PLL_HDMI_PARAMS(241500, mtl_c10_hdmi_241500),
+	C10PLL_HDMI_PARAMS(262750, mtl_c10_hdmi_262750),
+	C10PLL_HDMI_PARAMS(268500, mtl_c10_hdmi_268500),
+	C10PLL_HDMI_PARAMS(296703, mtl_c10_hdmi_296703),
+	C10PLL_HDMI_PARAMS(297000, mtl_c10_hdmi_297000),
+	C10PLL_HDMI_PARAMS(319750, mtl_c10_hdmi_319750),
+	C10PLL_HDMI_PARAMS(497750, mtl_c10_hdmi_497750),
+	C10PLL_HDMI_PARAMS(592000, mtl_c10_hdmi_592000),
+	C10PLL_HDMI_PARAMS(593407, mtl_c10_hdmi_593407),
+	C10PLL_HDMI_PARAMS(594000, mtl_c10_hdmi_594), /* Consolidated Table */
+	{}
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
@@ -2014,21 +2047,21 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
 		},
 };
 
-static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
-	&mtl_c20_hdmi_25_175,
-	&mtl_c20_hdmi_27_0,
-	&mtl_c20_hdmi_74_25,
-	&mtl_c20_hdmi_148_5,
-	&mtl_c20_hdmi_594,
-	&mtl_c20_hdmi_300,
-	&mtl_c20_hdmi_600,
-	&mtl_c20_hdmi_800,
-	&mtl_c20_hdmi_1000,
-	&mtl_c20_hdmi_1200,
-	NULL,
+static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = {
+	C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175),
+	C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0),
+	C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25),
+	C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5),
+	C20PLL_HDMI_PARAMS(594000, mtl_c20_hdmi_594),
+	C20PLL_HDMI_PARAMS(300000, mtl_c20_hdmi_300),
+	C20PLL_HDMI_PARAMS(600000, mtl_c20_hdmi_600),
+	C20PLL_HDMI_PARAMS(800000, mtl_c20_hdmi_800),
+	C20PLL_HDMI_PARAMS(1000000, mtl_c20_hdmi_1000),
+	C20PLL_HDMI_PARAMS(1200000, mtl_c20_hdmi_1200),
+	{}
 };
 
-static const struct intel_c10pll_state * const *
+static const struct intel_cx0pll_params *
 intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
 			struct intel_encoder *encoder)
 {
@@ -2183,16 +2216,16 @@ static int intel_c20pll_calc_port_clock(const struct intel_c20pll_state *pll_sta
  * intel_c20pll_calc_state_from_table().
  */
 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
-					      const struct intel_c10pll_state * const *tables,
+					      const struct intel_cx0pll_params *tables,
 					      bool is_dp, int port_clock, int lane_count,
 					      struct intel_cx0pll_state *pll_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	int i;
 
-	for (i = 0; tables[i]; i++) {
-		if (port_clock == tables[i]->clock) {
-			pll_state->c10 = *tables[i];
+	for (i = 0; tables[i].name; i++) {
+		if (port_clock == tables[i].clock_rate) {
+			pll_state->c10 = *tables[i].c10;
 			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
 			intel_c10pll_update_pll(encoder, pll_state);
 
@@ -2214,7 +2247,7 @@ static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
-	const struct intel_c10pll_state * const *tables;
+	const struct intel_cx0pll_params *tables;
 	int err;
 
 	tables = intel_c10pll_tables_get(crtc_state, encoder);
@@ -2505,7 +2538,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display,
 	return 0;
 }
 
-static const struct intel_c20pll_state * const *
+static const struct intel_cx0pll_params *
 intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
 {
@@ -2673,20 +2706,20 @@ static void intel_c20_program_vdr_params(struct intel_encoder *encoder,
 		      MB_WRITE_COMMITTED);
 }
 
-static const struct intel_c20pll_state *
+static const struct intel_cx0pll_params *
 intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
 {
-	const struct intel_c20pll_state * const *tables;
+	const struct intel_cx0pll_params *tables;
 	int i;
 
 	tables = intel_c20_pll_tables_get(crtc_state, encoder);
 	if (!tables)
 		return NULL;
 
-	for (i = 0; tables[i]; i++)
-		if (crtc_state->port_clock == tables[i]->clock)
-			return tables[i];
+	for (i = 0; tables[i].name; i++)
+		if (crtc_state->port_clock == tables[i].clock_rate)
+			return &tables[i];
 
 	return NULL;
 }
@@ -2695,13 +2728,13 @@ static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crt
 					      struct intel_encoder *encoder,
 					      struct intel_cx0pll_state *pll_state)
 {
-	const struct intel_c20pll_state *table;
+	const struct intel_cx0pll_params *table;
 
 	table = intel_c20_pll_find_table(crtc_state, encoder);
 	if (!table)
 		return -EINVAL;
 
-	pll_state->c20 = *table;
+	pll_state->c20 = *table->c20;
 
 	intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state));
 
-- 
2.34.1

[PATCH v2 07/15] drm/i915/lt_phy: Create macro for lt phy pll state

[Mika Kahola]

Create a macro for pll state for lt phy similar as
for cx0 case.

v2:
- Move addition of LT_PHY_PLL_DP/HDMI_PARAMS() to this patch.
- Fix end of table checking while looking up a table.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 83 +++++++++++++--------
 1 file changed, 50 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 74b0bc90c959..64e223f35fdf 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -436,15 +436,32 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
 	},
 };
 
-static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
-	&xe3plpd_lt_dp_rbr,
-	&xe3plpd_lt_dp_hbr1,
-	&xe3plpd_lt_dp_hbr2,
-	&xe3plpd_lt_dp_hbr3,
-	&xe3plpd_lt_dp_uhbr10,
-	&xe3plpd_lt_dp_uhbr13_5,
-	&xe3plpd_lt_dp_uhbr20,
-	NULL,
+struct intel_lt_phy_pll_params {
+	const char *name;
+	bool is_hdmi;
+	int clock_rate;
+	const struct intel_lt_phy_pll_state *state;
+};
+
+#define __LT_PHY_PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
+	.name = __stringify(__state), \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.state = &__state, \
+}
+
+#define LT_PHY_PLL_HDMI_PARAMS(__clock_rate, __state)	__LT_PHY_PLL_PARAMS(true, __clock_rate, __state)
+#define LT_PHY_PLL_DP_PARAMS(__clock_rate, __state)	__LT_PHY_PLL_PARAMS(false, __clock_rate, __state)
+
+static const struct intel_lt_phy_pll_params xe3plpd_lt_dp_tables[] = {
+	LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
+	LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
+	LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
+	LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
+	LT_PHY_PLL_DP_PARAMS(1000000, xe3plpd_lt_dp_uhbr10),
+	LT_PHY_PLL_DP_PARAMS(1350000, xe3plpd_lt_dp_uhbr13_5),
+	LT_PHY_PLL_DP_PARAMS(2000000, xe3plpd_lt_dp_uhbr20),
+	{}
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
@@ -717,17 +734,17 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
 	},
 };
 
-static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
-	&xe3plpd_lt_dp_rbr,
-	&xe3plpd_lt_edp_2_16,
-	&xe3plpd_lt_edp_2_43,
-	&xe3plpd_lt_dp_hbr1,
-	&xe3plpd_lt_edp_3_24,
-	&xe3plpd_lt_edp_4_32,
-	&xe3plpd_lt_dp_hbr2,
-	&xe3plpd_lt_edp_6_75,
-	&xe3plpd_lt_dp_hbr3,
-	NULL,
+static const struct intel_lt_phy_pll_params xe3plpd_lt_edp_tables[] = {
+	LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
+	LT_PHY_PLL_DP_PARAMS(216000, xe3plpd_lt_edp_2_16),
+	LT_PHY_PLL_DP_PARAMS(243000, xe3plpd_lt_edp_2_43),
+	LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
+	LT_PHY_PLL_DP_PARAMS(324000, xe3plpd_lt_edp_3_24),
+	LT_PHY_PLL_DP_PARAMS(432000, xe3plpd_lt_edp_4_32),
+	LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
+	LT_PHY_PLL_DP_PARAMS(675000, xe3plpd_lt_edp_6_75),
+	LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
+	{}
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
@@ -1000,13 +1017,13 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
 	},
 };
 
-static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
-	&xe3plpd_lt_hdmi_252,
-	&xe3plpd_lt_hdmi_272,
-	&xe3plpd_lt_hdmi_742p5,
-	&xe3plpd_lt_hdmi_1p485,
-	&xe3plpd_lt_hdmi_5p94,
-	NULL,
+static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
+	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
+	LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
+	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
+	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
+	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
+	{}
 };
 
 static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
@@ -1345,7 +1362,7 @@ static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, struct r
 	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
-static const struct intel_lt_phy_pll_state * const *
+static const struct intel_lt_phy_pll_params *
 intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
 {
@@ -1734,7 +1751,7 @@ intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display,
 	if (d8 == 0) {
 		drm_WARN_ON(display->drm,
 			    "Invalid port clock using lowest HDMI portclock\n");
-		return xe3plpd_lt_hdmi_252.clock;
+		return xe3plpd_lt_hdmi_tables[0].clock_rate;
 	}
 	m2div_int = (pll_reg_3  & REG_GENMASK(14, 5)) >> 5;
 	temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32;
@@ -1775,16 +1792,16 @@ int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
 {
-	const struct intel_lt_phy_pll_state * const *tables;
+	const struct intel_lt_phy_pll_params *tables;
 	int i;
 
 	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
 	if (!tables)
 		return -EINVAL;
 
-	for (i = 0; tables[i]; i++) {
-		if (crtc_state->port_clock == tables[i]->clock) {
-			crtc_state->dpll_hw_state.ltpll = *tables[i];
+	for (i = 0; tables[i].name; i++) {
+		if (crtc_state->port_clock == tables[i].clock_rate) {
+			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
 			if (intel_crtc_has_dp_encoder(crtc_state)) {
 				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
-- 
2.34.1

[PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock check

[Mika Kahola]

The hard coded clock rate stored in the PLL state will be removed by
a follow-up change. Prepare for that here to calculate instead the
clock from the PLL divider values in the PLL state. Since this
calculated clock can have a +-1 kHz difference wrt. the request clock,
use a fuzzy check when looking up the corresponding table entry.

v2:
- Use the stricter +-1 kHz allowed difference.
- Derive the clock from PLL dividers in intel_cx0pll_enable().
- Move corresponding fuzzy check for LT PHY PLLs to this patch.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 +++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c  |  6 ++++-
 3 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ab402bd8a125..4d006c14c049 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2211,6 +2211,11 @@ static int intel_c20pll_calc_port_clock(const struct intel_c20pll_state *pll_sta
 	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
 }
 
+bool intel_cx0pll_clock_matches(int clock1, int clock2)
+{
+	return abs(clock1 - clock2) <= 1;
+}
+
 /*
  * TODO: Convert the following to align with intel_c20pll_find_table() and
  * intel_c20pll_calc_state_from_table().
@@ -2224,7 +2229,10 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 	int i;
 
 	for (i = 0; tables[i].name; i++) {
-		if (port_clock == tables[i].clock_rate) {
+		int clock = intel_c10pll_calc_port_clock(tables[i].c10);
+
+		drm_WARN_ON(display->drm, !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
+		if (intel_cx0pll_clock_matches(port_clock, clock)) {
 			pll_state->c10 = *tables[i].c10;
 			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
 			intel_c10pll_update_pll(encoder, pll_state);
@@ -2710,6 +2718,7 @@ static const struct intel_cx0pll_params *
 intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	const struct intel_cx0pll_params *tables;
 	int i;
 
@@ -2717,9 +2726,13 @@ intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 	if (!tables)
 		return NULL;
 
-	for (i = 0; tables[i].name; i++)
-		if (crtc_state->port_clock == tables[i].clock_rate)
+	for (i = 0; tables[i].name; i++) {
+		int clock = intel_c20pll_calc_port_clock(tables[i].c20);
+
+		drm_WARN_ON(display->drm, !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
+		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock))
 			return &tables[i];
+	}
 
 	return NULL;
 }
@@ -3252,7 +3265,6 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 static void intel_cx0pll_enable(struct intel_encoder *encoder,
 				const struct intel_cx0pll_state *pll_state)
 {
-	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -3260,6 +3272,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
 					  INTEL_CX0_LANE0;
 	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
+	int port_clock;
+
+	if (pll_state->use_c10)
+		port_clock = intel_c10pll_calc_port_clock(&pll_state->c10);
+	else
+		port_clock = intel_c20pll_calc_port_clock(&pll_state->c20);
 
 	/*
 	 * Lane reversal is never used in DP-alt mode, in that case the
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 9f10113e2d18..3d9c580eb562 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder,
 				    int port_clock);
 void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
 
+bool intel_cx0pll_clock_matches(int clock1, int clock2);
 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
 			    struct intel_dpll_hw_state *hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 64e223f35fdf..e33f6f48a6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1792,6 +1792,7 @@ int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	const struct intel_lt_phy_pll_params *tables;
 	int i;
 
@@ -1800,7 +1801,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 
 	for (i = 0; tables[i].name; i++) {
-		if (crtc_state->port_clock == tables[i].clock_rate) {
+		int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
+
+		drm_WARN_ON(display->drm, !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
+		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock)) {
 			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
 			if (intel_crtc_has_dp_encoder(crtc_state)) {
 				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-- 
2.34.1

[PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates

[Mika Kahola]

HDMI FRL clock rates are incorrectly defined. Fix these
rates.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4d006c14c049..0f28d02b7a69 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1923,7 +1923,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
-	.clock = 3000000,
+	.clock = 300000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1948,7 +1948,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
-	.clock = 6000000,
+	.clock = 600000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1973,7 +1973,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
-	.clock = 8000000,
+	.clock = 800000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1998,7 +1998,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
-	.clock = 10000000,
+	.clock = 1000000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -2023,7 +2023,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
-	.clock = 12000000,
+	.clock = 1200000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
-- 
2.34.1

[PATCH v2 10/15] drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming

[Mika Kahola]

Since the clock rate is derived from the PLL divider values it can have
a +-1kHz difference wrt. the reference rates in the comparison

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 +++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c    | 18 ++++++++----------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0f28d02b7a69..ea807191cb4f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3013,6 +3013,12 @@ static void intel_c20_pll_program(struct intel_display *display,
 		      MB_WRITE_COMMITTED);
 }
 
+static bool is_mplla_clock_rate(int clock)
+{
+	return intel_cx0pll_clock_matches(clock, 1000000) ||
+	       intel_cx0pll_clock_matches(clock, 2000000);
+}
+
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_cx0pll_state *pll_state,
 					 int port_clock,
@@ -3038,7 +3044,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 
 	/* TODO: HDMI FRL */
 	/* DP2.0 10G and 20G rates enable MPLLA*/
-	if (port_clock == 1000000 || port_clock == 2000000)
+	if (is_mplla_clock_rate(port_clock))
 		val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
 	else
 		val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 055e68810d0d..63a88006e336 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -70,16 +70,14 @@
 
 bool intel_hdmi_is_frl(u32 clock)
 {
-	switch (clock) {
-	case 300000: /* 3 Gbps */
-	case 600000: /* 6 Gbps */
-	case 800000: /* 8 Gbps */
-	case 1000000: /* 10 Gbps */
-	case 1200000: /* 12 Gbps */
-		return true;
-	default:
-		return false;
-	}
+	u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(rates); i++)
+		if (intel_cx0pll_clock_matches(clock, rates[i]))
+			return true;
+
+	return false;
 }
 
 static void
-- 
2.34.1

[PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers

[Mika Kahola]

Add verification for pll table dividers. The port clock
is computed based on pll tables and, for hdmi case, the
algorithmic model is applied to calculate pll dividers.
If port clock differs more than +-1 kHz from expected value
an drm_warn() is thrown and pll divider differences are
printed out for debugging purposes.

v2:
- Move clock derivation from dividers in intel_cx0pll_enable()
  earlier in the patchset.
- Keep intel_cx0_pll_power_save_wa() in intel_dpll_sanitize_state()
- Use tables[i].name != NULL as a terminating condition.
- Drop duplicate intel_cx0pll_clock_matches() declaration in header.
- Use state vs. params term consistently in intel_c10pll_verify_clock()
  and intel_c20pll_verify_clock().

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 121 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   1 +
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   9 +-
 3 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ea807191cb4f..a8c37a14d427 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3824,3 +3824,124 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 		intel_cx0pll_disable(encoder);
 	}
 }
+
+static void intel_c10pll_verify_clock(struct intel_display *display,
+				      int precomputed_clock,
+				      const char *pll_state_name,
+				      const struct intel_c10pll_state *pll_state,
+				      bool is_precomputed_state)
+{
+	struct drm_printer p;
+	int clock;
+
+	clock = intel_c10pll_calc_port_clock(pll_state);
+
+	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
+		return;
+
+	drm_warn(display->drm,
+		 "PLL state %s (%s): clock difference too high: computed %d, pre-computed %d\n",
+		 pll_state_name,
+		 is_precomputed_state ? "precomputed" : "computed",
+		 clock, precomputed_clock);
+
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+	drm_printf(&p, "PLL state %s (%s):\n",
+		   pll_state_name,
+		   is_precomputed_state ? "precomputed" : "computed");
+	intel_c10pll_dump_hw_state(&p, pll_state);
+}
+
+static void intel_c10pll_verify_params(struct intel_display *display,
+				       const struct intel_cx0pll_params *pll_params)
+{
+	struct intel_c10pll_state pll_state;
+
+	intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c10, true);
+
+	if (!pll_params->is_hdmi)
+		return;
+
+	intel_snps_hdmi_pll_compute_c10pll(&pll_state, pll_params->clock_rate);
+
+	intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
+}
+
+static void intel_c20pll_verify_clock(struct intel_display *display,
+				      int precomputed_clock,
+				      const char *pll_state_name,
+				      const struct intel_c20pll_state *pll_state,
+				      bool is_precomputed_state)
+{
+	struct drm_printer p;
+	int clock;
+
+	clock = intel_c20pll_calc_port_clock(pll_state);
+
+	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
+		return;
+
+	drm_warn(display->drm,
+		 "PLL state %s (%s): clock difference too high: computed %d, pre-computed %d\n",
+		 pll_state_name,
+		 is_precomputed_state ? "precomputed" : "computed",
+		 clock, precomputed_clock);
+
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+	drm_printf(&p, "PLL state %s (%s):\n",
+		   pll_state_name,
+		   is_precomputed_state ? "precomputed" : "computed");
+	intel_c20pll_dump_hw_state(&p, pll_state);
+}
+
+static void intel_c20pll_verify_params(struct intel_display *display,
+				       const struct intel_cx0pll_params *pll_params)
+{
+	struct intel_c20pll_state pll_state;
+
+	intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c20, true);
+
+	if (!pll_params->is_hdmi)
+		return;
+
+	if (intel_c20_compute_hdmi_tmds_pll(display, pll_params->clock_rate, &pll_state) != 0)
+		return;
+
+	intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
+}
+
+static void intel_cx0pll_verify_tables(struct intel_display *display,
+				       const struct intel_cx0pll_params *tables)
+{
+	int i;
+
+	for (i = 0; tables[i].name; i++) {
+		if (tables[i].is_c10)
+			intel_c10pll_verify_params(display, &tables[i]);
+		else
+			intel_c20pll_verify_params(display, &tables[i]);
+	}
+}
+
+void intel_cx0pll_verify_plls(struct intel_display *display)
+{
+	/* C10 */
+	intel_cx0pll_verify_tables(display, mtl_c10_edp_tables);
+	intel_cx0pll_verify_tables(display, mtl_c10_dp_tables);
+	intel_cx0pll_verify_tables(display, mtl_c10_hdmi_tables);
+
+	/* C20 */
+	intel_cx0pll_verify_tables(display, xe2hpd_c20_edp_tables);
+	intel_cx0pll_verify_tables(display, mtl_c20_dp_tables);
+	intel_cx0pll_verify_tables(display, xe2hpd_c20_dp_tables);
+	intel_cx0pll_verify_tables(display, xe3lpd_c20_dp_edp_tables);
+	intel_cx0pll_verify_tables(display, mtl_c20_hdmi_tables);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 3d9c580eb562..c0ac67f7b11f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -78,6 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
 					struct intel_dpll_hw_state *hw_state);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 
+void intel_cx0pll_verify_plls(struct intel_display *display);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9aa84a430f09..7127bc2a0898 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4613,7 +4613,7 @@ void intel_dpll_init(struct intel_display *display)
 		dpll_mgr = &pch_pll_mgr;
 
 	if (!dpll_mgr)
-		return;
+		goto out_verify;
 
 	dpll_info = dpll_mgr->dpll_info;
 
@@ -4632,6 +4632,13 @@ void intel_dpll_init(struct intel_display *display)
 
 	display->dpll.mgr = dpll_mgr;
 	display->dpll.num_dpll = i;
+
+out_verify:
+	/*
+	 * TODO: Convert these to a KUnit test or dependent on a kconfig
+	 * debug option.
+	 */
+	intel_cx0pll_verify_plls(display);
 }
 
 /**
-- 
2.34.1

[PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Mika Kahola]

Add verification for lt phy pll dividers during boot. The port clock
is calculated from pll dividers and compared against the requested
port clock value. If there are a difference exceeding +-1 kHz an
drm_warn() is thrown out to indicate possible pll divider mismatch.

v2:
- Move the LT_PHY_PLL_PARAMS -> LT_PHY_PLL_DP/HDMI_PARAMS change
  earlier.
- Use tables[i].name != NULL as a terminating condition.
- Use state vs. params term consistently in intel_c10pll_verify_clock()
  and intel_c20pll_verify_clock().

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 63 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
 3 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7127bc2a0898..f35a9252f4e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -38,6 +38,7 @@
 #include "intel_dpll.h"
 #include "intel_dpll_mgr.h"
 #include "intel_hti.h"
+#include "intel_lt_phy.h"
 #include "intel_mg_phy_regs.h"
 #include "intel_pch_refclk.h"
 #include "intel_step.h"
@@ -4639,6 +4640,7 @@ void intel_dpll_init(struct intel_display *display)
 	 * debug option.
 	 */
 	intel_cx0pll_verify_plls(display);
+	intel_lt_phy_verify_plls(display);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index e33f6f48a6ce..13acfc7c0469 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2343,3 +2343,66 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
 		intel_lt_phy_pll_disable(encoder);
 
 }
+
+static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
+					  int precomputed_clock,
+					  const char *pll_state_name,
+					  const struct intel_lt_phy_pll_state *pll_state,
+					  bool is_precomputed_state)
+{
+	struct drm_printer p;
+	int clock;
+
+	clock = intel_lt_phy_calc_port_clock(display, pll_state);
+
+	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
+		return;
+
+	drm_warn(display->drm,
+		 "PLL state %s (%s): clock difference too high: computed %d, pre-computed %d\n",
+		 pll_state_name,
+		 is_precomputed_state ? "precomputed" : "computed",
+		 clock, precomputed_clock);
+
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+	drm_printf(&p, "PLL state %s (%s):\n",
+		   pll_state_name,
+		   is_precomputed_state ? "precomputed" : "computed");
+	intel_lt_phy_dump_hw_state(display, pll_state);
+}
+
+static void intel_lt_phy_pll_verify_params(struct intel_display *display,
+					   const struct intel_lt_phy_pll_params *pll_params)
+{
+	struct intel_lt_phy_pll_state pll_state;
+
+	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->state, true);
+
+	if (!pll_params->is_hdmi)
+		return;
+
+	if (intel_lt_phy_calculate_hdmi_state(&pll_state, pll_params->clock_rate) != 0)
+		return;
+
+	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
+}
+
+static void intel_lt_phy_pll_verify_tables(struct intel_display *display,
+					   const struct intel_lt_phy_pll_params *tables)
+{
+	int i;
+
+	for (i = 0; tables[i].name; i++)
+		intel_lt_phy_pll_verify_params(display, &tables[i]);
+}
+
+void intel_lt_phy_verify_plls(struct intel_display *display)
+{
+	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
+	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
+	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index c4999a55473e..56c5a875d93b 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -41,5 +41,6 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
+void intel_lt_phy_verify_plls(struct intel_display *display);
 
 #endif /* __INTEL_LT_PHY_H__ */
-- 
2.34.1

[PATCH v2 13/15] drm/i915/cx0: Drop C20 25.175 MHz rate

[Mika Kahola]

Drop C20 25.175 MHz pll table as with these
pll dividers the port clock will be incorrectly
calculated to 25.2 MHz. For 25.175 MHz rate the
PLl dividers are calculated algorithmically making
pll table for this rate redundant.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --------------------
 1 file changed, 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a8c37a14d427..5d0bca0f75b0 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1797,31 +1797,6 @@ static const struct intel_cx0pll_params mtl_c10_hdmi_tables[] = {
 	{}
 };
 
-static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
-	.clock = 25175,
-	.tx = {  0xbe88, /* tx cfg0 */
-		  0x9800, /* tx cfg1 */
-		  0x0000, /* tx cfg2 */
-		},
-	.cmn = { 0x0500, /* cmn cfg0*/
-		  0x0005, /* cmn cfg1 */
-		  0x0000, /* cmn cfg2 */
-		  0x0000, /* cmn cfg3 */
-		},
-	.mpllb = { 0xa0d2,	/* mpllb cfg0 */
-		   0x7d80,	/* mpllb cfg1 */
-		   0x0906,	/* mpllb cfg2 */
-		   0xbe40,	/* mpllb cfg3 */
-		   0x0000,	/* mpllb cfg4 */
-		   0x0000,	/* mpllb cfg5 */
-		   0x0200,	/* mpllb cfg6 */
-		   0x0001,	/* mpllb cfg7 */
-		   0x0000,	/* mpllb cfg8 */
-		   0x0000,	/* mpllb cfg9 */
-		   0x0001,	/* mpllb cfg10 */
-		},
-};
-
 static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
 	.clock = 27000,
 	.tx = {  0xbe88, /* tx cfg0 */
@@ -2048,7 +2023,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
 };
 
 static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = {
-	C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175),
 	C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0),
 	C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25),
 	C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5),
-- 
2.34.1

[PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 MHz rate

[Mika Kahola]

Drop 27.2 MHz pll table as with these pll dividers
the port clock will be incorrectly calculated to 27.0 MHz.
For 27.2 MHz rate the PLl dividers are calculated
algorithmically making pll table for this rate redundant.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 55 ---------------------
 1 file changed, 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 13acfc7c0469..bc73b1466bc4 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -801,60 +801,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
 	},
 };
 
-static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
-	.clock = 27200,
-	.config = {
-		0x84,
-		0x2d,
-		0x0,
-	},
-	.addr_msb = {
-		0x87,
-		0x87,
-		0x87,
-		0x87,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-		0x88,
-	},
-	.addr_lsb = {
-		0x10,
-		0x0c,
-		0x14,
-		0xe4,
-		0x0c,
-		0x10,
-		0x14,
-		0x18,
-		0x48,
-		0x40,
-		0x4c,
-		0x24,
-		0x44,
-	},
-	.data = {
-		{ 0x0,  0x4c, 0x2,  0x0  },
-		{ 0x0b, 0x15, 0x26, 0xa0 },
-		{ 0x60, 0x0,  0x0,  0x0  },
-		{ 0x8,  0x4,  0x96, 0x28 },
-		{ 0xfa, 0x0c, 0x84, 0x11 },
-		{ 0x80, 0x0f, 0xd9, 0x53 },
-		{ 0x86, 0x0,  0x0,  0x0  },
-		{ 0x1,  0xa0, 0x1,  0x0  },
-		{ 0x4b, 0x0,  0x0,  0x0  },
-		{ 0x28, 0x0,  0x0,  0x0  },
-		{ 0x0,  0x14, 0x2a, 0x14 },
-		{ 0x0,  0x0,  0x0,  0x0  },
-		{ 0x0,  0x0,  0x0,  0x0  },
-	},
-};
-
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
 	.clock = 74250,
 	.config = {
@@ -1019,7 +965,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
 
 static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
 	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
-	LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
 	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
 	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
 	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
-- 
2.34.1

[PATCH v2 15/15] drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables

[Mika Kahola]

PLL state structure has a member .clock. This is not needed as
the port clock is possible to calculate from the pll dividers.
Remove the .clock from the pll state structure.

v2: Keep the pll_state->clock assignment in
    intel_snps_hdmi_pll_compute_mpllb().

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 86 +------------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 -
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 26 ------
 .../drm/i915/display/intel_snps_hdmi_pll.c    |  2 -
 4 files changed, 2 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5d0bca0f75b0..2a353dfad87d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -547,7 +547,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
  */
 
 static const struct intel_c10pll_state mtl_c10_dp_rbr = {
-	.clock = 162000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0xB4,
@@ -573,7 +572,6 @@ static const struct intel_c10pll_state mtl_c10_dp_rbr = {
 };
 
 static const struct intel_c10pll_state mtl_c10_edp_r216 = {
-	.clock = 216000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0x4,
@@ -599,7 +597,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r216 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_edp_r243 = {
-	.clock = 243000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0x34,
@@ -625,7 +622,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r243 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
-	.clock = 270000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0xF4,
@@ -651,7 +647,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_edp_r324 = {
-	.clock = 324000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0xB4,
@@ -677,7 +672,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r324 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_edp_r432 = {
-	.clock = 432000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0x4,
@@ -703,7 +697,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r432 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
-	.clock = 540000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0xF4,
@@ -729,7 +722,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_edp_r675 = {
-	.clock = 675000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0xB4,
@@ -755,7 +747,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r675 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
-	.clock = 810000,
 	.tx = 0x10,
 	.cmn = 0x21,
 	.pll[0] = 0x34,
@@ -836,7 +827,6 @@ static const struct intel_cx0pll_params mtl_c10_edp_tables[] = {
 
 /* C20 basic DP 1.4 tables */
 static const struct intel_c20pll_state mtl_c20_dp_rbr = {
-	.clock = 162000,
 	.tx = {	0xbe88, /* tx cfg0 */
 		0x5800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -861,7 +851,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
 };
 
 static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
-	.clock = 270000,
 	.tx = {	0xbe88, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -886,7 +875,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
-	.clock = 540000,
 	.tx = {	0xbe88, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -911,7 +899,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
-	.clock = 810000,
 	.tx = {	0xbe88, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -937,7 +924,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
 
 /* C20 basic DP 2.0 tables */
 static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
-	.clock = 1000000, /* 10 Gbps */
 	.tx = {	0xbe21, /* tx cfg0 */
 		0xe800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -961,7 +947,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
-	.clock = 1350000, /* 13.5 Gbps */
 	.tx = {	0xbea0, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -986,7 +971,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
-	.clock = 2000000, /* 20 Gbps */
 	.tx = {	0xbe20, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -1025,7 +1009,6 @@ static const struct intel_cx0pll_params mtl_c20_dp_tables[] = {
  */
 
 static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
-	.clock = 216000,
 	.tx = { 0xbe88,
 		0x4800,
 		0x0000,
@@ -1050,7 +1033,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
-	.clock = 243000,
 	.tx = { 0xbe88,
 		0x4800,
 		0x0000,
@@ -1075,7 +1057,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
-	.clock = 324000,
 	.tx = { 0xbe88,
 		0x4800,
 		0x0000,
@@ -1100,7 +1081,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
-	.clock = 432000,
 	.tx = { 0xbe88,
 		0x4800,
 		0x0000,
@@ -1125,7 +1105,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
-	.clock = 675000,
 	.tx = { 0xbe88,
 		0x4800,
 		0x0000,
@@ -1163,7 +1142,6 @@ static const struct intel_cx0pll_params xe2hpd_c20_edp_tables[] = {
 };
 
 static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
-	.clock = 1350000, /* 13.5 Gbps */
 	.tx = {	0xbea0, /* tx cfg0 */
 		0x4800, /* tx cfg1 */
 		0x0000, /* tx cfg2 */
@@ -1218,7 +1196,6 @@ static const struct intel_cx0pll_params xe3lpd_c20_dp_edp_tables[] = {
  */
 
 static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
-	.clock = 25200,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x4,
@@ -1244,7 +1221,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
-	.clock = 27000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34,
@@ -1270,7 +1246,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
-	.clock = 74250,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4,
@@ -1296,7 +1271,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
-	.clock = 148500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4,
@@ -1322,7 +1296,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
-	.clock = 594000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4,
@@ -1349,7 +1322,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
 
 /* Precomputed C10 HDMI PLL tables */
 static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
-	.clock = 27027,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1359,7 +1331,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
-	.clock = 28320,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1369,7 +1340,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
-	.clock = 30240,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1379,7 +1349,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
-	.clock = 31500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1389,7 +1358,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
-	.clock = 36000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1399,7 +1367,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
-	.clock = 40000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1409,7 +1376,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
-	.clock = 49500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1419,7 +1385,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
-	.clock = 50000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1429,7 +1394,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
-	.clock = 57284,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1439,7 +1403,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
-	.clock = 58000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1449,7 +1412,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
-	.clock = 65000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1459,7 +1421,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
-	.clock = 71000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1469,7 +1430,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
-	.clock = 74176,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1479,7 +1439,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
-	.clock = 75000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1489,7 +1448,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
-	.clock = 78750,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1499,7 +1457,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
-	.clock = 85500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1509,7 +1466,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
-	.clock = 88750,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1519,7 +1475,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
-	.clock = 106500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1529,7 +1484,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
-	.clock = 108000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1539,7 +1493,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
-	.clock = 115500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1549,7 +1502,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
-	.clock = 119000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1559,7 +1511,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
-	.clock = 135000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1569,7 +1520,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
-	.clock = 138500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1579,7 +1529,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
-	.clock = 147160,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1589,7 +1538,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
-	.clock = 148352,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1599,7 +1547,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
-	.clock = 154000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1609,7 +1556,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
-	.clock = 162000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1619,7 +1565,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
-	.clock = 167000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1629,7 +1574,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
-	.clock = 197802,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1639,7 +1583,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
-	.clock = 198000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1649,7 +1592,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
-	.clock = 209800,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1659,7 +1601,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
-	.clock = 241500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1669,7 +1610,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
-	.clock = 262750,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1679,7 +1619,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
-	.clock = 268500,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1689,7 +1628,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
-	.clock = 296703,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1699,7 +1637,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
-	.clock = 297000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1709,7 +1646,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
-	.clock = 319750,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1719,7 +1655,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
-	.clock = 497750,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1729,7 +1664,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
-	.clock = 592000,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1739,7 +1673,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
 };
 
 static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
-	.clock = 593407,
 	.tx = 0x10,
 	.cmn = 0x1,
 	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1798,7 +1731,6 @@ static const struct intel_cx0pll_params mtl_c10_hdmi_tables[] = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
-	.clock = 27000,
 	.tx = {  0xbe88, /* tx cfg0 */
 		  0x9800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1823,7 +1755,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
-	.clock = 74250,
 	.tx = {  0xbe88, /* tx cfg0 */
 		  0x9800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1848,7 +1779,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
-	.clock = 148500,
 	.tx = {  0xbe88, /* tx cfg0 */
 		  0x9800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1873,7 +1803,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
-	.clock = 594000,
 	.tx = {  0xbe88, /* tx cfg0 */
 		  0x9800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1898,7 +1827,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
-	.clock = 300000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1923,7 +1851,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
-	.clock = 600000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1948,7 +1875,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
-	.clock = 800000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1973,7 +1899,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
-	.clock = 1000000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -1998,7 +1923,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
-	.clock = 1200000,
 	.tx = {  0xbe98, /* tx cfg0 */
 		  0x8800, /* tx cfg1 */
 		  0x0000, /* tx cfg2 */
@@ -2338,8 +2262,6 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
-	pll_state->clock = intel_c10pll_calc_port_clock(pll_state);
-
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
 
 	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
@@ -2384,8 +2306,7 @@ static void intel_c10pll_dump_hw_state(struct drm_printer *p,
 	unsigned int multiplier, tx_clk_div;
 
 	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
-	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
-		   hw_state->clock, str_yes_no(fracen));
+	drm_printf(p, "c10pll_hw_state: fracen: %s, ", str_yes_no(fracen));
 
 	if (fracen) {
 		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
@@ -2490,7 +2411,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display,
 	else
 		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
 
-	pll_state->clock	= port_clock;
 	pll_state->tx[0]	= 0xbe88;
 	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(display);
 	pll_state->tx[2]	= 0x0000;
@@ -2839,8 +2759,6 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 		}
 	}
 
-	pll_state->clock = intel_c20pll_calc_port_clock(pll_state);
-
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
@@ -2851,7 +2769,7 @@ static void intel_c20pll_dump_hw_state(struct drm_printer *p,
 {
 	int i;
 
-	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
+	drm_printf(p, "c20pll_hw_state:\n");
 	drm_printf(p,
 		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
 		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5b71c860515f..4cc14ce5eebe 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -241,14 +241,12 @@ struct intel_mpllb_state {
 };
 
 struct intel_c10pll_state {
-	u32 clock; /* in KHz */
 	u8 tx;
 	u8 cmn;
 	u8 pll[20];
 };
 
 struct intel_c20pll_state {
-	u32 clock; /* in kHz */
 	u16 tx[3];
 	u16 cmn[4];
 	union {
@@ -274,7 +272,6 @@ struct intel_cx0pll_state {
 };
 
 struct intel_lt_phy_pll_state {
-	u32 clock; /* in kHz */
 	u8 addr_msb[13];
 	u8 addr_lsb[13];
 	u8 data[13][4];
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index bc73b1466bc4..9a8ea09f6c00 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -59,7 +59,6 @@ struct lt_phy_params {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
-	.clock = 162000,
 	.config = {
 		0x83,
 		0x2d,
@@ -113,7 +112,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
-	.clock = 270000,
 	.config = {
 		0x8b,
 		0x2d,
@@ -167,7 +165,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
-	.clock = 540000,
 	.config = {
 		0x93,
 		0x2d,
@@ -221,7 +218,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
-	.clock = 810000,
 	.config = {
 		0x9b,
 		0x2d,
@@ -275,7 +271,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
-	.clock = 1000000,
 	.config = {
 		0x43,
 		0x2d,
@@ -329,7 +324,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
-	.clock = 1350000,
 	.config = {
 		0xcb,
 		0x2d,
@@ -383,7 +377,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
-	.clock = 2000000,
 	.config = {
 		0x53,
 		0x2d,
@@ -465,7 +458,6 @@ static const struct intel_lt_phy_pll_params xe3plpd_lt_dp_tables[] = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
-	.clock = 216000,
 	.config = {
 		0xa3,
 		0x2d,
@@ -519,7 +511,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
-	.clock = 243000,
 	.config = {
 		0xab,
 		0x2d,
@@ -573,7 +564,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
-	.clock = 324000,
 	.config = {
 		0xb3,
 		0x2d,
@@ -627,7 +617,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
-	.clock = 432000,
 	.config = {
 		0xbb,
 		0x2d,
@@ -681,7 +670,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
-	.clock = 675000,
 	.config = {
 		0xdb,
 		0x2d,
@@ -748,7 +736,6 @@ static const struct intel_lt_phy_pll_params xe3plpd_lt_edp_tables[] = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
-	.clock = 25200,
 	.config = {
 		0x84,
 		0x2d,
@@ -802,7 +789,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
-	.clock = 74250,
 	.config = {
 		0x84,
 		0x2d,
@@ -856,7 +842,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
-	.clock = 148500,
 	.config = {
 		0x84,
 		0x2d,
@@ -910,7 +895,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
 };
 
 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
-	.clock = 594000,
 	.config = {
 		0x84,
 		0x2d,
@@ -2182,7 +2166,6 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state,
 				       struct intel_lt_phy_pll_state *pll_state)
 {
-	struct intel_display *display = to_intel_display(encoder);
 	u8 owned_lane_mask;
 	u8 lane;
 	struct ref_tracker *wakeref;
@@ -2207,8 +2190,6 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 						  LT_PHY_VDR_X_DATAY(i, j));
 	}
 
-	pll_state->clock =
-		intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
@@ -2222,7 +2203,6 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 	struct intel_encoder *encoder;
 	struct intel_lt_phy_pll_state pll_hw_state = {};
 	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
-	int clock;
 	int i, j;
 
 	if (DISPLAY_VER(display) < 35)
@@ -2238,17 +2218,11 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 
 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
 	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
-	clock = intel_lt_phy_calc_port_clock(display, &new_crtc_state->dpll_hw_state.ltpll);
 
 	dig_port = enc_to_dig_port(encoder);
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		return;
 
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
-				 "[CRTC:%d:%s] mismatch in LT PHY: Register CLOCK (expected %d, found %d)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->clock, pll_hw_state.clock);
-
 	for (i = 0; i < 3; i++) {
 		INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i] != pll_sw_state->config[i],
 					 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG%d: (expected 0x%04x, found 0x%04x)",
diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
index a201edceee10..7fe6b4a18213 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
@@ -332,8 +332,6 @@ void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u6
 			      c10_curve_1, c10_curve_2, prescaler_divider,
 			      &pll_params);
 
-	pll_state->clock = pixel_clock;
-
 	pll_state->tx = 0x10;
 	pll_state->cmn = 0x1;
 	pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |
-- 
2.34.1

✗ CI.checkpatch: warning for drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)
URL   : https://patchwork.freedesktop.org/series/159089/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8f50e69d0ce3656564bbdf8b3e213d61470d463f
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 176151407a52e05308cb7390d79af83a1997fe17
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Wed Dec 17 17:19:55 2025 +0200

    drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables
    
    PLL state structure has a member .clock. This is not needed as
    the port clock is possible to calculate from the pll dividers.
    Remove the .clock from the pll state structure.
    
    v2: Keep the pll_state->clock assignment in
        intel_snps_hdmi_pll_compute_mpllb().
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch 605176fe40c828b491a1532367df157529895b87 drm-intel
794c3ab7e7d5 drm/i915/c10: Move C10 port clock calculation
a2283db79d78 drm/i915/c20: Move C20 port clock calculation
94e7889a0215 drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculation
56614d886f2d drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation
375af7865ff8 drm/i915/cx0: Drop encoder from port clock calculation
fccfcdeafc69 drm/i915/cx0: Create macro around pll tables
-:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__state' may be better as '(__state)' to avoid precedence issues
#51: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:794:
+#define __C10PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \
+	.name = __stringify(__state), \
+	.is_c10 = true, \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.c10 = &__state, \
+}

-:59: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__state' may be better as '(__state)' to avoid precedence issues
#59: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:802:
+#define __C20PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
+	.name = __stringify(__state), \
+	.is_c10 = false, \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.c20 = &__state, \
+}

-:68: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#68: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:811:
+#define C10PLL_DP_PARAMS(__clock_rate, __state)         __C10PLL_PARAMS(false, __clock_rate, __state)

-:71: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:814:
+#define C20PLL_DP_PARAMS(__clock_rate, __state)         __C20PLL_PARAMS(false, __clock_rate, __state)

total: 0 errors, 2 warnings, 2 checks, 391 lines checked
72a66cb1a31f drm/i915/lt_phy: Create macro for lt phy pll state
-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__state' may be better as '(__state)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:446:
+#define __LT_PHY_PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
+	.name = __stringify(__state), \
+	.is_hdmi = __is_hdmi, \
+	.clock_rate = __clock_rate, \
+	.state = &__state, \
+}

-:46: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:453:
+#define LT_PHY_PLL_HDMI_PARAMS(__clock_rate, __state)	__LT_PHY_PLL_PARAMS(true, __clock_rate, __state)

-:47: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:454:
+#define LT_PHY_PLL_DP_PARAMS(__clock_rate, __state)	__LT_PHY_PLL_PARAMS(false, __clock_rate, __state)

total: 0 errors, 2 warnings, 1 checks, 125 lines checked
f54167c28033 drm/i915/display: Add helper function for fuzzy clock check
38d3e27a659a drm/i915/cx0: Fix HDMI FRL clock rates
038a989576e2 drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming
8847d02ff871 drm/i915/cx0: Verify C10/C20 pll dividers
-:69: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#69: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3864:
+	intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c10, true);

-:76: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3871:
+	intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);

-:115: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#115: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3910:
+	intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c20, true);

-:123: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#123: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3918:
+	intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);

total: 0 errors, 4 warnings, 0 checks, 152 lines checked
b2ec1adc3c21 drm/i915/lt_phy: Add verification for lt phy pll dividers
-:85: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:2383:
+	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->state, true);

-:93: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#93: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:2391:
+	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);

total: 0 errors, 2 warnings, 0 checks, 86 lines checked
7cf9f46caa30 drm/i915/cx0: Drop C20 25.175 MHz rate
89b4bd46c010 drm/i915/lt_phy: Drop 27.2 MHz rate
176151407a52 drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables

✓ CI.KUnit: success for drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)
URL   : https://patchwork.freedesktop.org/series/159089/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:34:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:34:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[17:35:37] Starting KUnit Kernel (1/1)...
[17:35:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:35:37] ================== guc_buf (11 subtests) ===================
[17:35:37] [PASSED] test_smallest
[17:35:37] [PASSED] test_largest
[17:35:37] [PASSED] test_granular
[17:35:37] [PASSED] test_unique
[17:35:37] [PASSED] test_overlap
[17:35:37] [PASSED] test_reusable
[17:35:37] [PASSED] test_too_big
[17:35:37] [PASSED] test_flush
[17:35:37] [PASSED] test_lookup
[17:35:37] [PASSED] test_data
[17:35:37] [PASSED] test_class
[17:35:37] ===================== [PASSED] guc_buf =====================
[17:35:37] =================== guc_dbm (7 subtests) ===================
[17:35:37] [PASSED] test_empty
[17:35:37] [PASSED] test_default
[17:35:37] ======================== test_size  ========================
[17:35:37] [PASSED] 4
[17:35:37] [PASSED] 8
[17:35:37] [PASSED] 32
[17:35:37] [PASSED] 256
[17:35:37] ==================== [PASSED] test_size ====================
[17:35:37] ======================= test_reuse  ========================
[17:35:37] [PASSED] 4
[17:35:37] [PASSED] 8
[17:35:37] [PASSED] 32
[17:35:37] [PASSED] 256
[17:35:37] =================== [PASSED] test_reuse ====================
[17:35:37] =================== test_range_overlap  ====================
[17:35:37] [PASSED] 4
[17:35:37] [PASSED] 8
[17:35:37] [PASSED] 32
[17:35:37] [PASSED] 256
[17:35:37] =============== [PASSED] test_range_overlap ================
[17:35:37] =================== test_range_compact  ====================
[17:35:37] [PASSED] 4
[17:35:37] [PASSED] 8
[17:35:37] [PASSED] 32
[17:35:37] [PASSED] 256
[17:35:37] =============== [PASSED] test_range_compact ================
[17:35:37] ==================== test_range_spare  =====================
[17:35:37] [PASSED] 4
[17:35:37] [PASSED] 8
[17:35:37] [PASSED] 32
[17:35:37] [PASSED] 256
[17:35:37] ================ [PASSED] test_range_spare =================
[17:35:37] ===================== [PASSED] guc_dbm =====================
[17:35:37] =================== guc_idm (6 subtests) ===================
[17:35:37] [PASSED] bad_init
[17:35:37] [PASSED] no_init
[17:35:37] [PASSED] init_fini
[17:35:37] [PASSED] check_used
[17:35:37] [PASSED] check_quota
[17:35:37] [PASSED] check_all
[17:35:37] ===================== [PASSED] guc_idm =====================
[17:35:37] ================== no_relay (3 subtests) ===================
[17:35:37] [PASSED] xe_drops_guc2pf_if_not_ready
[17:35:37] [PASSED] xe_drops_guc2vf_if_not_ready
[17:35:37] [PASSED] xe_rejects_send_if_not_ready
[17:35:37] ==================== [PASSED] no_relay =====================
[17:35:37] ================== pf_relay (14 subtests) ==================
[17:35:37] [PASSED] pf_rejects_guc2pf_too_short
[17:35:37] [PASSED] pf_rejects_guc2pf_too_long
[17:35:37] [PASSED] pf_rejects_guc2pf_no_payload
[17:35:37] [PASSED] pf_fails_no_payload
[17:35:37] [PASSED] pf_fails_bad_origin
[17:35:37] [PASSED] pf_fails_bad_type
[17:35:37] [PASSED] pf_txn_reports_error
[17:35:37] [PASSED] pf_txn_sends_pf2guc
[17:35:37] [PASSED] pf_sends_pf2guc
[17:35:37] [SKIPPED] pf_loopback_nop
[17:35:37] [SKIPPED] pf_loopback_echo
[17:35:37] [SKIPPED] pf_loopback_fail
[17:35:37] [SKIPPED] pf_loopback_busy
[17:35:37] [SKIPPED] pf_loopback_retry
[17:35:37] ==================== [PASSED] pf_relay =====================
[17:35:37] ================== vf_relay (3 subtests) ===================
[17:35:37] [PASSED] vf_rejects_guc2vf_too_short
[17:35:37] [PASSED] vf_rejects_guc2vf_too_long
[17:35:37] [PASSED] vf_rejects_guc2vf_no_payload
[17:35:37] ==================== [PASSED] vf_relay =====================
[17:35:37] ================ pf_gt_config (6 subtests) =================
[17:35:37] [PASSED] fair_contexts_1vf
[17:35:37] [PASSED] fair_doorbells_1vf
[17:35:37] [PASSED] fair_ggtt_1vf
[17:35:37] ====================== fair_contexts  ======================
[17:35:37] [PASSED] 1 VF
[17:35:37] [PASSED] 2 VFs
[17:35:37] [PASSED] 3 VFs
[17:35:37] [PASSED] 4 VFs
[17:35:37] [PASSED] 5 VFs
[17:35:37] [PASSED] 6 VFs
[17:35:37] [PASSED] 7 VFs
[17:35:37] [PASSED] 8 VFs
[17:35:37] [PASSED] 9 VFs
[17:35:37] [PASSED] 10 VFs
[17:35:37] [PASSED] 11 VFs
[17:35:37] [PASSED] 12 VFs
[17:35:37] [PASSED] 13 VFs
[17:35:37] [PASSED] 14 VFs
[17:35:37] [PASSED] 15 VFs
[17:35:37] [PASSED] 16 VFs
[17:35:37] [PASSED] 17 VFs
[17:35:37] [PASSED] 18 VFs
[17:35:37] [PASSED] 19 VFs
[17:35:37] [PASSED] 20 VFs
[17:35:37] [PASSED] 21 VFs
[17:35:37] [PASSED] 22 VFs
[17:35:37] [PASSED] 23 VFs
[17:35:37] [PASSED] 24 VFs
[17:35:37] [PASSED] 25 VFs
[17:35:37] [PASSED] 26 VFs
[17:35:37] [PASSED] 27 VFs
[17:35:37] [PASSED] 28 VFs
[17:35:37] [PASSED] 29 VFs
[17:35:37] [PASSED] 30 VFs
[17:35:37] [PASSED] 31 VFs
[17:35:37] [PASSED] 32 VFs
[17:35:37] [PASSED] 33 VFs
[17:35:37] [PASSED] 34 VFs
[17:35:37] [PASSED] 35 VFs
[17:35:37] [PASSED] 36 VFs
[17:35:37] [PASSED] 37 VFs
[17:35:37] [PASSED] 38 VFs
[17:35:37] [PASSED] 39 VFs
[17:35:37] [PASSED] 40 VFs
[17:35:37] [PASSED] 41 VFs
[17:35:37] [PASSED] 42 VFs
[17:35:37] [PASSED] 43 VFs
[17:35:37] [PASSED] 44 VFs
[17:35:37] [PASSED] 45 VFs
[17:35:37] [PASSED] 46 VFs
[17:35:37] [PASSED] 47 VFs
[17:35:37] [PASSED] 48 VFs
[17:35:37] [PASSED] 49 VFs
[17:35:37] [PASSED] 50 VFs
[17:35:37] [PASSED] 51 VFs
[17:35:37] [PASSED] 52 VFs
[17:35:37] [PASSED] 53 VFs
[17:35:37] [PASSED] 54 VFs
[17:35:37] [PASSED] 55 VFs
[17:35:37] [PASSED] 56 VFs
[17:35:37] [PASSED] 57 VFs
[17:35:37] [PASSED] 58 VFs
[17:35:37] [PASSED] 59 VFs
[17:35:37] [PASSED] 60 VFs
[17:35:37] [PASSED] 61 VFs
[17:35:37] [PASSED] 62 VFs
[17:35:37] [PASSED] 63 VFs
[17:35:37] ================== [PASSED] fair_contexts ==================
[17:35:37] ===================== fair_doorbells  ======================
[17:35:37] [PASSED] 1 VF
[17:35:37] [PASSED] 2 VFs
[17:35:37] [PASSED] 3 VFs
[17:35:37] [PASSED] 4 VFs
[17:35:37] [PASSED] 5 VFs
[17:35:37] [PASSED] 6 VFs
[17:35:37] [PASSED] 7 VFs
[17:35:37] [PASSED] 8 VFs
[17:35:37] [PASSED] 9 VFs
[17:35:37] [PASSED] 10 VFs
[17:35:37] [PASSED] 11 VFs
[17:35:37] [PASSED] 12 VFs
[17:35:37] [PASSED] 13 VFs
[17:35:37] [PASSED] 14 VFs
[17:35:37] [PASSED] 15 VFs
[17:35:37] [PASSED] 16 VFs
[17:35:37] [PASSED] 17 VFs
[17:35:37] [PASSED] 18 VFs
[17:35:37] [PASSED] 19 VFs
[17:35:37] [PASSED] 20 VFs
[17:35:37] [PASSED] 21 VFs
[17:35:37] [PASSED] 22 VFs
[17:35:37] [PASSED] 23 VFs
[17:35:37] [PASSED] 24 VFs
[17:35:37] [PASSED] 25 VFs
[17:35:37] [PASSED] 26 VFs
[17:35:37] [PASSED] 27 VFs
[17:35:37] [PASSED] 28 VFs
[17:35:37] [PASSED] 29 VFs
[17:35:37] [PASSED] 30 VFs
[17:35:37] [PASSED] 31 VFs
[17:35:37] [PASSED] 32 VFs
[17:35:37] [PASSED] 33 VFs
[17:35:37] [PASSED] 34 VFs
[17:35:37] [PASSED] 35 VFs
[17:35:37] [PASSED] 36 VFs
[17:35:37] [PASSED] 37 VFs
[17:35:37] [PASSED] 38 VFs
[17:35:37] [PASSED] 39 VFs
[17:35:37] [PASSED] 40 VFs
[17:35:37] [PASSED] 41 VFs
[17:35:37] [PASSED] 42 VFs
[17:35:37] [PASSED] 43 VFs
[17:35:37] [PASSED] 44 VFs
[17:35:37] [PASSED] 45 VFs
[17:35:37] [PASSED] 46 VFs
[17:35:37] [PASSED] 47 VFs
[17:35:37] [PASSED] 48 VFs
[17:35:37] [PASSED] 49 VFs
[17:35:37] [PASSED] 50 VFs
[17:35:37] [PASSED] 51 VFs
[17:35:37] [PASSED] 52 VFs
[17:35:37] [PASSED] 53 VFs
[17:35:37] [PASSED] 54 VFs
[17:35:37] [PASSED] 55 VFs
[17:35:37] [PASSED] 56 VFs
[17:35:37] [PASSED] 57 VFs
[17:35:37] [PASSED] 58 VFs
[17:35:37] [PASSED] 59 VFs
[17:35:37] [PASSED] 60 VFs
[17:35:37] [PASSED] 61 VFs
[17:35:37] [PASSED] 62 VFs
[17:35:37] [PASSED] 63 VFs
[17:35:37] ================= [PASSED] fair_doorbells ==================
[17:35:37] ======================== fair_ggtt  ========================
[17:35:37] [PASSED] 1 VF
[17:35:37] [PASSED] 2 VFs
[17:35:37] [PASSED] 3 VFs
[17:35:37] [PASSED] 4 VFs
[17:35:37] [PASSED] 5 VFs
[17:35:37] [PASSED] 6 VFs
[17:35:37] [PASSED] 7 VFs
[17:35:37] [PASSED] 8 VFs
[17:35:37] [PASSED] 9 VFs
[17:35:37] [PASSED] 10 VFs
[17:35:37] [PASSED] 11 VFs
[17:35:37] [PASSED] 12 VFs
[17:35:37] [PASSED] 13 VFs
[17:35:37] [PASSED] 14 VFs
[17:35:37] [PASSED] 15 VFs
[17:35:37] [PASSED] 16 VFs
[17:35:37] [PASSED] 17 VFs
[17:35:37] [PASSED] 18 VFs
[17:35:37] [PASSED] 19 VFs
[17:35:37] [PASSED] 20 VFs
[17:35:37] [PASSED] 21 VFs
[17:35:37] [PASSED] 22 VFs
[17:35:37] [PASSED] 23 VFs
[17:35:37] [PASSED] 24 VFs
[17:35:37] [PASSED] 25 VFs
[17:35:37] [PASSED] 26 VFs
[17:35:37] [PASSED] 27 VFs
[17:35:37] [PASSED] 28 VFs
[17:35:37] [PASSED] 29 VFs
[17:35:37] [PASSED] 30 VFs
[17:35:37] [PASSED] 31 VFs
[17:35:37] [PASSED] 32 VFs
[17:35:37] [PASSED] 33 VFs
[17:35:37] [PASSED] 34 VFs
[17:35:37] [PASSED] 35 VFs
[17:35:37] [PASSED] 36 VFs
[17:35:37] [PASSED] 37 VFs
[17:35:37] [PASSED] 38 VFs
[17:35:37] [PASSED] 39 VFs
[17:35:37] [PASSED] 40 VFs
[17:35:37] [PASSED] 41 VFs
[17:35:37] [PASSED] 42 VFs
[17:35:37] [PASSED] 43 VFs
[17:35:37] [PASSED] 44 VFs
[17:35:37] [PASSED] 45 VFs
[17:35:37] [PASSED] 46 VFs
[17:35:37] [PASSED] 47 VFs
[17:35:37] [PASSED] 48 VFs
[17:35:37] [PASSED] 49 VFs
[17:35:37] [PASSED] 50 VFs
[17:35:37] [PASSED] 51 VFs
[17:35:37] [PASSED] 52 VFs
[17:35:37] [PASSED] 53 VFs
[17:35:37] [PASSED] 54 VFs
[17:35:37] [PASSED] 55 VFs
[17:35:37] [PASSED] 56 VFs
[17:35:37] [PASSED] 57 VFs
[17:35:37] [PASSED] 58 VFs
[17:35:37] [PASSED] 59 VFs
[17:35:37] [PASSED] 60 VFs
[17:35:37] [PASSED] 61 VFs
[17:35:37] [PASSED] 62 VFs
[17:35:37] [PASSED] 63 VFs
[17:35:37] ==================== [PASSED] fair_ggtt ====================
[17:35:37] ================== [PASSED] pf_gt_config ===================
[17:35:37] ===================== lmtt (1 subtest) =====================
[17:35:37] ======================== test_ops  =========================
[17:35:37] [PASSED] 2-level
[17:35:37] [PASSED] multi-level
[17:35:37] ==================== [PASSED] test_ops =====================
[17:35:37] ====================== [PASSED] lmtt =======================
[17:35:37] ================= pf_service (11 subtests) =================
[17:35:37] [PASSED] pf_negotiate_any
[17:35:37] [PASSED] pf_negotiate_base_match
[17:35:37] [PASSED] pf_negotiate_base_newer
[17:35:37] [PASSED] pf_negotiate_base_next
[17:35:37] [SKIPPED] pf_negotiate_base_older
[17:35:37] [PASSED] pf_negotiate_base_prev
[17:35:37] [PASSED] pf_negotiate_latest_match
[17:35:37] [PASSED] pf_negotiate_latest_newer
[17:35:37] [PASSED] pf_negotiate_latest_next
[17:35:37] [SKIPPED] pf_negotiate_latest_older
[17:35:37] [SKIPPED] pf_negotiate_latest_prev
[17:35:37] =================== [PASSED] pf_service ====================
[17:35:37] ================= xe_guc_g2g (2 subtests) ==================
[17:35:37] ============== xe_live_guc_g2g_kunit_default  ==============
[17:35:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:35:37] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:35:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:35:37] =================== [SKIPPED] xe_guc_g2g ===================
[17:35:37] =================== xe_mocs (2 subtests) ===================
[17:35:37] ================ xe_live_mocs_kernel_kunit  ================
[17:35:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:35:37] ================ xe_live_mocs_reset_kunit  =================
[17:35:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:35:37] ==================== [SKIPPED] xe_mocs =====================
[17:35:37] ================= xe_migrate (2 subtests) ==================
[17:35:37] ================= xe_migrate_sanity_kunit  =================
[17:35:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:35:37] ================== xe_validate_ccs_kunit  ==================
[17:35:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:35:37] =================== [SKIPPED] xe_migrate ===================
[17:35:37] ================== xe_dma_buf (1 subtest) ==================
[17:35:37] ==================== xe_dma_buf_kunit  =====================
[17:35:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:35:37] =================== [SKIPPED] xe_dma_buf ===================
[17:35:37] ================= xe_bo_shrink (1 subtest) =================
[17:35:37] =================== xe_bo_shrink_kunit  ====================
[17:35:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:35:37] ================== [SKIPPED] xe_bo_shrink ==================
[17:35:37] ==================== xe_bo (2 subtests) ====================
[17:35:37] ================== xe_ccs_migrate_kunit  ===================
[17:35:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:35:37] ==================== xe_bo_evict_kunit  ====================
[17:35:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:35:37] ===================== [SKIPPED] xe_bo ======================
[17:35:37] ==================== args (11 subtests) ====================
[17:35:37] [PASSED] count_args_test
[17:35:37] [PASSED] call_args_example
[17:35:37] [PASSED] call_args_test
[17:35:37] [PASSED] drop_first_arg_example
[17:35:37] [PASSED] drop_first_arg_test
[17:35:37] [PASSED] first_arg_example
[17:35:37] [PASSED] first_arg_test
[17:35:37] [PASSED] last_arg_example
[17:35:37] [PASSED] last_arg_test
[17:35:37] [PASSED] pick_arg_example
[17:35:37] [PASSED] sep_comma_example
[17:35:37] ====================== [PASSED] args =======================
[17:35:37] =================== xe_pci (3 subtests) ====================
[17:35:37] ==================== check_graphics_ip  ====================
[17:35:37] [PASSED] 12.00 Xe_LP
[17:35:37] [PASSED] 12.10 Xe_LP+
[17:35:37] [PASSED] 12.55 Xe_HPG
[17:35:37] [PASSED] 12.60 Xe_HPC
[17:35:37] [PASSED] 12.70 Xe_LPG
[17:35:37] [PASSED] 12.71 Xe_LPG
[17:35:37] [PASSED] 12.74 Xe_LPG+
[17:35:37] [PASSED] 20.01 Xe2_HPG
[17:35:37] [PASSED] 20.02 Xe2_HPG
[17:35:37] [PASSED] 20.04 Xe2_LPG
[17:35:37] [PASSED] 30.00 Xe3_LPG
[17:35:37] [PASSED] 30.01 Xe3_LPG
[17:35:37] [PASSED] 30.03 Xe3_LPG
[17:35:37] [PASSED] 30.04 Xe3_LPG
[17:35:37] [PASSED] 30.05 Xe3_LPG
[17:35:37] [PASSED] 35.11 Xe3p_XPC
[17:35:37] ================ [PASSED] check_graphics_ip ================
[17:35:37] ===================== check_media_ip  ======================
[17:35:37] [PASSED] 12.00 Xe_M
[17:35:37] [PASSED] 12.55 Xe_HPM
[17:35:37] [PASSED] 13.00 Xe_LPM+
[17:35:37] [PASSED] 13.01 Xe2_HPM
[17:35:37] [PASSED] 20.00 Xe2_LPM
[17:35:37] [PASSED] 30.00 Xe3_LPM
[17:35:37] [PASSED] 30.02 Xe3_LPM
[17:35:37] [PASSED] 35.00 Xe3p_LPM
[17:35:37] [PASSED] 35.03 Xe3p_HPM
[17:35:37] ================= [PASSED] check_media_ip ==================
[17:35:37] =================== check_platform_desc  ===================
[17:35:37] [PASSED] 0x9A60 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A68 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A70 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A40 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A49 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A59 (TIGERLAKE)
[17:35:37] [PASSED] 0x9A78 (TIGERLAKE)
[17:35:37] [PASSED] 0x9AC0 (TIGERLAKE)
[17:35:37] [PASSED] 0x9AC9 (TIGERLAKE)
[17:35:37] [PASSED] 0x9AD9 (TIGERLAKE)
[17:35:37] [PASSED] 0x9AF8 (TIGERLAKE)
[17:35:37] [PASSED] 0x4C80 (ROCKETLAKE)
[17:35:37] [PASSED] 0x4C8A (ROCKETLAKE)
[17:35:37] [PASSED] 0x4C8B (ROCKETLAKE)
[17:35:37] [PASSED] 0x4C8C (ROCKETLAKE)
[17:35:37] [PASSED] 0x4C90 (ROCKETLAKE)
[17:35:37] [PASSED] 0x4C9A (ROCKETLAKE)
[17:35:37] [PASSED] 0x4680 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4682 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4688 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x468A (ALDERLAKE_S)
[17:35:37] [PASSED] 0x468B (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4690 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4692 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4693 (ALDERLAKE_S)
[17:35:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46AA (ALDERLAKE_P)
[17:35:37] [PASSED] 0x462A (ALDERLAKE_P)
[17:35:37] [PASSED] 0x4626 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x4628 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[17:35:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:35:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:35:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:35:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:35:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:35:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:35:37] [PASSED] 0xA721 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA720 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:35:37] [PASSED] 0xA780 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA781 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA782 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA783 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA788 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA789 (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA78A (ALDERLAKE_S)
[17:35:37] [PASSED] 0xA78B (ALDERLAKE_S)
[17:35:37] [PASSED] 0x4905 (DG1)
[17:35:37] [PASSED] 0x4906 (DG1)
[17:35:37] [PASSED] 0x4907 (DG1)
[17:35:37] [PASSED] 0x4908 (DG1)
[17:35:37] [PASSED] 0x4909 (DG1)
[17:35:37] [PASSED] 0x56C0 (DG2)
[17:35:37] [PASSED] 0x56C2 (DG2)
[17:35:37] [PASSED] 0x56C1 (DG2)
[17:35:37] [PASSED] 0x7D51 (METEORLAKE)
[17:35:37] [PASSED] 0x7DD1 (METEORLAKE)
[17:35:37] [PASSED] 0x7D41 (METEORLAKE)
[17:35:37] [PASSED] 0x7D67 (METEORLAKE)
[17:35:37] [PASSED] 0xB640 (METEORLAKE)
[17:35:37] [PASSED] 0x56A0 (DG2)
[17:35:37] [PASSED] 0x56A1 (DG2)
[17:35:37] [PASSED] 0x56A2 (DG2)
[17:35:37] [PASSED] 0x56BE (DG2)
[17:35:37] [PASSED] 0x56BF (DG2)
[17:35:37] [PASSED] 0x5690 (DG2)
[17:35:37] [PASSED] 0x5691 (DG2)
[17:35:37] [PASSED] 0x5692 (DG2)
[17:35:37] [PASSED] 0x56A5 (DG2)
[17:35:37] [PASSED] 0x56A6 (DG2)
[17:35:37] [PASSED] 0x56B0 (DG2)
[17:35:37] [PASSED] 0x56B1 (DG2)
[17:35:37] [PASSED] 0x56BA (DG2)
[17:35:37] [PASSED] 0x56BB (DG2)
[17:35:37] [PASSED] 0x56BC (DG2)
[17:35:37] [PASSED] 0x56BD (DG2)
[17:35:37] [PASSED] 0x5693 (DG2)
[17:35:37] [PASSED] 0x5694 (DG2)
[17:35:37] [PASSED] 0x5695 (DG2)
[17:35:37] [PASSED] 0x56A3 (DG2)
[17:35:37] [PASSED] 0x56A4 (DG2)
[17:35:37] [PASSED] 0x56B2 (DG2)
[17:35:37] [PASSED] 0x56B3 (DG2)
[17:35:37] [PASSED] 0x5696 (DG2)
[17:35:37] [PASSED] 0x5697 (DG2)
[17:35:37] [PASSED] 0xB69 (PVC)
[17:35:37] [PASSED] 0xB6E (PVC)
[17:35:37] [PASSED] 0xBD4 (PVC)
[17:35:37] [PASSED] 0xBD5 (PVC)
[17:35:37] [PASSED] 0xBD6 (PVC)
[17:35:37] [PASSED] 0xBD7 (PVC)
[17:35:37] [PASSED] 0xBD8 (PVC)
[17:35:37] [PASSED] 0xBD9 (PVC)
[17:35:37] [PASSED] 0xBDA (PVC)
[17:35:37] [PASSED] 0xBDB (PVC)
[17:35:37] [PASSED] 0xBE0 (PVC)
[17:35:37] [PASSED] 0xBE1 (PVC)
[17:35:37] [PASSED] 0xBE5 (PVC)
[17:35:37] [PASSED] 0x7D40 (METEORLAKE)
[17:35:37] [PASSED] 0x7D45 (METEORLAKE)
[17:35:37] [PASSED] 0x7D55 (METEORLAKE)
[17:35:37] [PASSED] 0x7D60 (METEORLAKE)
[17:35:37] [PASSED] 0x7DD5 (METEORLAKE)
[17:35:37] [PASSED] 0x6420 (LUNARLAKE)
[17:35:37] [PASSED] 0x64A0 (LUNARLAKE)
[17:35:37] [PASSED] 0x64B0 (LUNARLAKE)
[17:35:37] [PASSED] 0xE202 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE209 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE20B (BATTLEMAGE)
[17:35:37] [PASSED] 0xE20C (BATTLEMAGE)
[17:35:37] [PASSED] 0xE20D (BATTLEMAGE)
[17:35:37] [PASSED] 0xE210 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE211 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE212 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE216 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE220 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE221 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE222 (BATTLEMAGE)
[17:35:37] [PASSED] 0xE223 (BATTLEMAGE)
[17:35:37] [PASSED] 0xB080 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB081 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB082 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB083 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB084 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB085 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB086 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB087 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB08F (PANTHERLAKE)
[17:35:37] [PASSED] 0xB090 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:35:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:35:37] [PASSED] 0xFD80 (PANTHERLAKE)
[17:35:37] [PASSED] 0xFD81 (PANTHERLAKE)
[17:35:37] [PASSED] 0xD740 (NOVALAKE_S)
[17:35:37] [PASSED] 0xD741 (NOVALAKE_S)
[17:35:37] [PASSED] 0xD742 (NOVALAKE_S)
[17:35:37] [PASSED] 0xD743 (NOVALAKE_S)
[17:35:37] [PASSED] 0xD744 (NOVALAKE_S)
[17:35:37] [PASSED] 0xD745 (NOVALAKE_S)
[17:35:37] [PASSED] 0x674C (CRESCENTISLAND)
[17:35:37] =============== [PASSED] check_platform_desc ===============
[17:35:37] ===================== [PASSED] xe_pci ======================
[17:35:37] =================== xe_rtp (2 subtests) ====================
[17:35:37] =============== xe_rtp_process_to_sr_tests  ================
[17:35:37] [PASSED] coalesce-same-reg
[17:35:37] [PASSED] no-match-no-add
[17:35:37] [PASSED] match-or
[17:35:37] [PASSED] match-or-xfail
[17:35:37] [PASSED] no-match-no-add-multiple-rules
[17:35:37] [PASSED] two-regs-two-entries
[17:35:37] [PASSED] clr-one-set-other
[17:35:37] [PASSED] set-field
[17:35:37] [PASSED] conflict-duplicate
[17:35:37] [PASSED] conflict-not-disjoint
[17:35:37] [PASSED] conflict-reg-type
[17:35:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:35:37] ================== xe_rtp_process_tests  ===================
[17:35:37] [PASSED] active1
[17:35:37] [PASSED] active2
[17:35:37] [PASSED] active-inactive
[17:35:37] [PASSED] inactive-active
[17:35:37] [PASSED] inactive-1st_or_active-inactive
[17:35:37] [PASSED] inactive-2nd_or_active-inactive
[17:35:37] [PASSED] inactive-last_or_active-inactive
[17:35:37] [PASSED] inactive-no_or_active-inactive
[17:35:37] ============== [PASSED] xe_rtp_process_tests ===============
[17:35:37] ===================== [PASSED] xe_rtp ======================
[17:35:37] ==================== xe_wa (1 subtest) =====================
[17:35:37] ======================== xe_wa_gt  =========================
[17:35:37] [PASSED] TIGERLAKE B0
[17:35:37] [PASSED] DG1 A0
[17:35:37] [PASSED] DG1 B0
[17:35:37] [PASSED] ALDERLAKE_S A0
[17:35:37] [PASSED] ALDERLAKE_S B0
[17:35:37] [PASSED] ALDERLAKE_S C0
[17:35:37] [PASSED] ALDERLAKE_S D0
[17:35:37] [PASSED] ALDERLAKE_P A0
[17:35:37] [PASSED] ALDERLAKE_P B0
[17:35:37] [PASSED] ALDERLAKE_P C0
[17:35:37] [PASSED] ALDERLAKE_S RPLS D0
[17:35:37] [PASSED] ALDERLAKE_P RPLU E0
[17:35:37] [PASSED] DG2 G10 C0
[17:35:37] [PASSED] DG2 G11 B1
[17:35:37] [PASSED] DG2 G12 A1
[17:35:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:35:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:35:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:35:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:35:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:35:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:35:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:35:37] ==================== [PASSED] xe_wa_gt =====================
[17:35:37] ====================== [PASSED] xe_wa ======================
[17:35:37] ============================================================
[17:35:37] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[17:35:37] Elapsed time: 43.718s total, 4.692s configuring, 38.559s building, 0.437s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:35:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:35:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[17:36:09] Starting KUnit Kernel (1/1)...
[17:36:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:36:09] ============ drm_test_pick_cmdline (2 subtests) ============
[17:36:09] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:36:09] =============== drm_test_pick_cmdline_named  ===============
[17:36:09] [PASSED] NTSC
[17:36:09] [PASSED] NTSC-J
[17:36:09] [PASSED] PAL
[17:36:09] [PASSED] PAL-M
[17:36:09] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:36:09] ============== [PASSED] drm_test_pick_cmdline ==============
[17:36:09] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:36:09] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:36:09] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:36:09] =========== drm_validate_clone_mode (2 subtests) ===========
[17:36:09] ============== drm_test_check_in_clone_mode  ===============
[17:36:09] [PASSED] in_clone_mode
[17:36:09] [PASSED] not_in_clone_mode
[17:36:09] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:36:09] =============== drm_test_check_valid_clones  ===============
[17:36:09] [PASSED] not_in_clone_mode
[17:36:09] [PASSED] valid_clone
[17:36:09] [PASSED] invalid_clone
[17:36:09] =========== [PASSED] drm_test_check_valid_clones ===========
[17:36:09] ============= [PASSED] drm_validate_clone_mode =============
[17:36:09] ============= drm_validate_modeset (1 subtest) =============
[17:36:09] [PASSED] drm_test_check_connector_changed_modeset
[17:36:09] ============== [PASSED] drm_validate_modeset ===============
[17:36:09] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:36:09] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:36:09] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:36:09] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:36:09] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:36:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:36:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:36:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:36:09] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:36:09] ============== drm_bridge_alloc (2 subtests) ===============
[17:36:09] [PASSED] drm_test_drm_bridge_alloc_basic
[17:36:09] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:36:09] ================ [PASSED] drm_bridge_alloc =================
[17:36:09] ================== drm_buddy (8 subtests) ==================
[17:36:09] [PASSED] drm_test_buddy_alloc_limit
[17:36:09] [PASSED] drm_test_buddy_alloc_optimistic
[17:36:09] [PASSED] drm_test_buddy_alloc_pessimistic
[17:36:09] [PASSED] drm_test_buddy_alloc_pathological
[17:36:09] [PASSED] drm_test_buddy_alloc_contiguous
[17:36:09] [PASSED] drm_test_buddy_alloc_clear
[17:36:10] [PASSED] drm_test_buddy_alloc_range_bias
[17:36:10] [PASSED] drm_test_buddy_fragmentation_performance
[17:36:10] ==================== [PASSED] drm_buddy ====================
[17:36:10] ============= drm_cmdline_parser (40 subtests) =============
[17:36:10] [PASSED] drm_test_cmdline_force_d_only
[17:36:10] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:36:10] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:36:10] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:36:10] [PASSED] drm_test_cmdline_force_e_only
[17:36:10] [PASSED] drm_test_cmdline_res
[17:36:10] [PASSED] drm_test_cmdline_res_vesa
[17:36:10] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:36:10] [PASSED] drm_test_cmdline_res_rblank
[17:36:10] [PASSED] drm_test_cmdline_res_bpp
[17:36:10] [PASSED] drm_test_cmdline_res_refresh
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:36:10] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:36:10] [PASSED] drm_test_cmdline_res_margins_force_on
[17:36:10] [PASSED] drm_test_cmdline_res_vesa_margins
[17:36:10] [PASSED] drm_test_cmdline_name
[17:36:10] [PASSED] drm_test_cmdline_name_bpp
[17:36:10] [PASSED] drm_test_cmdline_name_option
[17:36:10] [PASSED] drm_test_cmdline_name_bpp_option
[17:36:10] [PASSED] drm_test_cmdline_rotate_0
[17:36:10] [PASSED] drm_test_cmdline_rotate_90
[17:36:10] [PASSED] drm_test_cmdline_rotate_180
[17:36:10] [PASSED] drm_test_cmdline_rotate_270
[17:36:10] [PASSED] drm_test_cmdline_hmirror
[17:36:10] [PASSED] drm_test_cmdline_vmirror
[17:36:10] [PASSED] drm_test_cmdline_margin_options
[17:36:10] [PASSED] drm_test_cmdline_multiple_options
[17:36:10] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:36:10] [PASSED] drm_test_cmdline_extra_and_option
[17:36:10] [PASSED] drm_test_cmdline_freestanding_options
[17:36:10] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:36:10] [PASSED] drm_test_cmdline_panel_orientation
[17:36:10] ================ drm_test_cmdline_invalid  =================
[17:36:10] [PASSED] margin_only
[17:36:10] [PASSED] interlace_only
[17:36:10] [PASSED] res_missing_x
[17:36:10] [PASSED] res_missing_y
[17:36:10] [PASSED] res_bad_y
[17:36:10] [PASSED] res_missing_y_bpp
[17:36:10] [PASSED] res_bad_bpp
[17:36:10] [PASSED] res_bad_refresh
[17:36:10] [PASSED] res_bpp_refresh_force_on_off
[17:36:10] [PASSED] res_invalid_mode
[17:36:10] [PASSED] res_bpp_wrong_place_mode
[17:36:10] [PASSED] name_bpp_refresh
[17:36:10] [PASSED] name_refresh
[17:36:10] [PASSED] name_refresh_wrong_mode
[17:36:10] [PASSED] name_refresh_invalid_mode
[17:36:10] [PASSED] rotate_multiple
[17:36:10] [PASSED] rotate_invalid_val
[17:36:10] [PASSED] rotate_truncated
[17:36:10] [PASSED] invalid_option
[17:36:10] [PASSED] invalid_tv_option
[17:36:10] [PASSED] truncated_tv_option
[17:36:10] ============ [PASSED] drm_test_cmdline_invalid =============
[17:36:10] =============== drm_test_cmdline_tv_options  ===============
[17:36:10] [PASSED] NTSC
[17:36:10] [PASSED] NTSC_443
[17:36:10] [PASSED] NTSC_J
[17:36:10] [PASSED] PAL
[17:36:10] [PASSED] PAL_M
[17:36:10] [PASSED] PAL_N
[17:36:10] [PASSED] SECAM
[17:36:10] [PASSED] MONO_525
[17:36:10] [PASSED] MONO_625
[17:36:10] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:36:10] =============== [PASSED] drm_cmdline_parser ================
[17:36:10] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:36:10] [PASSED] drm_test_connector_hdmi_init_valid
[17:36:10] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:36:10] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:36:10] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:36:10] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:36:10] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:36:10] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:36:10] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:36:10] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:36:10] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:36:10] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:36:10] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:36:10] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:36:10] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:36:10] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:36:10] [PASSED] drm_test_connector_hdmi_init_null_product
[17:36:10] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:36:10] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:36:10] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:36:10] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:36:10] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:36:10] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:36:10] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:36:10] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:36:10] [PASSED] HDMI-A
[17:36:10] [PASSED] HDMI-B
[17:36:10] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:36:10] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:36:10] [PASSED] Unknown
[17:36:10] [PASSED] VGA
[17:36:10] [PASSED] DVI-I
[17:36:10] [PASSED] DVI-D
[17:36:10] [PASSED] DVI-A
[17:36:10] [PASSED] Composite
[17:36:10] [PASSED] SVIDEO
[17:36:10] [PASSED] LVDS
[17:36:10] [PASSED] Component
[17:36:10] [PASSED] DIN
[17:36:10] [PASSED] DP
[17:36:10] [PASSED] TV
[17:36:10] [PASSED] eDP
[17:36:10] [PASSED] Virtual
[17:36:10] [PASSED] DSI
[17:36:10] [PASSED] DPI
[17:36:10] [PASSED] Writeback
[17:36:10] [PASSED] SPI
[17:36:10] [PASSED] USB
[17:36:10] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:36:10] ============ [PASSED] drmm_connector_hdmi_init =============
[17:36:10] ============= drmm_connector_init (3 subtests) =============
[17:36:10] [PASSED] drm_test_drmm_connector_init
[17:36:10] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:36:10] ========= drm_test_drmm_connector_init_type_valid  =========
[17:36:10] [PASSED] Unknown
[17:36:10] [PASSED] VGA
[17:36:10] [PASSED] DVI-I
[17:36:10] [PASSED] DVI-D
[17:36:10] [PASSED] DVI-A
[17:36:10] [PASSED] Composite
[17:36:10] [PASSED] SVIDEO
[17:36:10] [PASSED] LVDS
[17:36:10] [PASSED] Component
[17:36:10] [PASSED] DIN
[17:36:10] [PASSED] DP
[17:36:10] [PASSED] HDMI-A
[17:36:10] [PASSED] HDMI-B
[17:36:10] [PASSED] TV
[17:36:10] [PASSED] eDP
[17:36:10] [PASSED] Virtual
[17:36:10] [PASSED] DSI
[17:36:10] [PASSED] DPI
[17:36:10] [PASSED] Writeback
[17:36:10] [PASSED] SPI
[17:36:10] [PASSED] USB
[17:36:10] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:36:10] =============== [PASSED] drmm_connector_init ===============
[17:36:10] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_init
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:36:10] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:36:10] [PASSED] Unknown
[17:36:10] [PASSED] VGA
[17:36:10] [PASSED] DVI-I
[17:36:10] [PASSED] DVI-D
[17:36:10] [PASSED] DVI-A
[17:36:10] [PASSED] Composite
[17:36:10] [PASSED] SVIDEO
[17:36:10] [PASSED] LVDS
[17:36:10] [PASSED] Component
[17:36:10] [PASSED] DIN
[17:36:10] [PASSED] DP
[17:36:10] [PASSED] HDMI-A
[17:36:10] [PASSED] HDMI-B
[17:36:10] [PASSED] TV
[17:36:10] [PASSED] eDP
[17:36:10] [PASSED] Virtual
[17:36:10] [PASSED] DSI
[17:36:10] [PASSED] DPI
[17:36:10] [PASSED] Writeback
[17:36:10] [PASSED] SPI
[17:36:10] [PASSED] USB
[17:36:10] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:36:10] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:36:10] [PASSED] Unknown
[17:36:10] [PASSED] VGA
[17:36:10] [PASSED] DVI-I
[17:36:10] [PASSED] DVI-D
[17:36:10] [PASSED] DVI-A
[17:36:10] [PASSED] Composite
[17:36:10] [PASSED] SVIDEO
[17:36:10] [PASSED] LVDS
[17:36:10] [PASSED] Component
[17:36:10] [PASSED] DIN
[17:36:10] [PASSED] DP
[17:36:10] [PASSED] HDMI-A
[17:36:10] [PASSED] HDMI-B
[17:36:10] [PASSED] TV
[17:36:10] [PASSED] eDP
[17:36:10] [PASSED] Virtual
[17:36:10] [PASSED] DSI
[17:36:10] [PASSED] DPI
[17:36:10] [PASSED] Writeback
[17:36:10] [PASSED] SPI
[17:36:10] [PASSED] USB
[17:36:10] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:36:10] =========== [PASSED] drm_connector_dynamic_init ============
[17:36:10] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:36:10] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:36:10] ======= drm_connector_dynamic_register (7 subtests) ========
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:36:10] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:36:10] ========= [PASSED] drm_connector_dynamic_register ==========
[17:36:10] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:36:10] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:36:10] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:36:10] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:36:10] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:36:10] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:36:10] [PASSED] NTSC
[17:36:10] [PASSED] NTSC-443
[17:36:10] [PASSED] NTSC-J
[17:36:10] [PASSED] PAL
[17:36:10] [PASSED] PAL-M
[17:36:10] [PASSED] PAL-N
[17:36:10] [PASSED] SECAM
[17:36:10] [PASSED] Mono
[17:36:10] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:36:10] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:36:10] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:36:10] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:36:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:36:10] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:36:10] [PASSED] VIC 96
[17:36:10] [PASSED] VIC 97
[17:36:10] [PASSED] VIC 101
[17:36:10] [PASSED] VIC 102
[17:36:10] [PASSED] VIC 106
[17:36:10] [PASSED] VIC 107
[17:36:10] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:36:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:36:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:36:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:36:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:36:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:36:10] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:36:10] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:36:10] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:36:10] [PASSED] Automatic
[17:36:10] [PASSED] Full
[17:36:10] [PASSED] Limited 16:235
[17:36:10] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:36:10] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:36:10] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:36:10] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:36:10] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:36:10] [PASSED] RGB
[17:36:10] [PASSED] YUV 4:2:0
[17:36:10] [PASSED] YUV 4:2:2
[17:36:10] [PASSED] YUV 4:4:4
[17:36:10] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:36:10] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:36:10] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:36:10] ============= drm_damage_helper (21 subtests) ==============
[17:36:10] [PASSED] drm_test_damage_iter_no_damage
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:36:10] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:36:10] [PASSED] drm_test_damage_iter_simple_damage
[17:36:10] [PASSED] drm_test_damage_iter_single_damage
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:36:10] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:36:10] [PASSED] drm_test_damage_iter_damage
[17:36:10] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:36:10] [PASSED] drm_test_damage_iter_damage_one_outside
[17:36:10] [PASSED] drm_test_damage_iter_damage_src_moved
[17:36:10] [PASSED] drm_test_damage_iter_damage_not_visible
[17:36:10] ================ [PASSED] drm_damage_helper ================
[17:36:10] ============== drm_dp_mst_helper (3 subtests) ==============
[17:36:10] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:36:10] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:36:10] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:36:10] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:36:10] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:36:10] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:36:10] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:36:10] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:36:10] [PASSED] Link rate 2000000 lane count 4
[17:36:10] [PASSED] Link rate 2000000 lane count 2
[17:36:10] [PASSED] Link rate 2000000 lane count 1
[17:36:10] [PASSED] Link rate 1350000 lane count 4
[17:36:10] [PASSED] Link rate 1350000 lane count 2
[17:36:10] [PASSED] Link rate 1350000 lane count 1
[17:36:10] [PASSED] Link rate 1000000 lane count 4
[17:36:10] [PASSED] Link rate 1000000 lane count 2
[17:36:10] [PASSED] Link rate 1000000 lane count 1
[17:36:10] [PASSED] Link rate 810000 lane count 4
[17:36:10] [PASSED] Link rate 810000 lane count 2
[17:36:10] [PASSED] Link rate 810000 lane count 1
[17:36:10] [PASSED] Link rate 540000 lane count 4
[17:36:10] [PASSED] Link rate 540000 lane count 2
[17:36:10] [PASSED] Link rate 540000 lane count 1
[17:36:10] [PASSED] Link rate 270000 lane count 4
[17:36:10] [PASSED] Link rate 270000 lane count 2
[17:36:10] [PASSED] Link rate 270000 lane count 1
[17:36:10] [PASSED] Link rate 162000 lane count 4
[17:36:10] [PASSED] Link rate 162000 lane count 2
[17:36:10] [PASSED] Link rate 162000 lane count 1
[17:36:10] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:36:10] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:36:10] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:36:10] [PASSED] DP_POWER_UP_PHY with port number
[17:36:10] [PASSED] DP_POWER_DOWN_PHY with port number
[17:36:10] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:36:10] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:36:10] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:36:10] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:36:10] [PASSED] DP_QUERY_PAYLOAD with port number
[17:36:10] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:36:10] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:36:10] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:36:10] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:36:10] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:36:10] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:36:10] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:36:10] [PASSED] DP_REMOTE_I2C_READ with port number
[17:36:10] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:36:10] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:36:10] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:36:10] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:36:10] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:36:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:36:10] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:36:10] ================ [PASSED] drm_dp_mst_helper ================
[17:36:10] ================== drm_exec (7 subtests) ===================
[17:36:10] [PASSED] sanitycheck
[17:36:10] [PASSED] test_lock
[17:36:10] [PASSED] test_lock_unlock
[17:36:10] [PASSED] test_duplicates
[17:36:10] [PASSED] test_prepare
[17:36:10] [PASSED] test_prepare_array
[17:36:10] [PASSED] test_multiple_loops
[17:36:10] ==================== [PASSED] drm_exec =====================
[17:36:10] =========== drm_format_helper_test (17 subtests) ===========
[17:36:10] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:36:10] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:36:10] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:36:10] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:36:10] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:36:10] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:36:10] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:36:10] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:36:10] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:36:10] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:36:10] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:36:10] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:36:10] ==================== drm_test_fb_swab  =====================
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ================ [PASSED] drm_test_fb_swab =================
[17:36:10] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:36:10] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:36:10] [PASSED] single_pixel_source_buffer
[17:36:10] [PASSED] single_pixel_clip_rectangle
[17:36:10] [PASSED] well_known_colors
[17:36:10] [PASSED] destination_pitch
[17:36:10] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:36:10] ================= drm_test_fb_clip_offset  =================
[17:36:10] [PASSED] pass through
[17:36:10] [PASSED] horizontal offset
[17:36:10] [PASSED] vertical offset
[17:36:10] [PASSED] horizontal and vertical offset
[17:36:10] [PASSED] horizontal offset (custom pitch)
[17:36:10] [PASSED] vertical offset (custom pitch)
[17:36:10] [PASSED] horizontal and vertical offset (custom pitch)
[17:36:10] ============= [PASSED] drm_test_fb_clip_offset =============
[17:36:10] =================== drm_test_fb_memcpy  ====================
[17:36:10] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:36:10] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:36:10] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:36:10] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:36:10] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:36:10] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:36:10] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:36:10] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:36:10] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:36:10] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:36:10] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:36:10] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:36:10] =============== [PASSED] drm_test_fb_memcpy ================
[17:36:10] ============= [PASSED] drm_format_helper_test ==============
[17:36:10] ================= drm_format (18 subtests) =================
[17:36:10] [PASSED] drm_test_format_block_width_invalid
[17:36:10] [PASSED] drm_test_format_block_width_one_plane
[17:36:10] [PASSED] drm_test_format_block_width_two_plane
[17:36:10] [PASSED] drm_test_format_block_width_three_plane
[17:36:10] [PASSED] drm_test_format_block_width_tiled
[17:36:10] [PASSED] drm_test_format_block_height_invalid
[17:36:10] [PASSED] drm_test_format_block_height_one_plane
[17:36:10] [PASSED] drm_test_format_block_height_two_plane
[17:36:10] [PASSED] drm_test_format_block_height_three_plane
[17:36:10] [PASSED] drm_test_format_block_height_tiled
[17:36:10] [PASSED] drm_test_format_min_pitch_invalid
[17:36:10] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:36:10] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:36:10] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:36:10] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:36:10] [PASSED] drm_test_format_min_pitch_two_plane
[17:36:10] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:36:10] [PASSED] drm_test_format_min_pitch_tiled
[17:36:10] =================== [PASSED] drm_format ====================
[17:36:10] ============== drm_framebuffer (10 subtests) ===============
[17:36:10] ========== drm_test_framebuffer_check_src_coords  ==========
[17:36:10] [PASSED] Success: source fits into fb
[17:36:10] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:36:10] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:36:10] [PASSED] Fail: overflowing fb with source width
[17:36:10] [PASSED] Fail: overflowing fb with source height
[17:36:10] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:36:10] [PASSED] drm_test_framebuffer_cleanup
[17:36:10] =============== drm_test_framebuffer_create  ===============
[17:36:10] [PASSED] ABGR8888 normal sizes
[17:36:10] [PASSED] ABGR8888 max sizes
[17:36:10] [PASSED] ABGR8888 pitch greater than min required
[17:36:10] [PASSED] ABGR8888 pitch less than min required
[17:36:10] [PASSED] ABGR8888 Invalid width
[17:36:10] [PASSED] ABGR8888 Invalid buffer handle
[17:36:10] [PASSED] No pixel format
[17:36:10] [PASSED] ABGR8888 Width 0
[17:36:10] [PASSED] ABGR8888 Height 0
[17:36:10] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:36:10] [PASSED] ABGR8888 Large buffer offset
[17:36:10] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:36:10] [PASSED] ABGR8888 Invalid flag
[17:36:10] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:36:10] [PASSED] ABGR8888 Valid buffer modifier
[17:36:10] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:36:10] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] NV12 Normal sizes
[17:36:10] [PASSED] NV12 Max sizes
[17:36:10] [PASSED] NV12 Invalid pitch
[17:36:10] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:36:10] [PASSED] NV12 different  modifier per-plane
[17:36:10] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:36:10] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] NV12 Modifier for inexistent plane
[17:36:10] [PASSED] NV12 Handle for inexistent plane
[17:36:10] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:36:10] [PASSED] YVU420 Normal sizes
[17:36:10] [PASSED] YVU420 Max sizes
[17:36:10] [PASSED] YVU420 Invalid pitch
[17:36:10] [PASSED] YVU420 Different pitches
[17:36:10] [PASSED] YVU420 Different buffer offsets/pitches
[17:36:10] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:36:10] [PASSED] YVU420 Valid modifier
[17:36:10] [PASSED] YVU420 Different modifiers per plane
[17:36:10] [PASSED] YVU420 Modifier for inexistent plane
[17:36:10] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:36:10] [PASSED] X0L2 Normal sizes
[17:36:10] [PASSED] X0L2 Max sizes
[17:36:10] [PASSED] X0L2 Invalid pitch
[17:36:10] [PASSED] X0L2 Pitch greater than minimum required
[17:36:10] [PASSED] X0L2 Handle for inexistent plane
[17:36:10] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:36:10] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:36:10] [PASSED] X0L2 Valid modifier
[17:36:10] [PASSED] X0L2 Modifier for inexistent plane
[17:36:10] =========== [PASSED] drm_test_framebuffer_create ===========
[17:36:10] [PASSED] drm_test_framebuffer_free
[17:36:10] [PASSED] drm_test_framebuffer_init
[17:36:10] [PASSED] drm_test_framebuffer_init_bad_format
[17:36:10] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:36:10] [PASSED] drm_test_framebuffer_lookup
[17:36:10] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:36:10] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:36:10] ================= [PASSED] drm_framebuffer =================
[17:36:10] ================ drm_gem_shmem (8 subtests) ================
[17:36:10] [PASSED] drm_gem_shmem_test_obj_create
[17:36:10] [PASSED] drm_gem_shmem_test_obj_create_private
[17:36:10] [PASSED] drm_gem_shmem_test_pin_pages
[17:36:10] [PASSED] drm_gem_shmem_test_vmap
[17:36:10] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:36:10] [PASSED] drm_gem_shmem_test_get_sg_table
[17:36:10] [PASSED] drm_gem_shmem_test_madvise
[17:36:10] [PASSED] drm_gem_shmem_test_purge
[17:36:10] ================== [PASSED] drm_gem_shmem ==================
[17:36:10] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:36:10] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:36:10] [PASSED] Automatic
[17:36:10] [PASSED] Full
[17:36:10] [PASSED] Limited 16:235
[17:36:10] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:36:10] [PASSED] drm_test_check_disable_connector
[17:36:10] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:36:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:36:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:36:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:36:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:36:10] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:36:10] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:36:10] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:36:10] [PASSED] drm_test_check_output_bpc_dvi
[17:36:10] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:36:10] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:36:10] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:36:10] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:36:10] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:36:10] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:36:10] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:36:10] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:36:10] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:36:10] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:36:10] [PASSED] drm_test_check_broadcast_rgb_value
[17:36:10] [PASSED] drm_test_check_bpc_8_value
[17:36:10] [PASSED] drm_test_check_bpc_10_value
[17:36:10] [PASSED] drm_test_check_bpc_12_value
[17:36:10] [PASSED] drm_test_check_format_value
[17:36:10] [PASSED] drm_test_check_tmds_char_value
[17:36:10] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:36:10] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:36:10] [PASSED] drm_test_check_mode_valid
[17:36:10] [PASSED] drm_test_check_mode_valid_reject
[17:36:10] [PASSED] drm_test_check_mode_valid_reject_rate
[17:36:10] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:36:10] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:36:10] ================= drm_managed (2 subtests) =================
[17:36:10] [PASSED] drm_test_managed_release_action
[17:36:10] [PASSED] drm_test_managed_run_action
[17:36:10] =================== [PASSED] drm_managed ===================
[17:36:10] =================== drm_mm (6 subtests) ====================
[17:36:10] [PASSED] drm_test_mm_init
[17:36:10] [PASSED] drm_test_mm_debug
[17:36:10] [PASSED] drm_test_mm_align32
[17:36:10] [PASSED] drm_test_mm_align64
[17:36:10] [PASSED] drm_test_mm_lowest
[17:36:10] [PASSED] drm_test_mm_highest
[17:36:10] ===================== [PASSED] drm_mm ======================
[17:36:10] ============= drm_modes_analog_tv (5 subtests) =============
[17:36:10] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:36:10] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:36:10] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:36:10] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:36:10] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:36:10] =============== [PASSED] drm_modes_analog_tv ===============
[17:36:10] ============== drm_plane_helper (2 subtests) ===============
[17:36:10] =============== drm_test_check_plane_state  ================
[17:36:10] [PASSED] clipping_simple
[17:36:10] [PASSED] clipping_rotate_reflect
[17:36:10] [PASSED] positioning_simple
[17:36:10] [PASSED] upscaling
[17:36:10] [PASSED] downscaling
[17:36:10] [PASSED] rounding1
[17:36:10] [PASSED] rounding2
[17:36:10] [PASSED] rounding3
[17:36:10] [PASSED] rounding4
[17:36:10] =========== [PASSED] drm_test_check_plane_state ============
[17:36:10] =========== drm_test_check_invalid_plane_state  ============
[17:36:10] [PASSED] positioning_invalid
[17:36:10] [PASSED] upscaling_invalid
[17:36:10] [PASSED] downscaling_invalid
[17:36:10] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:36:10] ================ [PASSED] drm_plane_helper =================
[17:36:10] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:36:10] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:36:10] [PASSED] None
[17:36:10] [PASSED] PAL
[17:36:10] [PASSED] NTSC
[17:36:10] [PASSED] Both, NTSC Default
[17:36:10] [PASSED] Both, PAL Default
[17:36:10] [PASSED] Both, NTSC Default, with PAL on command-line
[17:36:10] [PASSED] Both, PAL Default, with NTSC on command-line
[17:36:10] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:36:10] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:36:10] ================== drm_rect (9 subtests) ===================
[17:36:10] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:36:10] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:36:10] [PASSED] drm_test_rect_clip_scaled_clipped
[17:36:10] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:36:10] ================= drm_test_rect_intersect  =================
[17:36:10] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:36:10] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:36:10] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:36:10] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:36:10] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:36:10] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:36:10] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:36:10] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:36:10] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:36:10] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:36:10] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:36:10] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:36:10] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:36:10] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:36:10] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:36:10] ============= [PASSED] drm_test_rect_intersect =============
[17:36:10] ================ drm_test_rect_calc_hscale  ================
[17:36:10] [PASSED] normal use
[17:36:10] [PASSED] out of max range
[17:36:10] [PASSED] out of min range
[17:36:10] [PASSED] zero dst
[17:36:10] [PASSED] negative src
[17:36:10] [PASSED] negative dst
[17:36:10] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:36:10] ================ drm_test_rect_calc_vscale  ================
[17:36:10] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[17:36:10] [PASSED] out of max range
[17:36:10] [PASSED] out of min range
[17:36:10] [PASSED] zero dst
[17:36:10] [PASSED] negative src
[17:36:10] [PASSED] negative dst
[17:36:10] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:36:10] ================== drm_test_rect_rotate  ===================
[17:36:10] [PASSED] reflect-x
[17:36:10] [PASSED] reflect-y
[17:36:10] [PASSED] rotate-0
[17:36:10] [PASSED] rotate-90
[17:36:10] [PASSED] rotate-180
[17:36:10] [PASSED] rotate-270
[17:36:10] ============== [PASSED] drm_test_rect_rotate ===============
[17:36:10] ================ drm_test_rect_rotate_inv  =================
[17:36:10] [PASSED] reflect-x
[17:36:10] [PASSED] reflect-y
[17:36:10] [PASSED] rotate-0
[17:36:10] [PASSED] rotate-90
[17:36:10] [PASSED] rotate-180
[17:36:10] [PASSED] rotate-270
[17:36:10] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:36:10] ==================== [PASSED] drm_rect =====================
[17:36:10] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:36:10] ============ drm_test_sysfb_build_fourcc_list  =============
[17:36:10] [PASSED] no native formats
[17:36:10] [PASSED] XRGB8888 as native format
[17:36:10] [PASSED] remove duplicates
[17:36:10] [PASSED] convert alpha formats
[17:36:10] [PASSED] random formats
[17:36:10] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:36:10] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:36:10] ================== drm_fixp (2 subtests) ===================
[17:36:10] [PASSED] drm_test_int2fixp
[17:36:10] [PASSED] drm_test_sm2fixp
[17:36:10] ==================== [PASSED] drm_fixp =====================
[17:36:10] ============================================================
[17:36:10] Testing complete. Ran 624 tests: passed: 624
[17:36:10] Elapsed time: 32.265s total, 1.625s configuring, 30.223s building, 0.396s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:36:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:36:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[17:36:21] Starting KUnit Kernel (1/1)...
[17:36:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:36:21] ================= ttm_device (5 subtests) ==================
[17:36:21] [PASSED] ttm_device_init_basic
[17:36:21] [PASSED] ttm_device_init_multiple
[17:36:21] [PASSED] ttm_device_fini_basic
[17:36:21] [PASSED] ttm_device_init_no_vma_man
[17:36:21] ================== ttm_device_init_pools  ==================
[17:36:21] [PASSED] No DMA allocations, no DMA32 required
[17:36:21] [PASSED] DMA allocations, DMA32 required
[17:36:21] [PASSED] No DMA allocations, DMA32 required
[17:36:21] [PASSED] DMA allocations, no DMA32 required
[17:36:21] ============== [PASSED] ttm_device_init_pools ==============
[17:36:21] =================== [PASSED] ttm_device ====================
[17:36:21] ================== ttm_pool (8 subtests) ===================
[17:36:21] ================== ttm_pool_alloc_basic  ===================
[17:36:21] [PASSED] One page
[17:36:21] [PASSED] More than one page
[17:36:21] [PASSED] Above the allocation limit
[17:36:21] [PASSED] One page, with coherent DMA mappings enabled
[17:36:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:36:21] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:36:21] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:36:21] [PASSED] One page
[17:36:21] [PASSED] More than one page
[17:36:21] [PASSED] Above the allocation limit
[17:36:21] [PASSED] One page, with coherent DMA mappings enabled
[17:36:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:36:21] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:36:21] [PASSED] ttm_pool_alloc_order_caching_match
[17:36:21] [PASSED] ttm_pool_alloc_caching_mismatch
[17:36:21] [PASSED] ttm_pool_alloc_order_mismatch
[17:36:21] [PASSED] ttm_pool_free_dma_alloc
[17:36:21] [PASSED] ttm_pool_free_no_dma_alloc
[17:36:21] [PASSED] ttm_pool_fini_basic
[17:36:21] ==================== [PASSED] ttm_pool =====================
[17:36:21] ================ ttm_resource (8 subtests) =================
[17:36:21] ================= ttm_resource_init_basic  =================
[17:36:21] [PASSED] Init resource in TTM_PL_SYSTEM
[17:36:21] [PASSED] Init resource in TTM_PL_VRAM
[17:36:21] [PASSED] Init resource in a private placement
[17:36:21] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:36:21] ============= [PASSED] ttm_resource_init_basic =============
[17:36:21] [PASSED] ttm_resource_init_pinned
[17:36:21] [PASSED] ttm_resource_fini_basic
[17:36:21] [PASSED] ttm_resource_manager_init_basic
[17:36:21] [PASSED] ttm_resource_manager_usage_basic
[17:36:21] [PASSED] ttm_resource_manager_set_used_basic
[17:36:21] [PASSED] ttm_sys_man_alloc_basic
[17:36:21] [PASSED] ttm_sys_man_free_basic
[17:36:21] ================== [PASSED] ttm_resource ===================
[17:36:21] =================== ttm_tt (15 subtests) ===================
[17:36:21] ==================== ttm_tt_init_basic  ====================
[17:36:21] [PASSED] Page-aligned size
[17:36:21] [PASSED] Extra pages requested
[17:36:21] ================ [PASSED] ttm_tt_init_basic ================
[17:36:21] [PASSED] ttm_tt_init_misaligned
[17:36:21] [PASSED] ttm_tt_fini_basic
[17:36:21] [PASSED] ttm_tt_fini_sg
[17:36:21] [PASSED] ttm_tt_fini_shmem
[17:36:21] [PASSED] ttm_tt_create_basic
[17:36:21] [PASSED] ttm_tt_create_invalid_bo_type
[17:36:21] [PASSED] ttm_tt_create_ttm_exists
[17:36:21] [PASSED] ttm_tt_create_failed
[17:36:21] [PASSED] ttm_tt_destroy_basic
[17:36:21] [PASSED] ttm_tt_populate_null_ttm
[17:36:21] [PASSED] ttm_tt_populate_populated_ttm
[17:36:21] [PASSED] ttm_tt_unpopulate_basic
[17:36:21] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:36:21] [PASSED] ttm_tt_swapin_basic
[17:36:21] ===================== [PASSED] ttm_tt ======================
[17:36:21] =================== ttm_bo (14 subtests) ===================
[17:36:21] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:36:21] [PASSED] Cannot be interrupted and sleeps
[17:36:21] [PASSED] Cannot be interrupted, locks straight away
[17:36:21] [PASSED] Can be interrupted, sleeps
[17:36:21] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:36:21] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:36:21] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:36:21] [PASSED] ttm_bo_reserve_double_resv
[17:36:21] [PASSED] ttm_bo_reserve_interrupted
[17:36:21] [PASSED] ttm_bo_reserve_deadlock
[17:36:21] [PASSED] ttm_bo_unreserve_basic
[17:36:21] [PASSED] ttm_bo_unreserve_pinned
[17:36:21] [PASSED] ttm_bo_unreserve_bulk
[17:36:21] [PASSED] ttm_bo_fini_basic
[17:36:21] [PASSED] ttm_bo_fini_shared_resv
[17:36:21] [PASSED] ttm_bo_pin_basic
[17:36:21] [PASSED] ttm_bo_pin_unpin_resource
[17:36:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:36:21] ===================== [PASSED] ttm_bo ======================
[17:36:21] ============== ttm_bo_validate (21 subtests) ===============
[17:36:21] ============== ttm_bo_init_reserved_sys_man  ===============
[17:36:21] [PASSED] Buffer object for userspace
[17:36:21] [PASSED] Kernel buffer object
[17:36:21] [PASSED] Shared buffer object
[17:36:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:36:21] ============== ttm_bo_init_reserved_mock_man  ==============
[17:36:21] [PASSED] Buffer object for userspace
[17:36:21] [PASSED] Kernel buffer object
[17:36:21] [PASSED] Shared buffer object
[17:36:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:36:21] [PASSED] ttm_bo_init_reserved_resv
[17:36:21] ================== ttm_bo_validate_basic  ==================
[17:36:21] [PASSED] Buffer object for userspace
[17:36:21] [PASSED] Kernel buffer object
[17:36:21] [PASSED] Shared buffer object
[17:36:21] ============== [PASSED] ttm_bo_validate_basic ==============
[17:36:21] [PASSED] ttm_bo_validate_invalid_placement
[17:36:21] ============= ttm_bo_validate_same_placement  ==============
[17:36:21] [PASSED] System manager
[17:36:21] [PASSED] VRAM manager
[17:36:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:36:21] [PASSED] ttm_bo_validate_failed_alloc
[17:36:21] [PASSED] ttm_bo_validate_pinned
[17:36:21] [PASSED] ttm_bo_validate_busy_placement
[17:36:21] ================ ttm_bo_validate_multihop  =================
[17:36:21] [PASSED] Buffer object for userspace
[17:36:21] [PASSED] Kernel buffer object
[17:36:21] [PASSED] Shared buffer object
[17:36:21] ============ [PASSED] ttm_bo_validate_multihop =============
[17:36:21] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:36:21] [PASSED] Buffer object in system domain, no page vector
[17:36:21] [PASSED] Buffer object in system domain with an existing page vector
[17:36:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:36:21] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:36:21] [PASSED] Buffer object for userspace
[17:36:21] [PASSED] Kernel buffer object
[17:36:21] [PASSED] Shared buffer object
[17:36:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:36:21] [PASSED] ttm_bo_validate_move_fence_signaled
[17:36:21] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:36:21] [PASSED] Waits for GPU
[17:36:21] [PASSED] Tries to lock straight away
[17:36:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:36:21] [PASSED] ttm_bo_validate_happy_evict
[17:36:21] [PASSED] ttm_bo_validate_all_pinned_evict
[17:36:21] [PASSED] ttm_bo_validate_allowed_only_evict
[17:36:21] [PASSED] ttm_bo_validate_deleted_evict
[17:36:21] [PASSED] ttm_bo_validate_busy_domain_evict
[17:36:21] [PASSED] ttm_bo_validate_evict_gutting
[17:36:21] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:36:21] ================= [PASSED] ttm_bo_validate =================
[17:36:21] ============================================================
[17:36:21] Testing complete. Ran 101 tests: passed: 101
[17:36:21] Elapsed time: 11.086s total, 1.605s configuring, 9.215s building, 0.230s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2396 bytes --]

== Series Details ==

Series: drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)
URL   : https://patchwork.freedesktop.org/series/159089/
State : success

== Summary ==

CI Bug Log - changes from xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4_BAT -> xe-pw-159089v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159089v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_module_load@load:
    - bat-bmg-1:          [PASS][1] -> [ABORT][2] ([Intel XE#6887])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/bat-bmg-1/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/bat-bmg-1/igt@xe_module_load@load.html

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [PASS][3] -> [FAIL][4] ([Intel XE#6519])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
#### Possible fixes ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [FAIL][5] ([Intel XE#6520]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
  [Intel XE#6887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6887


Build changes
-------------

  * Linux: xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4 -> xe-pw-159089v2

  IGT_8669: 319db2ffba419f9711acc72895f065a818905efa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4: 2ff418ee5a913a98ae4771d114ff27f4b6364bf4
  xe-pw-159089v2: 159089v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/index.html

[-- Attachment #2: Type: text/html, Size: 3017 bytes --]

✗ Xe.CI.Full: failure for drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 72375 bytes --]

== Series Details ==

Series: drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2)
URL   : https://patchwork.freedesktop.org/series/159089/
State : failure

== Summary ==

CI Bug Log - changes from xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4_FULL -> xe-pw-159089v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-159089v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159089v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159089v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@core_getversion@basic:
    - shard-bmg:          [PASS][1] -> [FAIL][2] +2 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@core_getversion@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@core_getversion@basic.html

  * igt@xe_pm@s4-vm-bind-prefetch:
    - shard-lnl:          [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-lnl-7/igt@xe_pm@s4-vm-bind-prefetch.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-lnl-8/igt@xe_pm@s4-vm-bind-prefetch.html

  
Known issues
------------

  Here are the changes found in xe-pw-159089v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_setmaster@master-drop-set-user:
    - shard-bmg:          [PASS][5] -> [FAIL][6] ([Intel XE#4674])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@core_setmaster@master-drop-set-user.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@core_setmaster@master-drop-set-user.html

  * igt@fbdev@pan:
    - shard-bmg:          [PASS][7] -> [SKIP][8] ([Intel XE#2134])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@fbdev@pan.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@fbdev@pan.html

  * igt@intel_hwmon@hwmon-read:
    - shard-bmg:          [PASS][9] -> [SKIP][10] ([Intel XE#5177] / [Intel XE#6703])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@intel_hwmon@hwmon-read.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@intel_hwmon@hwmon-read.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#1124]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#3432])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2252])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-bmg:          [PASS][16] -> [SKIP][17] ([Intel XE#2291])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-10/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2291])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-bmg:          [PASS][19] -> [SKIP][20] ([Intel XE#2316]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_flip@2x-dpms-vs-vblank-race.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-bmg:          [PASS][21] -> [SKIP][22] ([Intel XE#6703]) +428 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_flip@wf_vblank-ts-check.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2293]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2312]) +6 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#4141])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2311]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2313]) +4 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2350])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#6886]) +4 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-bmg:          [PASS][30] -> [SKIP][31] ([Intel XE#6693])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_pm_rpm@modeset-non-lpsp.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-2/igt@kms_psr@fbc-psr-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#3414] / [Intel XE#3904])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12:
    - shard-lnl:          [PASS][35] -> [DMESG-WARN][36] ([Intel XE#4537]) +1 other test dmesg-warn
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-lnl-7/igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-lnl-8/igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2509])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#1499])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_vrr@flipline.html

  * igt@xe_create@invalid-pad:
    - shard-bmg:          [PASS][39] -> [SKIP][40] ([Intel XE#6557] / [Intel XE#6703]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@xe_create@invalid-pad.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_create@invalid-pad.html

  * igt@xe_eudebug@discovery-race-sigint:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#4837]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_eudebug@discovery-race-sigint.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2322]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6874]) +6 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_system_allocator@once-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4943]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-2/igt@xe_exec_system_allocator@once-mmap-free-huge-nomemset.html

  * igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [PASS][45] -> [FAIL][46] ([Intel XE#6251]) +1 other test fail
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#944])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_query@multigpu-query-mem-usage.html

  
#### Possible fixes ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [SKIP][48] ([Intel XE#6815]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@device_reset@unbind-reset-rebind.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@device_reset@unbind-reset-rebind.html

  * igt@fbdev@write:
    - shard-bmg:          [SKIP][50] ([Intel XE#2134]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@fbdev@write.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@fbdev@write.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][52] ([Intel XE#3862]) -> [PASS][53] +1 other test pass
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-bmg:          [SKIP][54] ([Intel XE#2291]) -> [PASS][55] +3 other tests pass
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-10/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][56] ([Intel XE#5299]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [SKIP][58] ([Intel XE#2316]) -> [PASS][59] +3 other tests pass
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_flip@2x-blocking-wf_vblank.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-10/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [INCOMPLETE][60] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][61] +1 other test pass
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-1/igt@kms_flip@flip-vs-suspend.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][62] ([Intel XE#1503]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc:
    - shard-bmg:          [SKIP][64] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][65] +5 other tests pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-bmg:          [SKIP][66] ([Intel XE#6693]) -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_pm_rpm@system-suspend-modeset.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-race:
    - shard-bmg:          [DMESG-WARN][68] ([Intel XE#5254]) -> [PASS][69] +2 other tests pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-race.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-race.html

  * igt@xe_sysfs_preempt_timeout@preempt_timeout_us-timeout:
    - shard-bmg:          [SKIP][70] ([Intel XE#6703]) -> [PASS][71] +427 other tests pass
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_sysfs_preempt_timeout@preempt_timeout_us-timeout.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_sysfs_preempt_timeout@preempt_timeout_us-timeout.html

  
#### Warnings ####

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-bmg:          [SKIP][72] ([Intel XE#2327]) -> [SKIP][73] ([Intel XE#6703]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_big_fb@linear-32bpp-rotate-90.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-bmg:          [SKIP][74] ([Intel XE#6703]) -> [SKIP][75] ([Intel XE#2327]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_big_fb@linear-64bpp-rotate-270.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-bmg:          [SKIP][76] ([Intel XE#1124]) -> [SKIP][77] ([Intel XE#6703]) +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          [SKIP][78] ([Intel XE#6703]) -> [SKIP][79] ([Intel XE#2328])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_big_fb@y-tiled-addfb.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          [SKIP][80] ([Intel XE#610]) -> [SKIP][81] ([Intel XE#6703])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          [SKIP][82] ([Intel XE#6703]) -> [SKIP][83] ([Intel XE#1124]) +6 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [SKIP][84] ([Intel XE#6703]) -> [SKIP][85] ([Intel XE#2314] / [Intel XE#2894])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
    - shard-bmg:          [SKIP][86] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][87] ([Intel XE#6703])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          [SKIP][88] ([Intel XE#367]) -> [SKIP][89] ([Intel XE#6703]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          [SKIP][90] ([Intel XE#6703]) -> [SKIP][91] ([Intel XE#367]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][92] ([Intel XE#2887]) -> [SKIP][93] ([Intel XE#6557] / [Intel XE#6703])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          [SKIP][94] ([Intel XE#6703]) -> [SKIP][95] ([Intel XE#2887]) +11 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs:
    - shard-bmg:          [SKIP][96] ([Intel XE#2887]) -> [SKIP][97] ([Intel XE#6703]) +10 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][98] ([Intel XE#6703]) -> [SKIP][99] ([Intel XE#3432])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          [SKIP][100] ([Intel XE#2724]) -> [SKIP][101] ([Intel XE#6703])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_cdclk@mode-transition.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-bmg:          [SKIP][102] ([Intel XE#6703]) -> [SKIP][103] ([Intel XE#2724])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_cdclk@mode-transition-all-outputs.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          [SKIP][104] ([Intel XE#6703]) -> [SKIP][105] ([Intel XE#2325]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_chamelium_color@ctm-0-50.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-bmg:          [SKIP][106] ([Intel XE#2325]) -> [SKIP][107] ([Intel XE#6703])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_chamelium_color@ctm-green-to-red.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-bmg:          [SKIP][108] ([Intel XE#6703]) -> [SKIP][109] ([Intel XE#2252]) +5 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_chamelium_hpd@dp-hpd-storm.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          [SKIP][110] ([Intel XE#2252]) -> [SKIP][111] ([Intel XE#6703]) +8 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][112] ([Intel XE#6703]) -> [SKIP][113] ([Intel XE#6507])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_chamelium_sharpness_filter@filter-basic.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [FAIL][114] ([Intel XE#1178]) -> [SKIP][115] ([Intel XE#6703]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_content_protection@atomic.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@content-type-change:
    - shard-bmg:          [SKIP][116] ([Intel XE#6703]) -> [SKIP][117] ([Intel XE#2341])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_content_protection@content-type-change.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          [SKIP][118] ([Intel XE#6703]) -> [SKIP][119] ([Intel XE#2390])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_content_protection@dp-mst-type-0.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          [SKIP][120] ([Intel XE#2320]) -> [SKIP][121] ([Intel XE#6703]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_cursor_crc@cursor-offscreen-256x85.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          [SKIP][122] ([Intel XE#6703]) -> [SKIP][123] ([Intel XE#2321]) +3 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x170.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-bmg:          [SKIP][124] ([Intel XE#2321]) -> [SKIP][125] ([Intel XE#6703])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_cursor_crc@cursor-random-512x512.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          [SKIP][126] ([Intel XE#6703]) -> [SKIP][127] ([Intel XE#2320]) +2 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][128] ([Intel XE#2291]) -> [SKIP][129] ([Intel XE#6703]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-bmg:          [SKIP][130] ([Intel XE#2286]) -> [SKIP][131] ([Intel XE#6703])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          [SKIP][132] ([Intel XE#6703]) -> [SKIP][133] ([Intel XE#2244])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-bmg:          [SKIP][134] ([Intel XE#2244]) -> [SKIP][135] ([Intel XE#6703]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_dsc@dsc-with-bpc.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          [SKIP][136] ([Intel XE#4422]) -> [SKIP][137] ([Intel XE#6703])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          [SKIP][138] ([Intel XE#6703]) -> [SKIP][139] ([Intel XE#4156])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_fbcon_fbt@fbc-suspend.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          [SKIP][140] ([Intel XE#6703]) -> [SKIP][141] ([Intel XE#1138])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_feature_discovery@display-4x.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          [SKIP][142] ([Intel XE#6703]) -> [SKIP][143] ([Intel XE#2374])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_feature_discovery@psr1.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-bmg:          [SKIP][144] ([Intel XE#2316]) -> [SKIP][145] ([Intel XE#6703])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [SKIP][146] ([Intel XE#6703]) -> [SKIP][147] ([Intel XE#2316]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-bmg:          [SKIP][148] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][149] ([Intel XE#6703]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-bmg:          [SKIP][150] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][151] ([Intel XE#2293] / [Intel XE#2380])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-bmg:          [SKIP][152] ([Intel XE#6703]) -> [SKIP][153] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
    - shard-bmg:          [SKIP][154] ([Intel XE#2311]) -> [SKIP][155] ([Intel XE#6703]) +16 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][156] ([Intel XE#4141]) -> [SKIP][157] ([Intel XE#2312]) +3 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][158] ([Intel XE#6703]) -> [SKIP][159] ([Intel XE#4141]) +8 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][160] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][161] ([Intel XE#2312])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][162] ([Intel XE#2312]) -> [SKIP][163] ([Intel XE#4141]) +2 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][164] ([Intel XE#4141]) -> [SKIP][165] ([Intel XE#6703]) +8 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][166] ([Intel XE#2312]) -> [SKIP][167] ([Intel XE#2311]) +8 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][168] ([Intel XE#6703]) -> [SKIP][169] ([Intel XE#2311]) +18 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][170] ([Intel XE#2311]) -> [SKIP][171] ([Intel XE#2312]) +2 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][172] ([Intel XE#2313]) -> [SKIP][173] ([Intel XE#6703]) +19 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-rte:
    - shard-bmg:          [SKIP][174] ([Intel XE#2312]) -> [SKIP][175] ([Intel XE#6703]) +7 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-rte.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-bmg:          [SKIP][176] ([Intel XE#6703]) -> [SKIP][177] ([Intel XE#2352])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][178] ([Intel XE#6703]) -> [SKIP][179] ([Intel XE#2313]) +16 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][180] ([Intel XE#2312]) -> [SKIP][181] ([Intel XE#2313]) +8 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][182] ([Intel XE#6703]) -> [SKIP][183] ([Intel XE#2312]) +8 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][184] ([Intel XE#2313]) -> [SKIP][185] ([Intel XE#2312]) +3 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][186] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][187] ([Intel XE#6703])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          [SKIP][188] ([Intel XE#6703]) -> [SKIP][189] ([Intel XE#6901])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_joiner@invalid-modeset-big-joiner.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          [SKIP][190] -> [SKIP][191] ([Intel XE#6703])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          [SKIP][192] ([Intel XE#5020]) -> [SKIP][193] ([Intel XE#6703])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_plane_multiple@tiling-yf.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
    - shard-bmg:          [SKIP][194] ([Intel XE#6886]) -> [SKIP][195] ([Intel XE#6703])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          [SKIP][196] ([Intel XE#6703]) -> [SKIP][197] ([Intel XE#870])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_pm_backlight@basic-brightness.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-bmg:          [SKIP][198] ([Intel XE#870]) -> [SKIP][199] ([Intel XE#6703])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_pm_backlight@fade-with-suspend.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          [SKIP][200] ([Intel XE#6703]) -> [SKIP][201] ([Intel XE#2391])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          [SKIP][202] ([Intel XE#2392]) -> [SKIP][203] ([Intel XE#6703])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_pm_dc@dc6-psr.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          [SKIP][204] ([Intel XE#6703]) -> [SKIP][205] ([Intel XE#2505])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_pm_dc@deep-pkgc.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          [SKIP][206] ([Intel XE#1439] / [Intel XE#836]) -> [SKIP][207] ([Intel XE#6693])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          [SKIP][208] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][209] ([Intel XE#1406] / [Intel XE#6703]) +6 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
    - shard-bmg:          [SKIP][210] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][211] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-bmg:          [SKIP][212] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][213] ([Intel XE#1406] / [Intel XE#2387])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_psr2_su@page_flip-xrgb8888.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr-basic:
    - shard-bmg:          [SKIP][214] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][215] ([Intel XE#1406] / [Intel XE#6703]) +8 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_psr@psr-basic.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_psr@psr-basic.html

  * igt@kms_psr@psr2-primary-page-flip:
    - shard-bmg:          [SKIP][216] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][217] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +8 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_psr@psr2-primary-page-flip.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_psr@psr2-primary-page-flip.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          [SKIP][218] ([Intel XE#1406] / [Intel XE#2414]) -> [SKIP][219] ([Intel XE#1406] / [Intel XE#6703])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-bmg:          [SKIP][220] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][221] ([Intel XE#6703]) +2 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_rotation_crc@bad-pixel-format.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-bmg:          [SKIP][222] ([Intel XE#6703]) -> [SKIP][223] ([Intel XE#2330])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-bmg:          [SKIP][224] ([Intel XE#6703]) -> [SKIP][225] ([Intel XE#3414] / [Intel XE#3904]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          [SKIP][226] ([Intel XE#2413]) -> [SKIP][227] ([Intel XE#6703])
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_scaling_modes@scaling-mode-full-aspect.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_sharpness_filter@filter-rotations:
    - shard-bmg:          [SKIP][228] ([Intel XE#6703]) -> [SKIP][229] ([Intel XE#6503]) +1 other test skip
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_sharpness_filter@filter-rotations.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@kms_sharpness_filter@filter-rotations.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-bmg:          [SKIP][230] ([Intel XE#6503]) -> [SKIP][231] ([Intel XE#6703]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][232] ([Intel XE#1729]) -> [SKIP][233] ([Intel XE#2426])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-bmg:          [SKIP][234] ([Intel XE#2450]) -> [SKIP][235] ([Intel XE#6557] / [Intel XE#6703])
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_tv_load_detect@load-detect.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          [SKIP][236] ([Intel XE#6703]) -> [SKIP][237] ([Intel XE#1499]) +1 other test skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@kms_vrr@flip-basic.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@max-min:
    - shard-bmg:          [SKIP][238] ([Intel XE#1499]) -> [SKIP][239] ([Intel XE#6703])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@kms_vrr@max-min.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@kms_vrr@max-min.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-bmg:          [SKIP][240] ([Intel XE#6703]) -> [SKIP][241] ([Intel XE#6599])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_compute@ccs-mode-basic.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_eudebug@basic-exec-queues-enable:
    - shard-bmg:          [SKIP][242] ([Intel XE#4837]) -> [SKIP][243] ([Intel XE#6703]) +4 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@xe_eudebug@basic-exec-queues-enable.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_eudebug@basic-exec-queues-enable.html

  * igt@xe_eudebug@discovery-empty-clients:
    - shard-bmg:          [SKIP][244] ([Intel XE#6703]) -> [SKIP][245] ([Intel XE#4837]) +4 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_eudebug@discovery-empty-clients.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_eudebug@discovery-empty-clients.html

  * igt@xe_eudebug_online@pagefault-write:
    - shard-bmg:          [SKIP][246] ([Intel XE#6703]) -> [SKIP][247] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_eudebug_online@pagefault-write.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_eudebug_online@pagefault-write.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          [SKIP][248] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][249] ([Intel XE#6703]) +5 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_eudebug_online@single-step.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_eudebug_online@single-step.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          [SKIP][250] ([Intel XE#6703]) -> [SKIP][251] ([Intel XE#2322]) +7 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          [SKIP][252] ([Intel XE#2322]) -> [SKIP][253] ([Intel XE#6703]) +6 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_exec_basic@multigpu-once-null-rebind.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
    - shard-bmg:          [SKIP][254] ([Intel XE#6874]) -> [SKIP][255] ([Intel XE#6703]) +21 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          [SKIP][256] ([Intel XE#6703]) -> [SKIP][257] ([Intel XE#6874]) +22 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          [SKIP][258] ([Intel XE#6703]) -> [SKIP][259] ([Intel XE#5007]) +1 other test skip
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge:
    - shard-bmg:          [SKIP][260] ([Intel XE#4943]) -> [SKIP][261] ([Intel XE#6703]) +19 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge:
    - shard-bmg:          [SKIP][262] ([Intel XE#6703]) -> [SKIP][263] ([Intel XE#4943]) +15 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          [SKIP][264] ([Intel XE#6703]) -> [SKIP][265] ([Intel XE#2459] / [Intel XE#2596])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_media_fill@media-fill.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_media_fill@media-fill.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          [SKIP][266] ([Intel XE#6703]) -> [SKIP][267] ([Intel XE#1420])
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_pat@pat-index-xehpc.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-9/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-bmg:          [SKIP][268] ([Intel XE#2284]) -> [SKIP][269] ([Intel XE#6703])
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-4/igt@xe_pm@d3cold-basic-exec.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@d3cold-i2c:
    - shard-bmg:          [SKIP][270] ([Intel XE#5694]) -> [SKIP][271] ([Intel XE#6703])
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_pm@d3cold-i2c.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          [SKIP][272] ([Intel XE#6703]) -> [SKIP][273] ([Intel XE#5742])
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_pm@d3hot-i2c.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-bmg:          [SKIP][274] ([Intel XE#6703]) -> [SKIP][275] ([Intel XE#2284]) +2 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_pm@s4-d3cold-basic-exec.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
    - shard-bmg:          [SKIP][276] ([Intel XE#6703]) -> [SKIP][277] ([Intel XE#4733])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-8/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          [SKIP][278] ([Intel XE#4733]) -> [SKIP][279] ([Intel XE#6703]) +2 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-8/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-5/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          [SKIP][280] ([Intel XE#6703]) -> [SKIP][281] ([Intel XE#944]) +2 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4/shard-bmg-5/igt@xe_query@multigpu-query-invalid-cs-cycles.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/shard-bmg-4/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
  [Intel XE#4674]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4674
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
  [Intel XE#5254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5254
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6693]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6693
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6815]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6815
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4 -> xe-pw-159089v2

  IGT_8669: 319db2ffba419f9711acc72895f065a818905efa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4258-2ff418ee5a913a98ae4771d114ff27f4b6364bf4: 2ff418ee5a913a98ae4771d114ff27f4b6364bf4
  xe-pw-159089v2: 159089v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159089v2/index.html

[-- Attachment #2: Type: text/html, Size: 90039 bytes --]

RE: [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Wednesday, December 17, 2025 8:50 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers
> 
> Add verification for pll table dividers. The port clock is computed based on pll
> tables and, for hdmi case, the algorithmic model is applied to calculate pll
> dividers.
> If port clock differs more than +-1 kHz from expected value an drm_warn() is
> thrown and pll divider differences are printed out for debugging purposes.
> 
> v2:
> - Move clock derivation from dividers in intel_cx0pll_enable()
>   earlier in the patchset.
> - Keep intel_cx0_pll_power_save_wa() in intel_dpll_sanitize_state()
> - Use tables[i].name != NULL as a terminating condition.
> - Drop duplicate intel_cx0pll_clock_matches() declaration in header.
> - Use state vs. params term consistently in intel_c10pll_verify_clock()
>   and intel_c20pll_verify_clock().
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 121 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   1 +
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   9 +-
>  3 files changed, 130 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index ea807191cb4f..a8c37a14d427 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3824,3 +3824,124 @@ void intel_cx0_pll_power_save_wa(struct
> intel_display *display)
>  		intel_cx0pll_disable(encoder);
>  	}
>  }
> +
> +static void intel_c10pll_verify_clock(struct intel_display *display,
> +				      int precomputed_clock,
> +				      const char *pll_state_name,
> +				      const struct intel_c10pll_state *pll_state,
> +				      bool is_precomputed_state)
> +{
> +	struct drm_printer p;
> +	int clock;
> +
> +	clock = intel_c10pll_calc_port_clock(pll_state);
> +
> +	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
> +		return;
> +
> +	drm_warn(display->drm,
> +		 "PLL state %s (%s): clock difference too high: computed %d,
> pre-computed %d\n",
> +		 pll_state_name,
> +		 is_precomputed_state ? "precomputed" : "computed",
> +		 clock, precomputed_clock);
> +
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> +
> +	drm_printf(&p, "PLL state %s (%s):\n",
> +		   pll_state_name,
> +		   is_precomputed_state ? "precomputed" : "computed");
> +	intel_c10pll_dump_hw_state(&p, pll_state); }
> +
> +static void intel_c10pll_verify_params(struct intel_display *display,
> +				       const struct intel_cx0pll_params
> *pll_params) {
> +	struct intel_c10pll_state pll_state;
> +
> +	intel_c10pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, pll_params->c10, true);
> +
> +	if (!pll_params->is_hdmi)
> +		return;
> +
> +	intel_snps_hdmi_pll_compute_c10pll(&pll_state,
> +pll_params->clock_rate);
> +
> +	intel_c10pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, &pll_state, false); }
> +
> +static void intel_c20pll_verify_clock(struct intel_display *display,
> +				      int precomputed_clock,
> +				      const char *pll_state_name,
> +				      const struct intel_c20pll_state *pll_state,
> +				      bool is_precomputed_state)
> +{
> +	struct drm_printer p;
> +	int clock;
> +
> +	clock = intel_c20pll_calc_port_clock(pll_state);
> +
> +	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
> +		return;
> +
> +	drm_warn(display->drm,
> +		 "PLL state %s (%s): clock difference too high: computed %d,
> pre-computed %d\n",
> +		 pll_state_name,
> +		 is_precomputed_state ? "precomputed" : "computed",
> +		 clock, precomputed_clock);
> +
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> +
> +	drm_printf(&p, "PLL state %s (%s):\n",
> +		   pll_state_name,
> +		   is_precomputed_state ? "precomputed" : "computed");
> +	intel_c20pll_dump_hw_state(&p, pll_state); }
> +
> +static void intel_c20pll_verify_params(struct intel_display *display,
> +				       const struct intel_cx0pll_params
> *pll_params) {
> +	struct intel_c20pll_state pll_state;
> +
> +	intel_c20pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, pll_params->c20, true);
> +
> +	if (!pll_params->is_hdmi)
> +		return;
> +
> +	if (intel_c20_compute_hdmi_tmds_pll(display, pll_params-
> >clock_rate, &pll_state) != 0)
> +		return;
> +
> +	intel_c20pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, &pll_state, false); }
> +
> +static void intel_cx0pll_verify_tables(struct intel_display *display,
> +				       const struct intel_cx0pll_params *tables)
> {
> +	int i;
> +
> +	for (i = 0; tables[i].name; i++) {
> +		if (tables[i].is_c10)
> +			intel_c10pll_verify_params(display, &tables[i]);
> +		else
> +			intel_c20pll_verify_params(display, &tables[i]);
> +	}
> +}
> +
> +void intel_cx0pll_verify_plls(struct intel_display *display) {
> +	/* C10 */
> +	intel_cx0pll_verify_tables(display, mtl_c10_edp_tables);
> +	intel_cx0pll_verify_tables(display, mtl_c10_dp_tables);
> +	intel_cx0pll_verify_tables(display, mtl_c10_hdmi_tables);
> +
> +	/* C20 */
> +	intel_cx0pll_verify_tables(display, xe2hpd_c20_edp_tables);
> +	intel_cx0pll_verify_tables(display, mtl_c20_dp_tables);
> +	intel_cx0pll_verify_tables(display, xe2hpd_c20_dp_tables);
> +	intel_cx0pll_verify_tables(display, xe3lpd_c20_dp_edp_tables);
> +	intel_cx0pll_verify_tables(display, mtl_c20_hdmi_tables); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 3d9c580eb562..c0ac67f7b11f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -78,6 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct
> intel_display *display,
>  					struct intel_dpll_hw_state
> *hw_state);  int intel_mtl_tbt_calc_port_clock(struct intel_encoder
> *encoder);
> 
> +void intel_cx0pll_verify_plls(struct intel_display *display);
>  void intel_cx0_pll_power_save_wa(struct intel_display *display);  void
> intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
>  				 const struct intel_crtc_state *crtc_state); diff
> --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9aa84a430f09..7127bc2a0898 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4613,7 +4613,7 @@ void intel_dpll_init(struct intel_display *display)
>  		dpll_mgr = &pch_pll_mgr;
> 
>  	if (!dpll_mgr)
> -		return;
> +		goto out_verify;
> 
>  	dpll_info = dpll_mgr->dpll_info;
> 
> @@ -4632,6 +4632,13 @@ void intel_dpll_init(struct intel_display *display)
> 
>  	display->dpll.mgr = dpll_mgr;
>  	display->dpll.num_dpll = i;
> +
> +out_verify:
> +	/*
> +	 * TODO: Convert these to a KUnit test or dependent on a kconfig
> +	 * debug option.
> +	 */
> +	intel_cx0pll_verify_plls(display);

According to me having this done during every boot does not make sense, maybe as a test it may but here having the driver
Spend time doing these calculations for every table for all the rates seems like a waste.
Specially when you take into account that all these tables are static which means you have the values and the algorithm beforehand
And before adding the static tables you can get this the algorithm tested against the table and fix it accordingly.
Also it should be the responsibility of anyone who adds any other static table to see if the clock matches.

Regards,
Suraj Kandpal

>  }
> 
>  /**
> --
> 2.34.1

RE: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Wednesday, December 17, 2025 8:50 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> dividers
> 
> Add verification for lt phy pll dividers during boot. The port clock is calculated
> from pll dividers and compared against the requested port clock value. If there
> are a difference exceeding +-1 kHz an
> drm_warn() is thrown out to indicate possible pll divider mismatch.
> 
> v2:
> - Move the LT_PHY_PLL_PARAMS -> LT_PHY_PLL_DP/HDMI_PARAMS change
>   earlier.
> - Use tables[i].name != NULL as a terminating condition.
> - Use state vs. params term consistently in intel_c10pll_verify_clock()
>   and intel_c20pll_verify_clock().
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 63 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
>  3 files changed, 66 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 7127bc2a0898..f35a9252f4e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -38,6 +38,7 @@
>  #include "intel_dpll.h"
>  #include "intel_dpll_mgr.h"
>  #include "intel_hti.h"
> +#include "intel_lt_phy.h"
>  #include "intel_mg_phy_regs.h"
>  #include "intel_pch_refclk.h"
>  #include "intel_step.h"
> @@ -4639,6 +4640,7 @@ void intel_dpll_init(struct intel_display *display)
>  	 * debug option.
>  	 */
>  	intel_cx0pll_verify_plls(display);
> +	intel_lt_phy_verify_plls(display);
>  }
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index e33f6f48a6ce..13acfc7c0469 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2343,3 +2343,66 @@ void intel_xe3plpd_pll_disable(struct
> intel_encoder *encoder)
>  		intel_lt_phy_pll_disable(encoder);
> 
>  }
> +
> +static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
> +					  int precomputed_clock,
> +					  const char *pll_state_name,
> +					  const struct intel_lt_phy_pll_state
> *pll_state,
> +					  bool is_precomputed_state)
> +{
> +	struct drm_printer p;
> +	int clock;
> +
> +	clock = intel_lt_phy_calc_port_clock(display, pll_state);
> +
> +	if (intel_cx0pll_clock_matches(clock, precomputed_clock))
> +		return;
> +
> +	drm_warn(display->drm,
> +		 "PLL state %s (%s): clock difference too high: computed %d,
> pre-computed %d\n",
> +		 pll_state_name,
> +		 is_precomputed_state ? "precomputed" : "computed",
> +		 clock, precomputed_clock);
> +
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> +
> +	drm_printf(&p, "PLL state %s (%s):\n",
> +		   pll_state_name,
> +		   is_precomputed_state ? "precomputed" : "computed");
> +	intel_lt_phy_dump_hw_state(display, pll_state); }
> +
> +static void intel_lt_phy_pll_verify_params(struct intel_display *display,
> +					   const struct
> intel_lt_phy_pll_params *pll_params) {
> +	struct intel_lt_phy_pll_state pll_state;
> +
> +	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, pll_params->state, true);
> +
> +	if (!pll_params->is_hdmi)
> +		return;
> +
> +	if (intel_lt_phy_calculate_hdmi_state(&pll_state, pll_params-
> >clock_rate) != 0)
> +		return;
> +
> +	intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate,
> +pll_params->name, &pll_state, false); }
> +
> +static void intel_lt_phy_pll_verify_tables(struct intel_display *display,
> +					   const struct
> intel_lt_phy_pll_params *tables) {
> +	int i;
> +
> +	for (i = 0; tables[i].name; i++)
> +		intel_lt_phy_pll_verify_params(display, &tables[i]); }
> +
> +void intel_lt_phy_verify_plls(struct intel_display *display) {
> +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); }

Same thing as the previous patch this is not needed.
Moreover we do not go through any algorithm for edp and dp tables for LT PHY hence the
Rate always matches. This patch should be dropped.

Regards,
Suraj Kandpal

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index c4999a55473e..56c5a875d93b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -41,5 +41,6 @@ intel_lt_phy_calculate_hdmi_state(struct
> intel_lt_phy_pll_state *lt_state,  void intel_xe3plpd_pll_enable(struct
> intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state);  void
> intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> +void intel_lt_phy_verify_plls(struct intel_display *display);
> 
>  #endif /* __INTEL_LT_PHY_H__ */
> --
> 2.34.1

RE: [PATCH v2 01/15] drm/i915/c10: Move C10 port clock calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 01/15] drm/i915/c10: Move C10 port clock calculation
> 
> Prepare removal of .clock member from pll state structures by moving
> intel_c10pll_calc_port_clock() function.
> 
> No functional changes.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 54 ++++++++++----------
>  1 file changed, 27 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f6d69627154e..5fb39c114078 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2103,6 +2103,33 @@ static bool cx0pll_state_is_dp(const struct
> intel_cx0pll_state *pll_state)
>  	return c20pll_state_is_dp(&pll_state->c20);
>  }
> 
> +static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> +					const struct intel_c10pll_state
> *pll_state) {
> +	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> +	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> +	int tmpclk = 0;
> +
> +	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> +		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> +		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
> +		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
> +	}
> +
> +	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> pll_state->pll[3]) << 8 |
> +		      pll_state->pll[2]) / 2 + 16;
> +
> +	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK,
> pll_state->pll[15]);
> +	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state-
> >pll[15]);
> +
> +	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier
> << 16) + frac_quot) +
> +				     DIV_ROUND_CLOSEST(refclk * frac_rem,
> frac_den),
> +				     10 << (tx_clk_div + 16));
> +	tmpclk *= (hdmi_div ? 2 : 1);
> +
> +	return tmpclk;
> +}
> +
>  /*
>   * TODO: Convert the following to align with intel_c20pll_find_table() and
>   * intel_c20pll_calc_state_from_table().
> @@ -2166,33 +2193,6 @@ static int intel_c10pll_calc_state(const struct
> intel_crtc_state *crtc_state,
>  	return 0;
>  }
> 
> -static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c10pll_state
> *pll_state)
> -{
> -	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> -	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> -	int tmpclk = 0;
> -
> -	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> -		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> -		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
> -		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
> -	}
> -
> -	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> pll_state->pll[3]) << 8 |
> -		      pll_state->pll[2]) / 2 + 16;
> -
> -	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK,
> pll_state->pll[15]);
> -	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state-
> >pll[15]);
> -
> -	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier
> << 16) + frac_quot) +
> -				     DIV_ROUND_CLOSEST(refclk * frac_rem,
> frac_den),
> -				     10 << (tx_clk_div + 16));
> -	tmpclk *= (hdmi_div ? 2 : 1);
> -
> -	return tmpclk;
> -}
> -
>  static int readout_enabled_lane_count(struct intel_encoder *encoder)  {
>  	struct intel_display *display = to_intel_display(encoder);
> --
> 2.34.1

RE: [PATCH v2 02/15] drm/i915/c20: Move C20 port clock calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 02/15] drm/i915/c20: Move C20 port clock calculation

Nit: Since the change is int cx0_phy.c I think its better to have i915/cx0 same for previous patch
Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Prepare removal of .clock member from the pll state structure by moving
> intel_c20pll_calc_port_clock() function.
> 
> No functional change.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 100 +++++++++----------
>  1 file changed, 50 insertions(+), 50 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 5fb39c114078..1deb865618b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2130,6 +2130,56 @@ static int intel_c10pll_calc_port_clock(struct
> intel_encoder *encoder,
>  	return tmpclk;
>  }
> 
> +static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state
> +*state) {
> +	return state->tx[0] & C20_PHY_USE_MPLLB; }
> +
> +static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> +					const struct intel_c20pll_state
> *pll_state) {
> +	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> +	unsigned int multiplier, refclk = 38400;
> +	unsigned int tx_clk_div;
> +	unsigned int ref_clk_mpllb_div;
> +	unsigned int fb_clk_div4_en;
> +	unsigned int ref, vco;
> +	unsigned int tx_rate_mult;
> +	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE,
> +pll_state->tx[0]);
> +
> +	if (intel_c20phy_use_mpllb(pll_state)) {
> +		tx_rate_mult = 1;
> +		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state-
> >mpllb[6]);
> +		frac_quot = pll_state->mpllb[8];
> +		frac_rem =  pll_state->mpllb[9];
> +		frac_den =  pll_state->mpllb[7];
> +		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mpllb[0]);
> +		tx_clk_div =
> REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
> +		ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
> +		fb_clk_div4_en = 0;
> +	} else {
> +		tx_rate_mult = 2;
> +		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state-
> >mplla[6]);
> +		frac_quot = pll_state->mplla[8];
> +		frac_rem =  pll_state->mplla[9];
> +		frac_den =  pll_state->mplla[7];
> +		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mplla[0]);
> +		tx_clk_div =
> REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
> +		ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
> +		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN,
> pll_state->mplla[0]);
> +	}
> +
> +	if (frac_en)
> +		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem,
> frac_den);
> +	else
> +		frac = 0;
> +
> +	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
> ref_clk_mpllb_div);
> +	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17
> - 2))
> ++ frac) >> 17, 10);
> +
> +	return vco << tx_rate_mult >> tx_clk_div >> tx_rate; }
> +
>  /*
>   * TODO: Convert the following to align with intel_c20pll_find_table() and
>   * intel_c20pll_calc_state_from_table().
> @@ -2702,56 +2752,6 @@ int intel_cx0pll_calc_state(const struct
> intel_crtc_state *crtc_state,
>  	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);  }
> 
> -static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) -{
> -	return state->tx[0] & C20_PHY_USE_MPLLB;
> -}
> -
> -static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c20pll_state
> *pll_state)
> -{
> -	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> -	unsigned int multiplier, refclk = 38400;
> -	unsigned int tx_clk_div;
> -	unsigned int ref_clk_mpllb_div;
> -	unsigned int fb_clk_div4_en;
> -	unsigned int ref, vco;
> -	unsigned int tx_rate_mult;
> -	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state-
> >tx[0]);
> -
> -	if (intel_c20phy_use_mpllb(pll_state)) {
> -		tx_rate_mult = 1;
> -		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state-
> >mpllb[6]);
> -		frac_quot = pll_state->mpllb[8];
> -		frac_rem =  pll_state->mpllb[9];
> -		frac_den =  pll_state->mpllb[7];
> -		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mpllb[0]);
> -		tx_clk_div =
> REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
> -		ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
> -		fb_clk_div4_en = 0;
> -	} else {
> -		tx_rate_mult = 2;
> -		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state-
> >mplla[6]);
> -		frac_quot = pll_state->mplla[8];
> -		frac_rem =  pll_state->mplla[9];
> -		frac_den =  pll_state->mplla[7];
> -		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
> pll_state->mplla[0]);
> -		tx_clk_div =
> REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
> -		ref_clk_mpllb_div =
> REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
> -		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN,
> pll_state->mplla[0]);
> -	}
> -
> -	if (frac_en)
> -		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem,
> frac_den);
> -	else
> -		frac = 0;
> -
> -	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
> ref_clk_mpllb_div);
> -	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17
> - 2)) + frac) >> 17, 10);
> -
> -	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
> -}
> -
>  static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
>  					  struct intel_cx0pll_state
> *cx0pll_state)  {
> --
> 2.34.1

RE: [PATCH v2 03/15] drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 03/15] drm/i915/cx0: Drop Cx0 crtc_state from HDMI
> TMDS pll divider calculation
> 
> Drop crtc_state from hdmi tmds calculation and replace with the parameters
> that are only required. Follow-up changes will call these functions without a

Nit: Capitalize acronyms so HDMI,TMDS, PLL

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> crtc_state available.
> 
> v2: Keep required crtc_state param for intel_c20_pll_tables_get()
>     and other functions calling this one.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1deb865618b7..664c48dc0ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2414,9 +2414,8 @@ static bool is_arrowlake_s_by_host_bridge(void)
>  	return pdev &&
> IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
>  }
> 
> -static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state
> *crtc_state)
> +static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_display *display)
>  {
> -	struct intel_display *display = to_intel_display(crtc_state);
>  	u16 tx_misc;
>  	u16 tx_dcc_cal_dac_ctrl_range = 8;
>  	u16 tx_term_ctrl = 2;
> @@ -2438,7 +2437,8 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(const
> struct intel_crtc_state *crtc_stat
>  		C20_PHY_TX_DCC_BYPASS |
> C20_PHY_TX_TERM_CTL(tx_term_ctrl));
>  }
> 
> -static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state
> *crtc_state,
> +static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display,
> +					   int port_clock,
>  					   struct intel_c20pll_state *pll_state)
> {
>  	u64 datarate;
> @@ -2452,10 +2452,10 @@ static int
> intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_s
>  	u8  mpllb_ana_freq_vco;
>  	u8  mpll_div_multiplier;
> 
> -	if (crtc_state->port_clock < 25175 || crtc_state->port_clock >
> 600000)
> +	if (port_clock < 25175 || port_clock > 600000)
>  		return -EINVAL;
> 
> -	datarate = ((u64)crtc_state->port_clock * 1000) * 10;
> +	datarate = ((u64)port_clock * 1000) * 10;
>  	mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ,
> (u64)datarate));
>  	vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256,
> (u64)datarate));
>  	vco_freq = (datarate << vco_freq_shift) >> 8; @@ -2477,9 +2477,9
> @@ static int intel_c20_compute_hdmi_tmds_pll(const struct
> intel_crtc_state *crtc_s
>  	else
>  		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
> 
> -	pll_state->clock	= crtc_state->port_clock;
> +	pll_state->clock	= port_clock;
>  	pll_state->tx[0]	= 0xbe88;
> -	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(crtc_state);
> +	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(display);
>  	pll_state->tx[2]	= 0x0000;
>  	pll_state->cmn[0]	= 0x0500;
>  	pll_state->cmn[1]	= 0x0005;
> @@ -2724,7 +2724,8 @@ static int intel_c20pll_calc_state(const struct
> intel_crtc_state *crtc_state,
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (!is_dp)
>  		/* TODO: Update SSC state for HDMI as well */
> -		err = intel_c20_compute_hdmi_tmds_pll(crtc_state,
> &hw_state->cx0pll.c20);
> +		err = intel_c20_compute_hdmi_tmds_pll(display, crtc_state-
> >port_clock,
> +						      &hw_state->cx0pll.c20);
> 
>  	if (err)
>  		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
> --
> 2.34.1

RE: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port
> calculation
> 
> Drop crtc_state from intel_lt_phy_calc_port_clock() function call and replace
> it with pll state instead. Follow-up changes will call these functions without a
> crtc_state available.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c    |  4 +++-
>  drivers/gpu/drm/i915/display/intel_dpll.c   |  3 ++-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 19 ++++++++-----------
> drivers/gpu/drm/i915/display/intel_lt_phy.h |  4 ++--
>  4 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index cb91d07cdaa6..d8739e2bb004 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4247,13 +4247,15 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,  static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
>  				   struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(encoder);
> +
>  	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state-
> >dpll_hw_state.ltpll);
> 
>  	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
>  		crtc_state->port_clock =
> intel_mtl_tbt_calc_port_clock(encoder);
>  	else
>  		crtc_state->port_clock =
> -			intel_lt_phy_calc_port_clock(encoder, crtc_state);
> +			intel_lt_phy_calc_port_clock(display,
> +&crtc_state->dpll_hw_state.ltpll);
>  	intel_ddi_get_config(encoder, crtc_state);  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a4f372c9e6fc..1b5b18fa0a36 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1219,6 +1219,7 @@ static int xe3plpd_crtc_compute_clock(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder =
>  		intel_get_crtc_new_encoder(state, crtc_state);
> +	struct intel_display *display = to_intel_display(encoder);
>  	int ret;
> 
>  	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder); @@ -1227,7
> +1228,7 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state
> *state,
> 
>  	/* TODO: Do the readback via intel_compute_shared_dplls() */
>  	crtc_state->port_clock =
> -			intel_lt_phy_calc_port_clock(encoder, crtc_state);
> +			intel_lt_phy_calc_port_clock(display,
> +&crtc_state->dpll_hw_state.ltpll);
> 
>  	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 939c8975fd4c..74b0bc90c959 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1679,7 +1679,8 @@ intel_lt_phy_calculate_hdmi_state(struct
> intel_lt_phy_pll_state *lt_state,  }
> 
>  static int
> -intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
> +intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display,
> +				  const struct intel_lt_phy_pll_state *lt_state)
>  {
>  #define REGVAL(i) (				\
>  	(lt_state->data[i][3])		|	\
> @@ -1688,9 +1689,6 @@ intel_lt_phy_calc_hdmi_port_clock(const struct
> intel_crtc_state *crtc_state)
>  	(lt_state->data[i][0] << 24)		\
>  )
> 
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	const struct intel_lt_phy_pll_state *lt_state =
> -		&crtc_state->dpll_hw_state.ltpll;
>  	int clk = 0;
>  	u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
>  	u64 temp0, temp1;
> @@ -1748,12 +1746,10 @@ intel_lt_phy_calc_hdmi_port_clock(const struct
> intel_crtc_state *crtc_state)  }
> 
>  int
> -intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> -			     const struct intel_crtc_state *crtc_state)
> +intel_lt_phy_calc_port_clock(struct intel_display *display,
> +			     const struct intel_lt_phy_pll_state *lt_state)
>  {
>  	int clk;
> -	const struct intel_lt_phy_pll_state *lt_state =
> -		&crtc_state->dpll_hw_state.ltpll;
>  	u8 mode, rate;
> 
>  	mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> @@ -1769,7 +1765,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder
> *encoder,
>  				      lt_state->config[0]);
>  		clk = intel_lt_phy_get_dp_clock(rate);
>  	} else {
> -		clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
> +		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
>  	}
> 
>  	return clk;
> @@ -2220,6 +2216,7 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  				       const struct intel_crtc_state *crtc_state,
>  				       struct intel_lt_phy_pll_state *pll_state)  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	u8 owned_lane_mask;
>  	u8 lane;
>  	struct ref_tracker *wakeref;
> @@ -2245,7 +2242,7 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  	}
> 
>  	pll_state->clock =
> -		intel_lt_phy_calc_port_clock(encoder, crtc_state);
> +		intel_lt_phy_calc_port_clock(display,
> +&crtc_state->dpll_hw_state.ltpll);

Readout_hw_state already has pll_state maybe you can directly pass that instead of what's inside crtc_state
Since by this point we would have read and dumped everything inside pll_state anyways.

Regards,
Suraj Kandpal

>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> @@ -2275,7 +2272,7 @@ void intel_lt_phy_pll_state_verify(struct
> intel_atomic_state *state,
> 
>  	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
>  	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state,
> &pll_hw_state);
> -	clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state);
> +	clock = intel_lt_phy_calc_port_clock(display,
> +&new_crtc_state->dpll_hw_state.ltpll);
> 
>  	dig_port = enc_to_dig_port(encoder);
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 7659c92b6c3c..c4999a55473e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -21,8 +21,8 @@ void intel_lt_phy_pll_disable(struct intel_encoder
> *encoder);  int  intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder);
> -int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> -				 const struct intel_crtc_state *crtc_state);
> +int intel_lt_phy_calc_port_clock(struct intel_display *display,
> +				 const struct intel_lt_phy_pll_state *lt_state);
>  void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *crtc_state);
> void intel_lt_phy_dump_hw_state(struct intel_display *display,
> --
> 2.34.1

RE: [PATCH v2 15/15] drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables

[Kandpal, Suraj]

> Subject: [PATCH v2 15/15] drm/i915/display: Remove .clock member from
> eDP/DP/HDMI pll tables
> 
> PLL state structure has a member .clock. This is not needed as the port clock
> is possible to calculate from the pll dividers.
> Remove the .clock from the pll state structure.

Sounds awkward maybe 
"Remove the encoder from being passed to the port clock calculation function."
Other than that,
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> v2: Keep the pll_state->clock assignment in
>     intel_snps_hdmi_pll_compute_mpllb().
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 86 +------------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 -
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 26 ------
>  .../drm/i915/display/intel_snps_hdmi_pll.c    |  2 -
>  4 files changed, 2 insertions(+), 115 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 5d0bca0f75b0..2a353dfad87d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -547,7 +547,6 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
>   */
> 
>  static const struct intel_c10pll_state mtl_c10_dp_rbr = {
> -	.clock = 162000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0xB4,
> @@ -573,7 +572,6 @@ static const struct intel_c10pll_state mtl_c10_dp_rbr
> = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_edp_r216 = {
> -	.clock = 216000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0x4,
> @@ -599,7 +597,6 @@ static const struct intel_c10pll_state
> mtl_c10_edp_r216 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_edp_r243 = {
> -	.clock = 243000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0x34,
> @@ -625,7 +622,6 @@ static const struct intel_c10pll_state
> mtl_c10_edp_r243 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
> -	.clock = 270000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0xF4,
> @@ -651,7 +647,6 @@ static const struct intel_c10pll_state
> mtl_c10_dp_hbr1 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_edp_r324 = {
> -	.clock = 324000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0xB4,
> @@ -677,7 +672,6 @@ static const struct intel_c10pll_state
> mtl_c10_edp_r324 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_edp_r432 = {
> -	.clock = 432000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0x4,
> @@ -703,7 +697,6 @@ static const struct intel_c10pll_state
> mtl_c10_edp_r432 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
> -	.clock = 540000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0xF4,
> @@ -729,7 +722,6 @@ static const struct intel_c10pll_state
> mtl_c10_dp_hbr2 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_edp_r675 = {
> -	.clock = 675000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0xB4,
> @@ -755,7 +747,6 @@ static const struct intel_c10pll_state
> mtl_c10_edp_r675 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
> -	.clock = 810000,
>  	.tx = 0x10,
>  	.cmn = 0x21,
>  	.pll[0] = 0x34,
> @@ -836,7 +827,6 @@ static const struct intel_cx0pll_params
> mtl_c10_edp_tables[] = {
> 
>  /* C20 basic DP 1.4 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> -	.clock = 162000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x5800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -861,7 +851,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr
> = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> -	.clock = 270000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -886,7 +875,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_hbr1 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> -	.clock = 540000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -911,7 +899,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_hbr2 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> -	.clock = 810000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -937,7 +924,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_hbr3 = {
> 
>  /* C20 basic DP 2.0 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> -	.clock = 1000000, /* 10 Gbps */
>  	.tx = {	0xbe21, /* tx cfg0 */
>  		0xe800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -961,7 +947,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr10 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> -	.clock = 1350000, /* 13.5 Gbps */
>  	.tx = {	0xbea0, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -986,7 +971,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr13_5 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> -	.clock = 2000000, /* 20 Gbps */
>  	.tx = {	0xbe20, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -1025,7 +1009,6 @@ static const struct intel_cx0pll_params
> mtl_c20_dp_tables[] = {
>   */
> 
>  static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> -	.clock = 216000,
>  	.tx = { 0xbe88,
>  		0x4800,
>  		0x0000,
> @@ -1050,7 +1033,6 @@ static const struct intel_c20pll_state
> xe2hpd_c20_edp_r216 = {  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> -	.clock = 243000,
>  	.tx = { 0xbe88,
>  		0x4800,
>  		0x0000,
> @@ -1075,7 +1057,6 @@ static const struct intel_c20pll_state
> xe2hpd_c20_edp_r243 = {  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> -	.clock = 324000,
>  	.tx = { 0xbe88,
>  		0x4800,
>  		0x0000,
> @@ -1100,7 +1081,6 @@ static const struct intel_c20pll_state
> xe2hpd_c20_edp_r324 = {  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> -	.clock = 432000,
>  	.tx = { 0xbe88,
>  		0x4800,
>  		0x0000,
> @@ -1125,7 +1105,6 @@ static const struct intel_c20pll_state
> xe2hpd_c20_edp_r432 = {  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
> -	.clock = 675000,
>  	.tx = { 0xbe88,
>  		0x4800,
>  		0x0000,
> @@ -1163,7 +1142,6 @@ static const struct intel_cx0pll_params
> xe2hpd_c20_edp_tables[] = {  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
> -	.clock = 1350000, /* 13.5 Gbps */
>  	.tx = {	0xbea0, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -1218,7 +1196,6 @@ static const struct intel_cx0pll_params
> xe3lpd_c20_dp_edp_tables[] = {
>   */
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
> -	.clock = 25200,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x4,
> @@ -1244,7 +1221,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_25_2 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
> -	.clock = 27000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34,
> @@ -1270,7 +1246,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_27_0 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
> -	.clock = 74250,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4,
> @@ -1296,7 +1271,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_74_25 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
> -	.clock = 148500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4,
> @@ -1322,7 +1296,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_148_5 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
> -	.clock = 594000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4,
> @@ -1349,7 +1322,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_594 = {
> 
>  /* Precomputed C10 HDMI PLL tables */
>  static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
> -	.clock = 27027,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1359,7 +1331,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_27027 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
> -	.clock = 28320,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1369,7 +1340,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_28320 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
> -	.clock = 30240,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1379,7 +1349,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_30240 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
> -	.clock = 31500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1389,7 +1358,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_31500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
> -	.clock = 36000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1399,7 +1367,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_36000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
> -	.clock = 40000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1409,7 +1376,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_40000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
> -	.clock = 49500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1419,7 +1385,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_49500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
> -	.clock = 50000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1429,7 +1394,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_50000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
> -	.clock = 57284,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1439,7 +1403,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_57284 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
> -	.clock = 58000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1449,7 +1412,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_58000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
> -	.clock = 65000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1459,7 +1421,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_65000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
> -	.clock = 71000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1469,7 +1430,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_71000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
> -	.clock = 74176,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1479,7 +1439,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_74176 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
> -	.clock = 75000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1489,7 +1448,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_75000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
> -	.clock = 78750,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1499,7 +1457,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_78750 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
> -	.clock = 85500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1509,7 +1466,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_85500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
> -	.clock = 88750,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1519,7 +1475,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_88750 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
> -	.clock = 106500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1529,7 +1484,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_106500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
> -	.clock = 108000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1539,7 +1493,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_108000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
> -	.clock = 115500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1549,7 +1502,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_115500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
> -	.clock = 119000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1559,7 +1511,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_119000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
> -	.clock = 135000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1569,7 +1520,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_135000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
> -	.clock = 138500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1579,7 +1529,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_138500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
> -	.clock = 147160,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1589,7 +1538,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_147160 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
> -	.clock = 148352,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1599,7 +1547,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_148352 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
> -	.clock = 154000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1609,7 +1556,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_154000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
> -	.clock = 162000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1619,7 +1565,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_162000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
> -	.clock = 167000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1629,7 +1574,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_167000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
> -	.clock = 197802,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1639,7 +1583,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_197802 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
> -	.clock = 198000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1649,7 +1592,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_198000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
> -	.clock = 209800,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1659,7 +1601,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_209800 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
> -	.clock = 241500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1669,7 +1610,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_241500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
> -	.clock = 262750,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1679,7 +1619,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_262750 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
> -	.clock = 268500,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1689,7 +1628,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_268500 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
> -	.clock = 296703,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1699,7 +1637,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_296703 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
> -	.clock = 297000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1709,7 +1646,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_297000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
> -	.clock = 319750,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1719,7 +1655,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_319750 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
> -	.clock = 497750,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1729,7 +1664,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_497750 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
> -	.clock = 592000,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1739,7 +1673,6 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_592000 = {  };
> 
>  static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
> -	.clock = 593407,
>  	.tx = 0x10,
>  	.cmn = 0x1,
>  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] =
> 0x00, @@ -1798,7 +1731,6 @@ static const struct intel_cx0pll_params
> mtl_c10_hdmi_tables[] = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> -	.clock = 27000,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1823,7 +1755,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_27_0 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> -	.clock = 74250,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1848,7 +1779,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_74_25 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> -	.clock = 148500,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1873,7 +1803,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_148_5 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> -	.clock = 594000,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1898,7 +1827,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_594 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> -	.clock = 300000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1923,7 +1851,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_300 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> -	.clock = 600000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1948,7 +1875,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_600 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> -	.clock = 800000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1973,7 +1899,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_800 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> -	.clock = 1000000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1998,7 +1923,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_1000 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> -	.clock = 1200000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -2338,8 +2262,6 @@ static void intel_c10pll_readout_hw_state(struct
> intel_encoder *encoder,
> 
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> 
> -	pll_state->clock = intel_c10pll_calc_port_clock(pll_state);
> -
>  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> 
>  	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
> @@ -2384,8 +2306,7 @@ static void intel_c10pll_dump_hw_state(struct
> drm_printer *p,
>  	unsigned int multiplier, tx_clk_div;
> 
>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> -	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
> -		   hw_state->clock, str_yes_no(fracen));
> +	drm_printf(p, "c10pll_hw_state: fracen: %s, ", str_yes_no(fracen));
> 
>  	if (fracen) {
>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; @@ -
> 2490,7 +2411,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct
> intel_display *display,
>  	else
>  		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
> 
> -	pll_state->clock	= port_clock;
>  	pll_state->tx[0]	= 0xbe88;
>  	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(display);
>  	pll_state->tx[2]	= 0x0000;
> @@ -2839,8 +2759,6 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
>  		}
>  	}
> 
> -	pll_state->clock = intel_c20pll_calc_port_clock(pll_state);
> -
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> 
>  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder,
> intel_c20phy_use_mpllb(pll_state));
> @@ -2851,7 +2769,7 @@ static void intel_c20pll_dump_hw_state(struct
> drm_printer *p,  {
>  	int i;
> 
> -	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
> +	drm_printf(p, "c20pll_hw_state:\n");
>  	drm_printf(p,
>  		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
>  		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); diff --
> git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 5b71c860515f..4cc14ce5eebe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -241,14 +241,12 @@ struct intel_mpllb_state {  };
> 
>  struct intel_c10pll_state {
> -	u32 clock; /* in KHz */
>  	u8 tx;
>  	u8 cmn;
>  	u8 pll[20];
>  };
> 
>  struct intel_c20pll_state {
> -	u32 clock; /* in kHz */
>  	u16 tx[3];
>  	u16 cmn[4];
>  	union {
> @@ -274,7 +272,6 @@ struct intel_cx0pll_state {  };
> 
>  struct intel_lt_phy_pll_state {
> -	u32 clock; /* in kHz */
>  	u8 addr_msb[13];
>  	u8 addr_lsb[13];
>  	u8 data[13][4];
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index bc73b1466bc4..9a8ea09f6c00 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -59,7 +59,6 @@ struct lt_phy_params {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> -	.clock = 162000,
>  	.config = {
>  		0x83,
>  		0x2d,
> @@ -113,7 +112,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_rbr = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
> -	.clock = 270000,
>  	.config = {
>  		0x8b,
>  		0x2d,
> @@ -167,7 +165,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_hbr1 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
> -	.clock = 540000,
>  	.config = {
>  		0x93,
>  		0x2d,
> @@ -221,7 +218,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_hbr2 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
> -	.clock = 810000,
>  	.config = {
>  		0x9b,
>  		0x2d,
> @@ -275,7 +271,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_hbr3 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
> -	.clock = 1000000,
>  	.config = {
>  		0x43,
>  		0x2d,
> @@ -329,7 +324,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_uhbr10 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
> -	.clock = 1350000,
>  	.config = {
>  		0xcb,
>  		0x2d,
> @@ -383,7 +377,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_uhbr13_5 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
> -	.clock = 2000000,
>  	.config = {
>  		0x53,
>  		0x2d,
> @@ -465,7 +458,6 @@ static const struct intel_lt_phy_pll_params
> xe3plpd_lt_dp_tables[] = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
> -	.clock = 216000,
>  	.config = {
>  		0xa3,
>  		0x2d,
> @@ -519,7 +511,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_edp_2_16 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
> -	.clock = 243000,
>  	.config = {
>  		0xab,
>  		0x2d,
> @@ -573,7 +564,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_edp_2_43 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
> -	.clock = 324000,
>  	.config = {
>  		0xb3,
>  		0x2d,
> @@ -627,7 +617,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_edp_3_24 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
> -	.clock = 432000,
>  	.config = {
>  		0xbb,
>  		0x2d,
> @@ -681,7 +670,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_edp_4_32 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
> -	.clock = 675000,
>  	.config = {
>  		0xdb,
>  		0x2d,
> @@ -748,7 +736,6 @@ static const struct intel_lt_phy_pll_params
> xe3plpd_lt_edp_tables[] = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
> -	.clock = 25200,
>  	.config = {
>  		0x84,
>  		0x2d,
> @@ -802,7 +789,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_252 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
> -	.clock = 74250,
>  	.config = {
>  		0x84,
>  		0x2d,
> @@ -856,7 +842,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_742p5 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
> -	.clock = 148500,
>  	.config = {
>  		0x84,
>  		0x2d,
> @@ -910,7 +895,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_1p485 = {  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
> -	.clock = 594000,
>  	.config = {
>  		0x84,
>  		0x2d,
> @@ -2182,7 +2166,6 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  				       const struct intel_crtc_state *crtc_state,
>  				       struct intel_lt_phy_pll_state *pll_state)  {
> -	struct intel_display *display = to_intel_display(encoder);
>  	u8 owned_lane_mask;
>  	u8 lane;
>  	struct ref_tracker *wakeref;
> @@ -2207,8 +2190,6 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  						  LT_PHY_VDR_X_DATAY(i, j));
>  	}
> 
> -	pll_state->clock =
> -		intel_lt_phy_calc_port_clock(display, &crtc_state-
> >dpll_hw_state.ltpll);
>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> @@ -2222,7 +2203,6 @@ void intel_lt_phy_pll_state_verify(struct
> intel_atomic_state *state,
>  	struct intel_encoder *encoder;
>  	struct intel_lt_phy_pll_state pll_hw_state = {};
>  	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state-
> >dpll_hw_state.ltpll;
> -	int clock;
>  	int i, j;
> 
>  	if (DISPLAY_VER(display) < 35)
> @@ -2238,17 +2218,11 @@ void intel_lt_phy_pll_state_verify(struct
> intel_atomic_state *state,
> 
>  	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
>  	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state,
> &pll_hw_state);
> -	clock = intel_lt_phy_calc_port_clock(display, &new_crtc_state-
> >dpll_hw_state.ltpll);
> 
>  	dig_port = enc_to_dig_port(encoder);
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		return;
> 
> -	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
> -				 "[CRTC:%d:%s] mismatch in LT PHY: Register
> CLOCK (expected %d, found %d)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 pll_sw_state->clock, pll_hw_state.clock);
> -
>  	for (i = 0; i < 3; i++) {
>  		INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i]
> != pll_sw_state->config[i],
>  					 "[CRTC:%d:%s] mismatch in LT PHY
> PLL CONFIG%d: (expected 0x%04x, found 0x%04x)", diff --git
> a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> index a201edceee10..7fe6b4a18213 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> @@ -332,8 +332,6 @@ void intel_snps_hdmi_pll_compute_c10pll(struct
> intel_c10pll_state *pll_state, u6
>  			      c10_curve_1, c10_curve_2, prescaler_divider,
>  			      &pll_params);
> 
> -	pll_state->clock = pixel_clock;
> -
>  	pll_state->tx = 0x10;
>  	pll_state->cmn = 0x1;
>  	pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN,
> pll_params.mpll_div5_en) |
> --
> 2.34.1

RE: [PATCH v2 06/15] drm/i915/cx0: Create macro around pll tables

[Kandpal, Suraj]

> Subject: [PATCH v2 06/15] drm/i915/cx0: Create macro around pll tables
> 
> Create macro for storing pll dividers with table name and clock rate.
> 
> v2: Preserve the terminating {} in each PLL table.
> 

Nit: Acronyms in capital (PLL everywhere)
With that fixed,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 301 ++++++++++---------
>  1 file changed, 167 insertions(+), 134 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b7ac89e32586..ab402bd8a125 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -780,25 +780,58 @@ static const struct intel_c10pll_state
> mtl_c10_dp_hbr3 = {
>  	.pll[19] = 0x23,
>  };
> 
> -static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = {
> -	&mtl_c10_dp_rbr,
> -	&mtl_c10_dp_hbr1,
> -	&mtl_c10_dp_hbr2,
> -	&mtl_c10_dp_hbr3,
> -	NULL,
> -};
> -
> -static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
> -	&mtl_c10_dp_rbr,
> -	&mtl_c10_edp_r216,
> -	&mtl_c10_edp_r243,
> -	&mtl_c10_dp_hbr1,
> -	&mtl_c10_edp_r324,
> -	&mtl_c10_edp_r432,
> -	&mtl_c10_dp_hbr2,
> -	&mtl_c10_edp_r675,
> -	&mtl_c10_dp_hbr3,
> -	NULL,
> +struct intel_cx0pll_params {
> +	const char *name;
> +	bool is_c10;
> +	bool is_hdmi;
> +	int clock_rate;
> +	union {
> +		const struct intel_c10pll_state *c10;
> +		const struct intel_c20pll_state *c20;
> +	};
> +};
> +
> +#define __C10PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \
> +	.name = __stringify(__state), \
> +	.is_c10 = true, \
> +	.is_hdmi = __is_hdmi, \
> +	.clock_rate = __clock_rate, \
> +	.c10 = &__state, \
> +}
> +
> +#define __C20PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
> +	.name = __stringify(__state), \
> +	.is_c10 = false, \
> +	.is_hdmi = __is_hdmi, \
> +	.clock_rate = __clock_rate, \
> +	.c20 = &__state, \
> +}
> +
> +#define C10PLL_HDMI_PARAMS(__clock_rate, __state)
> __C10PLL_PARAMS(true, __clock_rate, __state)
> +#define C10PLL_DP_PARAMS(__clock_rate, __state)
> __C10PLL_PARAMS(false, __clock_rate, __state)
> +
> +#define C20PLL_HDMI_PARAMS(__clock_rate, __state)
> __C20PLL_PARAMS(true, __clock_rate, __state)
> +#define C20PLL_DP_PARAMS(__clock_rate, __state)
> __C20PLL_PARAMS(false, __clock_rate, __state)
> +
> +static const struct intel_cx0pll_params mtl_c10_dp_tables[] = {
> +	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
> +	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
> +	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
> +	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
> +	{}
> +};
> +
> +static const struct intel_cx0pll_params mtl_c10_edp_tables[] = {
> +	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
> +	C10PLL_DP_PARAMS(216000, mtl_c10_edp_r216),
> +	C10PLL_DP_PARAMS(243000, mtl_c10_edp_r243),
> +	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
> +	C10PLL_DP_PARAMS(324000, mtl_c10_edp_r324),
> +	C10PLL_DP_PARAMS(432000, mtl_c10_edp_r432),
> +	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
> +	C10PLL_DP_PARAMS(675000, mtl_c10_edp_r675),
> +	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
> +	{}
>  };
> 
>  /* C20 basic DP 1.4 tables */
> @@ -976,15 +1009,15 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr20 = {
>  		},
>  };
> 
> -static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> -	&mtl_c20_dp_rbr,
> -	&mtl_c20_dp_hbr1,
> -	&mtl_c20_dp_hbr2,
> -	&mtl_c20_dp_hbr3,
> -	&mtl_c20_dp_uhbr10,
> -	&mtl_c20_dp_uhbr13_5,
> -	&mtl_c20_dp_uhbr20,
> -	NULL,
> +static const struct intel_cx0pll_params mtl_c20_dp_tables[] = {
> +	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
> +	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
> +	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
> +	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
> +	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
> +	C20PLL_DP_PARAMS(1350000, mtl_c20_dp_uhbr13_5),
> +	C20PLL_DP_PARAMS(2000000, mtl_c20_dp_uhbr20),
> +	{}
>  };
> 
>  /*
> @@ -1116,17 +1149,17 @@ static const struct intel_c20pll_state
> xe2hpd_c20_edp_r675 = {
>  		  },
>  };
> 
> -static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
> -	&mtl_c20_dp_rbr,
> -	&xe2hpd_c20_edp_r216,
> -	&xe2hpd_c20_edp_r243,
> -	&mtl_c20_dp_hbr1,
> -	&xe2hpd_c20_edp_r324,
> -	&xe2hpd_c20_edp_r432,
> -	&mtl_c20_dp_hbr2,
> -	&xe2hpd_c20_edp_r675,
> -	&mtl_c20_dp_hbr3,
> -	NULL,
> +static const struct intel_cx0pll_params xe2hpd_c20_edp_tables[] = {
> +	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
> +	C20PLL_DP_PARAMS(216000, xe2hpd_c20_edp_r216),
> +	C20PLL_DP_PARAMS(243000, xe2hpd_c20_edp_r243),
> +	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
> +	C20PLL_DP_PARAMS(324000, xe2hpd_c20_edp_r324),
> +	C20PLL_DP_PARAMS(432000, xe2hpd_c20_edp_r432),
> +	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
> +	C20PLL_DP_PARAMS(675000, xe2hpd_c20_edp_r675),
> +	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
> +	{}
>  };
> 
>  static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = { @@ -
> 1154,30 +1187,30 @@ static const struct intel_c20pll_state
> xe2hpd_c20_dp_uhbr13_5 = {
>  		},
>  };
> 
> -static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
> -	&mtl_c20_dp_rbr,
> -	&mtl_c20_dp_hbr1,
> -	&mtl_c20_dp_hbr2,
> -	&mtl_c20_dp_hbr3,
> -	&mtl_c20_dp_uhbr10,
> -	&xe2hpd_c20_dp_uhbr13_5,
> -	NULL,
> +static const struct intel_cx0pll_params xe2hpd_c20_dp_tables[] = {
> +	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
> +	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
> +	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
> +	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
> +	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
> +	C20PLL_DP_PARAMS(1350000, xe2hpd_c20_dp_uhbr13_5),
> +	{}
>  };
> 
> -static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
> -	&mtl_c20_dp_rbr,
> -	&xe2hpd_c20_edp_r216,
> -	&xe2hpd_c20_edp_r243,
> -	&mtl_c20_dp_hbr1,
> -	&xe2hpd_c20_edp_r324,
> -	&xe2hpd_c20_edp_r432,
> -	&mtl_c20_dp_hbr2,
> -	&xe2hpd_c20_edp_r675,
> -	&mtl_c20_dp_hbr3,
> -	&mtl_c20_dp_uhbr10,
> -	&xe2hpd_c20_dp_uhbr13_5,
> -	&mtl_c20_dp_uhbr20,
> -	NULL,
> +static const struct intel_cx0pll_params xe3lpd_c20_dp_edp_tables[] = {
> +	C20PLL_DP_PARAMS(162000, mtl_c20_dp_rbr),
> +	C20PLL_DP_PARAMS(216000, xe2hpd_c20_edp_r216),
> +	C20PLL_DP_PARAMS(243000, xe2hpd_c20_edp_r243),
> +	C20PLL_DP_PARAMS(270000, mtl_c20_dp_hbr1),
> +	C20PLL_DP_PARAMS(324000, xe2hpd_c20_edp_r324),
> +	C20PLL_DP_PARAMS(432000, xe2hpd_c20_edp_r432),
> +	C20PLL_DP_PARAMS(540000, mtl_c20_dp_hbr2),
> +	C20PLL_DP_PARAMS(675000, xe2hpd_c20_edp_r675),
> +	C20PLL_DP_PARAMS(810000, mtl_c20_dp_hbr3),
> +	C20PLL_DP_PARAMS(1000000, mtl_c20_dp_uhbr10),
> +	C20PLL_DP_PARAMS(1350000, xe2hpd_c20_dp_uhbr13_5),
> +	C20PLL_DP_PARAMS(2000000, mtl_c20_dp_uhbr20),
> +	{}
>  };
> 
>  /*
> @@ -1715,53 +1748,53 @@ static const struct intel_c10pll_state
> mtl_c10_hdmi_593407 = {
>  	.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19]
> = 0x23,  };
> 
> -static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
> -	&mtl_c10_hdmi_25_2, /* Consolidated Table */
> -	&mtl_c10_hdmi_27_0, /* Consolidated Table */
> -	&mtl_c10_hdmi_27027,
> -	&mtl_c10_hdmi_28320,
> -	&mtl_c10_hdmi_30240,
> -	&mtl_c10_hdmi_31500,
> -	&mtl_c10_hdmi_36000,
> -	&mtl_c10_hdmi_40000,
> -	&mtl_c10_hdmi_49500,
> -	&mtl_c10_hdmi_50000,
> -	&mtl_c10_hdmi_57284,
> -	&mtl_c10_hdmi_58000,
> -	&mtl_c10_hdmi_65000,
> -	&mtl_c10_hdmi_71000,
> -	&mtl_c10_hdmi_74176,
> -	&mtl_c10_hdmi_74_25, /* Consolidated Table */
> -	&mtl_c10_hdmi_75000,
> -	&mtl_c10_hdmi_78750,
> -	&mtl_c10_hdmi_85500,
> -	&mtl_c10_hdmi_88750,
> -	&mtl_c10_hdmi_106500,
> -	&mtl_c10_hdmi_108000,
> -	&mtl_c10_hdmi_115500,
> -	&mtl_c10_hdmi_119000,
> -	&mtl_c10_hdmi_135000,
> -	&mtl_c10_hdmi_138500,
> -	&mtl_c10_hdmi_147160,
> -	&mtl_c10_hdmi_148352,
> -	&mtl_c10_hdmi_148_5, /* Consolidated Table */
> -	&mtl_c10_hdmi_154000,
> -	&mtl_c10_hdmi_162000,
> -	&mtl_c10_hdmi_167000,
> -	&mtl_c10_hdmi_197802,
> -	&mtl_c10_hdmi_198000,
> -	&mtl_c10_hdmi_209800,
> -	&mtl_c10_hdmi_241500,
> -	&mtl_c10_hdmi_262750,
> -	&mtl_c10_hdmi_268500,
> -	&mtl_c10_hdmi_296703,
> -	&mtl_c10_hdmi_297000,
> -	&mtl_c10_hdmi_319750,
> -	&mtl_c10_hdmi_497750,
> -	&mtl_c10_hdmi_592000,
> -	&mtl_c10_hdmi_593407,
> -	&mtl_c10_hdmi_594, /* Consolidated Table */
> -	NULL,
> +static const struct intel_cx0pll_params mtl_c10_hdmi_tables[] = {
> +	C10PLL_HDMI_PARAMS(25200, mtl_c10_hdmi_25_2), /*
> Consolidated Table */
> +	C10PLL_HDMI_PARAMS(27000, mtl_c10_hdmi_27_0), /*
> Consolidated Table */
> +	C10PLL_HDMI_PARAMS(27027, mtl_c10_hdmi_27027),
> +	C10PLL_HDMI_PARAMS(28320, mtl_c10_hdmi_28320),
> +	C10PLL_HDMI_PARAMS(30240, mtl_c10_hdmi_30240),
> +	C10PLL_HDMI_PARAMS(31500, mtl_c10_hdmi_31500),
> +	C10PLL_HDMI_PARAMS(36000, mtl_c10_hdmi_36000),
> +	C10PLL_HDMI_PARAMS(40000, mtl_c10_hdmi_40000),
> +	C10PLL_HDMI_PARAMS(49500, mtl_c10_hdmi_49500),
> +	C10PLL_HDMI_PARAMS(50000, mtl_c10_hdmi_50000),
> +	C10PLL_HDMI_PARAMS(57284, mtl_c10_hdmi_57284),
> +	C10PLL_HDMI_PARAMS(58000, mtl_c10_hdmi_58000),
> +	C10PLL_HDMI_PARAMS(65000, mtl_c10_hdmi_65000),
> +	C10PLL_HDMI_PARAMS(71000, mtl_c10_hdmi_71000),
> +	C10PLL_HDMI_PARAMS(74176, mtl_c10_hdmi_74176),
> +	C10PLL_HDMI_PARAMS(74250, mtl_c10_hdmi_74_25), /*
> Consolidated Table */
> +	C10PLL_HDMI_PARAMS(75000, mtl_c10_hdmi_75000),
> +	C10PLL_HDMI_PARAMS(78750, mtl_c10_hdmi_78750),
> +	C10PLL_HDMI_PARAMS(85500, mtl_c10_hdmi_85500),
> +	C10PLL_HDMI_PARAMS(88750, mtl_c10_hdmi_88750),
> +	C10PLL_HDMI_PARAMS(106500, mtl_c10_hdmi_106500),
> +	C10PLL_HDMI_PARAMS(108000, mtl_c10_hdmi_108000),
> +	C10PLL_HDMI_PARAMS(115500, mtl_c10_hdmi_115500),
> +	C10PLL_HDMI_PARAMS(119000, mtl_c10_hdmi_119000),
> +	C10PLL_HDMI_PARAMS(135000, mtl_c10_hdmi_135000),
> +	C10PLL_HDMI_PARAMS(138500, mtl_c10_hdmi_138500),
> +	C10PLL_HDMI_PARAMS(147160, mtl_c10_hdmi_147160),
> +	C10PLL_HDMI_PARAMS(148352, mtl_c10_hdmi_148352),
> +	C10PLL_HDMI_PARAMS(148500, mtl_c10_hdmi_148_5), /*
> Consolidated Table */
> +	C10PLL_HDMI_PARAMS(154000, mtl_c10_hdmi_154000),
> +	C10PLL_HDMI_PARAMS(162000, mtl_c10_hdmi_162000),
> +	C10PLL_HDMI_PARAMS(167000, mtl_c10_hdmi_167000),
> +	C10PLL_HDMI_PARAMS(197802, mtl_c10_hdmi_197802),
> +	C10PLL_HDMI_PARAMS(198000, mtl_c10_hdmi_198000),
> +	C10PLL_HDMI_PARAMS(209800, mtl_c10_hdmi_209800),
> +	C10PLL_HDMI_PARAMS(241500, mtl_c10_hdmi_241500),
> +	C10PLL_HDMI_PARAMS(262750, mtl_c10_hdmi_262750),
> +	C10PLL_HDMI_PARAMS(268500, mtl_c10_hdmi_268500),
> +	C10PLL_HDMI_PARAMS(296703, mtl_c10_hdmi_296703),
> +	C10PLL_HDMI_PARAMS(297000, mtl_c10_hdmi_297000),
> +	C10PLL_HDMI_PARAMS(319750, mtl_c10_hdmi_319750),
> +	C10PLL_HDMI_PARAMS(497750, mtl_c10_hdmi_497750),
> +	C10PLL_HDMI_PARAMS(592000, mtl_c10_hdmi_592000),
> +	C10PLL_HDMI_PARAMS(593407, mtl_c10_hdmi_593407),
> +	C10PLL_HDMI_PARAMS(594000, mtl_c10_hdmi_594), /*
> Consolidated Table */
> +	{}
>  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { @@ -2014,21
> +2047,21 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
>  		},
>  };
> 
> -static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> -	&mtl_c20_hdmi_25_175,
> -	&mtl_c20_hdmi_27_0,
> -	&mtl_c20_hdmi_74_25,
> -	&mtl_c20_hdmi_148_5,
> -	&mtl_c20_hdmi_594,
> -	&mtl_c20_hdmi_300,
> -	&mtl_c20_hdmi_600,
> -	&mtl_c20_hdmi_800,
> -	&mtl_c20_hdmi_1000,
> -	&mtl_c20_hdmi_1200,
> -	NULL,
> +static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = {
> +	C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175),
> +	C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0),
> +	C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25),
> +	C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5),
> +	C20PLL_HDMI_PARAMS(594000, mtl_c20_hdmi_594),
> +	C20PLL_HDMI_PARAMS(300000, mtl_c20_hdmi_300),
> +	C20PLL_HDMI_PARAMS(600000, mtl_c20_hdmi_600),
> +	C20PLL_HDMI_PARAMS(800000, mtl_c20_hdmi_800),
> +	C20PLL_HDMI_PARAMS(1000000, mtl_c20_hdmi_1000),
> +	C20PLL_HDMI_PARAMS(1200000, mtl_c20_hdmi_1200),
> +	{}
>  };
> 
> -static const struct intel_c10pll_state * const *
> +static const struct intel_cx0pll_params *
>  intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
>  {
> @@ -2183,16 +2216,16 @@ static int intel_c20pll_calc_port_clock(const
> struct intel_c20pll_state *pll_sta
>   * intel_c20pll_calc_state_from_table().
>   */
>  static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
> -					      const struct intel_c10pll_state *
> const *tables,
> +					      const struct intel_cx0pll_params
> *tables,
>  					      bool is_dp, int port_clock, int
> lane_count,
>  					      struct intel_cx0pll_state
> *pll_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	int i;
> 
> -	for (i = 0; tables[i]; i++) {
> -		if (port_clock == tables[i]->clock) {
> -			pll_state->c10 = *tables[i];
> +	for (i = 0; tables[i].name; i++) {
> +		if (port_clock == tables[i].clock_rate) {
> +			pll_state->c10 = *tables[i].c10;
>  			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
>  			intel_c10pll_update_pll(encoder, pll_state);
> 
> @@ -2214,7 +2247,7 @@ static int intel_c10pll_calc_state(const struct
> intel_crtc_state *crtc_state,  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
> -	const struct intel_c10pll_state * const *tables;
> +	const struct intel_cx0pll_params *tables;
>  	int err;
> 
>  	tables = intel_c10pll_tables_get(crtc_state, encoder); @@ -2505,7
> +2538,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_display
> *display,
>  	return 0;
>  }
> 
> -static const struct intel_c20pll_state * const *
> +static const struct intel_cx0pll_params *
>  intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
>  {
> @@ -2673,20 +2706,20 @@ static void
> intel_c20_program_vdr_params(struct intel_encoder *encoder,
>  		      MB_WRITE_COMMITTED);
>  }
> 
> -static const struct intel_c20pll_state *
> +static const struct intel_cx0pll_params *
>  intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
>  {
> -	const struct intel_c20pll_state * const *tables;
> +	const struct intel_cx0pll_params *tables;
>  	int i;
> 
>  	tables = intel_c20_pll_tables_get(crtc_state, encoder);
>  	if (!tables)
>  		return NULL;
> 
> -	for (i = 0; tables[i]; i++)
> -		if (crtc_state->port_clock == tables[i]->clock)
> -			return tables[i];
> +	for (i = 0; tables[i].name; i++)
> +		if (crtc_state->port_clock == tables[i].clock_rate)
> +			return &tables[i];
> 
>  	return NULL;
>  }
> @@ -2695,13 +2728,13 @@ static int
> intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crt
>  					      struct intel_encoder *encoder,
>  					      struct intel_cx0pll_state
> *pll_state)  {
> -	const struct intel_c20pll_state *table;
> +	const struct intel_cx0pll_params *table;
> 
>  	table = intel_c20_pll_find_table(crtc_state, encoder);
>  	if (!table)
>  		return -EINVAL;
> 
> -	pll_state->c20 = *table;
> +	pll_state->c20 = *table->c20;
> 
>  	intel_cx0pll_update_ssc(encoder, pll_state,
> intel_crtc_has_dp_encoder(crtc_state));
> 
> --
> 2.34.1

RE: [PATCH v2 07/15] drm/i915/lt_phy: Create macro for lt phy pll state

[Kandpal, Suraj]

> Subject: [PATCH v2 07/15] drm/i915/lt_phy: Create macro for lt phy pll state
> 

*LT PHY PLL

> Create a macro for pll state for lt phy similar as for cx0 case.

* PLL state
* LT PHY 

With those fixed,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> v2:
> - Move addition of LT_PHY_PLL_DP/HDMI_PARAMS() to this patch.
> - Fix end of table checking while looking up a table.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 83 +++++++++++++--------
>  1 file changed, 50 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 74b0bc90c959..64e223f35fdf 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -436,15 +436,32 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_dp_uhbr20 = {
>  	},
>  };
> 
> -static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
> -	&xe3plpd_lt_dp_rbr,
> -	&xe3plpd_lt_dp_hbr1,
> -	&xe3plpd_lt_dp_hbr2,
> -	&xe3plpd_lt_dp_hbr3,
> -	&xe3plpd_lt_dp_uhbr10,
> -	&xe3plpd_lt_dp_uhbr13_5,
> -	&xe3plpd_lt_dp_uhbr20,
> -	NULL,
> +struct intel_lt_phy_pll_params {
> +	const char *name;
> +	bool is_hdmi;
> +	int clock_rate;
> +	const struct intel_lt_phy_pll_state *state; };
> +
> +#define __LT_PHY_PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
> +	.name = __stringify(__state), \
> +	.is_hdmi = __is_hdmi, \
> +	.clock_rate = __clock_rate, \
> +	.state = &__state, \
> +}
> +
> +#define LT_PHY_PLL_HDMI_PARAMS(__clock_rate, __state)
> 	__LT_PHY_PLL_PARAMS(true, __clock_rate, __state)
> +#define LT_PHY_PLL_DP_PARAMS(__clock_rate, __state)
> 	__LT_PHY_PLL_PARAMS(false, __clock_rate, __state)
> +
> +static const struct intel_lt_phy_pll_params xe3plpd_lt_dp_tables[] = {
> +	LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
> +	LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
> +	LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
> +	LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
> +	LT_PHY_PLL_DP_PARAMS(1000000, xe3plpd_lt_dp_uhbr10),
> +	LT_PHY_PLL_DP_PARAMS(1350000, xe3plpd_lt_dp_uhbr13_5),
> +	LT_PHY_PLL_DP_PARAMS(2000000, xe3plpd_lt_dp_uhbr20),
> +	{}
>  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = { @@ -
> 717,17 +734,17 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_edp_6_75 = {
>  	},
>  };
> 
> -static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
> -	&xe3plpd_lt_dp_rbr,
> -	&xe3plpd_lt_edp_2_16,
> -	&xe3plpd_lt_edp_2_43,
> -	&xe3plpd_lt_dp_hbr1,
> -	&xe3plpd_lt_edp_3_24,
> -	&xe3plpd_lt_edp_4_32,
> -	&xe3plpd_lt_dp_hbr2,
> -	&xe3plpd_lt_edp_6_75,
> -	&xe3plpd_lt_dp_hbr3,
> -	NULL,
> +static const struct intel_lt_phy_pll_params xe3plpd_lt_edp_tables[] = {
> +	LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
> +	LT_PHY_PLL_DP_PARAMS(216000, xe3plpd_lt_edp_2_16),
> +	LT_PHY_PLL_DP_PARAMS(243000, xe3plpd_lt_edp_2_43),
> +	LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
> +	LT_PHY_PLL_DP_PARAMS(324000, xe3plpd_lt_edp_3_24),
> +	LT_PHY_PLL_DP_PARAMS(432000, xe3plpd_lt_edp_4_32),
> +	LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
> +	LT_PHY_PLL_DP_PARAMS(675000, xe3plpd_lt_edp_6_75),
> +	LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
> +	{}
>  };
> 
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = { @@ -
> 1000,13 +1017,13 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_5p94 = {
>  	},
>  };
> 
> -static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
> -	&xe3plpd_lt_hdmi_252,
> -	&xe3plpd_lt_hdmi_272,
> -	&xe3plpd_lt_hdmi_742p5,
> -	&xe3plpd_lt_hdmi_1p485,
> -	&xe3plpd_lt_hdmi_5p94,
> -	NULL,
> +static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
> +	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
> +	LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
> +	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
> +	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
> +	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
> +	{}
>  };
> 
>  static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
> @@ -1345,7 +1362,7 @@ static void intel_lt_phy_transaction_end(struct
> intel_encoder *encoder, struct r
>  	intel_display_power_put(display, POWER_DOMAIN_DC_OFF,
> wakeref);  }
> 
> -static const struct intel_lt_phy_pll_state * const *
> +static const struct intel_lt_phy_pll_params *
>  intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder)
>  {
> @@ -1734,7 +1751,7 @@ intel_lt_phy_calc_hdmi_port_clock(struct
> intel_display *display,
>  	if (d8 == 0) {
>  		drm_WARN_ON(display->drm,
>  			    "Invalid port clock using lowest HDMI portclock\n");
> -		return xe3plpd_lt_hdmi_252.clock;
> +		return xe3plpd_lt_hdmi_tables[0].clock_rate;
>  	}
>  	m2div_int = (pll_reg_3  & REG_GENMASK(14, 5)) >> 5;
>  	temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32; @@ -1775,16
> +1792,16 @@ int  intel_lt_phy_pll_calc_state(struct intel_crtc_state
> *crtc_state,
>  			    struct intel_encoder *encoder)
>  {
> -	const struct intel_lt_phy_pll_state * const *tables;
> +	const struct intel_lt_phy_pll_params *tables;
>  	int i;
> 
>  	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
>  	if (!tables)
>  		return -EINVAL;
> 
> -	for (i = 0; tables[i]; i++) {
> -		if (crtc_state->port_clock == tables[i]->clock) {
> -			crtc_state->dpll_hw_state.ltpll = *tables[i];
> +	for (i = 0; tables[i].name; i++) {
> +		if (crtc_state->port_clock == tables[i].clock_rate) {
> +			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
>  			if (intel_crtc_has_dp_encoder(crtc_state)) {
>  				if (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))
>  					crtc_state-
> >dpll_hw_state.ltpll.config[2] = 1;
> --
> 2.34.1

RE: [PATCH v2 15/15] drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables

[Kandpal, Suraj]

> Subject: RE: [PATCH v2 15/15] drm/i915/display: Remove .clock member from
> eDP/DP/HDMI pll tables
> 
> > Subject: [PATCH v2 15/15] drm/i915/display: Remove .clock member from
> > eDP/DP/HDMI pll tables
> >
> > PLL state structure has a member .clock. This is not needed as the
> > port clock is possible to calculate from the pll dividers.
> > Remove the .clock from the pll state structure.
> 
> Sounds awkward maybe
> "Remove the encoder from being passed to the port clock calculation
> function."
> Other than that,
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 

Mailing client mess up this was supposed to be a comment for patch 5 of this series but RB still stands for this patch 

Regards,
Suraj Kandpal

> >
> > v2: Keep the pll_state->clock assignment in
> >     intel_snps_hdmi_pll_compute_mpllb().
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 86
> > +------------------ drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 -
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 26 ------
> >  .../drm/i915/display/intel_snps_hdmi_pll.c    |  2 -
> >  4 files changed, 2 insertions(+), 115 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 5d0bca0f75b0..2a353dfad87d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -547,7 +547,6 @@ void intel_cx0_phy_set_signal_levels(struct
> > intel_encoder *encoder,
> >   */
> >
> >  static const struct intel_c10pll_state mtl_c10_dp_rbr = {
> > -	.clock = 162000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0xB4,
> > @@ -573,7 +572,6 @@ static const struct intel_c10pll_state
> > mtl_c10_dp_rbr = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_edp_r216 = {
> > -	.clock = 216000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0x4,
> > @@ -599,7 +597,6 @@ static const struct intel_c10pll_state
> > mtl_c10_edp_r216 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_edp_r243 = {
> > -	.clock = 243000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0x34,
> > @@ -625,7 +622,6 @@ static const struct intel_c10pll_state
> > mtl_c10_edp_r243 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
> > -	.clock = 270000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0xF4,
> > @@ -651,7 +647,6 @@ static const struct intel_c10pll_state
> > mtl_c10_dp_hbr1 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_edp_r324 = {
> > -	.clock = 324000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0xB4,
> > @@ -677,7 +672,6 @@ static const struct intel_c10pll_state
> > mtl_c10_edp_r324 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_edp_r432 = {
> > -	.clock = 432000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0x4,
> > @@ -703,7 +697,6 @@ static const struct intel_c10pll_state
> > mtl_c10_edp_r432 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
> > -	.clock = 540000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0xF4,
> > @@ -729,7 +722,6 @@ static const struct intel_c10pll_state
> > mtl_c10_dp_hbr2 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_edp_r675 = {
> > -	.clock = 675000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0xB4,
> > @@ -755,7 +747,6 @@ static const struct intel_c10pll_state
> > mtl_c10_edp_r675 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
> > -	.clock = 810000,
> >  	.tx = 0x10,
> >  	.cmn = 0x21,
> >  	.pll[0] = 0x34,
> > @@ -836,7 +827,6 @@ static const struct intel_cx0pll_params
> > mtl_c10_edp_tables[] = {
> >
> >  /* C20 basic DP 1.4 tables */
> >  static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > -	.clock = 162000,
> >  	.tx = {	0xbe88, /* tx cfg0 */
> >  		0x5800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -861,7 +851,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_rbr = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > -	.clock = 270000,
> >  	.tx = {	0xbe88, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -886,7 +875,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_hbr1 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > -	.clock = 540000,
> >  	.tx = {	0xbe88, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -911,7 +899,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_hbr2 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > -	.clock = 810000,
> >  	.tx = {	0xbe88, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -937,7 +924,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_hbr3 = {
> >
> >  /* C20 basic DP 2.0 tables */
> >  static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > -	.clock = 1000000, /* 10 Gbps */
> >  	.tx = {	0xbe21, /* tx cfg0 */
> >  		0xe800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -961,7 +947,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_uhbr10 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > -	.clock = 1350000, /* 13.5 Gbps */
> >  	.tx = {	0xbea0, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -986,7 +971,6 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_uhbr13_5 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > -	.clock = 2000000, /* 20 Gbps */
> >  	.tx = {	0xbe20, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -1025,7 +1009,6 @@ static const struct intel_cx0pll_params
> > mtl_c20_dp_tables[] = {
> >   */
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> > -	.clock = 216000,
> >  	.tx = { 0xbe88,
> >  		0x4800,
> >  		0x0000,
> > @@ -1050,7 +1033,6 @@ static const struct intel_c20pll_state
> > xe2hpd_c20_edp_r216 = {  };
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> > -	.clock = 243000,
> >  	.tx = { 0xbe88,
> >  		0x4800,
> >  		0x0000,
> > @@ -1075,7 +1057,6 @@ static const struct intel_c20pll_state
> > xe2hpd_c20_edp_r243 = {  };
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> > -	.clock = 324000,
> >  	.tx = { 0xbe88,
> >  		0x4800,
> >  		0x0000,
> > @@ -1100,7 +1081,6 @@ static const struct intel_c20pll_state
> > xe2hpd_c20_edp_r324 = {  };
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> > -	.clock = 432000,
> >  	.tx = { 0xbe88,
> >  		0x4800,
> >  		0x0000,
> > @@ -1125,7 +1105,6 @@ static const struct intel_c20pll_state
> > xe2hpd_c20_edp_r432 = {  };
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
> > -	.clock = 675000,
> >  	.tx = { 0xbe88,
> >  		0x4800,
> >  		0x0000,
> > @@ -1163,7 +1142,6 @@ static const struct intel_cx0pll_params
> > xe2hpd_c20_edp_tables[] = {  };
> >
> >  static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
> > -	.clock = 1350000, /* 13.5 Gbps */
> >  	.tx = {	0xbea0, /* tx cfg0 */
> >  		0x4800, /* tx cfg1 */
> >  		0x0000, /* tx cfg2 */
> > @@ -1218,7 +1196,6 @@ static const struct intel_cx0pll_params
> > xe3lpd_c20_dp_edp_tables[] = {
> >   */
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
> > -	.clock = 25200,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x4,
> > @@ -1244,7 +1221,6 @@ static const struct intel_c10pll_state
> > mtl_c10_hdmi_25_2 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
> > -	.clock = 27000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34,
> > @@ -1270,7 +1246,6 @@ static const struct intel_c10pll_state
> > mtl_c10_hdmi_27_0 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
> > -	.clock = 74250,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4,
> > @@ -1296,7 +1271,6 @@ static const struct intel_c10pll_state
> > mtl_c10_hdmi_74_25 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
> > -	.clock = 148500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4,
> > @@ -1322,7 +1296,6 @@ static const struct intel_c10pll_state
> > mtl_c10_hdmi_148_5 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
> > -	.clock = 594000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4,
> > @@ -1349,7 +1322,6 @@ static const struct intel_c10pll_state
> > mtl_c10_hdmi_594 = {
> >
> >  /* Precomputed C10 HDMI PLL tables */  static const struct
> > intel_c10pll_state mtl_c10_hdmi_27027 = {
> > -	.clock = 27027,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1359,7 +1331,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_27027 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
> > -	.clock = 28320,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1369,7 +1340,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_28320 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
> > -	.clock = 30240,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1379,7 +1349,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_30240 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
> > -	.clock = 31500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1389,7 +1358,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_31500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
> > -	.clock = 36000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1399,7 +1367,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_36000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
> > -	.clock = 40000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1409,7 +1376,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_40000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
> > -	.clock = 49500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1419,7 +1385,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_49500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
> > -	.clock = 50000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1429,7 +1394,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_50000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
> > -	.clock = 57284,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1439,7 +1403,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_57284 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
> > -	.clock = 58000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1449,7 +1412,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_58000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
> > -	.clock = 65000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1459,7 +1421,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_65000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
> > -	.clock = 71000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1469,7 +1430,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_71000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
> > -	.clock = 74176,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1479,7 +1439,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_74176 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
> > -	.clock = 75000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1489,7 +1448,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_75000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
> > -	.clock = 78750,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1499,7 +1457,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_78750 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
> > -	.clock = 85500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1509,7 +1466,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_85500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
> > -	.clock = 88750,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1519,7 +1475,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_88750 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
> > -	.clock = 106500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1529,7 +1484,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_106500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
> > -	.clock = 108000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1539,7 +1493,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_108000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
> > -	.clock = 115500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1549,7 +1502,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_115500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
> > -	.clock = 119000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1559,7 +1511,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_119000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
> > -	.clock = 135000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1569,7 +1520,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_135000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
> > -	.clock = 138500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1579,7 +1529,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_138500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
> > -	.clock = 147160,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1589,7 +1538,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_147160 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
> > -	.clock = 148352,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1599,7 +1547,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_148352 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
> > -	.clock = 154000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1609,7 +1556,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_154000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
> > -	.clock = 162000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1619,7 +1565,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_162000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
> > -	.clock = 167000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1629,7 +1574,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_167000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
> > -	.clock = 197802,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1639,7 +1583,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_197802 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
> > -	.clock = 198000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1649,7 +1592,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_198000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
> > -	.clock = 209800,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1659,7 +1601,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_209800 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
> > -	.clock = 241500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1669,7 +1610,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_241500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
> > -	.clock = 262750,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1679,7 +1619,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_262750 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
> > -	.clock = 268500,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1689,7 +1628,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_268500 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
> > -	.clock = 296703,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1699,7 +1637,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_296703 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
> > -	.clock = 297000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1709,7 +1646,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_297000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
> > -	.clock = 319750,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1719,7 +1655,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_319750 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
> > -	.clock = 497750,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1729,7 +1664,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_497750 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
> > -	.clock = 592000,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1739,7 +1673,6 @@ static const struct
> > intel_c10pll_state
> > mtl_c10_hdmi_592000 = {  };
> >
> >  static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
> > -	.clock = 593407,
> >  	.tx = 0x10,
> >  	.cmn = 0x1,
> >  	.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00,
> > .pll[4] = 0x00, @@ -1798,7 +1731,6 @@ static const struct
> > intel_cx0pll_params mtl_c10_hdmi_tables[] = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> > -	.clock = 27000,
> >  	.tx = {  0xbe88, /* tx cfg0 */
> >  		  0x9800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1823,7 +1755,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_27_0 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> > -	.clock = 74250,
> >  	.tx = {  0xbe88, /* tx cfg0 */
> >  		  0x9800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1848,7 +1779,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_74_25 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> > -	.clock = 148500,
> >  	.tx = {  0xbe88, /* tx cfg0 */
> >  		  0x9800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1873,7 +1803,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_148_5 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> > -	.clock = 594000,
> >  	.tx = {  0xbe88, /* tx cfg0 */
> >  		  0x9800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1898,7 +1827,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_594 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > -	.clock = 300000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1923,7 +1851,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_300 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > -	.clock = 600000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1948,7 +1875,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_600 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > -	.clock = 800000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1973,7 +1899,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_800 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > -	.clock = 1000000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1998,7 +1923,6 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_1000 = {  };
> >
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > -	.clock = 1200000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -2338,8 +2262,6 @@ static void intel_c10pll_readout_hw_state(struct
> > intel_encoder *encoder,
> >
> >  	intel_cx0_phy_transaction_end(encoder, wakeref);
> >
> > -	pll_state->clock = intel_c10pll_calc_port_clock(pll_state);
> > -
> >  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> >
> >  	if (cx0pll_state->ssc_enabled !=
> > intel_c10pll_ssc_enabled(pll_state))
> > @@ -2384,8 +2306,7 @@ static void intel_c10pll_dump_hw_state(struct
> > drm_printer *p,
> >  	unsigned int multiplier, tx_clk_div;
> >
> >  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> > -	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
> > -		   hw_state->clock, str_yes_no(fracen));
> > +	drm_printf(p, "c10pll_hw_state: fracen: %s, ", str_yes_no(fracen));
> >
> >  	if (fracen) {
> >  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; @@ -
> > 2490,7 +2411,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct
> > intel_display *display,
> >  	else
> >  		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
> >
> > -	pll_state->clock	= port_clock;
> >  	pll_state->tx[0]	= 0xbe88;
> >  	pll_state->tx[1]	= intel_c20_hdmi_tmds_tx_cgf_1(display);
> >  	pll_state->tx[2]	= 0x0000;
> > @@ -2839,8 +2759,6 @@ static void intel_c20pll_readout_hw_state(struct
> > intel_encoder *encoder,
> >  		}
> >  	}
> >
> > -	pll_state->clock = intel_c20pll_calc_port_clock(pll_state);
> > -
> >  	intel_cx0_phy_transaction_end(encoder, wakeref);
> >
> >  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder,
> > intel_c20phy_use_mpllb(pll_state));
> > @@ -2851,7 +2769,7 @@ static void intel_c20pll_dump_hw_state(struct
> > drm_printer *p,  {
> >  	int i;
> >
> > -	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
> > +	drm_printf(p, "c20pll_hw_state:\n");
> >  	drm_printf(p,
> >  		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> >  		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); diff --
> git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 5b71c860515f..4cc14ce5eebe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -241,14 +241,12 @@ struct intel_mpllb_state {  };
> >
> >  struct intel_c10pll_state {
> > -	u32 clock; /* in KHz */
> >  	u8 tx;
> >  	u8 cmn;
> >  	u8 pll[20];
> >  };
> >
> >  struct intel_c20pll_state {
> > -	u32 clock; /* in kHz */
> >  	u16 tx[3];
> >  	u16 cmn[4];
> >  	union {
> > @@ -274,7 +272,6 @@ struct intel_cx0pll_state {  };
> >
> >  struct intel_lt_phy_pll_state {
> > -	u32 clock; /* in kHz */
> >  	u8 addr_msb[13];
> >  	u8 addr_lsb[13];
> >  	u8 data[13][4];
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index bc73b1466bc4..9a8ea09f6c00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -59,7 +59,6 @@ struct lt_phy_params {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> > -	.clock = 162000,
> >  	.config = {
> >  		0x83,
> >  		0x2d,
> > @@ -113,7 +112,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_rbr = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
> > -	.clock = 270000,
> >  	.config = {
> >  		0x8b,
> >  		0x2d,
> > @@ -167,7 +165,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_hbr1 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
> > -	.clock = 540000,
> >  	.config = {
> >  		0x93,
> >  		0x2d,
> > @@ -221,7 +218,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_hbr2 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
> > -	.clock = 810000,
> >  	.config = {
> >  		0x9b,
> >  		0x2d,
> > @@ -275,7 +271,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_hbr3 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
> > -	.clock = 1000000,
> >  	.config = {
> >  		0x43,
> >  		0x2d,
> > @@ -329,7 +324,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_uhbr10 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
> > -	.clock = 1350000,
> >  	.config = {
> >  		0xcb,
> >  		0x2d,
> > @@ -383,7 +377,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_dp_uhbr13_5 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
> > -	.clock = 2000000,
> >  	.config = {
> >  		0x53,
> >  		0x2d,
> > @@ -465,7 +458,6 @@ static const struct intel_lt_phy_pll_params
> > xe3plpd_lt_dp_tables[] = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
> > -	.clock = 216000,
> >  	.config = {
> >  		0xa3,
> >  		0x2d,
> > @@ -519,7 +511,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_edp_2_16 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
> > -	.clock = 243000,
> >  	.config = {
> >  		0xab,
> >  		0x2d,
> > @@ -573,7 +564,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_edp_2_43 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
> > -	.clock = 324000,
> >  	.config = {
> >  		0xb3,
> >  		0x2d,
> > @@ -627,7 +617,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_edp_3_24 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
> > -	.clock = 432000,
> >  	.config = {
> >  		0xbb,
> >  		0x2d,
> > @@ -681,7 +670,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_edp_4_32 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
> > -	.clock = 675000,
> >  	.config = {
> >  		0xdb,
> >  		0x2d,
> > @@ -748,7 +736,6 @@ static const struct intel_lt_phy_pll_params
> > xe3plpd_lt_edp_tables[] = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
> > -	.clock = 25200,
> >  	.config = {
> >  		0x84,
> >  		0x2d,
> > @@ -802,7 +789,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_hdmi_252 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
> > -	.clock = 74250,
> >  	.config = {
> >  		0x84,
> >  		0x2d,
> > @@ -856,7 +842,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_hdmi_742p5 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
> > -	.clock = 148500,
> >  	.config = {
> >  		0x84,
> >  		0x2d,
> > @@ -910,7 +895,6 @@ static const struct intel_lt_phy_pll_state
> > xe3plpd_lt_hdmi_1p485 = {  };
> >
> >  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
> > -	.clock = 594000,
> >  	.config = {
> >  		0x84,
> >  		0x2d,
> > @@ -2182,7 +2166,6 @@ void intel_lt_phy_pll_readout_hw_state(struct
> > intel_encoder *encoder,
> >  				       const struct intel_crtc_state *crtc_state,
> >  				       struct intel_lt_phy_pll_state *pll_state)  {
> > -	struct intel_display *display = to_intel_display(encoder);
> >  	u8 owned_lane_mask;
> >  	u8 lane;
> >  	struct ref_tracker *wakeref;
> > @@ -2207,8 +2190,6 @@ void intel_lt_phy_pll_readout_hw_state(struct
> > intel_encoder *encoder,
> >  						  LT_PHY_VDR_X_DATAY(i, j));
> >  	}
> >
> > -	pll_state->clock =
> > -		intel_lt_phy_calc_port_clock(display, &crtc_state-
> > >dpll_hw_state.ltpll);
> >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> >
> > @@ -2222,7 +2203,6 @@ void intel_lt_phy_pll_state_verify(struct
> > intel_atomic_state *state,
> >  	struct intel_encoder *encoder;
> >  	struct intel_lt_phy_pll_state pll_hw_state = {};
> >  	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state-
> > >dpll_hw_state.ltpll;
> > -	int clock;
> >  	int i, j;
> >
> >  	if (DISPLAY_VER(display) < 35)
> > @@ -2238,17 +2218,11 @@ void intel_lt_phy_pll_state_verify(struct
> > intel_atomic_state *state,
> >
> >  	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> >  	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state,
> > &pll_hw_state);
> > -	clock = intel_lt_phy_calc_port_clock(display, &new_crtc_state-
> > >dpll_hw_state.ltpll);
> >
> >  	dig_port = enc_to_dig_port(encoder);
> >  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> >  		return;
> >
> > -	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
> > -				 "[CRTC:%d:%s] mismatch in LT PHY: Register
> > CLOCK (expected %d, found %d)",
> > -				 crtc->base.base.id, crtc->base.name,
> > -				 pll_sw_state->clock, pll_hw_state.clock);
> > -
> >  	for (i = 0; i < 3; i++) {
> >  		INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i]
> !=
> > pll_sw_state->config[i],
> >  					 "[CRTC:%d:%s] mismatch in LT PHY
> PLL CONFIG%d: (expected
> > 0x%04x, found 0x%04x)", diff --git
> > a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> > b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> > index a201edceee10..7fe6b4a18213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> > @@ -332,8 +332,6 @@ void intel_snps_hdmi_pll_compute_c10pll(struct
> > intel_c10pll_state *pll_state, u6
> >  			      c10_curve_1, c10_curve_2, prescaler_divider,
> >  			      &pll_params);
> >
> > -	pll_state->clock = pixel_clock;
> > -
> >  	pll_state->tx = 0x10;
> >  	pll_state->cmn = 0x1;
> >  	pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN,
> > pll_params.mpll_div5_en) |
> > --
> > 2.34.1

RE: [PATCH v2 05/15] drm/i915/cx0: Drop encoder from port clock calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 05/15] drm/i915/cx0: Drop encoder from port clock
> calculation
> 
> For C10 and C20 we have unused encoder parameter passed to port clock
> calculation function. Remove encoder from passing it to port clock calculation
> function.
> 

Sounds awkward maybe 
"Remove the encoder from being passed to the port clock calculation function."
Other than that,
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 664c48dc0ce3..b7ac89e32586 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2103,8 +2103,7 @@ static bool cx0pll_state_is_dp(const struct
> intel_cx0pll_state *pll_state)
>  	return c20pll_state_is_dp(&pll_state->c20);
>  }
> 
> -static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c10pll_state
> *pll_state)
> +static int intel_c10pll_calc_port_clock(const struct intel_c10pll_state
> +*pll_state)
>  {
>  	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
>  	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; @@ -
> 2135,8 +2134,7 @@ static bool intel_c20phy_use_mpllb(const struct
> intel_c20pll_state *state)
>  	return state->tx[0] & C20_PHY_USE_MPLLB;  }
> 
> -static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c20pll_state
> *pll_state)
> +static int intel_c20pll_calc_port_clock(const struct intel_c20pll_state
> +*pll_state)
>  {
>  	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
>  	unsigned int multiplier, refclk = 38400; @@ -2325,7 +2323,7 @@
> static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> 
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> 
> -	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
> +	pll_state->clock = intel_c10pll_calc_port_clock(pll_state);
> 
>  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> 
> @@ -2821,7 +2819,7 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
>  		}
>  	}
> 
> -	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
> +	pll_state->clock = intel_c20pll_calc_port_clock(pll_state);
> 
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> 
> @@ -3713,9 +3711,9 @@ int intel_cx0pll_calc_port_clock(struct
> intel_encoder *encoder,
>  				 const struct intel_cx0pll_state *pll_state)  {
>  	if (intel_encoder_is_c10phy(encoder))
> -		return intel_c10pll_calc_port_clock(encoder, &pll_state-
> >c10);
> +		return intel_c10pll_calc_port_clock(&pll_state->c10);
> 
> -	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
> +	return intel_c20pll_calc_port_clock(&pll_state->c20);
>  }
> 
>  /*
> --
> 2.34.1

RE: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates

[Kandpal, Suraj]

> Subject: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates
> 
> HDMI FRL clock rates are incorrectly defined. Fix these rates.
> 

Patch can be dropped, you remove the .clock member anyway no point in having a patch whose code fix won't see
Light of day by end of series.

Regards,
Suraj Kandpal

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 4d006c14c049..0f28d02b7a69 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -1923,7 +1923,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_594 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> -	.clock = 3000000,
> +	.clock = 300000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1948,7 +1948,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_300 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> -	.clock = 6000000,
> +	.clock = 600000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1973,7 +1973,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_600 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> -	.clock = 8000000,
> +	.clock = 800000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1998,7 +1998,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_800 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> -	.clock = 10000000,
> +	.clock = 1000000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -2023,7 +2023,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_1000 = {  };
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> -	.clock = 12000000,
> +	.clock = 1200000,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x8800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> --
> 2.34.1

RE: [PATCH v2 13/15] drm/i915/cx0: Drop C20 25.175 MHz rate

[Kandpal, Suraj]

> Subject: [PATCH v2 13/15] drm/i915/cx0: Drop C20 25.175 MHz rate
> 
> Drop C20 25.175 MHz pll table as with these pll dividers the port clock will be
> incorrectly calculated to 25.2 MHz. For 25.175 MHz rate the PLl dividers are
> calculated algorithmically making pll table for this rate redundant.

* PLL
Other than that
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --------------------
>  1 file changed, 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a8c37a14d427..5d0bca0f75b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -1797,31 +1797,6 @@ static const struct intel_cx0pll_params
> mtl_c10_hdmi_tables[] = {
>  	{}
>  };
> 
> -static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> -	.clock = 25175,
> -	.tx = {  0xbe88, /* tx cfg0 */
> -		  0x9800, /* tx cfg1 */
> -		  0x0000, /* tx cfg2 */
> -		},
> -	.cmn = { 0x0500, /* cmn cfg0*/
> -		  0x0005, /* cmn cfg1 */
> -		  0x0000, /* cmn cfg2 */
> -		  0x0000, /* cmn cfg3 */
> -		},
> -	.mpllb = { 0xa0d2,	/* mpllb cfg0 */
> -		   0x7d80,	/* mpllb cfg1 */
> -		   0x0906,	/* mpllb cfg2 */
> -		   0xbe40,	/* mpllb cfg3 */
> -		   0x0000,	/* mpllb cfg4 */
> -		   0x0000,	/* mpllb cfg5 */
> -		   0x0200,	/* mpllb cfg6 */
> -		   0x0001,	/* mpllb cfg7 */
> -		   0x0000,	/* mpllb cfg8 */
> -		   0x0000,	/* mpllb cfg9 */
> -		   0x0001,	/* mpllb cfg10 */
> -		},
> -};
> -
>  static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
>  	.clock = 27000,
>  	.tx = {  0xbe88, /* tx cfg0 */
> @@ -2048,7 +2023,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_1200 = {  };
> 
>  static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = {
> -	C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175),
>  	C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0),
>  	C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25),
>  	C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5),
> --
> 2.34.1

RE: [PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 MHz rate

[Kandpal, Suraj]

> Subject: [PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 MHz rate
> 
> Drop 27.2 MHz pll table as with these pll dividers the port clock will be
> incorrectly calculated to 27.0 MHz.
> For 27.2 MHz rate the PLl dividers are calculated algorithmically making pll
> table for this rate redundant.

*PLL
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 55 ---------------------
>  1 file changed, 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 13acfc7c0469..bc73b1466bc4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -801,60 +801,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_252 = {
>  	},
>  };
> 
> -static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
> -	.clock = 27200,
> -	.config = {
> -		0x84,
> -		0x2d,
> -		0x0,
> -	},
> -	.addr_msb = {
> -		0x87,
> -		0x87,
> -		0x87,
> -		0x87,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -		0x88,
> -	},
> -	.addr_lsb = {
> -		0x10,
> -		0x0c,
> -		0x14,
> -		0xe4,
> -		0x0c,
> -		0x10,
> -		0x14,
> -		0x18,
> -		0x48,
> -		0x40,
> -		0x4c,
> -		0x24,
> -		0x44,
> -	},
> -	.data = {
> -		{ 0x0,  0x4c, 0x2,  0x0  },
> -		{ 0x0b, 0x15, 0x26, 0xa0 },
> -		{ 0x60, 0x0,  0x0,  0x0  },
> -		{ 0x8,  0x4,  0x96, 0x28 },
> -		{ 0xfa, 0x0c, 0x84, 0x11 },
> -		{ 0x80, 0x0f, 0xd9, 0x53 },
> -		{ 0x86, 0x0,  0x0,  0x0  },
> -		{ 0x1,  0xa0, 0x1,  0x0  },
> -		{ 0x4b, 0x0,  0x0,  0x0  },
> -		{ 0x28, 0x0,  0x0,  0x0  },
> -		{ 0x0,  0x14, 0x2a, 0x14 },
> -		{ 0x0,  0x0,  0x0,  0x0  },
> -		{ 0x0,  0x0,  0x0,  0x0  },
> -	},
> -};
> -
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
>  	.clock = 74250,
>  	.config = {
> @@ -1019,7 +965,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_5p94 = {
> 
>  static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
>  	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
> -	LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
>  	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
>  	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
>  	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
> --
> 2.34.1

RE: [PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock check

[Kandpal, Suraj]

> Subject: [PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock
> check
> 
> The hard coded clock rate stored in the PLL state will be removed by a follow-
> up change. Prepare for that here to calculate instead the clock from the PLL

Maybe fix the sentence up here a bit

> divider values in the PLL state. Since this calculated clock can have a +-1 kHz
> difference wrt. the request clock, use a fuzzy check when looking up the
> corresponding table entry.
> 
> v2:
> - Use the stricter +-1 kHz allowed difference.
> - Derive the clock from PLL dividers in intel_cx0pll_enable().
> - Move corresponding fuzzy check for LT PHY PLLs to this patch.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 +++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
> drivers/gpu/drm/i915/display/intel_lt_phy.c  |  6 ++++-
>  3 files changed, 28 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index ab402bd8a125..4d006c14c049 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2211,6 +2211,11 @@ static int intel_c20pll_calc_port_clock(const struct
> intel_c20pll_state *pll_sta
>  	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;  }
> 
> +bool intel_cx0pll_clock_matches(int clock1, int clock2) {
> +	return abs(clock1 - clock2) <= 1;
> +}
> +
>  /*
>   * TODO: Convert the following to align with intel_c20pll_find_table() and
>   * intel_c20pll_calc_state_from_table().
> @@ -2224,7 +2229,10 @@ static int intel_c10pll_calc_state_from_table(struct
> intel_encoder *encoder,
>  	int i;
> 
>  	for (i = 0; tables[i].name; i++) {
> -		if (port_clock == tables[i].clock_rate) {
> +		int clock = intel_c10pll_calc_port_clock(tables[i].c10);
> +
> +		drm_WARN_ON(display->drm,
> !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> +		if (intel_cx0pll_clock_matches(port_clock, clock)) {
>  			pll_state->c10 = *tables[i].c10;
>  			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
>  			intel_c10pll_update_pll(encoder, pll_state); @@ -
> 2710,6 +2718,7 @@ static const struct intel_cx0pll_params *
> intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	const struct intel_cx0pll_params *tables;
>  	int i;
> 
> @@ -2717,9 +2726,13 @@ intel_c20_pll_find_table(const struct
> intel_crtc_state *crtc_state,
>  	if (!tables)
>  		return NULL;
> 
> -	for (i = 0; tables[i].name; i++)
> -		if (crtc_state->port_clock == tables[i].clock_rate)
> +	for (i = 0; tables[i].name; i++) {
> +		int clock = intel_c20pll_calc_port_clock(tables[i].c20);
> +
> +		drm_WARN_ON(display->drm,
> !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> +		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock))
>  			return &tables[i];
> +	}
> 
>  	return NULL;
>  }
> @@ -3252,7 +3265,6 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  				const struct intel_cx0pll_state *pll_state)  {
> -	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state-
> >c20.clock;
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -
> 3260,6 +3272,12 @@ static void intel_cx0pll_enable(struct intel_encoder
> *encoder,
>  	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
>  					  INTEL_CX0_LANE0;
>  	struct ref_tracker *wakeref =
> intel_cx0_phy_transaction_begin(encoder);
> +	int port_clock;
> +
> +	if (pll_state->use_c10)
> +		port_clock = intel_c10pll_calc_port_clock(&pll_state->c10);
> +	else
> +		port_clock = intel_c20pll_calc_port_clock(&pll_state->c20);
> 
>  	/*
>  	 * Lane reversal is never used in DP-alt mode, in that case the diff --git
> a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9f10113e2d18..3d9c580eb562 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -43,6 +43,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder
> *encoder,
>  				    int port_clock);
>  void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
> 
> +bool intel_cx0pll_clock_matches(int clock1, int clock2);
>  int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder,
>  			    struct intel_dpll_hw_state *hw_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 64e223f35fdf..e33f6f48a6ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1792,6 +1792,7 @@ int
>  intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	const struct intel_lt_phy_pll_params *tables;
>  	int i;
> 
> @@ -1800,7 +1801,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state
> *crtc_state,
>  		return -EINVAL;
> 
>  	for (i = 0; tables[i].name; i++) {
> -		if (crtc_state->port_clock == tables[i].clock_rate) {
> +		int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
> +
> +		drm_WARN_ON(display->drm,
> !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> +		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock)) {

Having cx0pll_clock_matches get called in lt phy seems a bit weird
Was thinking if this function belong in Intel_dpll.c intel_dpll_clock_matches() sounds
Better and generalized

Regards,
Suraj Kandpal

>  			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
>  			if (intel_crtc_has_dp_encoder(crtc_state)) {
>  				if (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))
> --
> 2.34.1

Re: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation

[Imre Deak]

On Tue, Jan 06, 2026 at 05:49:15AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation
> > ...
> >
> > @@ -1748,12 +1746,10 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
> > }
> > 
> >  int
> > -intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> > -			     const struct intel_crtc_state *crtc_state)
> > +intel_lt_phy_calc_port_clock(struct intel_display *display,
> > +			     const struct intel_lt_phy_pll_state *lt_state)
> >  {
> >  	int clk;
> > -	const struct intel_lt_phy_pll_state *lt_state =
> > -		&crtc_state->dpll_hw_state.ltpll;
> >  	u8 mode, rate;
> > 
> >  	mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > @@ -1769,7 +1765,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> >  				      lt_state->config[0]);
> >  		clk = intel_lt_phy_get_dp_clock(rate);
> >  	} else {
> > -		clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
> > +		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
> >  	}
> > 
> >  	return clk;
> > @@ -2220,6 +2216,7 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> >  				       const struct intel_crtc_state *crtc_state,
> >  				       struct intel_lt_phy_pll_state *pll_state)
> > {
> > +	struct intel_display *display = to_intel_display(encoder);
> >  	u8 owned_lane_mask;
> >  	u8 lane;
> >  	struct ref_tracker *wakeref;
> > @@ -2245,7 +2242,7 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> >  	}
> > 
> >  	pll_state->clock =
> > -		intel_lt_phy_calc_port_clock(encoder, crtc_state);
> > +		intel_lt_phy_calc_port_clock(display,
> > +&crtc_state->dpll_hw_state.ltpll);
> 
> Readout_hw_state already has pll_state maybe you can directly pass
> that instead of what's inside crtc_state Since by this point we would
> have read and dumped everything inside pll_state anyways.

This is actually a fix of the existing code: crtc_state is the new state
of CTRC computed by the commit when intel_lt_phy_pll_readout_hw_state()
is called from intel_lt_phy_pll_state_verify(). That new CRTC state and
within that the new PLL state is what supposed to be verified, so
nothing from crtc_state should be used to derive the read-out pll_state.

In detail, for the verification intel_lt_phy_pll_readout_hw_state()
reads out the PLL state from the HW into pll_state passed to it, also
computing the corresponding PLL clock via
intel_lt_phy_calc_port_clock(). intel_lt_phy_pll_state_verify() verifies
then if the read-out PLL state in pll_state matches the state in
crtc_state->dpll_hw_state.ltpll. So computing pll_state->clock based on
crtc_state->dpll_hw_state.ltpll is incorrect based on the above (in the
existing code before this patchset) and as such the fix for it should be
a separate patch.

> Regards,
> Suraj Kandpal
> 
> >  	intel_lt_phy_transaction_end(encoder, wakeref);
> > }

Re: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates

[Imre Deak]

On Tue, Jan 06, 2026 at 06:04:18AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates
> > 
> > HDMI FRL clock rates are incorrectly defined. Fix these rates.
> 
> Patch can be dropped, you remove the .clock member anyway no point in
> having a patch whose code fix won't see Light of day by end of series.

Please don't drop this patch. The fix should be recorded in the git
history, even if the changed lines will be removed.

> 
> Regards,
> Suraj Kandpal
> 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 4d006c14c049..0f28d02b7a69 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -1923,7 +1923,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_594 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > -	.clock = 3000000,
> > +	.clock = 300000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1948,7 +1948,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_300 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > -	.clock = 6000000,
> > +	.clock = 600000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1973,7 +1973,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_600 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > -	.clock = 8000000,
> > +	.clock = 800000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1998,7 +1998,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_800 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > -	.clock = 10000000,
> > +	.clock = 1000000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -2023,7 +2023,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_1000 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > -	.clock = 12000000,
> > +	.clock = 1200000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > --
> > 2.34.1
> 

Re: [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers

[Imre Deak]

On Tue, Jan 06, 2026 at 05:04:48AM +0000, Kandpal, Suraj wrote:
> > ...
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 3d9c580eb562..c0ac67f7b11f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -78,6 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
> >  					struct intel_dpll_hw_state *hw_state);
> > int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> > 
> > +void intel_cx0pll_verify_plls(struct intel_display *display);
> >  void intel_cx0_pll_power_save_wa(struct intel_display *display); 
> > void
> > intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> >  				 const struct intel_crtc_state *crtc_state); diff
> > --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 9aa84a430f09..7127bc2a0898 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4613,7 +4613,7 @@ void intel_dpll_init(struct intel_display *display)
> >  		dpll_mgr = &pch_pll_mgr;
> > 
> >  	if (!dpll_mgr)
> > -		return;
> > +		goto out_verify;
> > 
> >  	dpll_info = dpll_mgr->dpll_info;
> > 
> > @@ -4632,6 +4632,13 @@ void intel_dpll_init(struct intel_display *display)
> > 
> >  	display->dpll.mgr = dpll_mgr;
> >  	display->dpll.num_dpll = i;
> > +
> > +out_verify:
> > +	/*
> > +	 * TODO: Convert these to a KUnit test or dependent on a kconfig
> > +	 * debug option.
> > +	 */
> > +	intel_cx0pll_verify_plls(display);
> 
> According to me having this done during every boot does not make
> sense, maybe as a test it may but here having the driver Spend time
> doing these calculations for every table for all the rates seems like
> a waste.

The overhead of the calculation is insignificant. There is also a TODO:
comment above to move it to KUnit/debug test which would remove even
that insignificant overhead.

> Specially when you take into account that all these tables
> are static which means you have the values and the algorithm
> beforehand And before adding the static tables you can get this the
> algorithm tested against the table and fix it accordingly.  Also it
> should be the responsibility of anyone who adds any other static table
> to see if the clock matches.

The purpose is to make sure that no PLL table entries are changed,
breaking them, after they were initially added, even if the initally
added entry was verified manually, separately.

Additionally the function calculating the PLL clock value from the
PLL dividers and the inverse function calculating the PLL divider values
from the clock must be also checked and kept correct against any
potential future change that would break these functions.

> Regards,
> Suraj Kandpal
> 
> >  }
> > 
> >  /**
> > --
> > 2.34.1
> 

Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Imre Deak]

On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> ...
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index e33f6f48a6ce..13acfc7c0469 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >
> > ...
> >
> > +void intel_lt_phy_verify_plls(struct intel_display *display)
> > +{
> > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
> > +}
>
> Same thing as the previous patch this is not needed.  Moreover we do
> not go through any algorithm for edp and dp tables for LT PHY hence
> the Rate always matches. This patch should be dropped.

Similarly to my comment on the previous patch, the tables entries should
be kept correct even after they were initially added. So please don't
drop this patch.

> Regards,
> Suraj Kandpal

RE: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates

[Kandpal, Suraj]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Thursday, January 8, 2026 7:49 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates
> 
> On Tue, Jan 06, 2026 at 06:04:18AM +0000, Kandpal, Suraj wrote:
> > > Subject: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates
> > >
> > > HDMI FRL clock rates are incorrectly defined. Fix these rates.
> >
> > Patch can be dropped, you remove the .clock member anyway no point in
> > having a patch whose code fix won't see Light of day by end of series.
> 
> Please don't drop this patch. The fix should be recorded in the git history, even
> if the changed lines will be removed.

In that case LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> >
> > Regards,
> > Suraj Kandpal
> >
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
> > >  1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index 4d006c14c049..0f28d02b7a69 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -1923,7 +1923,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_hdmi_594 = {  };
> > >
> > >  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > > -	.clock = 3000000,
> > > +	.clock = 300000,
> > >  	.tx = {  0xbe98, /* tx cfg0 */
> > >  		  0x8800, /* tx cfg1 */
> > >  		  0x0000, /* tx cfg2 */
> > > @@ -1948,7 +1948,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_hdmi_300 = {  };
> > >
> > >  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > > -	.clock = 6000000,
> > > +	.clock = 600000,
> > >  	.tx = {  0xbe98, /* tx cfg0 */
> > >  		  0x8800, /* tx cfg1 */
> > >  		  0x0000, /* tx cfg2 */
> > > @@ -1973,7 +1973,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_hdmi_600 = {  };
> > >
> > >  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > > -	.clock = 8000000,
> > > +	.clock = 800000,
> > >  	.tx = {  0xbe98, /* tx cfg0 */
> > >  		  0x8800, /* tx cfg1 */
> > >  		  0x0000, /* tx cfg2 */
> > > @@ -1998,7 +1998,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_hdmi_800 = {  };
> > >
> > >  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > > -	.clock = 10000000,
> > > +	.clock = 1000000,
> > >  	.tx = {  0xbe98, /* tx cfg0 */
> > >  		  0x8800, /* tx cfg1 */
> > >  		  0x0000, /* tx cfg2 */
> > > @@ -2023,7 +2023,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_hdmi_1000 = {  };
> > >
> > >  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > > -	.clock = 12000000,
> > > +	.clock = 1200000,
> > >  	.tx = {  0xbe98, /* tx cfg0 */
> > >  		  0x8800, /* tx cfg1 */
> > >  		  0x0000, /* tx cfg2 */
> > > --
> > > 2.34.1
> >

RE: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Kandpal, Suraj]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Thursday, January 8, 2026 8:06 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> dividers
> 
> On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > ...
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index e33f6f48a6ce..13acfc7c0469 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > >
> > > ...
> > >
> > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); }
> >
> > Same thing as the previous patch this is not needed.  Moreover we do
> > not go through any algorithm for edp and dp tables for LT PHY hence
> > the Rate always matches. This patch should be dropped.
> 
> Similarly to my comment on the previous patch, the tables entries should be
> kept correct even after they were initially added. So please don't drop this
> patch.

But testing DP eDP tables still does not make sense here since they don't go through the traditional
HDMI algo that CX0 go through the clock rate in a way is signalled just by a single entry of VDR0_CONFIG
So other than verifying table for HDMI the rest need not be done.

Regards,
Suraj Kandpal

> 
> > Regards,
> > Suraj Kandpal

RE: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Friday, 9 January 2026 6.12
> To: Deak, Imre <imre.deak@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers
> 
> 
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Thursday, January 8, 2026 8:06 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Kahola, Mika <mika.kahola@intel.com>;
> > intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt
> > phy pll dividers
> >
> > On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > > ...
> > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index e33f6f48a6ce..13acfc7c0469 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > >
> > > > ...
> > > >
> > > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
> > > > +}
> > >
> > > Same thing as the previous patch this is not needed.  Moreover we do
> > > not go through any algorithm for edp and dp tables for LT PHY hence
> > > the Rate always matches. This patch should be dropped.
> >
> > Similarly to my comment on the previous patch, the tables entries
> > should be kept correct even after they were initially added. So please
> > don't drop this patch.
> 
> But testing DP eDP tables still does not make sense here since they don’t go through the traditional HDMI algo that CX0 go through
> the clock rate in a way is signalled just by a single entry of VDR0_CONFIG So other than verifying table for HDMI the rest need not
> be done.

The idea of checking all tables was that if table entries will be updated for any reason, we would do this health check for pll dividers. As Imre mentioned already, this health check could be part of KUnit testing. For future work, adding a test to KUnit would be preferable way to go.

> 
> Regards,
> Suraj Kandpal
> 
> >
> > > Regards,
> > > Suraj Kandpal

Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Imre Deak]

On Fri, Jan 09, 2026 at 06:12:25AM +0200, Kandpal, Suraj wrote:
> 
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Thursday, January 8, 2026 8:06 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> > intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> > dividers
> > 
> > On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > > ...
> > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index e33f6f48a6ce..13acfc7c0469 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > >
> > > > ...
> > > >
> > > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); }
> > >
> > > Same thing as the previous patch this is not needed.  Moreover we do
> > > not go through any algorithm for edp and dp tables for LT PHY hence
> > > the Rate always matches. This patch should be dropped.
> > 
> > Similarly to my comment on the previous patch, the tables entries should be
> > kept correct even after they were initially added. So please don't drop this
> > patch.
> 
> But testing DP eDP tables still does not make sense here since they
> don't go through the traditional HDMI algo that CX0 go through the
> clock rate in a way is signalled just by a single entry of VDR0_CONFIG
> So other than verifying table for HDMI the rest need not be done.

The LT PHY DP/eDP PLL determination of the PLL clock from the PLL state
and the inverse determination of the PLL state from the PLL clock is
just the same as for HDMI. The fact that the PLL state is just the
VDR0_CONFIG register value for eDP/DP vs. the PLL divider values for
HDMI is odd and should be looked into and fixed in my opinion (so that
we know that the rest of the eDP/DP PLL state is actually correct), but
this difference between eDP/DP vs. HDMI is irrelevant. What matters is
that the PLL clock is calculated from the PLL state and we do need a way
to verify that the PLL clock matches the PLL state and the functions
converting between the two are also correct (and all these things stay
correct even after the initial addition of the table entries and the
functions).

> > 
> > > Regards,
> > > Suraj Kandpal

RE: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Kandpal, Suraj]

> Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> dividers
> 
> On Fri, Jan 09, 2026 at 06:12:25AM +0200, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Thursday, January 8, 2026 8:06 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Cc: Kahola, Mika <mika.kahola@intel.com>;
> > > intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for
> > > lt phy pll dividers
> > >
> > > On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > > > ...
> > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > index e33f6f48a6ce..13acfc7c0469 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > >
> > > > > ...
> > > > >
> > > > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > > > +	intel_lt_phy_pll_verify_tables(display,
> > > > > +xe3plpd_lt_hdmi_tables); }
> > > >
> > > > Same thing as the previous patch this is not needed.  Moreover we
> > > > do not go through any algorithm for edp and dp tables for LT PHY
> > > > hence the Rate always matches. This patch should be dropped.
> > >
> > > Similarly to my comment on the previous patch, the tables entries
> > > should be kept correct even after they were initially added. So
> > > please don't drop this patch.
> >
> > But testing DP eDP tables still does not make sense here since they
> > don't go through the traditional HDMI algo that CX0 go through the
> > clock rate in a way is signalled just by a single entry of VDR0_CONFIG
> > So other than verifying table for HDMI the rest need not be done.
> 
> The LT PHY DP/eDP PLL determination of the PLL clock from the PLL state and
> the inverse determination of the PLL state from the PLL clock is just the same as
> for HDMI. The fact that the PLL state is just the VDR0_CONFIG register value for
> eDP/DP vs. the PLL divider values for HDMI is odd and should be looked into
> and fixed in my opinion (so that we know that the rest of the eDP/DP PLL state
> is actually correct), but this difference between eDP/DP vs. HDMI is irrelevant.
> What matters is that the PLL clock is calculated from the PLL state and we do
> need a way to verify that the PLL clock matches the PLL state and the functions
> converting between the two are also correct (and all these things stay correct
> even after the initial addition of the table entries and the functions).
> 

Hmm,
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> > >
> > > > Regards,
> > > > Suraj Kandpal

RE: [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers

[Kandpal, Suraj]

> Subject: Re: [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers
> 
> On Tue, Jan 06, 2026 at 05:04:48AM +0000, Kandpal, Suraj wrote:
> > > ...
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > index 3d9c580eb562..c0ac67f7b11f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > > @@ -78,6 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct
> intel_display *display,
> > >  					struct intel_dpll_hw_state *hw_state);
> int
> > > intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> > >
> > > +void intel_cx0pll_verify_plls(struct intel_display *display);
> > >  void intel_cx0_pll_power_save_wa(struct intel_display *display);
> > > void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> > >  				 const struct intel_crtc_state *crtc_state); diff -
> -git
> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index 9aa84a430f09..7127bc2a0898 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -4613,7 +4613,7 @@ void intel_dpll_init(struct intel_display *display)
> > >  		dpll_mgr = &pch_pll_mgr;
> > >
> > >  	if (!dpll_mgr)
> > > -		return;
> > > +		goto out_verify;
> > >
> > >  	dpll_info = dpll_mgr->dpll_info;
> > >
> > > @@ -4632,6 +4632,13 @@ void intel_dpll_init(struct intel_display
> > > *display)
> > >
> > >  	display->dpll.mgr = dpll_mgr;
> > >  	display->dpll.num_dpll = i;
> > > +
> > > +out_verify:
> > > +	/*
> > > +	 * TODO: Convert these to a KUnit test or dependent on a kconfig
> > > +	 * debug option.
> > > +	 */
> > > +	intel_cx0pll_verify_plls(display);
> >
> > According to me having this done during every boot does not make
> > sense, maybe as a test it may but here having the driver Spend time
> > doing these calculations for every table for all the rates seems like
> > a waste.
> 
> The overhead of the calculation is insignificant. There is also a TODO:
> comment above to move it to KUnit/debug test which would remove even that
> insignificant overhead.
> 
> > Specially when you take into account that all these tables are static
> > which means you have the values and the algorithm beforehand And
> > before adding the static tables you can get this the algorithm tested
> > against the table and fix it accordingly.  Also it should be the
> > responsibility of anyone who adds any other static table to see if the
> > clock matches.
> 
> The purpose is to make sure that no PLL table entries are changed, breaking
> them, after they were initially added, even if the initally added entry was
> verified manually, separately.
> 
> Additionally the function calculating the PLL clock value from the PLL dividers
> and the inverse function calculating the PLL divider values from the clock must
> be also checked and kept correct against any potential future change that
> would break these functions.

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> > Regards,
> > Suraj Kandpal
> >
> > >  }
> > >
> > >  /**
> > > --
> > > 2.34.1
> >

RE: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation

[Kandpal, Suraj]

> Subject: Re: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port
> calculation
> 
> On Tue, Jan 06, 2026 at 05:49:15AM +0000, Kandpal, Suraj wrote:
> > > Subject: [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state
> > > for port calculation ...
> > >
> > > @@ -1748,12 +1746,10 @@ intel_lt_phy_calc_hdmi_port_clock(const
> > > struct intel_crtc_state *crtc_state) }
> > >
> > >  int
> > > -intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
> > > -			     const struct intel_crtc_state *crtc_state)
> > > +intel_lt_phy_calc_port_clock(struct intel_display *display,
> > > +			     const struct intel_lt_phy_pll_state *lt_state)
> > >  {
> > >  	int clk;
> > > -	const struct intel_lt_phy_pll_state *lt_state =
> > > -		&crtc_state->dpll_hw_state.ltpll;
> > >  	u8 mode, rate;
> > >
> > >  	mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > > @@ -1769,7 +1765,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder
> *encoder,
> > >  				      lt_state->config[0]);
> > >  		clk = intel_lt_phy_get_dp_clock(rate);
> > >  	} else {
> > > -		clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
> > > +		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
> > >  	}
> > >
> > >  	return clk;
> > > @@ -2220,6 +2216,7 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
> > >  				       const struct intel_crtc_state *crtc_state,
> > >  				       struct intel_lt_phy_pll_state *pll_state) {
> > > +	struct intel_display *display = to_intel_display(encoder);
> > >  	u8 owned_lane_mask;
> > >  	u8 lane;
> > >  	struct ref_tracker *wakeref;
> > > @@ -2245,7 +2242,7 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
> > >  	}
> > >
> > >  	pll_state->clock =
> > > -		intel_lt_phy_calc_port_clock(encoder, crtc_state);
> > > +		intel_lt_phy_calc_port_clock(display,
> > > +&crtc_state->dpll_hw_state.ltpll);
> >
> > Readout_hw_state already has pll_state maybe you can directly pass
> > that instead of what's inside crtc_state Since by this point we would
> > have read and dumped everything inside pll_state anyways.
> 
> This is actually a fix of the existing code: crtc_state is the new state of CTRC
> computed by the commit when intel_lt_phy_pll_readout_hw_state()
> is called from intel_lt_phy_pll_state_verify(). That new CRTC state and within
> that the new PLL state is what supposed to be verified, so nothing from
> crtc_state should be used to derive the read-out pll_state.
> 
> In detail, for the verification intel_lt_phy_pll_readout_hw_state()
> reads out the PLL state from the HW into pll_state passed to it, also computing
> the corresponding PLL clock via intel_lt_phy_calc_port_clock().
> intel_lt_phy_pll_state_verify() verifies then if the read-out PLL state in pll_state
> matches the state in crtc_state->dpll_hw_state.ltpll. So computing pll_state-
> >clock based on crtc_state->dpll_hw_state.ltpll is incorrect based on the above
> (in the existing code before this patchset) and as such the fix for it should be a
> separate patch.
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> > Regards,
> > Suraj Kandpal
> >
> > >  	intel_lt_phy_transaction_end(encoder, wakeref); }

RE: [PATCH v2 10/15] drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming

[Kandpal, Suraj]

> Subject: [PATCH v2 10/15] drm/i915/cx0: Add a fuzzy check for DP/HDMI clock
> rates during programming
> 
> Since the clock rate is derived from the PLL divider values it can have a +-1kHz
> difference wrt. the reference rates in the comparison

This LGTM but patch 8 needs to go through changes that will reflect here will hold on to RB till then

Regards,
Suraj Kandpal

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 +++++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c    | 18 ++++++++----------
>  2 files changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 0f28d02b7a69..ea807191cb4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3013,6 +3013,12 @@ static void intel_c20_pll_program(struct
> intel_display *display,
>  		      MB_WRITE_COMMITTED);
>  }
> 
> +static bool is_mplla_clock_rate(int clock) {
> +	return intel_cx0pll_clock_matches(clock, 1000000) ||
> +	       intel_cx0pll_clock_matches(clock, 2000000); }
> +
>  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  					 const struct intel_cx0pll_state
> *pll_state,
>  					 int port_clock,
> @@ -3038,7 +3044,7 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
> 
>  	/* TODO: HDMI FRL */
>  	/* DP2.0 10G and 20G rates enable MPLLA*/
> -	if (port_clock == 1000000 || port_clock == 2000000)
> +	if (is_mplla_clock_rate(port_clock))
>  		val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
>  	else
>  		val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 055e68810d0d..63a88006e336 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -70,16 +70,14 @@
> 
>  bool intel_hdmi_is_frl(u32 clock)
>  {
> -	switch (clock) {
> -	case 300000: /* 3 Gbps */
> -	case 600000: /* 6 Gbps */
> -	case 800000: /* 8 Gbps */
> -	case 1000000: /* 10 Gbps */
> -	case 1200000: /* 12 Gbps */
> -		return true;
> -	default:
> -		return false;
> -	}
> +	u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(rates); i++)
> +		if (intel_cx0pll_clock_matches(clock, rates[i]))
> +			return true;
> +
> +	return false;
>  }
> 
>  static void
> --
> 2.34.1

RE: [PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock check

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Thursday, 8 January 2026 5.54
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock check
> 
> > Subject: [PATCH v2 08/15] drm/i915/display: Add helper function for
> > fuzzy clock check
> >
> > The hard coded clock rate stored in the PLL state will be removed by a
> > follow- up change. Prepare for that here to calculate instead the
> > clock from the PLL
> 
> Maybe fix the sentence up here a bit
> 
> > divider values in the PLL state. Since this calculated clock can have
> > a +-1 kHz difference wrt. the request clock, use a fuzzy check when
> > looking up the corresponding table entry.
> >
> > v2:
> > - Use the stricter +-1 kHz allowed difference.
> > - Derive the clock from PLL dividers in intel_cx0pll_enable().
> > - Move corresponding fuzzy check for LT PHY PLLs to this patch.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26
> > +++++++++++++++++--- drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1
> > + drivers/gpu/drm/i915/display/intel_lt_phy.c  |  6 ++++-
> >  3 files changed, 28 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index ab402bd8a125..4d006c14c049 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2211,6 +2211,11 @@ static int intel_c20pll_calc_port_clock(const
> > struct intel_c20pll_state *pll_sta
> >  	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;  }
> >
> > +bool intel_cx0pll_clock_matches(int clock1, int clock2) {
> > +	return abs(clock1 - clock2) <= 1;
> > +}
> > +
> >  /*
> >   * TODO: Convert the following to align with intel_c20pll_find_table() and
> >   * intel_c20pll_calc_state_from_table().
> > @@ -2224,7 +2229,10 @@ static int
> > intel_c10pll_calc_state_from_table(struct
> > intel_encoder *encoder,
> >  	int i;
> >
> >  	for (i = 0; tables[i].name; i++) {
> > -		if (port_clock == tables[i].clock_rate) {
> > +		int clock = intel_c10pll_calc_port_clock(tables[i].c10);
> > +
> > +		drm_WARN_ON(display->drm,
> > !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> > +		if (intel_cx0pll_clock_matches(port_clock, clock)) {
> >  			pll_state->c10 = *tables[i].c10;
> >  			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
> >  			intel_c10pll_update_pll(encoder, pll_state); @@ -
> > 2710,6 +2718,7 @@ static const struct intel_cx0pll_params *
> > intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
> >  			 struct intel_encoder *encoder)
> >  {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> >  	const struct intel_cx0pll_params *tables;
> >  	int i;
> >
> > @@ -2717,9 +2726,13 @@ intel_c20_pll_find_table(const struct
> > intel_crtc_state *crtc_state,
> >  	if (!tables)
> >  		return NULL;
> >
> > -	for (i = 0; tables[i].name; i++)
> > -		if (crtc_state->port_clock == tables[i].clock_rate)
> > +	for (i = 0; tables[i].name; i++) {
> > +		int clock = intel_c20pll_calc_port_clock(tables[i].c20);
> > +
> > +		drm_WARN_ON(display->drm,
> > !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> > +		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock))
> >  			return &tables[i];
> > +	}
> >
> >  	return NULL;
> >  }
> > @@ -3252,7 +3265,6 @@ static u32 intel_cx0_get_pclk_pll_ack(u8
> > lane_mask) static void intel_cx0pll_enable(struct intel_encoder *encoder,
> >  				const struct intel_cx0pll_state *pll_state)  {
> > -	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state-
> > >c20.clock;
> >  	struct intel_display *display = to_intel_display(encoder);
> >  	enum phy phy = intel_encoder_to_phy(encoder);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -
> > 3260,6 +3272,12 @@ static void intel_cx0pll_enable(struct
> > intel_encoder *encoder,
> >  	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> >  					  INTEL_CX0_LANE0;
> >  	struct ref_tracker *wakeref =
> > intel_cx0_phy_transaction_begin(encoder);
> > +	int port_clock;
> > +
> > +	if (pll_state->use_c10)
> > +		port_clock = intel_c10pll_calc_port_clock(&pll_state->c10);
> > +	else
> > +		port_clock = intel_c20pll_calc_port_clock(&pll_state->c20);
> >
> >  	/*
> >  	 * Lane reversal is never used in DP-alt mode, in that case the diff
> > --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 9f10113e2d18..3d9c580eb562 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -43,6 +43,7 @@ void intel_mtl_tbt_pll_enable_clock(struct
> > intel_encoder *encoder,
> >  				    int port_clock);
> >  void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
> >
> > +bool intel_cx0pll_clock_matches(int clock1, int clock2);
> >  int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> >  			    struct intel_encoder *encoder,
> >  			    struct intel_dpll_hw_state *hw_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 64e223f35fdf..e33f6f48a6ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1792,6 +1792,7 @@ int
> >  intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> >  			    struct intel_encoder *encoder)  {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> >  	const struct intel_lt_phy_pll_params *tables;
> >  	int i;
> >
> > @@ -1800,7 +1801,10 @@ intel_lt_phy_pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> >  		return -EINVAL;
> >
> >  	for (i = 0; tables[i].name; i++) {
> > -		if (crtc_state->port_clock == tables[i].clock_rate) {
> > +		int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
> > +
> > +		drm_WARN_ON(display->drm,
> > !intel_cx0pll_clock_matches(clock, tables[i].clock_rate));
> > +		if (intel_cx0pll_clock_matches(crtc_state->port_clock, clock)) {
> 
> Having cx0pll_clock_matches get called in lt phy seems a bit weird Was thinking if this function belong in Intel_dpll.c
> intel_dpll_clock_matches() sounds Better and generalized

Yes, you're right. The naming doesn't really match with the lt phy anymore. I will update this for the next version.

> 
> Regards,
> Suraj Kandpal
> 
> >  			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
> >  			if (intel_crtc_has_dp_encoder(crtc_state)) {
> >  				if (intel_crtc_has_type(crtc_state,
> > INTEL_OUTPUT_EDP))
> > --
> > 2.34.1