* [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
@ 2026-03-05 8:18 ` Arun R Murthy
2026-03-05 9:18 ` Jani Nikula
2026-03-05 16:29 ` Imre Deak
2026-03-05 8:18 ` [PATCH RFC 2/4] drm/i915/dp: Read LTTPR caps followed by " Arun R Murthy
` (7 subsequent siblings)
8 siblings, 2 replies; 18+ messages in thread
From: Arun R Murthy @ 2026-03-05 8:18 UTC (permalink / raw)
To: Imre Deak, Ville Syrjälä, Jani Nikula
Cc: dri-devel, intel-gfx, intel-xe, Arun R Murthy
We at present have drm_dp_Read_lttpr_common_caps to read the LTTPR caps,
but this function required DPRX caps to be passed. As per the DP2.1 spec
section 3.6.8.6.1, section 2.12.1, section 2.12.3 (Link Policy) the
LTTPR caps is to be read first followed by the DPRX capability.
Hence adding another function to read the LTTPR caps without the need
for DPRX caps.
In order to handle the issue
https://gitlab.freedesktop.org/drm/intel/-/issues/4531
of reading corrupted values for LTTPR caps on few pannels with DP Rev 1.2
the workaround of reducing the block size to 1 and reading one block at a
time is done by checking for a valid link rate.
Fixes: 657586e474bd ("drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities")
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 63 +++++++++++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 2 ++
2 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index a697cc227e28964cd8322803298178e7d788e820..9fe7db73027a43b01c4d12927f1f0e61444658e5 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3050,6 +3050,69 @@ static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
return 0;
}
+static bool drm_dp_valid_link_rate(u8 link_rate)
+{
+ switch (link_rate) {
+ case 0x06:
+ case 0x0a:
+ case 0x14:
+ case 0x1e:
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * drm_dp_read_lttpr_caps - read the LTTPR capabilities
+ * @aux: DisplayPort AUX channel
+ * @caps: buffer to return the capability info in
+ *
+ * Read capabilities common to all LTTPRs.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
+ u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+ /*
+ * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
+ * corrupted values when reading from the 0xF0000- range with a block
+ * size bigger than 1.
+ * For DP as per the spec DP2.1 section 3.6.8.6.1, section 2.12.1, section
+ * 2.12.3 (Link Policy) the LTTPR caps is to be read first followed by the
+ * DPRX capability.
+ * So ideally we dont have DPCD_REV yet to check for the revision, instead
+ * check for the correctness of the read value and in found corrupted read
+ * block by block.
+ */
+ int block_size;
+ int offset;
+ int ret;
+ int address = DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV;
+ int buf_size = DP_LTTPR_COMMON_CAP_SIZE;
+
+ ret = drm_dp_dpcd_read_data(aux, address, &caps, buf_size);
+ if (ret < 0)
+ return ret;
+
+ if (caps[0] == 0x14) {
+ if (!drm_dp_valid_link_rate(caps[1])) {
+ block_size = 1;
+ for (offset = 0; offset < buf_size; offset += block_size) {
+ ret = drm_dp_dpcd_read_data(aux,
+ address + offset,
+ &caps[offset],
+ block_size);
+ if (ret < 0)
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_lttpr_caps);
+
/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 1d0acd58f48676f60ff6a07cc6812f72cbb452e8..def145e67011c325b790c807f934b288304260c1 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -755,6 +755,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
const struct drm_dp_desc *desc);
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
+int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
+ u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without DPRX caps
2026-03-05 8:18 ` [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without " Arun R Murthy
@ 2026-03-05 9:18 ` Jani Nikula
2026-03-06 4:08 ` Murthy, Arun R
2026-03-05 16:29 ` Imre Deak
1 sibling, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2026-03-05 9:18 UTC (permalink / raw)
To: Arun R Murthy, Imre Deak, Ville Syrjälä
Cc: dri-devel, intel-gfx, intel-xe, Arun R Murthy
On Thu, 05 Mar 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> We at present have drm_dp_Read_lttpr_common_caps to read the LTTPR caps,
> but this function required DPRX caps to be passed. As per the DP2.1 spec
> section 3.6.8.6.1, section 2.12.1, section 2.12.3 (Link Policy) the
> LTTPR caps is to be read first followed by the DPRX capability.
> Hence adding another function to read the LTTPR caps without the need
> for DPRX caps.
If the spec says something, why are we keeping the function that does it
the other way?
> In order to handle the issue
> https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> of reading corrupted values for LTTPR caps on few pannels with DP Rev 1.2
> the workaround of reducing the block size to 1 and reading one block at a
> time is done by checking for a valid link rate.
>
> Fixes: 657586e474bd ("drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities")
You're not calling the code being added here. This can't fix anything on
its own. This is not how the Fixes: tag works.
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 63 +++++++++++++++++++++++++++++++++
> include/drm/display/drm_dp_helper.h | 2 ++
> 2 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index a697cc227e28964cd8322803298178e7d788e820..9fe7db73027a43b01c4d12927f1f0e61444658e5 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3050,6 +3050,69 @@ static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
> return 0;
> }
>
> +static bool drm_dp_valid_link_rate(u8 link_rate)
> +{
> + switch (link_rate) {
> + case 0x06:
> + case 0x0a:
> + case 0x14:
> + case 0x1e:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +/**
> + * drm_dp_read_lttpr_caps - read the LTTPR capabilities
> + * @aux: DisplayPort AUX channel
> + * @caps: buffer to return the capability info in
> + *
> + * Read capabilities common to all LTTPRs.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + /*
> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
> + * corrupted values when reading from the 0xF0000- range with a block
> + * size bigger than 1.
> + * For DP as per the spec DP2.1 section 3.6.8.6.1, section 2.12.1, section
> + * 2.12.3 (Link Policy) the LTTPR caps is to be read first followed by the
> + * DPRX capability.
> + * So ideally we dont have DPCD_REV yet to check for the revision, instead
> + * check for the correctness of the read value and in found corrupted read
> + * block by block.
> + */
> + int block_size;
> + int offset;
> + int ret;
> + int address = DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV;
> + int buf_size = DP_LTTPR_COMMON_CAP_SIZE;
> +
> + ret = drm_dp_dpcd_read_data(aux, address, &caps, buf_size);
> + if (ret < 0)
> + return ret;
> +
> + if (caps[0] == 0x14) {
> + if (!drm_dp_valid_link_rate(caps[1])) {
So you first read the whole thing once, and then in some cases read the
whole thing again one byte at a time?
Everything about this smells like a quirk for a specific display, not
something you do normally. We shouldn't have to have two ways to read
the lttpr caps in the normal case.
> + block_size = 1;
What's the point with the variable?
> + for (offset = 0; offset < buf_size; offset += block_size) {
> + ret = drm_dp_dpcd_read_data(aux,
> + address + offset,
> + &caps[offset],
> + block_size);
> + if (ret < 0)
> + return ret;
> + }
> + }
> + }
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_read_lttpr_caps);
> +
> /**
> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> * @aux: DisplayPort AUX channel
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 1d0acd58f48676f60ff6a07cc6812f72cbb452e8..def145e67011c325b790c807f934b288304260c1 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -755,6 +755,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
> const struct drm_dp_desc *desc);
> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>
> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without DPRX caps
2026-03-05 9:18 ` Jani Nikula
@ 2026-03-06 4:08 ` Murthy, Arun R
0 siblings, 0 replies; 18+ messages in thread
From: Murthy, Arun R @ 2026-03-06 4:08 UTC (permalink / raw)
To: Jani Nikula, Imre Deak, Ville Syrjälä
Cc: dri-devel, intel-gfx, intel-xe
On 05-03-2026 14:48, Jani Nikula wrote:
> On Thu, 05 Mar 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> We at present have drm_dp_Read_lttpr_common_caps to read the LTTPR caps,
>> but this function required DPRX caps to be passed. As per the DP2.1 spec
>> section 3.6.8.6.1, section 2.12.1, section 2.12.3 (Link Policy) the
>> LTTPR caps is to be read first followed by the DPRX capability.
>> Hence adding another function to read the LTTPR caps without the need
>> for DPRX caps.
> If the spec says something, why are we keeping the function that does it
> the other way?
Sure will remove the other one!
>
>> In order to handle the issue
>> https://gitlab.freedesktop.org/drm/intel/-/issues/4531
>> of reading corrupted values for LTTPR caps on few pannels with DP Rev 1.2
>> the workaround of reducing the block size to 1 and reading one block at a
>> time is done by checking for a valid link rate.
>>
>> Fixes: 657586e474bd ("drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities")
> You're not calling the code being added here. This can't fix anything on
> its own. This is not how the Fixes: tag works.
Got it, will remove the Fixes tag and just provide ref to this patch for
getting to know the issue.
>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> drivers/gpu/drm/display/drm_dp_helper.c | 63 +++++++++++++++++++++++++++++++++
>> include/drm/display/drm_dp_helper.h | 2 ++
>> 2 files changed, 65 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index a697cc227e28964cd8322803298178e7d788e820..9fe7db73027a43b01c4d12927f1f0e61444658e5 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -3050,6 +3050,69 @@ static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
>> return 0;
>> }
>>
>> +static bool drm_dp_valid_link_rate(u8 link_rate)
>> +{
>> + switch (link_rate) {
>> + case 0x06:
>> + case 0x0a:
>> + case 0x14:
>> + case 0x1e:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +/**
>> + * drm_dp_read_lttpr_caps - read the LTTPR capabilities
>> + * @aux: DisplayPort AUX channel
>> + * @caps: buffer to return the capability info in
>> + *
>> + * Read capabilities common to all LTTPRs.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
>> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
>> +{
>> + /*
>> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
>> + * corrupted values when reading from the 0xF0000- range with a block
>> + * size bigger than 1.
>> + * For DP as per the spec DP2.1 section 3.6.8.6.1, section 2.12.1, section
>> + * 2.12.3 (Link Policy) the LTTPR caps is to be read first followed by the
>> + * DPRX capability.
>> + * So ideally we dont have DPCD_REV yet to check for the revision, instead
>> + * check for the correctness of the read value and in found corrupted read
>> + * block by block.
>> + */
>> + int block_size;
>> + int offset;
>> + int ret;
>> + int address = DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV;
>> + int buf_size = DP_LTTPR_COMMON_CAP_SIZE;
>> +
>> + ret = drm_dp_dpcd_read_data(aux, address, &caps, buf_size);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (caps[0] == 0x14) {
>> + if (!drm_dp_valid_link_rate(caps[1])) {
> So you first read the whole thing once, and then in some cases read the
> whole thing again one byte at a time?
Yes, this was one option that I could think and the other option
mentioned in the cover letter, i.e read the lttpr caps, and then read
the dprx caps, now check if DPCD rev > 1.4 then re-read the lttpr 1
block at a time.
Another open would be do we need to address this issue and add a
workaround in the driver as the DP2.1 Spec says that LTTPR is supported
only from DPCD rev 1.4 onwards and in this case the workaround that we
are trying to add is for a DPCD rev 1.2 panel with LTTPR.
>
> Everything about this smells like a quirk for a specific display, not
> something you do normally. We shouldn't have to have two ways to read
> the lttpr caps in the normal case.
Agree adding this as a quirk makes the code straight as per the spec and
cleaner.
>> + block_size = 1;
> What's the point with the variable?
will replace with a magic value.
Thanks and Regards,
Arun R Murthy
-------------------
>
>> + for (offset = 0; offset < buf_size; offset += block_size) {
>> + ret = drm_dp_dpcd_read_data(aux,
>> + address + offset,
>> + &caps[offset],
>> + block_size);
>> + if (ret < 0)
>> + return ret;
>> + }
>> + }
>> + }
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_read_lttpr_caps);
>> +
>> /**
>> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
>> * @aux: DisplayPort AUX channel
>> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
>> index 1d0acd58f48676f60ff6a07cc6812f72cbb452e8..def145e67011c325b790c807f934b288304260c1 100644
>> --- a/include/drm/display/drm_dp_helper.h
>> +++ b/include/drm/display/drm_dp_helper.h
>> @@ -755,6 +755,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
>> const struct drm_dp_desc *desc);
>> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>>
>> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
>> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
>> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
>> const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without DPRX caps
2026-03-05 8:18 ` [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without " Arun R Murthy
2026-03-05 9:18 ` Jani Nikula
@ 2026-03-05 16:29 ` Imre Deak
2026-03-06 4:10 ` Murthy, Arun R
1 sibling, 1 reply; 18+ messages in thread
From: Imre Deak @ 2026-03-05 16:29 UTC (permalink / raw)
To: Arun R Murthy
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On Thu, Mar 05, 2026 at 01:48:11PM +0530, Arun R Murthy wrote:
> We at present have drm_dp_Read_lttpr_common_caps to read the LTTPR caps,
> but this function required DPRX caps to be passed. As per the DP2.1 spec
> section 3.6.8.6.1, section 2.12.1, section 2.12.3 (Link Policy) the
> LTTPR caps is to be read first followed by the DPRX capability.
> Hence adding another function to read the LTTPR caps without the need
> for DPRX caps.
>
> In order to handle the issue
> https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> of reading corrupted values for LTTPR caps on few pannels with DP Rev 1.2
> the workaround of reducing the block size to 1 and reading one block at a
> time is done by checking for a valid link rate.
>
> Fixes: 657586e474bd ("drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities")
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 63 +++++++++++++++++++++++++++++++++
> include/drm/display/drm_dp_helper.h | 2 ++
> 2 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index a697cc227e28964cd8322803298178e7d788e820..9fe7db73027a43b01c4d12927f1f0e61444658e5 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3050,6 +3050,69 @@ static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
> return 0;
> }
>
> +static bool drm_dp_valid_link_rate(u8 link_rate)
> +{
> + switch (link_rate) {
> + case 0x06:
> + case 0x0a:
> + case 0x14:
> + case 0x1e:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +/**
> + * drm_dp_read_lttpr_caps - read the LTTPR capabilities
> + * @aux: DisplayPort AUX channel
> + * @caps: buffer to return the capability info in
> + *
> + * Read capabilities common to all LTTPRs.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + /*
> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
> + * corrupted values when reading from the 0xF0000- range with a block
> + * size bigger than 1.
> + * For DP as per the spec DP2.1 section 3.6.8.6.1, section 2.12.1, section
> + * 2.12.3 (Link Policy) the LTTPR caps is to be read first followed by the
> + * DPRX capability.
> + * So ideally we dont have DPCD_REV yet to check for the revision, instead
> + * check for the correctness of the read value and in found corrupted read
> + * block by block.
> + */
> + int block_size;
> + int offset;
> + int ret;
> + int address = DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV;
> + int buf_size = DP_LTTPR_COMMON_CAP_SIZE;
> +
> + ret = drm_dp_dpcd_read_data(aux, address, &caps, buf_size);
> + if (ret < 0)
> + return ret;
> +
> + if (caps[0] == 0x14) {
> + if (!drm_dp_valid_link_rate(caps[1])) {
I don't think the code can depend on what will be in caps[1] (i.e.
DP_MAX_LINK_RATE_PHY_REPEATER / 0xF0001) after the monitor returned a
corrupted value when reading this register. That is the code cannot
depend on this register value being a valid link rate encoding or
some other value.
> + block_size = 1;
> + for (offset = 0; offset < buf_size; offset += block_size) {
> + ret = drm_dp_dpcd_read_data(aux,
> + address + offset,
> + &caps[offset],
> + block_size);
> + if (ret < 0)
> + return ret;
> + }
> + }
> + }
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_read_lttpr_caps);
> +
> /**
> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> * @aux: DisplayPort AUX channel
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 1d0acd58f48676f60ff6a07cc6812f72cbb452e8..def145e67011c325b790c807f934b288304260c1 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -755,6 +755,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
> const struct drm_dp_desc *desc);
> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>
> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without DPRX caps
2026-03-05 16:29 ` Imre Deak
@ 2026-03-06 4:10 ` Murthy, Arun R
0 siblings, 0 replies; 18+ messages in thread
From: Murthy, Arun R @ 2026-03-06 4:10 UTC (permalink / raw)
To: imre.deak
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On 05-03-2026 21:59, Imre Deak wrote:
> On Thu, Mar 05, 2026 at 01:48:11PM +0530, Arun R Murthy wrote:
>> We at present have drm_dp_Read_lttpr_common_caps to read the LTTPR caps,
>> but this function required DPRX caps to be passed. As per the DP2.1 spec
>> section 3.6.8.6.1, section 2.12.1, section 2.12.3 (Link Policy) the
>> LTTPR caps is to be read first followed by the DPRX capability.
>> Hence adding another function to read the LTTPR caps without the need
>> for DPRX caps.
>>
>> In order to handle the issue
>> https://gitlab.freedesktop.org/drm/intel/-/issues/4531
>> of reading corrupted values for LTTPR caps on few pannels with DP Rev 1.2
>> the workaround of reducing the block size to 1 and reading one block at a
>> time is done by checking for a valid link rate.
>>
>> Fixes: 657586e474bd ("drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities")
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> drivers/gpu/drm/display/drm_dp_helper.c | 63 +++++++++++++++++++++++++++++++++
>> include/drm/display/drm_dp_helper.h | 2 ++
>> 2 files changed, 65 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index a697cc227e28964cd8322803298178e7d788e820..9fe7db73027a43b01c4d12927f1f0e61444658e5 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -3050,6 +3050,69 @@ static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
>> return 0;
>> }
>>
>> +static bool drm_dp_valid_link_rate(u8 link_rate)
>> +{
>> + switch (link_rate) {
>> + case 0x06:
>> + case 0x0a:
>> + case 0x14:
>> + case 0x1e:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +/**
>> + * drm_dp_read_lttpr_caps - read the LTTPR capabilities
>> + * @aux: DisplayPort AUX channel
>> + * @caps: buffer to return the capability info in
>> + *
>> + * Read capabilities common to all LTTPRs.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
>> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
>> +{
>> + /*
>> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
>> + * corrupted values when reading from the 0xF0000- range with a block
>> + * size bigger than 1.
>> + * For DP as per the spec DP2.1 section 3.6.8.6.1, section 2.12.1, section
>> + * 2.12.3 (Link Policy) the LTTPR caps is to be read first followed by the
>> + * DPRX capability.
>> + * So ideally we dont have DPCD_REV yet to check for the revision, instead
>> + * check for the correctness of the read value and in found corrupted read
>> + * block by block.
>> + */
>> + int block_size;
>> + int offset;
>> + int ret;
>> + int address = DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV;
>> + int buf_size = DP_LTTPR_COMMON_CAP_SIZE;
>> +
>> + ret = drm_dp_dpcd_read_data(aux, address, &caps, buf_size);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (caps[0] == 0x14) {
>> + if (!drm_dp_valid_link_rate(caps[1])) {
> I don't think the code can depend on what will be in caps[1] (i.e.
> DP_MAX_LINK_RATE_PHY_REPEATER / 0xF0001) after the monitor returned a
> corrupted value when reading this register. That is the code cannot
> depend on this register value being a valid link rate encoding or
> some other value.
I have mentioned another option as well in the cover letter, i.e read
the lttpr caps and then the dprx caps. Now check the DPCD rev and if <
1.4 re-read the lttpr caps one block at a time.
Thanks and Regards,
Arun R Murthy
------------------
>> + block_size = 1;
>> + for (offset = 0; offset < buf_size; offset += block_size) {
>> + ret = drm_dp_dpcd_read_data(aux,
>> + address + offset,
>> + &caps[offset],
>> + block_size);
>> + if (ret < 0)
>> + return ret;
>> + }
>> + }
>> + }
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_read_lttpr_caps);
>> +
>> /**
>> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
>> * @aux: DisplayPort AUX channel
>> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
>> index 1d0acd58f48676f60ff6a07cc6812f72cbb452e8..def145e67011c325b790c807f934b288304260c1 100644
>> --- a/include/drm/display/drm_dp_helper.h
>> +++ b/include/drm/display/drm_dp_helper.h
>> @@ -755,6 +755,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
>> const struct drm_dp_desc *desc);
>> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>>
>> +int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
>> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
>> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
>> const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
>>
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RFC 2/4] drm/i915/dp: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
2026-03-05 8:18 ` [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without " Arun R Murthy
@ 2026-03-05 8:18 ` Arun R Murthy
2026-03-05 8:18 ` [PATCH RFC 3/4] drm/i915/dp: On HPD read " Arun R Murthy
` (6 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Arun R Murthy @ 2026-03-05 8:18 UTC (permalink / raw)
To: Imre Deak, Ville Syrjälä, Jani Nikula
Cc: dri-devel, intel-gfx, intel-xe, Arun R Murthy
As per the DP spec DP2.1 section 3.6.8.6.1, section 2.12.1,
section 2.12.3 (Link Policy) the LTTPR caps is to be read first followed
by the DPRX capability.
Read the LTTPR capabilities followed by the DPRX capabilities and then
the ULP capabilities.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 35 ++++++++++------------
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b900eb3c480502d89736fefa111eba4..68ab938f18f3b6f3c889f408cd1901041834fe82 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -93,13 +93,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
phy_caps);
}
-static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
- const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
{
int ret;
- ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
- intel_dp->lttpr_common_caps);
+ ret = drm_dp_read_lttpr_caps(&intel_dp->aux, intel_dp->lttpr_common_caps);
if (ret < 0)
goto reset_caps;
@@ -145,12 +143,12 @@ bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
* Return the number of detected LTTPRs in non-transparent mode or 0 if the
* LTTPRs are in transparent mode or the detection failed.
*/
-static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
{
int lttpr_count;
int ret;
- if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
+ if (!intel_dp_read_lttpr_common_caps(intel_dp))
return 0;
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
@@ -195,19 +193,16 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_
return 0;
}
-static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, int lttpr_count)
{
- int lttpr_count;
int i;
- lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);
-
for (i = 0; i < lttpr_count; i++) {
- intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
+ intel_dp_read_lttpr_phy_caps(intel_dp, intel_dp->dpcd, DP_PHY_LTTPR(i));
drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));
}
- return lttpr_count;
+ return 0;
}
int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
@@ -261,23 +256,23 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
*/
if (!intel_dp_is_edp(intel_dp) &&
(DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {
- u8 dpcd[DP_RECEIVER_CAP_SIZE];
- int err = intel_dp_read_dprx_caps(intel_dp, dpcd);
-
- if (err != 0)
- return err;
-
- lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
+ /*
+ * Spec DP2.1 section 3.6.8.6.1, section 2.12.1, section 2.12.3
+ * (Link Policy) the LTTPR caps is to be read first followed by
+ * the DPRX capability
+ */
+ lttpr_count = intel_dp_init_lttpr(intel_dp);
}
/*
* The DPTX shall read the DPRX caps after LTTPR detection, so re-read
* it here.
*/
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
+ if (intel_dp_read_dprx_caps(intel_dp, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);
return -EIO;
}
+ intel_dp_init_lttpr_phys(intel_dp, lttpr_count);
return lttpr_count;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RFC 3/4] drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
2026-03-05 8:18 ` [PATCH RFC 1/4] drm/display/dp: Read LTTPR caps without " Arun R Murthy
2026-03-05 8:18 ` [PATCH RFC 2/4] drm/i915/dp: Read LTTPR caps followed by " Arun R Murthy
@ 2026-03-05 8:18 ` Arun R Murthy
2026-03-05 8:18 ` [PATCH RFC 4/4] drm/i915/dp: DPRX/LTTPR caps for DP should be read once Arun R Murthy
` (5 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Arun R Murthy @ 2026-03-05 8:18 UTC (permalink / raw)
To: Imre Deak, Ville Syrjälä, Jani Nikula
Cc: dri-devel, intel-gfx, intel-xe, Arun R Murthy
On HPD for DP read LTTPR caps and then read the DPRX caps. Dont directly
read the DPRX caps at first as per Spec DP2.1 Sec 3.6.8.1
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +--
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_link_training.h | 1 -
drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +--
4 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0c03b6fb6fd82b0b010fe5f7591ce5e0d8d2d04c..956099e90b32aae5ae21d472ab5dc9dd7d110f60 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6811,7 +6811,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
{
struct intel_display *display = to_intel_display(dig_port);
struct intel_dp *intel_dp = &dig_port->dp;
- u8 dpcd[DP_RECEIVER_CAP_SIZE];
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
(long_hpd ||
@@ -6847,7 +6846,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
if (long_hpd) {
intel_dp_dpcd_set_probe(intel_dp, true);
- intel_dp_read_dprx_caps(intel_dp, dpcd);
+ intel_dp_init_lttpr_and_dprx_caps(intel_dp);
intel_dp->reset_link_params = true;
intel_dp_invalidate_source_oui(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 68ab938f18f3b6f3c889f408cd1901041834fe82..76a5bfb507c34733db09cd7c2ba9895afcbf6b10 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -205,7 +205,7 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, int lttpr_count)
return 0;
}
-int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_display *display = to_intel_display(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db087b73d2ec479c6f31104e97243061..d5f35637b7f375bdc7bdd01c25137fb9f0de37dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -13,7 +13,6 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_dp;
-int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 1fd1ac8d556d84bd794b965ba6f513ee4550f060..6fe9ff757f264a1064ca3e77e4a2bb8c1228214a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -337,7 +337,6 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
struct intel_display *display = to_intel_display(intel_dp);
struct intel_connector *connector = intel_dp->attached_connector;
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 pipe_mask;
int err = 0;
@@ -360,7 +359,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
* capabilities were updated already during resume.
*/
if (!dpcd_updated) {
- err = intel_dp_read_dprx_caps(intel_dp, dpcd);
+ err = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
if (err) {
drm_dp_tunnel_set_io_error(intel_dp->tunnel);
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RFC 4/4] drm/i915/dp: DPRX/LTTPR caps for DP should be read once
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (2 preceding siblings ...)
2026-03-05 8:18 ` [PATCH RFC 3/4] drm/i915/dp: On HPD read " Arun R Murthy
@ 2026-03-05 8:18 ` Arun R Murthy
2026-03-05 16:11 ` [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Imre Deak
` (4 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Arun R Murthy @ 2026-03-05 8:18 UTC (permalink / raw)
To: Imre Deak, Ville Syrjälä, Jani Nikula
Cc: dri-devel, intel-gfx, intel-xe, Arun R Murthy
The DPRX/LTTPR caps for DP is read on detect and should be read only
once. This value is stored in intl_dp struct and will be retained until
hotplug.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 76a5bfb507c34733db09cd7c2ba9895afcbf6b10..b78fc69cf21dea630313a5c93ff4bd3670f32293 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -250,6 +250,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
struct intel_display *display = to_intel_display(intel_dp);
int lttpr_count = 0;
+ /* this function is meant to be called only once */
+ drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
+
/*
* Detecting LTTPRs must be avoided on platforms with an AUX timeout
* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (3 preceding siblings ...)
2026-03-05 8:18 ` [PATCH RFC 4/4] drm/i915/dp: DPRX/LTTPR caps for DP should be read once Arun R Murthy
@ 2026-03-05 16:11 ` Imre Deak
2026-03-06 4:29 ` Murthy, Arun R
2026-03-06 4:29 ` Murthy, Arun R
2026-03-06 3:42 ` ✗ CI.checkpatch: warning for " Patchwork
` (3 subsequent siblings)
8 siblings, 2 replies; 18+ messages in thread
From: Imre Deak @ 2026-03-05 16:11 UTC (permalink / raw)
To: Arun R Murthy
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On Thu, Mar 05, 2026 at 01:48:10PM +0530, Arun R Murthy wrote:
> As per the spec DP2.1 section 3.6.8.6.1, section 2.12.1,
> section 2.12.3 (Link Policy) the LTTPR caps is to be read first
> followed by the DPRX capability.
Not exactly. The Standard requires reading the DPRX capabilities after
the LTTPR caps are read. The driver does read the DPRX caps after
reading the LTTPR caps. The DP Standard does not mandate that the first
read after a sink is connected (i.e. after the HPD signal of the sink is
asserted) must be an LTTPR capability read and cannot be any other DPCD
register read. In fact this would be impossible to guarantee, a DPRX
capability read - or any DPCD register read for that matter - could
happen at any point and so it could happen right after the HPD signal
got asserted.
> Git log shows that initially drm dp helper exposed function to read
> lttpr caps. Driver reads the lttpr caps and then the dprx caps.
> For a particular issue
> https://gitlab.freedesktop.org/drm/intel/-/issues/3415
> as a workaround reading dprx caps was done first to know if the panel is
> < DP1.4 and then read 1 block at a time for lttpr caps.
>
> This can be handled in a better way and two such ways is what I see.
> 1. Read LTTPR caps followed by DPRX caps as per the spec. Then on
> reading dprx caps if revision < 1.4 then re-read the lttpr caps one
> block at a time.
>
> 2. Read LTTPR caps and if 8b/10b check for correctness of the link rate
> supported(lttpr caps 0xf0001), if some corrupted value is read then read
> one block at a time.
The driver does read the DPRX capabilities after reading the LTTPR
capabilities. This is what the standard mandates.
The workaround for issues/3415 depends on the DPCD_REV value, so this is
read separately before reading the LTTPR caps. I don't see a better way
to implement the workaround and such read is not prohibited by the DP
Standard either. So I don't see the point of the changes in this
patchset.
> I am open for either of the two or you have any other options as well I
> am open.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> Arun R Murthy (4):
> drm/display/dp: Read LTTPR caps without DPRX caps
> drm/i915/dp: Read LTTPR caps followed by DPRX caps
> drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
> drm/i915/dp: DPRX/LTTPR caps for DP should be read once
>
> drivers/gpu/drm/display/drm_dp_helper.c | 63 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> .../gpu/drm/i915/display/intel_dp_link_training.c | 40 +++++++-------
> .../gpu/drm/i915/display/intel_dp_link_training.h | 1 -
> drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +-
> include/drm/display/drm_dp_helper.h | 2 +
> 6 files changed, 86 insertions(+), 26 deletions(-)
> ---
> base-commit: cfc20c776480fda8c1b0517b187bb71ec0781cd4
> change-id: 20260305-dp_aux-1e27599e06c8
>
> Best regards,
> --
> Arun R Murthy <arun.r.murthy@intel.com>
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps
2026-03-05 16:11 ` [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Imre Deak
@ 2026-03-06 4:29 ` Murthy, Arun R
2026-03-06 9:46 ` Imre Deak
2026-03-06 4:29 ` Murthy, Arun R
1 sibling, 1 reply; 18+ messages in thread
From: Murthy, Arun R @ 2026-03-06 4:29 UTC (permalink / raw)
To: imre.deak
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On 05-03-2026 21:41, Imre Deak wrote:
> On Thu, Mar 05, 2026 at 01:48:10PM +0530, Arun R Murthy wrote:
>> As per the spec DP2.1 section 3.6.8.6.1, section 2.12.1,
>> section 2.12.3 (Link Policy) the LTTPR caps is to be read first
>> followed by the DPRX capability.
> Not exactly. The Standard requires reading the DPRX capabilities after
> the LTTPR caps are read.
I also mean the same, sorry if my wordings were complex.
> The driver does read the DPRX caps after
> reading the LTTPR caps.
In intel_dp_link_training.c function intel_dp_init_lttpr_and_dprx_caps()
int err = intel_dp_read_dprx_caps()
if (err != 0)
return err;
lttpr_count = intel_dp_init_lttpr()
Here we are reading dprx caps and then passing this dprx caps to the the
func intel_dp_init_lttpr(). I think this will be a deviation of the spec.
> The DP Standard does not mandate that the first
> read after a sink is connected (i.e. after the HPD signal of the sink is
> asserted) must be an LTTPR capability read and cannot be any other DPCD
> register read. In fact this would be impossible to guarantee, a DPRX
> capability read - or any DPCD register read for that matter - could
> happen at any point and so it could happen right after the HPD signal
> got asserted.
Spec DP2.1 Section 3.6.8.6.1 LTTPR Recognition
After HPD is propagated from the DPRX to the DPTX, a DP Source device
with a DPTX shall
read specific registers within the DPCD LTTPR Capability and ID Field
(DPCD F0000h through
F0009h; see Section 3.6.5)
After LTTPR recognition, a DP Source device with a DPTX shall read the
DP Sink device with
a DPRX’s capability by reading the DisplayID or legacy EDID and the
DPRX’s Receiver
Capability field (DPCD 00000h through 000FFh; see Table 2-232).
>> Git log shows that initially drm dp helper exposed function to read
>> lttpr caps. Driver reads the lttpr caps and then the dprx caps.
>> For a particular issue
>> https://gitlab.freedesktop.org/drm/intel/-/issues/3415
>> as a workaround reading dprx caps was done first to know if the panel is
>> < DP1.4 and then read 1 block at a time for lttpr caps.
>>
>> This can be handled in a better way and two such ways is what I see.
>> 1. Read LTTPR caps followed by DPRX caps as per the spec. Then on
>> reading dprx caps if revision < 1.4 then re-read the lttpr caps one
>> block at a time.
>>
>> 2. Read LTTPR caps and if 8b/10b check for correctness of the link rate
>> supported(lttpr caps 0xf0001), if some corrupted value is read then read
>> one block at a time.
> The driver does read the DPRX capabilities after reading the LTTPR
> capabilities. This is what the standard mandates.
Yes but before reading the LTTPR capabilities also DPRX capabilities is
read. Have added ref to the code snipped above.
Please let me know if my understanding is wrong.
>
> The workaround for issues/3415 depends on the DPCD_REV value, so this is
> read separately before reading the LTTPR caps. I don't see a better way
> to implement the workaround and such read is not prohibited by the DP
> Standard either. So I don't see the point of the changes in this
> patchset.
As Jani pointed this can be added as a quirk for that particular panel
instead of mandating this kind of reading dprx caps first and then
reading the lttpr caps for all the monitors.
Thanks and Regards,
Arun R Murthy
-------------------
>
>> I am open for either of the two or you have any other options as well I
>> am open.
>>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> Arun R Murthy (4):
>> drm/display/dp: Read LTTPR caps without DPRX caps
>> drm/i915/dp: Read LTTPR caps followed by DPRX caps
>> drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
>> drm/i915/dp: DPRX/LTTPR caps for DP should be read once
>>
>> drivers/gpu/drm/display/drm_dp_helper.c | 63 ++++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
>> .../gpu/drm/i915/display/intel_dp_link_training.c | 40 +++++++-------
>> .../gpu/drm/i915/display/intel_dp_link_training.h | 1 -
>> drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +-
>> include/drm/display/drm_dp_helper.h | 2 +
>> 6 files changed, 86 insertions(+), 26 deletions(-)
>> ---
>> base-commit: cfc20c776480fda8c1b0517b187bb71ec0781cd4
>> change-id: 20260305-dp_aux-1e27599e06c8
>>
>> Best regards,
>> --
>> Arun R Murthy <arun.r.murthy@intel.com>
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps
2026-03-06 4:29 ` Murthy, Arun R
@ 2026-03-06 9:46 ` Imre Deak
2026-03-10 8:58 ` Murthy, Arun R
0 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2026-03-06 9:46 UTC (permalink / raw)
To: Murthy, Arun R
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On Fri, Mar 06, 2026 at 09:59:10AM +0530, Murthy, Arun R wrote:
>
> On 05-03-2026 21:41, Imre Deak wrote:
> > On Thu, Mar 05, 2026 at 01:48:10PM +0530, Arun R Murthy wrote:
> > > As per the spec DP2.1 section 3.6.8.6.1, section 2.12.1,
> > > section 2.12.3 (Link Policy) the LTTPR caps is to be read first
> > > followed by the DPRX capability.
> > Not exactly. The Standard requires reading the DPRX capabilities after
> > the LTTPR caps are read.
>
> I also mean the same, sorry if my wordings were complex.
>
> > The driver does read the DPRX caps after
> > reading the LTTPR caps.
>
> In intel_dp_link_training.c function intel_dp_init_lttpr_and_dprx_caps()
>
> int err = intel_dp_read_dprx_caps()
> if (err != 0)
> return err;
> lttpr_count = intel_dp_init_lttpr()
>
> Here we are reading dprx caps and then passing this dprx caps to the the
> func intel_dp_init_lttpr(). I think this will be a deviation of the spec.
No, it's not a deviation of the spec, because the spec does not forbid
reading the DPCD_REV or other DPCD registers before reading the LTTPR
capability registers and it cannot really forbid this as I explained.
What the spec requires is reading the DPRX capabilities after the LTTPR
capabilities were read out, which the driver does: after the above lines
there is also:
/*
* The DPTX shall read the DPRX caps after LTTPR detection, so re-read
* it here.
*/
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) ...
> > The DP Standard does not mandate that the first read after a sink is
> > connected (i.e. after the HPD signal of the sink is asserted) must
> > be an LTTPR capability read and cannot be any other DPCD register
> > read. In fact this would be impossible to guarantee, a DPRX
> > capability read - or any DPCD register read for that matter - could
> > happen at any point and so it could happen right after the HPD
> > signal got asserted.
>
> Spec DP2.1 Section 3.6.8.6.1 LTTPR Recognition After HPD is propagated
> from the DPRX to the DPTX, a DP Source device with a DPTX shall read
> specific registers within the DPCD LTTPR Capability and ID Field (DPCD
> F0000h through F0009h; see Section 3.6.5) After LTTPR recognition, a
> DP Source device with a DPTX shall read the DP Sink device with a
> DPRX’s capability by reading the DisplayID or legacy EDID and the
> DPRX’s Receiver Capability field (DPCD 00000h through 000FFh; see
> Table 2-232).
The above does not prohibit reading non-LTTPR DPCD registers before
reading F0000h - F0009h, and it cannot forbid this as explained above.
> > > Git log shows that initially drm dp helper exposed function to read
> > > lttpr caps. Driver reads the lttpr caps and then the dprx caps.
> > > For a particular issue
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3415
> > > as a workaround reading dprx caps was done first to know if the panel is
> > > < DP1.4 and then read 1 block at a time for lttpr caps.
> > >
> > > This can be handled in a better way and two such ways is what I see.
> > > 1. Read LTTPR caps followed by DPRX caps as per the spec. Then on
> > > reading dprx caps if revision < 1.4 then re-read the lttpr caps one
> > > block at a time.
> > >
> > > 2. Read LTTPR caps and if 8b/10b check for correctness of the link rate
> > > supported(lttpr caps 0xf0001), if some corrupted value is read then read
> > > one block at a time.
>
> > The driver does read the DPRX capabilities after reading the LTTPR
> > capabilities. This is what the standard mandates.
>
> Yes but before reading the LTTPR capabilities also DPRX capabilities is
> read. Have added ref to the code snipped above.
This is not forbidden by the specification.
> Please let me know if my understanding is wrong.
>
> > The workaround for issues/3415 depends on the DPCD_REV value, so this is
> > read separately before reading the LTTPR caps. I don't see a better way
> > to implement the workaround and such read is not prohibited by the DP
> > Standard either. So I don't see the point of the changes in this
> > patchset.
>
> As Jani pointed this can be added as a quirk for that particular panel
> instead of mandating this kind of reading dprx caps first and then reading
> the lttpr caps for all the monitors.
There is already a quirk in the driver - to read out the LTTPR
capabilities 1 byte at a time - and the quirk is applied based on the
DPCD_REV register value of the monitor.
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
> >
> > > I am open for either of the two or you have any other options as well I
> > > am open.
> > >
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > > Arun R Murthy (4):
> > > drm/display/dp: Read LTTPR caps without DPRX caps
> > > drm/i915/dp: Read LTTPR caps followed by DPRX caps
> > > drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
> > > drm/i915/dp: DPRX/LTTPR caps for DP should be read once
> > >
> > > drivers/gpu/drm/display/drm_dp_helper.c | 63 ++++++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> > > .../gpu/drm/i915/display/intel_dp_link_training.c | 40 +++++++-------
> > > .../gpu/drm/i915/display/intel_dp_link_training.h | 1 -
> > > drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +-
> > > include/drm/display/drm_dp_helper.h | 2 +
> > > 6 files changed, 86 insertions(+), 26 deletions(-)
> > > ---
> > > base-commit: cfc20c776480fda8c1b0517b187bb71ec0781cd4
> > > change-id: 20260305-dp_aux-1e27599e06c8
> > >
> > > Best regards,
> > > --
> > > Arun R Murthy <arun.r.murthy@intel.com>
> > >
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps
2026-03-06 9:46 ` Imre Deak
@ 2026-03-10 8:58 ` Murthy, Arun R
0 siblings, 0 replies; 18+ messages in thread
From: Murthy, Arun R @ 2026-03-10 8:58 UTC (permalink / raw)
To: imre.deak
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
I understand that with race conditions from user get_connector it still
cannot guarantee that lttpr caps are read first, dropping this patch for
now!
Thanks and Regards,
Arun R Murthy
-------------------
On 06-03-2026 15:16, Imre Deak wrote:
> On Fri, Mar 06, 2026 at 09:59:10AM +0530, Murthy, Arun R wrote:
>> On 05-03-2026 21:41, Imre Deak wrote:
>>> On Thu, Mar 05, 2026 at 01:48:10PM +0530, Arun R Murthy wrote:
>>>> As per the spec DP2.1 section 3.6.8.6.1, section 2.12.1,
>>>> section 2.12.3 (Link Policy) the LTTPR caps is to be read first
>>>> followed by the DPRX capability.
>>> Not exactly. The Standard requires reading the DPRX capabilities after
>>> the LTTPR caps are read.
>> I also mean the same, sorry if my wordings were complex.
>>
>>> The driver does read the DPRX caps after
>>> reading the LTTPR caps.
>> In intel_dp_link_training.c function intel_dp_init_lttpr_and_dprx_caps()
>>
>> int err = intel_dp_read_dprx_caps()
>> if (err != 0)
>> return err;
>> lttpr_count = intel_dp_init_lttpr()
>>
>> Here we are reading dprx caps and then passing this dprx caps to the the
>> func intel_dp_init_lttpr(). I think this will be a deviation of the spec.
> No, it's not a deviation of the spec, because the spec does not forbid
> reading the DPCD_REV or other DPCD registers before reading the LTTPR
> capability registers and it cannot really forbid this as I explained.
>
> What the spec requires is reading the DPRX capabilities after the LTTPR
> capabilities were read out, which the driver does: after the above lines
> there is also:
>
> /*
> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> * it here.
> */
> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) ...
>
>>> The DP Standard does not mandate that the first read after a sink is
>>> connected (i.e. after the HPD signal of the sink is asserted) must
>>> be an LTTPR capability read and cannot be any other DPCD register
>>> read. In fact this would be impossible to guarantee, a DPRX
>>> capability read - or any DPCD register read for that matter - could
>>> happen at any point and so it could happen right after the HPD
>>> signal got asserted.
>> Spec DP2.1 Section 3.6.8.6.1 LTTPR Recognition After HPD is propagated
>> from the DPRX to the DPTX, a DP Source device with a DPTX shall read
>> specific registers within the DPCD LTTPR Capability and ID Field (DPCD
>> F0000h through F0009h; see Section 3.6.5) After LTTPR recognition, a
>> DP Source device with a DPTX shall read the DP Sink device with a
>> DPRX’s capability by reading the DisplayID or legacy EDID and the
>> DPRX’s Receiver Capability field (DPCD 00000h through 000FFh; see
>> Table 2-232).
> The above does not prohibit reading non-LTTPR DPCD registers before
> reading F0000h - F0009h, and it cannot forbid this as explained above.
>
>>>> Git log shows that initially drm dp helper exposed function to read
>>>> lttpr caps. Driver reads the lttpr caps and then the dprx caps.
>>>> For a particular issue
>>>> https://gitlab.freedesktop.org/drm/intel/-/issues/3415
>>>> as a workaround reading dprx caps was done first to know if the panel is
>>>> < DP1.4 and then read 1 block at a time for lttpr caps.
>>>>
>>>> This can be handled in a better way and two such ways is what I see.
>>>> 1. Read LTTPR caps followed by DPRX caps as per the spec. Then on
>>>> reading dprx caps if revision < 1.4 then re-read the lttpr caps one
>>>> block at a time.
>>>>
>>>> 2. Read LTTPR caps and if 8b/10b check for correctness of the link rate
>>>> supported(lttpr caps 0xf0001), if some corrupted value is read then read
>>>> one block at a time.
>>> The driver does read the DPRX capabilities after reading the LTTPR
>>> capabilities. This is what the standard mandates.
>> Yes but before reading the LTTPR capabilities also DPRX capabilities is
>> read. Have added ref to the code snipped above.
> This is not forbidden by the specification.
>
>> Please let me know if my understanding is wrong.
>>
>>> The workaround for issues/3415 depends on the DPCD_REV value, so this is
>>> read separately before reading the LTTPR caps. I don't see a better way
>>> to implement the workaround and such read is not prohibited by the DP
>>> Standard either. So I don't see the point of the changes in this
>>> patchset.
>> As Jani pointed this can be added as a quirk for that particular panel
>> instead of mandating this kind of reading dprx caps first and then reading
>> the lttpr caps for all the monitors.
> There is already a quirk in the driver - to read out the LTTPR
> capabilities 1 byte at a time - and the quirk is applied based on the
> DPCD_REV register value of the monitor.
>
>> Thanks and Regards,
>> Arun R Murthy
>> -------------------
>>
>>>> I am open for either of the two or you have any other options as well I
>>>> am open.
>>>>
>>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>>> ---
>>>> Arun R Murthy (4):
>>>> drm/display/dp: Read LTTPR caps without DPRX caps
>>>> drm/i915/dp: Read LTTPR caps followed by DPRX caps
>>>> drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
>>>> drm/i915/dp: DPRX/LTTPR caps for DP should be read once
>>>>
>>>> drivers/gpu/drm/display/drm_dp_helper.c | 63 ++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
>>>> .../gpu/drm/i915/display/intel_dp_link_training.c | 40 +++++++-------
>>>> .../gpu/drm/i915/display/intel_dp_link_training.h | 1 -
>>>> drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +-
>>>> include/drm/display/drm_dp_helper.h | 2 +
>>>> 6 files changed, 86 insertions(+), 26 deletions(-)
>>>> ---
>>>> base-commit: cfc20c776480fda8c1b0517b187bb71ec0781cd4
>>>> change-id: 20260305-dp_aux-1e27599e06c8
>>>>
>>>> Best regards,
>>>> --
>>>> Arun R Murthy <arun.r.murthy@intel.com>
>>>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps
2026-03-05 16:11 ` [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Imre Deak
2026-03-06 4:29 ` Murthy, Arun R
@ 2026-03-06 4:29 ` Murthy, Arun R
1 sibling, 0 replies; 18+ messages in thread
From: Murthy, Arun R @ 2026-03-06 4:29 UTC (permalink / raw)
To: imre.deak
Cc: Ville Syrjälä, Jani Nikula, dri-devel, intel-gfx,
intel-xe
On 05-03-2026 21:41, Imre Deak wrote:
> On Thu, Mar 05, 2026 at 01:48:10PM +0530, Arun R Murthy wrote:
>> As per the spec DP2.1 section 3.6.8.6.1, section 2.12.1,
>> section 2.12.3 (Link Policy) the LTTPR caps is to be read first
>> followed by the DPRX capability.
> Not exactly. The Standard requires reading the DPRX capabilities after
> the LTTPR caps are read.
I also mean the same, sorry if my wordings were complex.
> The driver does read the DPRX caps after
> reading the LTTPR caps.
In intel_dp_link_training.c function intel_dp_init_lttpr_and_dprx_caps()
int err = intel_dp_read_dprx_caps()
if (err != 0)
return err;
lttpr_count = intel_dp_init_lttpr()
Here we are reading dprx caps and then passing this dprx caps to the the
func intel_dp_init_lttpr(). I think this will be a deviation of the spec.
> The DP Standard does not mandate that the first
> read after a sink is connected (i.e. after the HPD signal of the sink is
> asserted) must be an LTTPR capability read and cannot be any other DPCD
> register read. In fact this would be impossible to guarantee, a DPRX
> capability read - or any DPCD register read for that matter - could
> happen at any point and so it could happen right after the HPD signal
> got asserted.
Spec DP2.1 Section 3.6.8.6.1 LTTPR Recognition
After HPD is propagated from the DPRX to the DPTX, a DP Source device
with a DPTX shall
read specific registers within the DPCD LTTPR Capability and ID Field
(DPCD F0000h through
F0009h; see Section 3.6.5)
After LTTPR recognition, a DP Source device with a DPTX shall read the
DP Sink device with
a DPRX’s capability by reading the DisplayID or legacy EDID and the
DPRX’s Receiver
Capability field (DPCD 00000h through 000FFh; see Table 2-232).
>> Git log shows that initially drm dp helper exposed function to read
>> lttpr caps. Driver reads the lttpr caps and then the dprx caps.
>> For a particular issue
>> https://gitlab.freedesktop.org/drm/intel/-/issues/3415
>> as a workaround reading dprx caps was done first to know if the panel is
>> < DP1.4 and then read 1 block at a time for lttpr caps.
>>
>> This can be handled in a better way and two such ways is what I see.
>> 1. Read LTTPR caps followed by DPRX caps as per the spec. Then on
>> reading dprx caps if revision < 1.4 then re-read the lttpr caps one
>> block at a time.
>>
>> 2. Read LTTPR caps and if 8b/10b check for correctness of the link rate
>> supported(lttpr caps 0xf0001), if some corrupted value is read then read
>> one block at a time.
> The driver does read the DPRX capabilities after reading the LTTPR
> capabilities. This is what the standard mandates.
Yes but before reading the LTTPR capabilities also DPRX capabilities is
read. Have added ref to the code snipped above.
Please let me know if my understanding is wrong.
>
> The workaround for issues/3415 depends on the DPCD_REV value, so this is
> read separately before reading the LTTPR caps. I don't see a better way
> to implement the workaround and such read is not prohibited by the DP
> Standard either. So I don't see the point of the changes in this
> patchset.
As Jani commented this can be added as a quirk for that particular panel
instead of mandating this kind of reading dprx caps first and then
reading the lttpr caps for all the monitors.
Thanks and Regards,
Arun R Murthy
-------------------
>
>> I am open for either of the two or you have any other options as well I
>> am open.
>>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> Arun R Murthy (4):
>> drm/display/dp: Read LTTPR caps without DPRX caps
>> drm/i915/dp: Read LTTPR caps followed by DPRX caps
>> drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
>> drm/i915/dp: DPRX/LTTPR caps for DP should be read once
>>
>> drivers/gpu/drm/display/drm_dp_helper.c | 63 ++++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
>> .../gpu/drm/i915/display/intel_dp_link_training.c | 40 +++++++-------
>> .../gpu/drm/i915/display/intel_dp_link_training.h | 1 -
>> drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 3 +-
>> include/drm/display/drm_dp_helper.h | 2 +
>> 6 files changed, 86 insertions(+), 26 deletions(-)
>> ---
>> base-commit: cfc20c776480fda8c1b0517b187bb71ec0781cd4
>> change-id: 20260305-dp_aux-1e27599e06c8
>>
>> Best regards,
>> --
>> Arun R Murthy <arun.r.murthy@intel.com>
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ CI.checkpatch: warning for DP: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (4 preceding siblings ...)
2026-03-05 16:11 ` [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Imre Deak
@ 2026-03-06 3:42 ` Patchwork
2026-03-06 3:44 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-06 3:42 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: DP: Read LTTPR caps followed by DPRX caps
URL : https://patchwork.freedesktop.org/series/162641/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 63df2fffda77eeac4dc0d0485a91d44db77ac63e
Author: Arun R Murthy <arun.r.murthy@intel.com>
Date: Thu Mar 5 13:48:14 2026 +0530
drm/i915/dp: DPRX/LTTPR caps for DP should be read once
The DPRX/LTTPR caps for DP is read on detect and should be read only
once. This value is stored in intl_dp struct and will be retained until
hotplug.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
+ /mt/dim checkpatch 79792a2fc5d37b5446e543f1de05158ab0f551c9 drm-intel
432ac5d30d49 drm/display/dp: Read LTTPR caps without DPRX caps
-:105: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#105: FILE: include/drm/display/drm_dp_helper.h:759:
+int drm_dp_read_lttpr_caps(struct drm_dp_aux *aux,
+ u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
total: 0 errors, 0 warnings, 1 checks, 77 lines checked
d0de58ea46ad drm/i915/dp: Read LTTPR caps followed by DPRX caps
e95770d03946 drm/i915/dp: On HPD read LTTPR caps followed by DPRX caps
63df2fffda77 drm/i915/dp: DPRX/LTTPR caps for DP should be read once
^ permalink raw reply [flat|nested] 18+ messages in thread* ✓ CI.KUnit: success for DP: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (5 preceding siblings ...)
2026-03-06 3:42 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2026-03-06 3:44 ` Patchwork
2026-03-06 4:33 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-03-07 1:55 ` ✗ Xe.CI.FULL: " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-06 3:44 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: DP: Read LTTPR caps followed by DPRX caps
URL : https://patchwork.freedesktop.org/series/162641/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[03:43:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:43:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[03:43:46] Starting KUnit Kernel (1/1)...
[03:43:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:43:46] ================== guc_buf (11 subtests) ===================
[03:43:46] [PASSED] test_smallest
[03:43:46] [PASSED] test_largest
[03:43:46] [PASSED] test_granular
[03:43:46] [PASSED] test_unique
[03:43:46] [PASSED] test_overlap
[03:43:46] [PASSED] test_reusable
[03:43:46] [PASSED] test_too_big
[03:43:46] [PASSED] test_flush
[03:43:46] [PASSED] test_lookup
[03:43:46] [PASSED] test_data
[03:43:46] [PASSED] test_class
[03:43:46] ===================== [PASSED] guc_buf =====================
[03:43:46] =================== guc_dbm (7 subtests) ===================
[03:43:46] [PASSED] test_empty
[03:43:46] [PASSED] test_default
[03:43:46] ======================== test_size ========================
[03:43:46] [PASSED] 4
[03:43:46] [PASSED] 8
[03:43:46] [PASSED] 32
[03:43:46] [PASSED] 256
[03:43:46] ==================== [PASSED] test_size ====================
[03:43:46] ======================= test_reuse ========================
[03:43:46] [PASSED] 4
[03:43:46] [PASSED] 8
[03:43:46] [PASSED] 32
[03:43:46] [PASSED] 256
[03:43:46] =================== [PASSED] test_reuse ====================
[03:43:46] =================== test_range_overlap ====================
[03:43:46] [PASSED] 4
[03:43:46] [PASSED] 8
[03:43:46] [PASSED] 32
[03:43:46] [PASSED] 256
[03:43:46] =============== [PASSED] test_range_overlap ================
[03:43:46] =================== test_range_compact ====================
[03:43:46] [PASSED] 4
[03:43:46] [PASSED] 8
[03:43:46] [PASSED] 32
[03:43:46] [PASSED] 256
[03:43:46] =============== [PASSED] test_range_compact ================
[03:43:46] ==================== test_range_spare =====================
[03:43:46] [PASSED] 4
[03:43:46] [PASSED] 8
[03:43:46] [PASSED] 32
[03:43:46] [PASSED] 256
[03:43:46] ================ [PASSED] test_range_spare =================
[03:43:46] ===================== [PASSED] guc_dbm =====================
[03:43:46] =================== guc_idm (6 subtests) ===================
[03:43:46] [PASSED] bad_init
[03:43:46] [PASSED] no_init
[03:43:46] [PASSED] init_fini
[03:43:46] [PASSED] check_used
[03:43:46] [PASSED] check_quota
[03:43:46] [PASSED] check_all
[03:43:46] ===================== [PASSED] guc_idm =====================
[03:43:46] ================== no_relay (3 subtests) ===================
[03:43:46] [PASSED] xe_drops_guc2pf_if_not_ready
[03:43:46] [PASSED] xe_drops_guc2vf_if_not_ready
[03:43:46] [PASSED] xe_rejects_send_if_not_ready
[03:43:46] ==================== [PASSED] no_relay =====================
[03:43:46] ================== pf_relay (14 subtests) ==================
[03:43:46] [PASSED] pf_rejects_guc2pf_too_short
[03:43:46] [PASSED] pf_rejects_guc2pf_too_long
[03:43:46] [PASSED] pf_rejects_guc2pf_no_payload
[03:43:46] [PASSED] pf_fails_no_payload
[03:43:46] [PASSED] pf_fails_bad_origin
[03:43:46] [PASSED] pf_fails_bad_type
[03:43:46] [PASSED] pf_txn_reports_error
[03:43:46] [PASSED] pf_txn_sends_pf2guc
[03:43:46] [PASSED] pf_sends_pf2guc
[03:43:46] [SKIPPED] pf_loopback_nop
[03:43:46] [SKIPPED] pf_loopback_echo
[03:43:46] [SKIPPED] pf_loopback_fail
[03:43:46] [SKIPPED] pf_loopback_busy
[03:43:46] [SKIPPED] pf_loopback_retry
[03:43:46] ==================== [PASSED] pf_relay =====================
[03:43:46] ================== vf_relay (3 subtests) ===================
[03:43:46] [PASSED] vf_rejects_guc2vf_too_short
[03:43:46] [PASSED] vf_rejects_guc2vf_too_long
[03:43:46] [PASSED] vf_rejects_guc2vf_no_payload
[03:43:46] ==================== [PASSED] vf_relay =====================
[03:43:46] ================ pf_gt_config (9 subtests) =================
[03:43:46] [PASSED] fair_contexts_1vf
[03:43:46] [PASSED] fair_doorbells_1vf
[03:43:46] [PASSED] fair_ggtt_1vf
[03:43:46] ====================== fair_vram_1vf ======================
[03:43:46] [PASSED] 3.50 GiB
[03:43:46] [PASSED] 11.5 GiB
[03:43:46] [PASSED] 15.5 GiB
[03:43:46] [PASSED] 31.5 GiB
[03:43:46] [PASSED] 63.5 GiB
[03:43:46] [PASSED] 1.91 GiB
[03:43:46] ================== [PASSED] fair_vram_1vf ==================
[03:43:46] ================ fair_vram_1vf_admin_only =================
[03:43:46] [PASSED] 3.50 GiB
[03:43:46] [PASSED] 11.5 GiB
[03:43:46] [PASSED] 15.5 GiB
[03:43:46] [PASSED] 31.5 GiB
[03:43:46] [PASSED] 63.5 GiB
[03:43:46] [PASSED] 1.91 GiB
[03:43:46] ============ [PASSED] fair_vram_1vf_admin_only =============
[03:43:46] ====================== fair_contexts ======================
[03:43:46] [PASSED] 1 VF
[03:43:46] [PASSED] 2 VFs
[03:43:46] [PASSED] 3 VFs
[03:43:46] [PASSED] 4 VFs
[03:43:46] [PASSED] 5 VFs
[03:43:46] [PASSED] 6 VFs
[03:43:46] [PASSED] 7 VFs
[03:43:46] [PASSED] 8 VFs
[03:43:46] [PASSED] 9 VFs
[03:43:46] [PASSED] 10 VFs
[03:43:46] [PASSED] 11 VFs
[03:43:46] [PASSED] 12 VFs
[03:43:46] [PASSED] 13 VFs
[03:43:46] [PASSED] 14 VFs
[03:43:46] [PASSED] 15 VFs
[03:43:46] [PASSED] 16 VFs
[03:43:46] [PASSED] 17 VFs
[03:43:46] [PASSED] 18 VFs
[03:43:46] [PASSED] 19 VFs
[03:43:46] [PASSED] 20 VFs
[03:43:46] [PASSED] 21 VFs
[03:43:46] [PASSED] 22 VFs
[03:43:46] [PASSED] 23 VFs
[03:43:46] [PASSED] 24 VFs
[03:43:46] [PASSED] 25 VFs
[03:43:46] [PASSED] 26 VFs
[03:43:46] [PASSED] 27 VFs
[03:43:46] [PASSED] 28 VFs
[03:43:46] [PASSED] 29 VFs
[03:43:46] [PASSED] 30 VFs
[03:43:46] [PASSED] 31 VFs
[03:43:46] [PASSED] 32 VFs
[03:43:46] [PASSED] 33 VFs
[03:43:46] [PASSED] 34 VFs
[03:43:46] [PASSED] 35 VFs
[03:43:46] [PASSED] 36 VFs
[03:43:46] [PASSED] 37 VFs
[03:43:46] [PASSED] 38 VFs
[03:43:46] [PASSED] 39 VFs
[03:43:46] [PASSED] 40 VFs
[03:43:46] [PASSED] 41 VFs
[03:43:46] [PASSED] 42 VFs
[03:43:46] [PASSED] 43 VFs
[03:43:46] [PASSED] 44 VFs
[03:43:46] [PASSED] 45 VFs
[03:43:46] [PASSED] 46 VFs
[03:43:46] [PASSED] 47 VFs
[03:43:46] [PASSED] 48 VFs
[03:43:46] [PASSED] 49 VFs
[03:43:46] [PASSED] 50 VFs
[03:43:46] [PASSED] 51 VFs
[03:43:46] [PASSED] 52 VFs
[03:43:46] [PASSED] 53 VFs
[03:43:46] [PASSED] 54 VFs
[03:43:46] [PASSED] 55 VFs
[03:43:46] [PASSED] 56 VFs
[03:43:46] [PASSED] 57 VFs
[03:43:46] [PASSED] 58 VFs
[03:43:46] [PASSED] 59 VFs
[03:43:46] [PASSED] 60 VFs
[03:43:46] [PASSED] 61 VFs
[03:43:46] [PASSED] 62 VFs
[03:43:46] [PASSED] 63 VFs
[03:43:46] ================== [PASSED] fair_contexts ==================
[03:43:46] ===================== fair_doorbells ======================
[03:43:46] [PASSED] 1 VF
[03:43:46] [PASSED] 2 VFs
[03:43:46] [PASSED] 3 VFs
[03:43:46] [PASSED] 4 VFs
[03:43:46] [PASSED] 5 VFs
[03:43:46] [PASSED] 6 VFs
[03:43:46] [PASSED] 7 VFs
[03:43:46] [PASSED] 8 VFs
[03:43:46] [PASSED] 9 VFs
[03:43:46] [PASSED] 10 VFs
[03:43:46] [PASSED] 11 VFs
[03:43:46] [PASSED] 12 VFs
[03:43:46] [PASSED] 13 VFs
[03:43:46] [PASSED] 14 VFs
[03:43:46] [PASSED] 15 VFs
[03:43:46] [PASSED] 16 VFs
[03:43:46] [PASSED] 17 VFs
[03:43:46] [PASSED] 18 VFs
[03:43:46] [PASSED] 19 VFs
[03:43:46] [PASSED] 20 VFs
[03:43:46] [PASSED] 21 VFs
[03:43:46] [PASSED] 22 VFs
[03:43:46] [PASSED] 23 VFs
[03:43:46] [PASSED] 24 VFs
[03:43:46] [PASSED] 25 VFs
[03:43:46] [PASSED] 26 VFs
[03:43:46] [PASSED] 27 VFs
[03:43:46] [PASSED] 28 VFs
[03:43:46] [PASSED] 29 VFs
[03:43:46] [PASSED] 30 VFs
[03:43:46] [PASSED] 31 VFs
[03:43:46] [PASSED] 32 VFs
[03:43:46] [PASSED] 33 VFs
[03:43:46] [PASSED] 34 VFs
[03:43:46] [PASSED] 35 VFs
[03:43:46] [PASSED] 36 VFs
[03:43:46] [PASSED] 37 VFs
[03:43:46] [PASSED] 38 VFs
[03:43:46] [PASSED] 39 VFs
[03:43:46] [PASSED] 40 VFs
[03:43:46] [PASSED] 41 VFs
[03:43:46] [PASSED] 42 VFs
[03:43:46] [PASSED] 43 VFs
[03:43:46] [PASSED] 44 VFs
[03:43:46] [PASSED] 45 VFs
[03:43:46] [PASSED] 46 VFs
[03:43:46] [PASSED] 47 VFs
[03:43:46] [PASSED] 48 VFs
[03:43:46] [PASSED] 49 VFs
[03:43:46] [PASSED] 50 VFs
[03:43:46] [PASSED] 51 VFs
[03:43:46] [PASSED] 52 VFs
[03:43:46] [PASSED] 53 VFs
[03:43:46] [PASSED] 54 VFs
[03:43:46] [PASSED] 55 VFs
[03:43:46] [PASSED] 56 VFs
[03:43:46] [PASSED] 57 VFs
[03:43:46] [PASSED] 58 VFs
[03:43:46] [PASSED] 59 VFs
[03:43:46] [PASSED] 60 VFs
[03:43:46] [PASSED] 61 VFs
[03:43:46] [PASSED] 62 VFs
[03:43:46] [PASSED] 63 VFs
[03:43:46] ================= [PASSED] fair_doorbells ==================
[03:43:46] ======================== fair_ggtt ========================
[03:43:46] [PASSED] 1 VF
[03:43:46] [PASSED] 2 VFs
[03:43:46] [PASSED] 3 VFs
[03:43:46] [PASSED] 4 VFs
[03:43:46] [PASSED] 5 VFs
[03:43:46] [PASSED] 6 VFs
[03:43:46] [PASSED] 7 VFs
[03:43:46] [PASSED] 8 VFs
[03:43:46] [PASSED] 9 VFs
[03:43:46] [PASSED] 10 VFs
[03:43:46] [PASSED] 11 VFs
[03:43:46] [PASSED] 12 VFs
[03:43:46] [PASSED] 13 VFs
[03:43:46] [PASSED] 14 VFs
[03:43:46] [PASSED] 15 VFs
[03:43:46] [PASSED] 16 VFs
[03:43:46] [PASSED] 17 VFs
[03:43:46] [PASSED] 18 VFs
[03:43:46] [PASSED] 19 VFs
[03:43:46] [PASSED] 20 VFs
[03:43:46] [PASSED] 21 VFs
[03:43:46] [PASSED] 22 VFs
[03:43:46] [PASSED] 23 VFs
[03:43:46] [PASSED] 24 VFs
[03:43:46] [PASSED] 25 VFs
[03:43:46] [PASSED] 26 VFs
[03:43:46] [PASSED] 27 VFs
[03:43:46] [PASSED] 28 VFs
[03:43:46] [PASSED] 29 VFs
[03:43:46] [PASSED] 30 VFs
[03:43:46] [PASSED] 31 VFs
[03:43:46] [PASSED] 32 VFs
[03:43:46] [PASSED] 33 VFs
[03:43:46] [PASSED] 34 VFs
[03:43:46] [PASSED] 35 VFs
[03:43:46] [PASSED] 36 VFs
[03:43:46] [PASSED] 37 VFs
[03:43:46] [PASSED] 38 VFs
[03:43:46] [PASSED] 39 VFs
[03:43:46] [PASSED] 40 VFs
[03:43:46] [PASSED] 41 VFs
[03:43:46] [PASSED] 42 VFs
[03:43:46] [PASSED] 43 VFs
[03:43:46] [PASSED] 44 VFs
[03:43:46] [PASSED] 45 VFs
[03:43:46] [PASSED] 46 VFs
[03:43:46] [PASSED] 47 VFs
[03:43:46] [PASSED] 48 VFs
[03:43:46] [PASSED] 49 VFs
[03:43:46] [PASSED] 50 VFs
[03:43:46] [PASSED] 51 VFs
[03:43:46] [PASSED] 52 VFs
[03:43:46] [PASSED] 53 VFs
[03:43:46] [PASSED] 54 VFs
[03:43:46] [PASSED] 55 VFs
[03:43:46] [PASSED] 56 VFs
[03:43:46] [PASSED] 57 VFs
[03:43:46] [PASSED] 58 VFs
[03:43:46] [PASSED] 59 VFs
[03:43:46] [PASSED] 60 VFs
[03:43:46] [PASSED] 61 VFs
[03:43:46] [PASSED] 62 VFs
[03:43:46] [PASSED] 63 VFs
[03:43:46] ==================== [PASSED] fair_ggtt ====================
[03:43:46] ======================== fair_vram ========================
[03:43:46] [PASSED] 1 VF
[03:43:46] [PASSED] 2 VFs
[03:43:46] [PASSED] 3 VFs
[03:43:46] [PASSED] 4 VFs
[03:43:46] [PASSED] 5 VFs
[03:43:46] [PASSED] 6 VFs
[03:43:46] [PASSED] 7 VFs
[03:43:46] [PASSED] 8 VFs
[03:43:46] [PASSED] 9 VFs
[03:43:46] [PASSED] 10 VFs
[03:43:46] [PASSED] 11 VFs
[03:43:46] [PASSED] 12 VFs
[03:43:46] [PASSED] 13 VFs
[03:43:46] [PASSED] 14 VFs
[03:43:46] [PASSED] 15 VFs
[03:43:46] [PASSED] 16 VFs
[03:43:46] [PASSED] 17 VFs
[03:43:46] [PASSED] 18 VFs
[03:43:46] [PASSED] 19 VFs
[03:43:46] [PASSED] 20 VFs
[03:43:46] [PASSED] 21 VFs
[03:43:46] [PASSED] 22 VFs
[03:43:46] [PASSED] 23 VFs
[03:43:46] [PASSED] 24 VFs
[03:43:46] [PASSED] 25 VFs
[03:43:46] [PASSED] 26 VFs
[03:43:46] [PASSED] 27 VFs
[03:43:46] [PASSED] 28 VFs
[03:43:46] [PASSED] 29 VFs
[03:43:46] [PASSED] 30 VFs
[03:43:46] [PASSED] 31 VFs
[03:43:46] [PASSED] 32 VFs
[03:43:46] [PASSED] 33 VFs
[03:43:46] [PASSED] 34 VFs
[03:43:46] [PASSED] 35 VFs
[03:43:46] [PASSED] 36 VFs
[03:43:46] [PASSED] 37 VFs
[03:43:46] [PASSED] 38 VFs
[03:43:46] [PASSED] 39 VFs
[03:43:46] [PASSED] 40 VFs
[03:43:46] [PASSED] 41 VFs
[03:43:46] [PASSED] 42 VFs
[03:43:46] [PASSED] 43 VFs
[03:43:46] [PASSED] 44 VFs
[03:43:46] [PASSED] 45 VFs
[03:43:46] [PASSED] 46 VFs
[03:43:46] [PASSED] 47 VFs
[03:43:46] [PASSED] 48 VFs
[03:43:46] [PASSED] 49 VFs
[03:43:46] [PASSED] 50 VFs
[03:43:46] [PASSED] 51 VFs
[03:43:46] [PASSED] 52 VFs
[03:43:46] [PASSED] 53 VFs
[03:43:46] [PASSED] 54 VFs
[03:43:46] [PASSED] 55 VFs
[03:43:46] [PASSED] 56 VFs
[03:43:46] [PASSED] 57 VFs
[03:43:46] [PASSED] 58 VFs
[03:43:46] [PASSED] 59 VFs
[03:43:46] [PASSED] 60 VFs
[03:43:46] [PASSED] 61 VFs
[03:43:46] [PASSED] 62 VFs
[03:43:46] [PASSED] 63 VFs
[03:43:46] ==================== [PASSED] fair_vram ====================
[03:43:46] ================== [PASSED] pf_gt_config ===================
[03:43:46] ===================== lmtt (1 subtest) =====================
[03:43:46] ======================== test_ops =========================
[03:43:46] [PASSED] 2-level
[03:43:46] [PASSED] multi-level
[03:43:46] ==================== [PASSED] test_ops =====================
[03:43:46] ====================== [PASSED] lmtt =======================
[03:43:46] ================= pf_service (11 subtests) =================
[03:43:46] [PASSED] pf_negotiate_any
[03:43:46] [PASSED] pf_negotiate_base_match
[03:43:46] [PASSED] pf_negotiate_base_newer
[03:43:46] [PASSED] pf_negotiate_base_next
[03:43:46] [SKIPPED] pf_negotiate_base_older
[03:43:46] [PASSED] pf_negotiate_base_prev
[03:43:46] [PASSED] pf_negotiate_latest_match
[03:43:46] [PASSED] pf_negotiate_latest_newer
[03:43:46] [PASSED] pf_negotiate_latest_next
[03:43:46] [SKIPPED] pf_negotiate_latest_older
[03:43:46] [SKIPPED] pf_negotiate_latest_prev
[03:43:46] =================== [PASSED] pf_service ====================
[03:43:46] ================= xe_guc_g2g (2 subtests) ==================
[03:43:46] ============== xe_live_guc_g2g_kunit_default ==============
[03:43:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[03:43:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[03:43:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[03:43:46] =================== [SKIPPED] xe_guc_g2g ===================
[03:43:46] =================== xe_mocs (2 subtests) ===================
[03:43:46] ================ xe_live_mocs_kernel_kunit ================
[03:43:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[03:43:46] ================ xe_live_mocs_reset_kunit =================
[03:43:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[03:43:46] ==================== [SKIPPED] xe_mocs =====================
[03:43:46] ================= xe_migrate (2 subtests) ==================
[03:43:46] ================= xe_migrate_sanity_kunit =================
[03:43:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[03:43:46] ================== xe_validate_ccs_kunit ==================
[03:43:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[03:43:46] =================== [SKIPPED] xe_migrate ===================
[03:43:46] ================== xe_dma_buf (1 subtest) ==================
[03:43:46] ==================== xe_dma_buf_kunit =====================
[03:43:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[03:43:46] =================== [SKIPPED] xe_dma_buf ===================
[03:43:46] ================= xe_bo_shrink (1 subtest) =================
[03:43:46] =================== xe_bo_shrink_kunit ====================
[03:43:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[03:43:46] ================== [SKIPPED] xe_bo_shrink ==================
[03:43:46] ==================== xe_bo (2 subtests) ====================
[03:43:46] ================== xe_ccs_migrate_kunit ===================
[03:43:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[03:43:46] ==================== xe_bo_evict_kunit ====================
[03:43:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[03:43:46] ===================== [SKIPPED] xe_bo ======================
[03:43:46] ==================== args (13 subtests) ====================
[03:43:46] [PASSED] count_args_test
[03:43:46] [PASSED] call_args_example
[03:43:46] [PASSED] call_args_test
[03:43:46] [PASSED] drop_first_arg_example
[03:43:46] [PASSED] drop_first_arg_test
[03:43:46] [PASSED] first_arg_example
[03:43:46] [PASSED] first_arg_test
[03:43:46] [PASSED] last_arg_example
[03:43:46] [PASSED] last_arg_test
[03:43:46] [PASSED] pick_arg_example
[03:43:46] [PASSED] if_args_example
[03:43:46] [PASSED] if_args_test
[03:43:46] [PASSED] sep_comma_example
[03:43:46] ====================== [PASSED] args =======================
[03:43:46] =================== xe_pci (3 subtests) ====================
[03:43:46] ==================== check_graphics_ip ====================
[03:43:46] [PASSED] 12.00 Xe_LP
[03:43:46] [PASSED] 12.10 Xe_LP+
[03:43:46] [PASSED] 12.55 Xe_HPG
[03:43:46] [PASSED] 12.60 Xe_HPC
[03:43:46] [PASSED] 12.70 Xe_LPG
[03:43:46] [PASSED] 12.71 Xe_LPG
[03:43:46] [PASSED] 12.74 Xe_LPG+
[03:43:46] [PASSED] 20.01 Xe2_HPG
[03:43:46] [PASSED] 20.02 Xe2_HPG
[03:43:46] [PASSED] 20.04 Xe2_LPG
[03:43:46] [PASSED] 30.00 Xe3_LPG
[03:43:46] [PASSED] 30.01 Xe3_LPG
[03:43:46] [PASSED] 30.03 Xe3_LPG
[03:43:46] [PASSED] 30.04 Xe3_LPG
[03:43:46] [PASSED] 30.05 Xe3_LPG
[03:43:46] [PASSED] 35.10 Xe3p_LPG
[03:43:46] [PASSED] 35.11 Xe3p_XPC
[03:43:46] ================ [PASSED] check_graphics_ip ================
[03:43:46] ===================== check_media_ip ======================
[03:43:46] [PASSED] 12.00 Xe_M
[03:43:46] [PASSED] 12.55 Xe_HPM
[03:43:46] [PASSED] 13.00 Xe_LPM+
[03:43:46] [PASSED] 13.01 Xe2_HPM
[03:43:46] [PASSED] 20.00 Xe2_LPM
[03:43:46] [PASSED] 30.00 Xe3_LPM
[03:43:46] [PASSED] 30.02 Xe3_LPM
[03:43:46] [PASSED] 35.00 Xe3p_LPM
[03:43:46] [PASSED] 35.03 Xe3p_HPM
[03:43:46] ================= [PASSED] check_media_ip ==================
[03:43:46] =================== check_platform_desc ===================
[03:43:46] [PASSED] 0x9A60 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A68 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A70 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A40 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A49 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A59 (TIGERLAKE)
[03:43:46] [PASSED] 0x9A78 (TIGERLAKE)
[03:43:46] [PASSED] 0x9AC0 (TIGERLAKE)
[03:43:46] [PASSED] 0x9AC9 (TIGERLAKE)
[03:43:46] [PASSED] 0x9AD9 (TIGERLAKE)
[03:43:46] [PASSED] 0x9AF8 (TIGERLAKE)
[03:43:46] [PASSED] 0x4C80 (ROCKETLAKE)
[03:43:46] [PASSED] 0x4C8A (ROCKETLAKE)
[03:43:46] [PASSED] 0x4C8B (ROCKETLAKE)
[03:43:46] [PASSED] 0x4C8C (ROCKETLAKE)
[03:43:46] [PASSED] 0x4C90 (ROCKETLAKE)
[03:43:46] [PASSED] 0x4C9A (ROCKETLAKE)
[03:43:46] [PASSED] 0x4680 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4682 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4688 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x468A (ALDERLAKE_S)
[03:43:46] [PASSED] 0x468B (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4690 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4692 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4693 (ALDERLAKE_S)
[03:43:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46AA (ALDERLAKE_P)
[03:43:46] [PASSED] 0x462A (ALDERLAKE_P)
[03:43:46] [PASSED] 0x4626 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x4628 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[03:43:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[03:43:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[03:43:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[03:43:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[03:43:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[03:43:46] [PASSED] 0xA721 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA720 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[03:43:46] [PASSED] 0xA780 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA781 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA782 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA783 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA788 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA789 (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA78A (ALDERLAKE_S)
[03:43:46] [PASSED] 0xA78B (ALDERLAKE_S)
[03:43:46] [PASSED] 0x4905 (DG1)
[03:43:46] [PASSED] 0x4906 (DG1)
[03:43:46] [PASSED] 0x4907 (DG1)
[03:43:46] [PASSED] 0x4908 (DG1)
[03:43:46] [PASSED] 0x4909 (DG1)
[03:43:46] [PASSED] 0x56C0 (DG2)
[03:43:46] [PASSED] 0x56C2 (DG2)
[03:43:46] [PASSED] 0x56C1 (DG2)
[03:43:46] [PASSED] 0x7D51 (METEORLAKE)
[03:43:46] [PASSED] 0x7DD1 (METEORLAKE)
[03:43:46] [PASSED] 0x7D41 (METEORLAKE)
[03:43:46] [PASSED] 0x7D67 (METEORLAKE)
[03:43:46] [PASSED] 0xB640 (METEORLAKE)
[03:43:46] [PASSED] 0x56A0 (DG2)
[03:43:46] [PASSED] 0x56A1 (DG2)
[03:43:46] [PASSED] 0x56A2 (DG2)
[03:43:46] [PASSED] 0x56BE (DG2)
[03:43:46] [PASSED] 0x56BF (DG2)
[03:43:46] [PASSED] 0x5690 (DG2)
[03:43:46] [PASSED] 0x5691 (DG2)
[03:43:46] [PASSED] 0x5692 (DG2)
[03:43:46] [PASSED] 0x56A5 (DG2)
[03:43:46] [PASSED] 0x56A6 (DG2)
[03:43:46] [PASSED] 0x56B0 (DG2)
[03:43:46] [PASSED] 0x56B1 (DG2)
[03:43:46] [PASSED] 0x56BA (DG2)
[03:43:46] [PASSED] 0x56BB (DG2)
[03:43:46] [PASSED] 0x56BC (DG2)
[03:43:46] [PASSED] 0x56BD (DG2)
[03:43:46] [PASSED] 0x5693 (DG2)
[03:43:46] [PASSED] 0x5694 (DG2)
[03:43:46] [PASSED] 0x5695 (DG2)
[03:43:46] [PASSED] 0x56A3 (DG2)
[03:43:46] [PASSED] 0x56A4 (DG2)
[03:43:46] [PASSED] 0x56B2 (DG2)
[03:43:46] [PASSED] 0x56B3 (DG2)
[03:43:46] [PASSED] 0x5696 (DG2)
[03:43:46] [PASSED] 0x5697 (DG2)
[03:43:46] [PASSED] 0xB69 (PVC)
[03:43:46] [PASSED] 0xB6E (PVC)
[03:43:46] [PASSED] 0xBD4 (PVC)
[03:43:46] [PASSED] 0xBD5 (PVC)
[03:43:46] [PASSED] 0xBD6 (PVC)
[03:43:46] [PASSED] 0xBD7 (PVC)
[03:43:46] [PASSED] 0xBD8 (PVC)
[03:43:46] [PASSED] 0xBD9 (PVC)
[03:43:46] [PASSED] 0xBDA (PVC)
[03:43:46] [PASSED] 0xBDB (PVC)
[03:43:46] [PASSED] 0xBE0 (PVC)
[03:43:46] [PASSED] 0xBE1 (PVC)
[03:43:46] [PASSED] 0xBE5 (PVC)
[03:43:46] [PASSED] 0x7D40 (METEORLAKE)
[03:43:46] [PASSED] 0x7D45 (METEORLAKE)
[03:43:46] [PASSED] 0x7D55 (METEORLAKE)
[03:43:46] [PASSED] 0x7D60 (METEORLAKE)
[03:43:46] [PASSED] 0x7DD5 (METEORLAKE)
[03:43:46] [PASSED] 0x6420 (LUNARLAKE)
[03:43:46] [PASSED] 0x64A0 (LUNARLAKE)
[03:43:46] [PASSED] 0x64B0 (LUNARLAKE)
[03:43:46] [PASSED] 0xE202 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE209 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE20B (BATTLEMAGE)
[03:43:46] [PASSED] 0xE20C (BATTLEMAGE)
[03:43:46] [PASSED] 0xE20D (BATTLEMAGE)
[03:43:46] [PASSED] 0xE210 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE211 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE212 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE216 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE220 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE221 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE222 (BATTLEMAGE)
[03:43:46] [PASSED] 0xE223 (BATTLEMAGE)
[03:43:46] [PASSED] 0xB080 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB081 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB082 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB083 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB084 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB085 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB086 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB087 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB08F (PANTHERLAKE)
[03:43:46] [PASSED] 0xB090 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[03:43:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[03:43:46] [PASSED] 0xFD80 (PANTHERLAKE)
[03:43:46] [PASSED] 0xFD81 (PANTHERLAKE)
[03:43:46] [PASSED] 0xD740 (NOVALAKE_S)
[03:43:46] [PASSED] 0xD741 (NOVALAKE_S)
[03:43:46] [PASSED] 0xD742 (NOVALAKE_S)
[03:43:46] [PASSED] 0xD743 (NOVALAKE_S)
[03:43:46] [PASSED] 0xD744 (NOVALAKE_S)
[03:43:46] [PASSED] 0xD745 (NOVALAKE_S)
[03:43:46] [PASSED] 0x674C (CRESCENTISLAND)
[03:43:46] [PASSED] 0xD750 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD751 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD752 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD753 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD754 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD755 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD756 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD757 (NOVALAKE_P)
[03:43:46] [PASSED] 0xD75F (NOVALAKE_P)
[03:43:46] =============== [PASSED] check_platform_desc ===============
[03:43:46] ===================== [PASSED] xe_pci ======================
[03:43:46] =================== xe_rtp (2 subtests) ====================
[03:43:46] =============== xe_rtp_process_to_sr_tests ================
[03:43:46] [PASSED] coalesce-same-reg
[03:43:46] [PASSED] no-match-no-add
[03:43:46] [PASSED] match-or
[03:43:46] [PASSED] match-or-xfail
[03:43:46] [PASSED] no-match-no-add-multiple-rules
[03:43:46] [PASSED] two-regs-two-entries
[03:43:46] [PASSED] clr-one-set-other
[03:43:46] [PASSED] set-field
[03:43:46] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[03:43:46] [PASSED] conflict-not-disjoint
[03:43:46] [PASSED] conflict-reg-type
[03:43:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[03:43:46] ================== xe_rtp_process_tests ===================
[03:43:46] [PASSED] active1
[03:43:46] [PASSED] active2
[03:43:46] [PASSED] active-inactive
[03:43:46] [PASSED] inactive-active
[03:43:46] [PASSED] inactive-1st_or_active-inactive
[03:43:46] [PASSED] inactive-2nd_or_active-inactive
[03:43:46] [PASSED] inactive-last_or_active-inactive
[03:43:46] [PASSED] inactive-no_or_active-inactive
[03:43:46] ============== [PASSED] xe_rtp_process_tests ===============
[03:43:46] ===================== [PASSED] xe_rtp ======================
[03:43:46] ==================== xe_wa (1 subtest) =====================
[03:43:46] ======================== xe_wa_gt =========================
[03:43:46] [PASSED] TIGERLAKE B0
[03:43:46] [PASSED] DG1 A0
[03:43:46] [PASSED] DG1 B0
[03:43:46] [PASSED] ALDERLAKE_S A0
[03:43:46] [PASSED] ALDERLAKE_S B0
[03:43:46] [PASSED] ALDERLAKE_S C0
[03:43:46] [PASSED] ALDERLAKE_S D0
[03:43:46] [PASSED] ALDERLAKE_P A0
[03:43:46] [PASSED] ALDERLAKE_P B0
[03:43:46] [PASSED] ALDERLAKE_P C0
[03:43:46] [PASSED] ALDERLAKE_S RPLS D0
[03:43:46] [PASSED] ALDERLAKE_P RPLU E0
[03:43:46] [PASSED] DG2 G10 C0
[03:43:46] [PASSED] DG2 G11 B1
[03:43:46] [PASSED] DG2 G12 A1
[03:43:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:43:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:43:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[03:43:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[03:43:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[03:43:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[03:43:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[03:43:46] ==================== [PASSED] xe_wa_gt =====================
[03:43:46] ====================== [PASSED] xe_wa ======================
[03:43:46] ============================================================
[03:43:46] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[03:43:46] Elapsed time: 43.500s total, 4.775s configuring, 38.057s building, 0.615s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[03:43:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:43:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[03:44:17] Starting KUnit Kernel (1/1)...
[03:44:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:44:17] ============ drm_test_pick_cmdline (2 subtests) ============
[03:44:17] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[03:44:17] =============== drm_test_pick_cmdline_named ===============
[03:44:17] [PASSED] NTSC
[03:44:17] [PASSED] NTSC-J
[03:44:17] [PASSED] PAL
[03:44:17] [PASSED] PAL-M
[03:44:17] =========== [PASSED] drm_test_pick_cmdline_named ===========
[03:44:17] ============== [PASSED] drm_test_pick_cmdline ==============
[03:44:17] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[03:44:17] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[03:44:17] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[03:44:17] =========== drm_validate_clone_mode (2 subtests) ===========
[03:44:17] ============== drm_test_check_in_clone_mode ===============
[03:44:17] [PASSED] in_clone_mode
[03:44:17] [PASSED] not_in_clone_mode
[03:44:17] ========== [PASSED] drm_test_check_in_clone_mode ===========
[03:44:17] =============== drm_test_check_valid_clones ===============
[03:44:17] [PASSED] not_in_clone_mode
[03:44:17] [PASSED] valid_clone
[03:44:17] [PASSED] invalid_clone
[03:44:17] =========== [PASSED] drm_test_check_valid_clones ===========
[03:44:17] ============= [PASSED] drm_validate_clone_mode =============
[03:44:17] ============= drm_validate_modeset (1 subtest) =============
[03:44:17] [PASSED] drm_test_check_connector_changed_modeset
[03:44:17] ============== [PASSED] drm_validate_modeset ===============
[03:44:17] ====== drm_test_bridge_get_current_state (2 subtests) ======
[03:44:17] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[03:44:17] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[03:44:17] ======== [PASSED] drm_test_bridge_get_current_state ========
[03:44:17] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[03:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[03:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[03:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[03:44:17] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[03:44:17] ============== drm_bridge_alloc (2 subtests) ===============
[03:44:17] [PASSED] drm_test_drm_bridge_alloc_basic
[03:44:17] [PASSED] drm_test_drm_bridge_alloc_get_put
[03:44:17] ================ [PASSED] drm_bridge_alloc =================
[03:44:17] ============= drm_cmdline_parser (40 subtests) =============
[03:44:17] [PASSED] drm_test_cmdline_force_d_only
[03:44:17] [PASSED] drm_test_cmdline_force_D_only_dvi
[03:44:17] [PASSED] drm_test_cmdline_force_D_only_hdmi
[03:44:17] [PASSED] drm_test_cmdline_force_D_only_not_digital
[03:44:17] [PASSED] drm_test_cmdline_force_e_only
[03:44:17] [PASSED] drm_test_cmdline_res
[03:44:17] [PASSED] drm_test_cmdline_res_vesa
[03:44:17] [PASSED] drm_test_cmdline_res_vesa_rblank
[03:44:17] [PASSED] drm_test_cmdline_res_rblank
[03:44:17] [PASSED] drm_test_cmdline_res_bpp
[03:44:17] [PASSED] drm_test_cmdline_res_refresh
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[03:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[03:44:17] [PASSED] drm_test_cmdline_res_margins_force_on
[03:44:17] [PASSED] drm_test_cmdline_res_vesa_margins
[03:44:17] [PASSED] drm_test_cmdline_name
[03:44:17] [PASSED] drm_test_cmdline_name_bpp
[03:44:17] [PASSED] drm_test_cmdline_name_option
[03:44:17] [PASSED] drm_test_cmdline_name_bpp_option
[03:44:17] [PASSED] drm_test_cmdline_rotate_0
[03:44:17] [PASSED] drm_test_cmdline_rotate_90
[03:44:17] [PASSED] drm_test_cmdline_rotate_180
[03:44:17] [PASSED] drm_test_cmdline_rotate_270
[03:44:17] [PASSED] drm_test_cmdline_hmirror
[03:44:17] [PASSED] drm_test_cmdline_vmirror
[03:44:17] [PASSED] drm_test_cmdline_margin_options
[03:44:17] [PASSED] drm_test_cmdline_multiple_options
[03:44:17] [PASSED] drm_test_cmdline_bpp_extra_and_option
[03:44:17] [PASSED] drm_test_cmdline_extra_and_option
[03:44:17] [PASSED] drm_test_cmdline_freestanding_options
[03:44:17] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[03:44:17] [PASSED] drm_test_cmdline_panel_orientation
[03:44:17] ================ drm_test_cmdline_invalid =================
[03:44:17] [PASSED] margin_only
[03:44:17] [PASSED] interlace_only
[03:44:17] [PASSED] res_missing_x
[03:44:17] [PASSED] res_missing_y
[03:44:17] [PASSED] res_bad_y
[03:44:17] [PASSED] res_missing_y_bpp
[03:44:17] [PASSED] res_bad_bpp
[03:44:17] [PASSED] res_bad_refresh
[03:44:17] [PASSED] res_bpp_refresh_force_on_off
[03:44:17] [PASSED] res_invalid_mode
[03:44:17] [PASSED] res_bpp_wrong_place_mode
[03:44:17] [PASSED] name_bpp_refresh
[03:44:17] [PASSED] name_refresh
[03:44:17] [PASSED] name_refresh_wrong_mode
[03:44:17] [PASSED] name_refresh_invalid_mode
[03:44:17] [PASSED] rotate_multiple
[03:44:17] [PASSED] rotate_invalid_val
[03:44:17] [PASSED] rotate_truncated
[03:44:17] [PASSED] invalid_option
[03:44:17] [PASSED] invalid_tv_option
[03:44:17] [PASSED] truncated_tv_option
[03:44:17] ============ [PASSED] drm_test_cmdline_invalid =============
[03:44:17] =============== drm_test_cmdline_tv_options ===============
[03:44:17] [PASSED] NTSC
[03:44:17] [PASSED] NTSC_443
[03:44:17] [PASSED] NTSC_J
[03:44:17] [PASSED] PAL
[03:44:17] [PASSED] PAL_M
[03:44:17] [PASSED] PAL_N
[03:44:17] [PASSED] SECAM
[03:44:17] [PASSED] MONO_525
[03:44:17] [PASSED] MONO_625
[03:44:17] =========== [PASSED] drm_test_cmdline_tv_options ===========
[03:44:17] =============== [PASSED] drm_cmdline_parser ================
[03:44:17] ========== drmm_connector_hdmi_init (20 subtests) ==========
[03:44:17] [PASSED] drm_test_connector_hdmi_init_valid
[03:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_8
[03:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_10
[03:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_12
[03:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[03:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_null
[03:44:17] [PASSED] drm_test_connector_hdmi_init_formats_empty
[03:44:17] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[03:44:17] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[03:44:17] [PASSED] supported_formats=0x9 yuv420_allowed=1
[03:44:17] [PASSED] supported_formats=0x9 yuv420_allowed=0
[03:44:17] [PASSED] supported_formats=0x3 yuv420_allowed=1
[03:44:17] [PASSED] supported_formats=0x3 yuv420_allowed=0
[03:44:17] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[03:44:17] [PASSED] drm_test_connector_hdmi_init_null_ddc
[03:44:17] [PASSED] drm_test_connector_hdmi_init_null_product
[03:44:17] [PASSED] drm_test_connector_hdmi_init_null_vendor
[03:44:17] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[03:44:17] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[03:44:17] [PASSED] drm_test_connector_hdmi_init_product_valid
[03:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[03:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[03:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[03:44:17] ========= drm_test_connector_hdmi_init_type_valid =========
[03:44:17] [PASSED] HDMI-A
[03:44:17] [PASSED] HDMI-B
[03:44:17] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[03:44:17] ======== drm_test_connector_hdmi_init_type_invalid ========
[03:44:17] [PASSED] Unknown
[03:44:17] [PASSED] VGA
[03:44:17] [PASSED] DVI-I
[03:44:17] [PASSED] DVI-D
[03:44:17] [PASSED] DVI-A
[03:44:17] [PASSED] Composite
[03:44:17] [PASSED] SVIDEO
[03:44:17] [PASSED] LVDS
[03:44:17] [PASSED] Component
[03:44:17] [PASSED] DIN
[03:44:17] [PASSED] DP
[03:44:17] [PASSED] TV
[03:44:17] [PASSED] eDP
[03:44:17] [PASSED] Virtual
[03:44:17] [PASSED] DSI
[03:44:17] [PASSED] DPI
[03:44:17] [PASSED] Writeback
[03:44:17] [PASSED] SPI
[03:44:17] [PASSED] USB
[03:44:17] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[03:44:17] ============ [PASSED] drmm_connector_hdmi_init =============
[03:44:17] ============= drmm_connector_init (3 subtests) =============
[03:44:17] [PASSED] drm_test_drmm_connector_init
[03:44:17] [PASSED] drm_test_drmm_connector_init_null_ddc
[03:44:17] ========= drm_test_drmm_connector_init_type_valid =========
[03:44:17] [PASSED] Unknown
[03:44:17] [PASSED] VGA
[03:44:17] [PASSED] DVI-I
[03:44:17] [PASSED] DVI-D
[03:44:17] [PASSED] DVI-A
[03:44:17] [PASSED] Composite
[03:44:17] [PASSED] SVIDEO
[03:44:17] [PASSED] LVDS
[03:44:17] [PASSED] Component
[03:44:17] [PASSED] DIN
[03:44:17] [PASSED] DP
[03:44:17] [PASSED] HDMI-A
[03:44:17] [PASSED] HDMI-B
[03:44:17] [PASSED] TV
[03:44:17] [PASSED] eDP
[03:44:17] [PASSED] Virtual
[03:44:17] [PASSED] DSI
[03:44:17] [PASSED] DPI
[03:44:17] [PASSED] Writeback
[03:44:17] [PASSED] SPI
[03:44:17] [PASSED] USB
[03:44:17] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[03:44:17] =============== [PASSED] drmm_connector_init ===============
[03:44:17] ========= drm_connector_dynamic_init (6 subtests) ==========
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_init
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_init_properties
[03:44:17] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[03:44:17] [PASSED] Unknown
[03:44:17] [PASSED] VGA
[03:44:17] [PASSED] DVI-I
[03:44:17] [PASSED] DVI-D
[03:44:17] [PASSED] DVI-A
[03:44:17] [PASSED] Composite
[03:44:17] [PASSED] SVIDEO
[03:44:17] [PASSED] LVDS
[03:44:17] [PASSED] Component
[03:44:17] [PASSED] DIN
[03:44:17] [PASSED] DP
[03:44:17] [PASSED] HDMI-A
[03:44:17] [PASSED] HDMI-B
[03:44:17] [PASSED] TV
[03:44:17] [PASSED] eDP
[03:44:17] [PASSED] Virtual
[03:44:17] [PASSED] DSI
[03:44:17] [PASSED] DPI
[03:44:17] [PASSED] Writeback
[03:44:17] [PASSED] SPI
[03:44:17] [PASSED] USB
[03:44:17] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[03:44:17] ======== drm_test_drm_connector_dynamic_init_name =========
[03:44:17] [PASSED] Unknown
[03:44:17] [PASSED] VGA
[03:44:17] [PASSED] DVI-I
[03:44:17] [PASSED] DVI-D
[03:44:17] [PASSED] DVI-A
[03:44:17] [PASSED] Composite
[03:44:17] [PASSED] SVIDEO
[03:44:17] [PASSED] LVDS
[03:44:17] [PASSED] Component
[03:44:17] [PASSED] DIN
[03:44:17] [PASSED] DP
[03:44:17] [PASSED] HDMI-A
[03:44:17] [PASSED] HDMI-B
[03:44:17] [PASSED] TV
[03:44:17] [PASSED] eDP
[03:44:17] [PASSED] Virtual
[03:44:17] [PASSED] DSI
[03:44:17] [PASSED] DPI
[03:44:17] [PASSED] Writeback
[03:44:17] [PASSED] SPI
[03:44:17] [PASSED] USB
[03:44:17] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[03:44:17] =========== [PASSED] drm_connector_dynamic_init ============
[03:44:17] ==== drm_connector_dynamic_register_early (4 subtests) =====
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[03:44:17] ====== [PASSED] drm_connector_dynamic_register_early =======
[03:44:17] ======= drm_connector_dynamic_register (7 subtests) ========
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[03:44:17] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[03:44:17] ========= [PASSED] drm_connector_dynamic_register ==========
[03:44:17] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[03:44:17] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[03:44:17] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[03:44:17] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[03:44:17] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[03:44:17] ========== drm_test_get_tv_mode_from_name_valid ===========
[03:44:17] [PASSED] NTSC
[03:44:17] [PASSED] NTSC-443
[03:44:17] [PASSED] NTSC-J
[03:44:17] [PASSED] PAL
[03:44:17] [PASSED] PAL-M
[03:44:17] [PASSED] PAL-N
[03:44:17] [PASSED] SECAM
[03:44:17] [PASSED] Mono
[03:44:17] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[03:44:17] [PASSED] drm_test_get_tv_mode_from_name_truncated
[03:44:17] ============ [PASSED] drm_get_tv_mode_from_name ============
[03:44:17] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[03:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[03:44:17] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[03:44:17] [PASSED] VIC 96
[03:44:17] [PASSED] VIC 97
[03:44:17] [PASSED] VIC 101
[03:44:17] [PASSED] VIC 102
[03:44:17] [PASSED] VIC 106
[03:44:17] [PASSED] VIC 107
[03:44:17] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[03:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[03:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[03:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[03:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[03:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[03:44:17] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[03:44:17] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[03:44:17] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[03:44:17] [PASSED] Automatic
[03:44:17] [PASSED] Full
[03:44:17] [PASSED] Limited 16:235
[03:44:17] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[03:44:17] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[03:44:17] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[03:44:17] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[03:44:17] === drm_test_drm_hdmi_connector_get_output_format_name ====
[03:44:17] [PASSED] RGB
[03:44:17] [PASSED] YUV 4:2:0
[03:44:17] [PASSED] YUV 4:2:2
[03:44:17] [PASSED] YUV 4:4:4
[03:44:17] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[03:44:17] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[03:44:17] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[03:44:17] ============= drm_damage_helper (21 subtests) ==============
[03:44:17] [PASSED] drm_test_damage_iter_no_damage
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_src_moved
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_not_visible
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[03:44:17] [PASSED] drm_test_damage_iter_no_damage_no_fb
[03:44:17] [PASSED] drm_test_damage_iter_simple_damage
[03:44:17] [PASSED] drm_test_damage_iter_single_damage
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_outside_src
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_src_moved
[03:44:17] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[03:44:17] [PASSED] drm_test_damage_iter_damage
[03:44:17] [PASSED] drm_test_damage_iter_damage_one_intersect
[03:44:17] [PASSED] drm_test_damage_iter_damage_one_outside
[03:44:17] [PASSED] drm_test_damage_iter_damage_src_moved
[03:44:17] [PASSED] drm_test_damage_iter_damage_not_visible
[03:44:17] ================ [PASSED] drm_damage_helper ================
[03:44:17] ============== drm_dp_mst_helper (3 subtests) ==============
[03:44:17] ============== drm_test_dp_mst_calc_pbn_mode ==============
[03:44:17] [PASSED] Clock 154000 BPP 30 DSC disabled
[03:44:17] [PASSED] Clock 234000 BPP 30 DSC disabled
[03:44:17] [PASSED] Clock 297000 BPP 24 DSC disabled
[03:44:17] [PASSED] Clock 332880 BPP 24 DSC enabled
[03:44:17] [PASSED] Clock 324540 BPP 24 DSC enabled
[03:44:17] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[03:44:17] ============== drm_test_dp_mst_calc_pbn_div ===============
[03:44:17] [PASSED] Link rate 2000000 lane count 4
[03:44:17] [PASSED] Link rate 2000000 lane count 2
[03:44:17] [PASSED] Link rate 2000000 lane count 1
[03:44:17] [PASSED] Link rate 1350000 lane count 4
[03:44:17] [PASSED] Link rate 1350000 lane count 2
[03:44:17] [PASSED] Link rate 1350000 lane count 1
[03:44:17] [PASSED] Link rate 1000000 lane count 4
[03:44:17] [PASSED] Link rate 1000000 lane count 2
[03:44:17] [PASSED] Link rate 1000000 lane count 1
[03:44:17] [PASSED] Link rate 810000 lane count 4
[03:44:17] [PASSED] Link rate 810000 lane count 2
[03:44:17] [PASSED] Link rate 810000 lane count 1
[03:44:17] [PASSED] Link rate 540000 lane count 4
[03:44:17] [PASSED] Link rate 540000 lane count 2
[03:44:17] [PASSED] Link rate 540000 lane count 1
[03:44:17] [PASSED] Link rate 270000 lane count 4
[03:44:17] [PASSED] Link rate 270000 lane count 2
[03:44:17] [PASSED] Link rate 270000 lane count 1
[03:44:17] [PASSED] Link rate 162000 lane count 4
[03:44:17] [PASSED] Link rate 162000 lane count 2
[03:44:17] [PASSED] Link rate 162000 lane count 1
[03:44:17] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[03:44:17] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[03:44:17] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[03:44:17] [PASSED] DP_POWER_UP_PHY with port number
[03:44:17] [PASSED] DP_POWER_DOWN_PHY with port number
[03:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[03:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[03:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[03:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[03:44:17] [PASSED] DP_QUERY_PAYLOAD with port number
[03:44:17] [PASSED] DP_QUERY_PAYLOAD with VCPI
[03:44:17] [PASSED] DP_REMOTE_DPCD_READ with port number
[03:44:17] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[03:44:17] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[03:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[03:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[03:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[03:44:17] [PASSED] DP_REMOTE_I2C_READ with port number
[03:44:17] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[03:44:17] [PASSED] DP_REMOTE_I2C_READ with transactions array
[03:44:17] [PASSED] DP_REMOTE_I2C_WRITE with port number
[03:44:17] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[03:44:17] [PASSED] DP_REMOTE_I2C_WRITE with data array
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[03:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[03:44:17] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[03:44:17] ================ [PASSED] drm_dp_mst_helper ================
[03:44:17] ================== drm_exec (7 subtests) ===================
[03:44:17] [PASSED] sanitycheck
[03:44:17] [PASSED] test_lock
[03:44:17] [PASSED] test_lock_unlock
[03:44:17] [PASSED] test_duplicates
[03:44:17] [PASSED] test_prepare
[03:44:17] [PASSED] test_prepare_array
[03:44:17] [PASSED] test_multiple_loops
[03:44:17] ==================== [PASSED] drm_exec =====================
[03:44:17] =========== drm_format_helper_test (17 subtests) ===========
[03:44:17] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[03:44:17] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[03:44:17] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[03:44:17] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[03:44:17] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[03:44:17] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[03:44:17] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[03:44:17] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[03:44:17] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[03:44:17] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[03:44:17] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[03:44:17] ============== drm_test_fb_xrgb8888_to_mono ===============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[03:44:17] ==================== drm_test_fb_swab =====================
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ================ [PASSED] drm_test_fb_swab =================
[03:44:17] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[03:44:17] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[03:44:17] [PASSED] single_pixel_source_buffer
[03:44:17] [PASSED] single_pixel_clip_rectangle
[03:44:17] [PASSED] well_known_colors
[03:44:17] [PASSED] destination_pitch
[03:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[03:44:17] ================= drm_test_fb_clip_offset =================
[03:44:17] [PASSED] pass through
[03:44:17] [PASSED] horizontal offset
[03:44:17] [PASSED] vertical offset
[03:44:17] [PASSED] horizontal and vertical offset
[03:44:17] [PASSED] horizontal offset (custom pitch)
[03:44:17] [PASSED] vertical offset (custom pitch)
[03:44:17] [PASSED] horizontal and vertical offset (custom pitch)
[03:44:17] ============= [PASSED] drm_test_fb_clip_offset =============
[03:44:17] =================== drm_test_fb_memcpy ====================
[03:44:17] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[03:44:17] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[03:44:17] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[03:44:17] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[03:44:17] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[03:44:17] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[03:44:17] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[03:44:17] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[03:44:17] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[03:44:17] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[03:44:17] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[03:44:17] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[03:44:17] =============== [PASSED] drm_test_fb_memcpy ================
[03:44:17] ============= [PASSED] drm_format_helper_test ==============
[03:44:17] ================= drm_format (18 subtests) =================
[03:44:17] [PASSED] drm_test_format_block_width_invalid
[03:44:17] [PASSED] drm_test_format_block_width_one_plane
[03:44:17] [PASSED] drm_test_format_block_width_two_plane
[03:44:17] [PASSED] drm_test_format_block_width_three_plane
[03:44:17] [PASSED] drm_test_format_block_width_tiled
[03:44:17] [PASSED] drm_test_format_block_height_invalid
[03:44:17] [PASSED] drm_test_format_block_height_one_plane
[03:44:17] [PASSED] drm_test_format_block_height_two_plane
[03:44:17] [PASSED] drm_test_format_block_height_three_plane
[03:44:17] [PASSED] drm_test_format_block_height_tiled
[03:44:17] [PASSED] drm_test_format_min_pitch_invalid
[03:44:17] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[03:44:17] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[03:44:17] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[03:44:17] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[03:44:17] [PASSED] drm_test_format_min_pitch_two_plane
[03:44:17] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[03:44:17] [PASSED] drm_test_format_min_pitch_tiled
[03:44:17] =================== [PASSED] drm_format ====================
[03:44:17] ============== drm_framebuffer (10 subtests) ===============
[03:44:17] ========== drm_test_framebuffer_check_src_coords ==========
[03:44:17] [PASSED] Success: source fits into fb
[03:44:17] [PASSED] Fail: overflowing fb with x-axis coordinate
[03:44:17] [PASSED] Fail: overflowing fb with y-axis coordinate
[03:44:17] [PASSED] Fail: overflowing fb with source width
[03:44:17] [PASSED] Fail: overflowing fb with source height
[03:44:17] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[03:44:17] [PASSED] drm_test_framebuffer_cleanup
[03:44:17] =============== drm_test_framebuffer_create ===============
[03:44:17] [PASSED] ABGR8888 normal sizes
[03:44:17] [PASSED] ABGR8888 max sizes
[03:44:17] [PASSED] ABGR8888 pitch greater than min required
[03:44:17] [PASSED] ABGR8888 pitch less than min required
[03:44:17] [PASSED] ABGR8888 Invalid width
[03:44:17] [PASSED] ABGR8888 Invalid buffer handle
[03:44:17] [PASSED] No pixel format
[03:44:17] [PASSED] ABGR8888 Width 0
[03:44:17] [PASSED] ABGR8888 Height 0
[03:44:17] [PASSED] ABGR8888 Out of bound height * pitch combination
[03:44:17] [PASSED] ABGR8888 Large buffer offset
[03:44:17] [PASSED] ABGR8888 Buffer offset for inexistent plane
[03:44:17] [PASSED] ABGR8888 Invalid flag
[03:44:17] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[03:44:17] [PASSED] ABGR8888 Valid buffer modifier
[03:44:17] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[03:44:17] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] NV12 Normal sizes
[03:44:17] [PASSED] NV12 Max sizes
[03:44:17] [PASSED] NV12 Invalid pitch
[03:44:17] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[03:44:17] [PASSED] NV12 different modifier per-plane
[03:44:17] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[03:44:17] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] NV12 Modifier for inexistent plane
[03:44:17] [PASSED] NV12 Handle for inexistent plane
[03:44:17] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[03:44:17] [PASSED] YVU420 Normal sizes
[03:44:17] [PASSED] YVU420 Max sizes
[03:44:17] [PASSED] YVU420 Invalid pitch
[03:44:17] [PASSED] YVU420 Different pitches
[03:44:17] [PASSED] YVU420 Different buffer offsets/pitches
[03:44:17] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[03:44:17] [PASSED] YVU420 Valid modifier
[03:44:17] [PASSED] YVU420 Different modifiers per plane
[03:44:17] [PASSED] YVU420 Modifier for inexistent plane
[03:44:17] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[03:44:17] [PASSED] X0L2 Normal sizes
[03:44:17] [PASSED] X0L2 Max sizes
[03:44:17] [PASSED] X0L2 Invalid pitch
[03:44:17] [PASSED] X0L2 Pitch greater than minimum required
[03:44:17] [PASSED] X0L2 Handle for inexistent plane
[03:44:17] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[03:44:17] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[03:44:17] [PASSED] X0L2 Valid modifier
[03:44:17] [PASSED] X0L2 Modifier for inexistent plane
[03:44:17] =========== [PASSED] drm_test_framebuffer_create ===========
[03:44:17] [PASSED] drm_test_framebuffer_free
[03:44:17] [PASSED] drm_test_framebuffer_init
[03:44:17] [PASSED] drm_test_framebuffer_init_bad_format
[03:44:17] [PASSED] drm_test_framebuffer_init_dev_mismatch
[03:44:17] [PASSED] drm_test_framebuffer_lookup
[03:44:17] [PASSED] drm_test_framebuffer_lookup_inexistent
[03:44:17] [PASSED] drm_test_framebuffer_modifiers_not_supported
[03:44:17] ================= [PASSED] drm_framebuffer =================
[03:44:17] ================ drm_gem_shmem (8 subtests) ================
[03:44:17] [PASSED] drm_gem_shmem_test_obj_create
[03:44:17] [PASSED] drm_gem_shmem_test_obj_create_private
[03:44:17] [PASSED] drm_gem_shmem_test_pin_pages
[03:44:17] [PASSED] drm_gem_shmem_test_vmap
[03:44:17] [PASSED] drm_gem_shmem_test_get_sg_table
[03:44:17] [PASSED] drm_gem_shmem_test_get_pages_sgt
[03:44:17] [PASSED] drm_gem_shmem_test_madvise
[03:44:17] [PASSED] drm_gem_shmem_test_purge
[03:44:17] ================== [PASSED] drm_gem_shmem ==================
[03:44:17] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[03:44:17] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[03:44:17] [PASSED] Automatic
[03:44:17] [PASSED] Full
[03:44:17] [PASSED] Limited 16:235
[03:44:17] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[03:44:17] [PASSED] drm_test_check_disable_connector
[03:44:17] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[03:44:17] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[03:44:17] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[03:44:17] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[03:44:17] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[03:44:17] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[03:44:17] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[03:44:17] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[03:44:17] [PASSED] drm_test_check_output_bpc_dvi
[03:44:17] [PASSED] drm_test_check_output_bpc_format_vic_1
[03:44:17] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[03:44:17] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[03:44:17] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[03:44:17] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[03:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[03:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[03:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[03:44:17] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[03:44:17] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[03:44:17] [PASSED] drm_test_check_broadcast_rgb_value
[03:44:17] [PASSED] drm_test_check_bpc_8_value
[03:44:17] [PASSED] drm_test_check_bpc_10_value
[03:44:17] [PASSED] drm_test_check_bpc_12_value
[03:44:17] [PASSED] drm_test_check_format_value
[03:44:17] [PASSED] drm_test_check_tmds_char_value
[03:44:17] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[03:44:17] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[03:44:17] [PASSED] drm_test_check_mode_valid
[03:44:17] [PASSED] drm_test_check_mode_valid_reject
[03:44:17] [PASSED] drm_test_check_mode_valid_reject_rate
[03:44:17] [PASSED] drm_test_check_mode_valid_reject_max_clock
[03:44:17] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[03:44:17] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[03:44:17] [PASSED] drm_test_check_infoframes
[03:44:17] [PASSED] drm_test_check_reject_avi_infoframe
[03:44:17] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[03:44:17] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[03:44:17] [PASSED] drm_test_check_reject_audio_infoframe
[03:44:17] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[03:44:17] ================= drm_managed (2 subtests) =================
[03:44:17] [PASSED] drm_test_managed_release_action
[03:44:17] [PASSED] drm_test_managed_run_action
[03:44:17] =================== [PASSED] drm_managed ===================
[03:44:17] =================== drm_mm (6 subtests) ====================
[03:44:17] [PASSED] drm_test_mm_init
[03:44:17] [PASSED] drm_test_mm_debug
[03:44:17] [PASSED] drm_test_mm_align32
[03:44:17] [PASSED] drm_test_mm_align64
[03:44:17] [PASSED] drm_test_mm_lowest
[03:44:17] [PASSED] drm_test_mm_highest
[03:44:17] ===================== [PASSED] drm_mm ======================
[03:44:17] ============= drm_modes_analog_tv (5 subtests) =============
[03:44:17] [PASSED] drm_test_modes_analog_tv_mono_576i
[03:44:17] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[03:44:17] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[03:44:17] [PASSED] drm_test_modes_analog_tv_pal_576i
[03:44:17] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[03:44:17] =============== [PASSED] drm_modes_analog_tv ===============
[03:44:17] ============== drm_plane_helper (2 subtests) ===============
[03:44:17] =============== drm_test_check_plane_state ================
[03:44:17] [PASSED] clipping_simple
[03:44:17] [PASSED] clipping_rotate_reflect
[03:44:17] [PASSED] positioning_simple
[03:44:17] [PASSED] upscaling
[03:44:17] [PASSED] downscaling
[03:44:17] [PASSED] rounding1
[03:44:17] [PASSED] rounding2
[03:44:17] [PASSED] rounding3
[03:44:17] [PASSED] rounding4
[03:44:17] =========== [PASSED] drm_test_check_plane_state ============
[03:44:17] =========== drm_test_check_invalid_plane_state ============
[03:44:17] [PASSED] positioning_invalid
[03:44:17] [PASSED] upscaling_invalid
[03:44:17] [PASSED] downscaling_invalid
[03:44:17] ======= [PASSED] drm_test_check_invalid_plane_state ========
[03:44:17] ================ [PASSED] drm_plane_helper =================
[03:44:17] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[03:44:17] ====== drm_test_connector_helper_tv_get_modes_check =======
[03:44:17] [PASSED] None
[03:44:17] [PASSED] PAL
[03:44:17] [PASSED] NTSC
[03:44:17] [PASSED] Both, NTSC Default
[03:44:17] [PASSED] Both, PAL Default
[03:44:17] [PASSED] Both, NTSC Default, with PAL on command-line
[03:44:17] [PASSED] Both, PAL Default, with NTSC on command-line
[03:44:17] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[03:44:17] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[03:44:17] ================== drm_rect (9 subtests) ===================
[03:44:17] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[03:44:17] [PASSED] drm_test_rect_clip_scaled_not_clipped
[03:44:17] [PASSED] drm_test_rect_clip_scaled_clipped
[03:44:17] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[03:44:17] ================= drm_test_rect_intersect =================
[03:44:17] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[03:44:17] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[03:44:17] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[03:44:17] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[03:44:17] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[03:44:17] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[03:44:17] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[03:44:17] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[03:44:17] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[03:44:17] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[03:44:17] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[03:44:17] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[03:44:17] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[03:44:17] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[03:44:17] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[03:44:17] ============= [PASSED] drm_test_rect_intersect =============
[03:44:17] ================ drm_test_rect_calc_hscale ================
[03:44:17] [PASSED] normal use
[03:44:17] [PASSED] out of max range
[03:44:17] [PASSED] out of min range
[03:44:17] [PASSED] zero dst
[03:44:17] [PASSED] negative src
[03:44:17] [PASSED] negative dst
[03:44:17] ============ [PASSED] drm_test_rect_calc_hscale ============
[03:44:17] ================ drm_test_rect_calc_vscale ================
[03:44:17] [PASSED] normal use
[03:44:17] [PASSED] out of max range
[03:44:17] [PASSED] out of min range
[03:44:17] [PASSED] zero dst
[03:44:17] [PASSED] negative src
[03:44:17] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[03:44:17] ============ [PASSED] drm_test_rect_calc_vscale ============
[03:44:17] ================== drm_test_rect_rotate ===================
[03:44:17] [PASSED] reflect-x
[03:44:17] [PASSED] reflect-y
[03:44:17] [PASSED] rotate-0
[03:44:17] [PASSED] rotate-90
[03:44:17] [PASSED] rotate-180
[03:44:17] [PASSED] rotate-270
[03:44:17] ============== [PASSED] drm_test_rect_rotate ===============
[03:44:17] ================ drm_test_rect_rotate_inv =================
[03:44:17] [PASSED] reflect-x
[03:44:17] [PASSED] reflect-y
[03:44:17] [PASSED] rotate-0
[03:44:17] [PASSED] rotate-90
[03:44:17] [PASSED] rotate-180
[03:44:17] [PASSED] rotate-270
[03:44:17] ============ [PASSED] drm_test_rect_rotate_inv =============
[03:44:17] ==================== [PASSED] drm_rect =====================
[03:44:17] ============ drm_sysfb_modeset_test (1 subtest) ============
[03:44:17] ============ drm_test_sysfb_build_fourcc_list =============
[03:44:17] [PASSED] no native formats
[03:44:17] [PASSED] XRGB8888 as native format
[03:44:17] [PASSED] remove duplicates
[03:44:17] [PASSED] convert alpha formats
[03:44:17] [PASSED] random formats
[03:44:17] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[03:44:17] ============= [PASSED] drm_sysfb_modeset_test ==============
[03:44:17] ================== drm_fixp (2 subtests) ===================
[03:44:17] [PASSED] drm_test_int2fixp
[03:44:17] [PASSED] drm_test_sm2fixp
[03:44:17] ==================== [PASSED] drm_fixp =====================
[03:44:17] ============================================================
[03:44:17] Testing complete. Ran 621 tests: passed: 621
[03:44:17] Elapsed time: 30.809s total, 1.682s configuring, 28.910s building, 0.177s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[03:44:17] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:44:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[03:44:28] Starting KUnit Kernel (1/1)...
[03:44:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:44:28] ================= ttm_device (5 subtests) ==================
[03:44:28] [PASSED] ttm_device_init_basic
[03:44:28] [PASSED] ttm_device_init_multiple
[03:44:28] [PASSED] ttm_device_fini_basic
[03:44:28] [PASSED] ttm_device_init_no_vma_man
[03:44:28] ================== ttm_device_init_pools ==================
[03:44:28] [PASSED] No DMA allocations, no DMA32 required
[03:44:28] [PASSED] DMA allocations, DMA32 required
[03:44:28] [PASSED] No DMA allocations, DMA32 required
[03:44:28] [PASSED] DMA allocations, no DMA32 required
[03:44:28] ============== [PASSED] ttm_device_init_pools ==============
[03:44:28] =================== [PASSED] ttm_device ====================
[03:44:28] ================== ttm_pool (8 subtests) ===================
[03:44:28] ================== ttm_pool_alloc_basic ===================
[03:44:28] [PASSED] One page
[03:44:28] [PASSED] More than one page
[03:44:28] [PASSED] Above the allocation limit
[03:44:28] [PASSED] One page, with coherent DMA mappings enabled
[03:44:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:44:28] ============== [PASSED] ttm_pool_alloc_basic ===============
[03:44:28] ============== ttm_pool_alloc_basic_dma_addr ==============
[03:44:28] [PASSED] One page
[03:44:28] [PASSED] More than one page
[03:44:28] [PASSED] Above the allocation limit
[03:44:28] [PASSED] One page, with coherent DMA mappings enabled
[03:44:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:44:28] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[03:44:28] [PASSED] ttm_pool_alloc_order_caching_match
[03:44:28] [PASSED] ttm_pool_alloc_caching_mismatch
[03:44:28] [PASSED] ttm_pool_alloc_order_mismatch
[03:44:28] [PASSED] ttm_pool_free_dma_alloc
[03:44:28] [PASSED] ttm_pool_free_no_dma_alloc
[03:44:28] [PASSED] ttm_pool_fini_basic
[03:44:28] ==================== [PASSED] ttm_pool =====================
[03:44:28] ================ ttm_resource (8 subtests) =================
[03:44:28] ================= ttm_resource_init_basic =================
[03:44:28] [PASSED] Init resource in TTM_PL_SYSTEM
[03:44:28] [PASSED] Init resource in TTM_PL_VRAM
[03:44:28] [PASSED] Init resource in a private placement
[03:44:28] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[03:44:28] ============= [PASSED] ttm_resource_init_basic =============
[03:44:28] [PASSED] ttm_resource_init_pinned
[03:44:28] [PASSED] ttm_resource_fini_basic
[03:44:28] [PASSED] ttm_resource_manager_init_basic
[03:44:28] [PASSED] ttm_resource_manager_usage_basic
[03:44:28] [PASSED] ttm_resource_manager_set_used_basic
[03:44:28] [PASSED] ttm_sys_man_alloc_basic
[03:44:28] [PASSED] ttm_sys_man_free_basic
[03:44:28] ================== [PASSED] ttm_resource ===================
[03:44:28] =================== ttm_tt (15 subtests) ===================
[03:44:28] ==================== ttm_tt_init_basic ====================
[03:44:28] [PASSED] Page-aligned size
[03:44:28] [PASSED] Extra pages requested
[03:44:28] ================ [PASSED] ttm_tt_init_basic ================
[03:44:28] [PASSED] ttm_tt_init_misaligned
[03:44:28] [PASSED] ttm_tt_fini_basic
[03:44:28] [PASSED] ttm_tt_fini_sg
[03:44:28] [PASSED] ttm_tt_fini_shmem
[03:44:28] [PASSED] ttm_tt_create_basic
[03:44:28] [PASSED] ttm_tt_create_invalid_bo_type
[03:44:28] [PASSED] ttm_tt_create_ttm_exists
[03:44:28] [PASSED] ttm_tt_create_failed
[03:44:28] [PASSED] ttm_tt_destroy_basic
[03:44:28] [PASSED] ttm_tt_populate_null_ttm
[03:44:28] [PASSED] ttm_tt_populate_populated_ttm
[03:44:28] [PASSED] ttm_tt_unpopulate_basic
[03:44:28] [PASSED] ttm_tt_unpopulate_empty_ttm
[03:44:28] [PASSED] ttm_tt_swapin_basic
[03:44:28] ===================== [PASSED] ttm_tt ======================
[03:44:28] =================== ttm_bo (14 subtests) ===================
[03:44:28] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[03:44:28] [PASSED] Cannot be interrupted and sleeps
[03:44:28] [PASSED] Cannot be interrupted, locks straight away
[03:44:28] [PASSED] Can be interrupted, sleeps
[03:44:28] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[03:44:28] [PASSED] ttm_bo_reserve_locked_no_sleep
[03:44:28] [PASSED] ttm_bo_reserve_no_wait_ticket
[03:44:28] [PASSED] ttm_bo_reserve_double_resv
[03:44:28] [PASSED] ttm_bo_reserve_interrupted
[03:44:28] [PASSED] ttm_bo_reserve_deadlock
[03:44:28] [PASSED] ttm_bo_unreserve_basic
[03:44:28] [PASSED] ttm_bo_unreserve_pinned
[03:44:28] [PASSED] ttm_bo_unreserve_bulk
[03:44:28] [PASSED] ttm_bo_fini_basic
[03:44:28] [PASSED] ttm_bo_fini_shared_resv
[03:44:28] [PASSED] ttm_bo_pin_basic
[03:44:28] [PASSED] ttm_bo_pin_unpin_resource
[03:44:28] [PASSED] ttm_bo_multiple_pin_one_unpin
[03:44:28] ===================== [PASSED] ttm_bo ======================
[03:44:28] ============== ttm_bo_validate (21 subtests) ===============
[03:44:28] ============== ttm_bo_init_reserved_sys_man ===============
[03:44:28] [PASSED] Buffer object for userspace
[03:44:28] [PASSED] Kernel buffer object
[03:44:28] [PASSED] Shared buffer object
[03:44:28] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[03:44:28] ============== ttm_bo_init_reserved_mock_man ==============
[03:44:28] [PASSED] Buffer object for userspace
[03:44:28] [PASSED] Kernel buffer object
[03:44:28] [PASSED] Shared buffer object
[03:44:28] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[03:44:28] [PASSED] ttm_bo_init_reserved_resv
[03:44:28] ================== ttm_bo_validate_basic ==================
[03:44:28] [PASSED] Buffer object for userspace
[03:44:28] [PASSED] Kernel buffer object
[03:44:28] [PASSED] Shared buffer object
[03:44:28] ============== [PASSED] ttm_bo_validate_basic ==============
[03:44:28] [PASSED] ttm_bo_validate_invalid_placement
[03:44:28] ============= ttm_bo_validate_same_placement ==============
[03:44:28] [PASSED] System manager
[03:44:28] [PASSED] VRAM manager
[03:44:28] ========= [PASSED] ttm_bo_validate_same_placement ==========
[03:44:28] [PASSED] ttm_bo_validate_failed_alloc
[03:44:28] [PASSED] ttm_bo_validate_pinned
[03:44:28] [PASSED] ttm_bo_validate_busy_placement
[03:44:28] ================ ttm_bo_validate_multihop =================
[03:44:28] [PASSED] Buffer object for userspace
[03:44:28] [PASSED] Kernel buffer object
[03:44:28] [PASSED] Shared buffer object
[03:44:28] ============ [PASSED] ttm_bo_validate_multihop =============
[03:44:28] ========== ttm_bo_validate_no_placement_signaled ==========
[03:44:28] [PASSED] Buffer object in system domain, no page vector
[03:44:28] [PASSED] Buffer object in system domain with an existing page vector
[03:44:28] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[03:44:28] ======== ttm_bo_validate_no_placement_not_signaled ========
[03:44:28] [PASSED] Buffer object for userspace
[03:44:28] [PASSED] Kernel buffer object
[03:44:28] [PASSED] Shared buffer object
[03:44:28] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[03:44:28] [PASSED] ttm_bo_validate_move_fence_signaled
[03:44:28] ========= ttm_bo_validate_move_fence_not_signaled =========
[03:44:28] [PASSED] Waits for GPU
[03:44:28] [PASSED] Tries to lock straight away
[03:44:28] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[03:44:28] [PASSED] ttm_bo_validate_happy_evict
[03:44:28] [PASSED] ttm_bo_validate_all_pinned_evict
[03:44:28] [PASSED] ttm_bo_validate_allowed_only_evict
[03:44:28] [PASSED] ttm_bo_validate_deleted_evict
[03:44:28] [PASSED] ttm_bo_validate_busy_domain_evict
[03:44:28] [PASSED] ttm_bo_validate_evict_gutting
[03:44:28] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[03:44:28] ================= [PASSED] ttm_bo_validate =================
[03:44:28] ============================================================
[03:44:28] Testing complete. Ran 101 tests: passed: 101
[03:44:29] Elapsed time: 11.183s total, 1.657s configuring, 9.260s building, 0.236s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* ✗ Xe.CI.BAT: failure for DP: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (6 preceding siblings ...)
2026-03-06 3:44 ` ✓ CI.KUnit: success " Patchwork
@ 2026-03-06 4:33 ` Patchwork
2026-03-07 1:55 ` ✗ Xe.CI.FULL: " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-06 4:33 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2945 bytes --]
== Series Details ==
Series: DP: Read LTTPR caps followed by DPRX caps
URL : https://patchwork.freedesktop.org/series/162641/
State : failure
== Summary ==
CI Bug Log - changes from xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2_BAT -> xe-pw-162641v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-162641v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-162641v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-162641v1_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_module_load@load:
- bat-dg2-oem2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/bat-dg2-oem2/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/bat-dg2-oem2/igt@xe_module_load@load.html
- bat-wcl-1: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/bat-wcl-1/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/bat-wcl-1/igt@xe_module_load@load.html
- bat-lnl-1: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/bat-lnl-1/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/bat-lnl-1/igt@xe_module_load@load.html
- bat-adlp-7: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/bat-adlp-7/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/bat-adlp-7/igt@xe_module_load@load.html
- bat-ptl-2: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/bat-ptl-2/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/bat-ptl-2/igt@xe_module_load@load.html
Build changes
-------------
* Linux: xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2 -> xe-pw-162641v1
IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2: ce63d46cc8fc3bb754efb93026b55acaa616cfa2
xe-pw-162641v1: 162641v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/index.html
[-- Attachment #2: Type: text/html, Size: 3560 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* ✗ Xe.CI.FULL: failure for DP: Read LTTPR caps followed by DPRX caps
2026-03-05 8:18 [PATCH RFC 0/4] DP: Read LTTPR caps followed by DPRX caps Arun R Murthy
` (7 preceding siblings ...)
2026-03-06 4:33 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-03-07 1:55 ` Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-07 1:55 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 15641 bytes --]
== Series Details ==
Series: DP: Read LTTPR caps followed by DPRX caps
URL : https://patchwork.freedesktop.org/series/162641/
State : failure
== Summary ==
CI Bug Log - changes from xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2_FULL -> xe-pw-162641v1_FULL
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with xe-pw-162641v1_FULL need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-162641v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-162641v1_FULL:
### IGT changes ###
#### Warnings ####
* igt@xe_module_load@load:
- shard-lnl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [SKIP][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([Intel XE#378] / [Intel XE#7405]) -> ([DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-7/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-5/igt@xe_module_load@load.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-5/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-5/igt@xe_module_load@load.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-4/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-7/igt@xe_module_load@load.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-2/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-2/igt@xe_module_load@load.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-4/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-3/igt@xe_module_load@load.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-6/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-6/igt@xe_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-6/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-1/igt@xe_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-1/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-8/igt@xe_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-8/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-8/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-4/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-4/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-8/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-3/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-2/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-1/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-3/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-lnl-7/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-1/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-1/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-1/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-1/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-8/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-8/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-8/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-4/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-4/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-4/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-6/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-6/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-6/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-3/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-3/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-3/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-2/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-2/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-2/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-7/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-7/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-7/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-5/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-5/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-lnl-5/igt@xe_module_load@load.html
- shard-bmg: ([PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [SKIP][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) ([Intel XE#2457] / [Intel XE#7405]) -> ([ABORT][78], [ABORT][79], [ABORT][80], [ABORT][81], [ABORT][82], [ABORT][83], [ABORT][84], [ABORT][85], [ABORT][86], [ABORT][87], [ABORT][88], [ABORT][89], [ABORT][90], [ABORT][91], [ABORT][92], [ABORT][93], [ABORT][94], [ABORT][95], [ABORT][96], [ABORT][97], [ABORT][98], [ABORT][99], [ABORT][100])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-7/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-7/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-6/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-8/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-5/igt@xe_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-5/igt@xe_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-5/igt@xe_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-7/igt@xe_module_load@load.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-3/igt@xe_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-1/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-1/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-1/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-8/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-6/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-3/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-9/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-3/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-6/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-4/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-4/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-9/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-10/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-10/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-2/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-2/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2/shard-bmg-4/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-4/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-4/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-8/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-8/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-8/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-10/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-10/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-1/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-1/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-7/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-7/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-9/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-9/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-9/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-2/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-2/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-2/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-6/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-6/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-3/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-3/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-5/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/shard-bmg-5/igt@xe_module_load@load.html
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
Build changes
-------------
* Linux: xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2 -> xe-pw-162641v1
IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4670-ce63d46cc8fc3bb754efb93026b55acaa616cfa2: ce63d46cc8fc3bb754efb93026b55acaa616cfa2
xe-pw-162641v1: 162641v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162641v1/index.html
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