Re: [PATCH v9 01/22] arm64: cpufeature: Add cpucap for HPMN0

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: cpufeature: Missing AArch32 ID_DFR1_EL1_HPMN0 in ftr_id_dfr1 array
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commit 5ba8cce217bacafa8dc1ca20dcd2a95acd9bf835
Author: Colton Lewis <coltonlewis@google.com>

arm64: cpufeature: Add cpucap for HPMN0

This commit adds a CPU capability for FEAT_HPMN0, allowing MDCR_EL2.HPMN to
specify 0 counters reserved for the guest. It updates the tools/sysreg
definition to UnsignedEnum and adds the corresponding feature tracking.

> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 32102c3912fa7..f8431cf858619 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
[ ... ]
> @@ -564,6 +564,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
>  };
>  
>  static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0),

[Severity: Medium]
Does this also require updating the AArch32 counterpart register ID_DFR1_EL1
in the ftr_id_dfr1 array?

By adding ID_AA64DFR0_EL1_HPMN0 as FTR_NONSTRICT here but omitting the field
mapping from ftr_id_dfr1, the AArch32 view remains implicitly STRICT. On a
system with asymmetric HPMN0 support across CPUs, when a secondary CPU
boots and executes update_32bit_cpu_features(), it triggers
check_update_ftr_reg(SYS_ID_DFR1_EL1). 

This could cause the boot sanity checks to unexpectedly fail and taint the
kernel due to the STRICT default conflicting with this NONSTRICT definition.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260924172928.2110956-1-coltonlewis@google.com?part=1