Re: [PATCH v9 18/22] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters

[sashiko-bot@kernel.org]

> Because ARM hardware is not yet capable of direct PPI injection into
> guests, guest counters trigger physical PMU interrupts that must be
> handled by the host PMU interrupt handler.
> 
> In armv8pmu_handle_irq(), clear the overflow flags in hardware for host
> counters, restrict host perf event handling to bits in cpuc->cntr_mask,
> and pass the overflow flags to kvm_pmu_handle_guest_irq(). The KVM hook
> clears the guest counter overflow flags in hardware and records them in
> the running vCPU's virtual PMOVSSET_EL0 register for subsequent guest
> interrupt injection.
> 
> Additionally, provide kvm_pmu_host_start() and kvm_pmu_host_stop() so
> that armv8pmu_start() and armv8pmu_stop() toggle MDCR_EL2.HPME rather
> than PMCR_EL0.E when a partitioned guest's PMU state is loaded on the
> CPU.
> 
> Signed-off-by: Colton Lewis <coltonlewis@google.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260924172928.2110956-1-coltonlewis@google.com?part=18