From: Marc Zyngier <maz@kernel.org>
To: "Sascha Bischoff"
<Sascha.Bischoff@arm.com>,sashiko-reviews@lists.linux.dev
Cc: "Oliver Upton" <oupton@kernel.org>,
kvm@vger.kernel.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts
Date: Sat, 25 Jul 2026 11:08:03 +0100 [thread overview]
Message-ID: <8733x7qt4s.wl-maz@kernel.org> (raw)
In-Reply-To: <20260724111920.6F63C1F00A3F@smtp.kernel.org>
On Fri, 24 Jul 2026 12:19:20 +0100,
sashiko-bot@kernel.org wrote:
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Failed ACPI GSI registration for maintenance IRQ due to missing GICv5 hardware IRQ type encoding.
> --
[...]
> [Severity: High]
> Does this fail to register the maintenance IRQ?
>
> acpi_register_gsi() passes the raw maint_irq directly into fwspec.param[0].
> However, the GICv5 PPI domain select function expects the hardware IRQ type to
> be encoded in the upper bits:
>
> drivers/irqchip/irq-gic-v5.c:gicv5_irq_ppi_domain_select() {
> ...
> if (is_fwnode_irqchip(fwspec->fwnode))
> hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]);
>
> if (hwirq_type != GICV5_HWIRQ_TYPE_PPI)
> return 0;
> ...
> }
>
> Because the raw MADT value doesn't have the GICV5_HWIRQ_TYPE_PPI bits set, the
> mapping will be rejected. Should the GSI be encoded with the PPI type before
> calling acpi_register_gsi()?
Where is this coming from? I can't even find any public documentation
for ACPI GICv5 support...
Sascha?
M.
--
Jazz isn't dead. It just smells funny.
next prev parent reply other threads:[~2026-07-25 10:06 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10 ` sashiko-bot
2026-07-25 9:06 ` Marc Zyngier
2026-07-25 9:18 ` Marc Zyngier
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-25 10:08 ` Marc Zyngier [this message]
2026-07-25 9:35 ` Marc Zyngier
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14 ` sashiko-bot
2026-07-25 10:10 ` Marc Zyngier
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-25 10:40 ` Marc Zyngier
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11 ` sashiko-bot
2026-07-25 10:56 ` Marc Zyngier
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22 ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20 ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30 ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45 ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33 ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
[not found] ` <20260724104819.1296803-35-sascha.bischoff@arm.com>
2026-07-24 11:46 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI sashiko-bot
[not found] ` <20260724104819.1296803-31-sascha.bischoff@arm.com>
2026-07-24 11:52 ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() sashiko-bot
[not found] ` <20260724104819.1296803-36-sascha.bischoff@arm.com>
2026-07-24 12:02 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs sashiko-bot
[not found] ` <20260724104819.1296803-42-sascha.bischoff@arm.com>
2026-07-24 12:02 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS attribute tests sashiko-bot
[not found] ` <20260724104819.1296803-33-sascha.bischoff@arm.com>
2026-07-24 12:05 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region sashiko-bot
[not found] ` <20260724104819.1296803-43-sascha.bischoff@arm.com>
2026-07-24 12:06 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS attribute tests sashiko-bot
[not found] ` <20260724104819.1296803-32-sascha.bischoff@arm.com>
2026-07-24 12:09 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors sashiko-bot
[not found] ` <20260724104819.1296803-47-sascha.bischoff@arm.com>
2026-07-24 12:15 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests sashiko-bot
[not found] ` <20260724104819.1296803-48-sascha.bischoff@arm.com>
2026-07-24 12:18 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests sashiko-bot
[not found] ` <20260724104819.1296803-38-sascha.bischoff@arm.com>
2026-07-24 12:19 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs sashiko-bot
[not found] ` <20260724104819.1296803-30-sascha.bischoff@arm.com>
2026-07-24 12:19 ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd sashiko-bot
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