Re: [PATCH 23/38] arm64: cpufeature: Detect PE support for FEAT_NMI

[Vladimir Murzin <vladimir.murzin@arm.com>]

On 9/16/26 10:22, Jinjie Ruan wrote:
> 
> 在 2026/9/14 18:20, Vladimir Murzin 写道:
>> From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>>
>> Use of FEAT_NMI requires that all the PEs in the system and the GIC
>> have NMI support. This patch implements the PE part of that detection.
>>
>> In order to avoid problematic interactions between real and pseudo NMIs
>> we disable the architected feature if the user has enabled pseudo NMIs
>> on the command line. If this is done on a system where support for the
>> architected feature is detected then a warning is printed during boot in
>> order to help users spot what is likely to be a misconfiguration.
>>
>> As KVM does not care about the host kernel supporting FEAT_NMI or not
>> to allow guests to use it, split the CPU cap in two : ARM64_HAS_NMI is
>> the hardware support, ARM64_NMI is the kernel making use of it.
>>
>> Co-developed-by: Mark Brown <broonie@kernel.org>
>> Signed-off-by: Mark Brown <broonie@kernel.org>
>> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>> Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>
>> ---
>>  arch/arm64/include/asm/cpucaps.h    |  2 +
>>  arch/arm64/include/asm/cpufeature.h | 10 +++++
>>  arch/arm64/kernel/cpufeature.c      | 68 ++++++++++++++++++++++++++++-
>>  arch/arm64/tools/cpucaps            |  2 +
>>  4 files changed, 81 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
>> index 76350b38f0d7..1a4ef4e94997 100644
>> --- a/arch/arm64/include/asm/cpucaps.h
>> +++ b/arch/arm64/include/asm/cpucaps.h
>> @@ -75,6 +75,8 @@ cpucap_is_possible(const unsigned int cap)
>>  		return IS_ENABLED(CONFIG_HW_PERF_EVENTS);
>>  	case ARM64_HAS_LSUI:
>>  		return IS_ENABLED(CONFIG_ARM64_LSUI);
>> +	case ARM64_NMI:
>> +		return IS_ENABLED(CONFIG_ARM64_NMI);
>>  	}
>>  
>>  	return true;
>> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
>> index 09aa80df602a..c8b1bacdd161 100644
>> --- a/arch/arm64/include/asm/cpufeature.h
>> +++ b/arch/arm64/include/asm/cpufeature.h
>> @@ -809,6 +809,16 @@ static __always_inline bool system_uses_irq_prio_masking(void)
>>  	return alternative_has_cap_unlikely(ARM64_HAS_GIC_PRIO_MASKING);
>>  }
>>  
>> +static __always_inline bool system_supports_nmi(void)
>> +{
>> +	return alternative_has_cap_unlikely(ARM64_HAS_NMI);
>> +}
>> +
>> +static __always_inline bool system_uses_nmi(void)
>> +{
>> +	return alternative_has_cap_unlikely(ARM64_NMI);
>> +}
>> +
>>  static inline bool system_supports_mte(void)
>>  {
>>  	return alternative_has_cap_unlikely(ARM64_MTE);
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 32102c3912fa..f9fe7a875f85 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -83,13 +83,14 @@
>>  #include <asm/cpu_ops.h>
>>  #include <asm/fpsimd.h>
>>  #include <asm/hwcap.h>
>> +#include <asm/hypervisor.h>
>>  #include <asm/insn.h>
>> +#include <asm/interrupts/common_flags.h>
>>  #include <asm/kvm_host.h>
>>  #include <asm/mmu.h>
>>  #include <asm/mmu_context.h>
>>  #include <asm/mpam.h>
>>  #include <asm/mte.h>
>> -#include <asm/hypervisor.h>
>>  #include <asm/processor.h>
>>  #include <asm/smp.h>
>>  #include <asm/sysreg.h>
>> @@ -315,6 +316,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
>>  	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS),
>>  		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0),
>>  	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_NMI_SHIFT, 4, 0),
>>  	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
>>  		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
>>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
>> @@ -2341,6 +2343,51 @@ static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry
>>  }
>>  #endif
>>  
>> +#ifdef CONFIG_ARM64_NMI
>> +static bool can_use_nmi(const struct arm64_cpu_capabilities *entry, int scope)
>> +{
>> +	/*
>> +	 * ARM64_HAS_NMI has a lower index, and is a boot CPU
>> +	 * feature, so will be detected earlier.
>> +	 */
>> +	BUILD_BUG_ON(ARM64_NMI <= ARM64_HAS_NMI);
>> +	if (!cpus_have_cap(ARM64_HAS_NMI))
>> +		return false;
>> +
>> +	/*
>> +	 * Having both real and pseudo NMIs enabled simultaneously is
>> +	 * likely to cause confusion.  Since pseudo NMIs must be
>> +	 * enabled with an explicit command line option, if the user
>> +	 * has set that option on a system with real NMIs for some
>> +	 * reason assume they know what they're doing.
>> +	 *
>> +	 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
>> +	 * feature, so will be detected earlier.
>> +	 */
>> +	BUILD_BUG_ON(IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
>> +			(ARM64_NMI <= ARM64_HAS_GIC_PRIO_MASKING));
>> +	if (cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) {
>> +		pr_info_once("Pseudo NMI enabled, not using architected NMI\n");
>> +		return false;
> Hi, Vladimir,
> 
> The user's actual requirement may be to use FEAT_NMI by default when it
> is available, and fall back to pseudo-NMI otherwise, since pseudo-NMI
> has inherent noise and is only a second choice when there is no hardware
> support. Can we design it this way?
> 

Hi Jinjie,

Hmm, currently users have to explicitly opt in to pseudo-NMI (enable
the config option and pass irqchip.gicv3_pseudo_nmi=1 on the command
line), and those users would continue to use pseudo-NMI even if
FEAT_NMI is available.

What you are asking is to prefer FEAT_NMI over pseudo-NMI when it is
available, effectively turning the explicit opt-in to pseudo-NMI into
a hint rather than a strict request, correct?

Cheers
Vladimir

> Best regards,
> Jinjie
> 
>> +	}
>> +
>> +	return true;
>> +}
>> +
>> +static void nmi_enable(const struct arm64_cpu_capabilities *__unused)
>> +{
>> +	/*
>> +	 * Enable use of NMIs controlled by ALLINT, SPINTMASK should
>> +	 * be clear by default but make it explicit that we are using
>> +	 * this mode.  Ensure that ALLINT is clear first in order to
>> +	 * avoid leaving things masked.
>> +	 */
>> +	_allint_clear();
>> +	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPINTMASK, SCTLR_EL1_NMI);
>> +	isb();
>> +}
>> +#endif
>> +
>>  static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry,
>>  				 int scope)
>>  {
>> @@ -3233,6 +3280,25 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>>  		.matches = has_cpuid_feature,
>>  		ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP)
>>  	},
>> +#endif
>> +	{
>> +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
>> +		.capability = ARM64_HAS_NMI,
>> +		.matches = has_cpuid_feature,
>> +		ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, NMI, IMP)
>> +	},
>> +#ifdef CONFIG_ARM64_NMI
>> +	/*
>> +	 * Depends on ARM64_HAS_NMI
>> +	 * Checks for conflict with pseudo-NMIs, giving them priority.
>> +	 */
>> +	{
>> +		.desc = "Non-maskable Interrupts",
>> +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
>> +		.capability = ARM64_NMI,
>> +		.matches = can_use_nmi,
>> +		.cpu_enable = nmi_enable,
>> +	},
>>  #endif
>>  	{},
>>  };
>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
>> index 2775ba3359cf..531583822ec2 100644
>> --- a/arch/arm64/tools/cpucaps
>> +++ b/arch/arm64/tools/cpucaps
>> @@ -52,6 +52,7 @@ HAS_LS64_V
>>  HAS_LSUI
>>  HAS_MOPS
>>  HAS_NESTED_VIRT
>> +HAS_NMI
>>  HAS_NV2P1
>>  HAS_NV3
>>  HAS_PAN
>> @@ -82,6 +83,7 @@ MTE
>>  MTE_ASYMM
>>  MTE_FAR
>>  MTE_STORE_ONLY
>> +NMI
>>  SME
>>  SME_FA64
>>  SME2
>