* [PATCH 0/2] MediaTek MT6735 syscon clock/reset controller support
@ 2024-10-21 12:16 Yassine Oudjana
2024-10-21 12:16 ` [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Yassine Oudjana
2024-10-21 12:16 ` [PATCH 2/2] clk: mediatek: Add drivers " Yassine Oudjana
0 siblings, 2 replies; 8+ messages in thread
From: Yassine Oudjana @ 2024-10-21 12:16 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih
Cc: Yassine Oudjana, Yassine Oudjana, linux-clk, devicetree,
linux-kernel, linux-mediatek, linux-arm-kernel
From: Yassine Oudjana <y.oudjana@protonmail.com>
These patches are part of a larger effort to support the MT6735 SoC family
in mainline Linux. More patches can found here[1].
This series adds support for clocks and resets of the following blocks:
- IMGSYS (Camera)
- MFGCFG (GPU)
- VDECSYS (Video decoder)
- VENCSYS (Video encoder, also has JPEG codec clocks)
[1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging
Yassine Oudjana (2):
dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and
reset controllers
clk: mediatek: Add drivers for MT6735 syscon clock and reset
controllers
.../bindings/clock/mediatek,syscon.yaml | 4 +
MAINTAINERS | 10 +++
drivers/clk/mediatek/Kconfig | 32 ++++++++
drivers/clk/mediatek/Makefile | 4 +
drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 +++++++++++++
drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 ++++++++++++++
drivers/clk/mediatek/clk-mt6735-vdecsys.c | 81 +++++++++++++++++++
drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 ++++++++++++
.../clock/mediatek,mt6735-imgsys.h | 15 ++++
.../clock/mediatek,mt6735-mfgcfg.h | 8 ++
.../clock/mediatek,mt6735-vdecsys.h | 9 +++
.../clock/mediatek,mt6735-vencsys.h | 11 +++
.../reset/mediatek,mt6735-mfgcfg.h | 9 +++
.../reset/mediatek,mt6735-vdecsys.h | 10 +++
14 files changed, 364 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
--
2.47.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-10-21 12:16 [PATCH 0/2] MediaTek MT6735 syscon clock/reset controller support Yassine Oudjana @ 2024-10-21 12:16 ` Yassine Oudjana 2024-10-21 16:56 ` Conor Dooley 2024-10-22 9:04 ` AngeloGioacchino Del Regno 2024-10-21 12:16 ` [PATCH 2/2] clk: mediatek: Add drivers " Yassine Oudjana 1 sibling, 2 replies; 8+ messages in thread From: Yassine Oudjana @ 2024-10-21 12:16 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih Cc: Yassine Oudjana, Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel From: Yassine Oudjana <y.oudjana@protonmail.com> Add device tree bindings for syscon clock and reset controllers (IMGSYS, MFGCFG, VDECSYS and VENCSYS). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> --- .../bindings/clock/mediatek,syscon.yaml | 4 ++++ MAINTAINERS | 6 ++++++ .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ 8 files changed, 72 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index 10483e26878fb..a86a64893c675 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -28,6 +28,10 @@ properties: - mediatek,mt2712-mfgcfg - mediatek,mt2712-vdecsys - mediatek,mt2712-vencsys + - mediatek,mt6735-imgsys + - mediatek,mt6735-mfgcfg + - mediatek,mt6735-vdecsys + - mediatek,mt6735-vencsys - mediatek,mt6765-camsys - mediatek,mt6765-imgsys - mediatek,mt6765-mipi0a diff --git a/MAINTAINERS b/MAINTAINERS index 2ce38c6c0e6ff..25484783f6a0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14537,11 +14537,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau <nbd@nbd.name> diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h new file mode 100644 index 0000000000000..f250c26c5eb4d --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H + +#define CLK_IMG_SMI_LARB2 0 +#define CLK_IMG_CAM_SMI 1 +#define CLK_IMG_CAM_CAM 2 +#define CLK_IMG_SEN_TG 3 +#define CLK_IMG_SEN_CAM 4 +#define CLK_IMG_CAM_SV 5 +#define CLK_IMG_SUFOD 6 +#define CLK_IMG_FD 7 + +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h new file mode 100644 index 0000000000000..d2d99a48348a0 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H + +#define CLK_MFG_BG3D 0 + +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h new file mode 100644 index 0000000000000..f94cec10c89ff --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H + +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h new file mode 100644 index 0000000000000..e5a9cb4f269ff --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H + +#define CLK_VENC_SMI_LARB3 0 +#define CLK_VENC_VENC 1 +#define CLK_VENC_JPGENC 2 +#define CLK_VENC_JPGDEC 3 + +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h new file mode 100644 index 0000000000000..c489242b226e2 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H + +#define MT6735_MFG_RST0_AXI 0 +#define MT6735_MFG_RST0_G3D 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h new file mode 100644 index 0000000000000..90ad73af50a3f --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H + +#define MT6735_VDEC_RST0_VDEC 0 + +#define MT6735_VDEC_RST1_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ -- 2.47.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-10-21 12:16 ` [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Yassine Oudjana @ 2024-10-21 16:56 ` Conor Dooley 2024-10-22 9:36 ` AngeloGioacchino Del Regno 2024-10-22 9:04 ` AngeloGioacchino Del Regno 1 sibling, 1 reply; 8+ messages in thread From: Conor Dooley @ 2024-10-21 16:56 UTC (permalink / raw) To: Yassine Oudjana Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih, Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 7018 bytes --] On Mon, Oct 21, 2024 at 03:16:15PM +0300, Yassine Oudjana wrote: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Add device tree bindings for syscon clock and reset controllers (IMGSYS, > MFGCFG, VDECSYS and VENCSYS). > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > .../bindings/clock/mediatek,syscon.yaml | 4 ++++ > MAINTAINERS | 6 ++++++ > .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ > .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ > .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ > .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ > .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ > .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ Is it really necessary to have individual files foe each of these? Seems a bit extra, no? Cheers, Conor. > 8 files changed, 72 insertions(+) > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > index 10483e26878fb..a86a64893c675 100644 > --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > @@ -28,6 +28,10 @@ properties: > - mediatek,mt2712-mfgcfg > - mediatek,mt2712-vdecsys > - mediatek,mt2712-vencsys > + - mediatek,mt6735-imgsys > + - mediatek,mt6735-mfgcfg > + - mediatek,mt6735-vdecsys > + - mediatek,mt6735-vencsys > - mediatek,mt6765-camsys > - mediatek,mt6765-imgsys > - mediatek,mt6765-mipi0a > diff --git a/MAINTAINERS b/MAINTAINERS > index 2ce38c6c0e6ff..25484783f6a0b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14537,11 +14537,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c > F: drivers/clk/mediatek/clk-mt6735-pericfg.c > F: drivers/clk/mediatek/clk-mt6735-topckgen.c > F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h > F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h > +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h > F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h > +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h > F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h > +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h > +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > > MEDIATEK MT76 WIRELESS LAN DRIVER > M: Felix Fietkau <nbd@nbd.name> > diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h > new file mode 100644 > index 0000000000000..f250c26c5eb4d > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H > +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H > + > +#define CLK_IMG_SMI_LARB2 0 > +#define CLK_IMG_CAM_SMI 1 > +#define CLK_IMG_CAM_CAM 2 > +#define CLK_IMG_SEN_TG 3 > +#define CLK_IMG_SEN_CAM 4 > +#define CLK_IMG_CAM_SV 5 > +#define CLK_IMG_SUFOD 6 > +#define CLK_IMG_FD 7 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > new file mode 100644 > index 0000000000000..d2d99a48348a0 > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > @@ -0,0 +1,8 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H > +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H > + > +#define CLK_MFG_BG3D 0 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > new file mode 100644 > index 0000000000000..f94cec10c89ff > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H > +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H > + > +#define CLK_VDEC_VDEC 0 > +#define CLK_VDEC_SMI_LARB1 1 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h > new file mode 100644 > index 0000000000000..e5a9cb4f269ff > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h > @@ -0,0 +1,11 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H > +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H > + > +#define CLK_VENC_SMI_LARB3 0 > +#define CLK_VENC_VENC 1 > +#define CLK_VENC_JPGENC 2 > +#define CLK_VENC_JPGDEC 3 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ > diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > new file mode 100644 > index 0000000000000..c489242b226e2 > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H > +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H > + > +#define MT6735_MFG_RST0_AXI 0 > +#define MT6735_MFG_RST0_G3D 1 > + > +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ > diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > new file mode 100644 > index 0000000000000..90ad73af50a3f > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > @@ -0,0 +1,10 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H > +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H > + > +#define MT6735_VDEC_RST0_VDEC 0 > + > +#define MT6735_VDEC_RST1_SMI_LARB1 1 > + > +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ > -- > 2.47.0 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-10-21 16:56 ` Conor Dooley @ 2024-10-22 9:36 ` AngeloGioacchino Del Regno 2024-10-22 17:23 ` Conor Dooley 0 siblings, 1 reply; 8+ messages in thread From: AngeloGioacchino Del Regno @ 2024-10-22 9:36 UTC (permalink / raw) To: Conor Dooley, Yassine Oudjana Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih, Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel Il 21/10/24 18:56, Conor Dooley ha scritto: > On Mon, Oct 21, 2024 at 03:16:15PM +0300, Yassine Oudjana wrote: >> From: Yassine Oudjana <y.oudjana@protonmail.com> >> >> Add device tree bindings for syscon clock and reset controllers (IMGSYS, >> MFGCFG, VDECSYS and VENCSYS). >> >> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> >> --- >> .../bindings/clock/mediatek,syscon.yaml | 4 ++++ >> MAINTAINERS | 6 ++++++ >> .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ >> .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ >> .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ >> .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ >> .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ >> .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ > > Is it really necessary to have individual files foe each of these? Seems > a bit extra, no? > It's only good for including smaller headers in each driver (and/or DT, but then the SoC DT will anyway include them all). I'm fine with that, but I'm also fine with one header for clock and one for reset. So.. Conor, it's however you prefer :-) Cheers, Angelo > Cheers, > Conor. > >> 8 files changed, 72 insertions(+) >> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h >> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h >> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h >> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h >> create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h >> create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h >> >> diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml >> index 10483e26878fb..a86a64893c675 100644 >> --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml >> +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml >> @@ -28,6 +28,10 @@ properties: >> - mediatek,mt2712-mfgcfg >> - mediatek,mt2712-vdecsys >> - mediatek,mt2712-vencsys >> + - mediatek,mt6735-imgsys >> + - mediatek,mt6735-mfgcfg >> + - mediatek,mt6735-vdecsys >> + - mediatek,mt6735-vencsys >> - mediatek,mt6765-camsys >> - mediatek,mt6765-imgsys >> - mediatek,mt6765-mipi0a >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 2ce38c6c0e6ff..25484783f6a0b 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -14537,11 +14537,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c >> F: drivers/clk/mediatek/clk-mt6735-pericfg.c >> F: drivers/clk/mediatek/clk-mt6735-topckgen.c >> F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h >> +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h >> F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h >> +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h >> F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h >> F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h >> +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h >> +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h >> F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h >> +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h >> F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h >> +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h >> >> MEDIATEK MT76 WIRELESS LAN DRIVER >> M: Felix Fietkau <nbd@nbd.name> >> diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h >> new file mode 100644 >> index 0000000000000..f250c26c5eb4d >> --- /dev/null >> +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h >> @@ -0,0 +1,15 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H >> +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H >> + >> +#define CLK_IMG_SMI_LARB2 0 >> +#define CLK_IMG_CAM_SMI 1 >> +#define CLK_IMG_CAM_CAM 2 >> +#define CLK_IMG_SEN_TG 3 >> +#define CLK_IMG_SEN_CAM 4 >> +#define CLK_IMG_CAM_SV 5 >> +#define CLK_IMG_SUFOD 6 >> +#define CLK_IMG_FD 7 >> + >> +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ >> diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h >> new file mode 100644 >> index 0000000000000..d2d99a48348a0 >> --- /dev/null >> +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h >> @@ -0,0 +1,8 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H >> +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H >> + >> +#define CLK_MFG_BG3D 0 >> + >> +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ >> diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h >> new file mode 100644 >> index 0000000000000..f94cec10c89ff >> --- /dev/null >> +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h >> @@ -0,0 +1,9 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H >> +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H >> + >> +#define CLK_VDEC_VDEC 0 >> +#define CLK_VDEC_SMI_LARB1 1 >> + >> +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ >> diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h >> new file mode 100644 >> index 0000000000000..e5a9cb4f269ff >> --- /dev/null >> +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h >> @@ -0,0 +1,11 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H >> +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H >> + >> +#define CLK_VENC_SMI_LARB3 0 >> +#define CLK_VENC_VENC 1 >> +#define CLK_VENC_JPGENC 2 >> +#define CLK_VENC_JPGDEC 3 >> + >> +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ >> diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h >> new file mode 100644 >> index 0000000000000..c489242b226e2 >> --- /dev/null >> +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h >> @@ -0,0 +1,9 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H >> +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H >> + >> +#define MT6735_MFG_RST0_AXI 0 >> +#define MT6735_MFG_RST0_G3D 1 >> + >> +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ >> diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h >> new file mode 100644 >> index 0000000000000..90ad73af50a3f >> --- /dev/null >> +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h >> @@ -0,0 +1,10 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H >> +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H >> + >> +#define MT6735_VDEC_RST0_VDEC 0 >> + >> +#define MT6735_VDEC_RST1_SMI_LARB1 1 >> + >> +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ >> -- >> 2.47.0 >> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-10-22 9:36 ` AngeloGioacchino Del Regno @ 2024-10-22 17:23 ` Conor Dooley 0 siblings, 0 replies; 8+ messages in thread From: Conor Dooley @ 2024-10-22 17:23 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: Yassine Oudjana, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih, Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 1599 bytes --] On Tue, Oct 22, 2024 at 11:36:20AM +0200, AngeloGioacchino Del Regno wrote: > Il 21/10/24 18:56, Conor Dooley ha scritto: > > On Mon, Oct 21, 2024 at 03:16:15PM +0300, Yassine Oudjana wrote: > > > From: Yassine Oudjana <y.oudjana@protonmail.com> > > > > > > Add device tree bindings for syscon clock and reset controllers (IMGSYS, > > > MFGCFG, VDECSYS and VENCSYS). > > > > > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > > > --- > > > .../bindings/clock/mediatek,syscon.yaml | 4 ++++ > > > MAINTAINERS | 6 ++++++ > > > .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ > > > .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ > > > .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ > > > .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ > > > .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ > > > .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ > > > > Is it really necessary to have individual files foe each of these? Seems > > a bit extra, no? > > > > It's only good for including smaller headers in each driver (and/or DT, but > then the SoC DT will anyway include them all). > > I'm fine with that, but I'm also fine with one header for clock and one for reset. > > So.. Conor, it's however you prefer :-) It's not worth respinning for, IMO, but I think having 8 and 9 line header files for 2 definitions is silly. Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-10-21 12:16 ` [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Yassine Oudjana 2024-10-21 16:56 ` Conor Dooley @ 2024-10-22 9:04 ` AngeloGioacchino Del Regno 1 sibling, 0 replies; 8+ messages in thread From: AngeloGioacchino Del Regno @ 2024-10-22 9:04 UTC (permalink / raw) To: Yassine Oudjana, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih Cc: Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel Il 21/10/24 14:16, Yassine Oudjana ha scritto: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Add device tree bindings for syscon clock and reset controllers (IMGSYS, > MFGCFG, VDECSYS and VENCSYS). > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > .../bindings/clock/mediatek,syscon.yaml | 4 ++++ > MAINTAINERS | 6 ++++++ > .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ > .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ > .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ > .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ > .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ > .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ > 8 files changed, 72 insertions(+) > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > ..snip.. > diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > new file mode 100644 > index 0000000000000..90ad73af50a3f > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > @@ -0,0 +1,10 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H > +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H > + > +#define MT6735_VDEC_RST0_VDEC 0 > + Since you anyway have to send a new version, please remove this extra and unneeded blank line for v2. Anyway... Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers 2024-10-21 12:16 [PATCH 0/2] MediaTek MT6735 syscon clock/reset controller support Yassine Oudjana 2024-10-21 12:16 ` [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Yassine Oudjana @ 2024-10-21 12:16 ` Yassine Oudjana 2024-10-22 9:05 ` AngeloGioacchino Del Regno 1 sibling, 1 reply; 8+ messages in thread From: Yassine Oudjana @ 2024-10-21 12:16 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih Cc: Yassine Oudjana, Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel From: Yassine Oudjana <y.oudjana@protonmail.com> Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> --- MAINTAINERS | 4 ++ drivers/clk/mediatek/Kconfig | 32 +++++++++ drivers/clk/mediatek/Makefile | 4 ++ drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 ++++++++++++++++ drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 +++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vdecsys.c | 81 +++++++++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 +++++++++++++++ 7 files changed, 292 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c diff --git a/MAINTAINERS b/MAINTAINERS index 25484783f6a0b..939f9d29fc9bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14533,9 +14533,13 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c +F: drivers/clk/mediatek/clk-mt6735-imgsys.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c +F: drivers/clk/mediatek/clk-mt6735-vdecsys.c +F: drivers/clk/mediatek/clk-mt6735-vencsys.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7a33f9e92d963..4dd6d2d6263fd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -133,6 +133,38 @@ config COMMON_CLK_MT6735 by apmixedsys, topckgen, infracfg and pericfg on the MediaTek MT6735 SoC. +config COMMON_CLK_MT6735_IMGSYS + tristate "Clock driver for MediaTek MT6735 imgsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks provided by imgsys + on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_MFGCFG + tristate "Clock driver for MediaTek MT6735 mfgcfg" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks and resets provided + by mfgcfg on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VDECSYS + tristate "Clock driver for MediaTek MT6735 vdecsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks and resets provided + by vdecsys on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VENCSYS + tristate "Clock driver for MediaTek MT6735 vencsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks provided by vencsys + on the MediaTek MT6735 SoC. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 70456ffc6c492..6efec95406bd5 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed. obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediatek/clk-mt6735-imgsys.c new file mode 100644 index 0000000000000..c564f8f724324 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mediatek,mt6735-imgsys.h> + +#define IMG_CG_CON 0x00 +#define IMG_CG_SET 0x04 +#define IMG_CG_CLR 0x08 + +static struct mtk_gate_regs imgsys_cg_regs = { + .set_ofs = IMG_CG_SET, + .clr_ofs = IMG_CG_CLR, + .sta_ofs = IMG_CG_CON, +}; + +static const struct mtk_gate imgsys_gates[] = { + GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr), +}; + +static const struct mtk_clk_desc imgsys_clks = { + .clks = imgsys_gates, + .num_clks = ARRAY_SIZE(imgsys_gates), +}; + +static const struct of_device_id of_match_mt6735_imgsys[] = { + { .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_imgsys = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6735-imgsys", + .of_match_table = of_match_mt6735_imgsys, + }, +}; +module_platform_driver(clk_mt6735_imgsys); + +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); +MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c new file mode 100644 index 0000000000000..1f5aedddf209d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mediatek,mt6735-mfgcfg.h> + +#define MFG_CG_CON 0x00 +#define MFG_CG_SET 0x04 +#define MFG_CG_CLR 0x08 +#define MFG_RESET 0x0c + +static struct mtk_gate_regs mfgcfg_cg_regs = { + .set_ofs = MFG_CG_SET, + .clr_ofs = MFG_CG_CLR, + .sta_ofs = MFG_CG_CON, +}; + +static const struct mtk_gate mfgcfg_gates[] = { + GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_gate_ops_setclr), +}; + +static u16 mfgcfg_rst_ofs[] = { MFG_RESET }; + +static const struct mtk_clk_rst_desc mfgcfg_resets = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = mfgcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(mfgcfg_rst_ofs) +}; + +static const struct mtk_clk_desc mfgcfg_clks = { + .clks = mfgcfg_gates, + .num_clks = ARRAY_SIZE(mfgcfg_gates), + + .rst_desc = &mfgcfg_resets +}; + +static const struct of_device_id of_match_mt6735_mfgcfg[] = { + { .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_mfgcfg = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6735-mfgcfg", + .of_match_table = of_match_mt6735_mfgcfg, + }, +}; +module_platform_driver(clk_mt6735_mfgcfg); + +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); +MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediatek/clk-mt6735-vdecsys.c new file mode 100644 index 0000000000000..f59b481aaa6da --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mediatek,mt6735-vdecsys.h> +#include <dt-bindings/reset/mediatek,mt6735-vdecsys.h> + +#define VDEC_CKEN_SET 0x00 +#define VDEC_CKEN_CLR 0x04 +#define SMI_LARB1_CKEN_SET 0x08 +#define SMI_LARB1_CKEN_CLR 0x0c +#define VDEC_RESETB_CON 0x10 +#define SMI_LARB1_RESETB_CON 0x14 + +#define RST_NR_PER_BANK 32 + +static struct mtk_gate_regs vdec_cg_regs = { + .set_ofs = VDEC_CKEN_SET, + .clr_ofs = VDEC_CKEN_CLR, + .sta_ofs = VDEC_CKEN_SET, +}; + +static struct mtk_gate_regs smi_larb1_cg_regs = { + .set_ofs = SMI_LARB1_CKEN_SET, + .clr_ofs = SMI_LARB1_CKEN_CLR, + .sta_ofs = SMI_LARB1_CKEN_SET, +}; + +static const struct mtk_gate vdecsys_gates[] = { + GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv), +}; + +static u16 vdecsys_rst_bank_ofs[] = { VDEC_RESETB_CON, SMI_LARB1_RESETB_CON }; + +static u16 vdecsys_rst_idx_map[] = { + [MT6735_VDEC_RST0_VDEC] = 0 * RST_NR_PER_BANK + 0, + + [MT6735_VDEC_RST1_SMI_LARB1] = 1 * RST_NR_PER_BANK + 0, +}; + +static const struct mtk_clk_rst_desc vdecsys_resets = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = vdecsys_rst_bank_ofs, + .rst_bank_nr = ARRAY_SIZE(vdecsys_rst_bank_ofs), + .rst_idx_map = vdecsys_rst_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(vdecsys_rst_idx_map) +}; + +static const struct mtk_clk_desc vdecsys_clks = { + .clks = vdecsys_gates, + .num_clks = ARRAY_SIZE(vdecsys_gates), + + .rst_desc = &vdecsys_resets +}; + +static const struct of_device_id of_match_mt6735_vdecsys[] = { + { .compatible = "mediatek,mt6735-vdecsys", .data = &vdecsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vdecsys = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6735-vdecsys", + .of_match_table = of_match_mt6735_vdecsys, + }, +}; +module_platform_driver(clk_mt6735_vdecsys); + +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); +MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediatek/clk-mt6735-vencsys.c new file mode 100644 index 0000000000000..8dec7f98492ac --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mediatek,mt6735-vencsys.h> + +#define VENC_CG_CON 0x00 +#define VENC_CG_SET 0x04 +#define VENC_CG_CLR 0x08 + +static struct mtk_gate_regs venc_cg_regs = { + .set_ofs = VENC_CG_SET, + .clr_ofs = VENC_CG_CLR, + .sta_ofs = VENC_CG_CON, +}; + +static const struct mtk_gate vencsys_gates[] = { + GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv), +}; + +static const struct mtk_clk_desc vencsys_clks = { + .clks = vencsys_gates, + .num_clks = ARRAY_SIZE(vencsys_gates), +}; + +static const struct of_device_id of_match_mt6735_vencsys[] = { + { .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vencsys = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6735-vencsys", + .of_match_table = of_match_mt6735_vencsys, + }, +}; +module_platform_driver(clk_mt6735_vencsys); + +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); +MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver"); +MODULE_LICENSE("GPL"); -- 2.47.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers 2024-10-21 12:16 ` [PATCH 2/2] clk: mediatek: Add drivers " Yassine Oudjana @ 2024-10-22 9:05 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 8+ messages in thread From: AngeloGioacchino Del Regno @ 2024-10-22 9:05 UTC (permalink / raw) To: Yassine Oudjana, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Philipp Zabel, Lukas Bulwahn, Daniel Golle, Sam Shih Cc: Yassine Oudjana, linux-clk, devicetree, linux-kernel, linux-mediatek, linux-arm-kernel Il 21/10/24 14:16, Yassine Oudjana ha scritto: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets > on MT6735. > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > --- > MAINTAINERS | 4 ++ > drivers/clk/mediatek/Kconfig | 32 +++++++++ > drivers/clk/mediatek/Makefile | 4 ++ > drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 ++++++++++++++++ > drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 +++++++++++++++++ > drivers/clk/mediatek/clk-mt6735-vdecsys.c | 81 +++++++++++++++++++++++ > drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 +++++++++++++++ > 7 files changed, 292 insertions(+) > create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c > create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c > create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c > create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 25484783f6a0b..939f9d29fc9bf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14533,9 +14533,13 @@ L: linux-clk@vger.kernel.org > L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c > +F: drivers/clk/mediatek/clk-mt6735-imgsys.c > F: drivers/clk/mediatek/clk-mt6735-infracfg.c > +F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c > F: drivers/clk/mediatek/clk-mt6735-pericfg.c > F: drivers/clk/mediatek/clk-mt6735-topckgen.c > +F: drivers/clk/mediatek/clk-mt6735-vdecsys.c > +F: drivers/clk/mediatek/clk-mt6735-vencsys.c > F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h > F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig > index 7a33f9e92d963..4dd6d2d6263fd 100644 > --- a/drivers/clk/mediatek/Kconfig > +++ b/drivers/clk/mediatek/Kconfig > @@ -133,6 +133,38 @@ config COMMON_CLK_MT6735 > by apmixedsys, topckgen, infracfg and pericfg on the > MediaTek MT6735 SoC. > > +config COMMON_CLK_MT6735_IMGSYS > + tristate "Clock driver for MediaTek MT6735 imgsys" > + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST If this depends on COMMON_CLK_MT6735, it automatically also depends on ARCH_MEDIATEK, because the former cannot be selected without satisfying the dependency on the latter. Also, with those being really dependant on COMMON_CLK_MT6735, it does not make any sense to COMPILE_TEST those alone anyway... > + select COMMON_CLK_MEDIATEK The same goes for this select statement: it's already done when selecting COMMON_CLK_MT6735. Finally: config COMMON_CLK_MT6735_IMGSYS tristate "Clock driver for MediaTek MT6735 imgsys" depends on COMMON_CLK_MT6735 help blah blah blah is just fine - and shorter too :-) > + help > + This enables a driver for clocks provided by imgsys > + on the MediaTek MT6735 SoC. > + > +config COMMON_CLK_MT6735_MFGCFG > + tristate "Clock driver for MediaTek MT6735 mfgcfg" > + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST > + select COMMON_CLK_MEDIATEK > + help > + This enables a driver for clocks and resets provided > + by mfgcfg on the MediaTek MT6735 SoC. > + > +config COMMON_CLK_MT6735_VDECSYS > + tristate "Clock driver for MediaTek MT6735 vdecsys" > + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST > + select COMMON_CLK_MEDIATEK > + help > + This enables a driver for clocks and resets provided > + by vdecsys on the MediaTek MT6735 SoC. > + > +config COMMON_CLK_MT6735_VENCSYS > + tristate "Clock driver for MediaTek MT6735 vencsys" > + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST > + select COMMON_CLK_MEDIATEK > + help > + This enables a driver for clocks provided by vencsys > + on the MediaTek MT6735 SoC. > + > config COMMON_CLK_MT6765 > bool "Clock driver for MediaTek MT6765" > depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ..snip.. > diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediatek/clk-mt6735-vdecsys.c > new file mode 100644 > index 0000000000000..f59b481aaa6da > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c > @@ -0,0 +1,81 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > + > +#include "clk-gate.h" > +#include "clk-mtk.h" > + > +#include <dt-bindings/clock/mediatek,mt6735-vdecsys.h> > +#include <dt-bindings/reset/mediatek,mt6735-vdecsys.h> > + ..snip.. > +static u16 vdecsys_rst_bank_ofs[] = { VDEC_RESETB_CON, SMI_LARB1_RESETB_CON }; > + > +static u16 vdecsys_rst_idx_map[] = { > + [MT6735_VDEC_RST0_VDEC] = 0 * RST_NR_PER_BANK + 0, > + Please remove this extra blank line, it's not needed. > + [MT6735_VDEC_RST1_SMI_LARB1] = 1 * RST_NR_PER_BANK + 0, > +}; > + > +static const struct mtk_clk_rst_desc vdecsys_resets = { > + .version = MTK_RST_SIMPLE, > + .rst_bank_ofs = vdecsys_rst_bank_ofs, > + .rst_bank_nr = ARRAY_SIZE(vdecsys_rst_bank_ofs), > + .rst_idx_map = vdecsys_rst_idx_map, > + .rst_idx_map_nr = ARRAY_SIZE(vdecsys_rst_idx_map) > +}; > + > +static const struct mtk_clk_desc vdecsys_clks = { > + .clks = vdecsys_gates, > + .num_clks = ARRAY_SIZE(vdecsys_gates), > + same here. > + .rst_desc = &vdecsys_resets > +}; > + The rest looks good, and I'm confident that you're getting my R-b on v2. Cheers, Angelo ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-10-22 17:43 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-10-21 12:16 [PATCH 0/2] MediaTek MT6735 syscon clock/reset controller support Yassine Oudjana 2024-10-21 12:16 ` [PATCH 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Yassine Oudjana 2024-10-21 16:56 ` Conor Dooley 2024-10-22 9:36 ` AngeloGioacchino Del Regno 2024-10-22 17:23 ` Conor Dooley 2024-10-22 9:04 ` AngeloGioacchino Del Regno 2024-10-21 12:16 ` [PATCH 2/2] clk: mediatek: Add drivers " Yassine Oudjana 2024-10-22 9:05 ` AngeloGioacchino Del Regno
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