* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-11 11:26 [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world Anshuman Khandual
@ 2021-02-12 14:31 ` Alexandru Elisei
2021-02-12 15:44 ` Suzuki K Poulose
2021-02-12 17:33 ` Alexandru Elisei
2021-02-25 18:30 ` Mark Rutland
2 siblings, 1 reply; 7+ messages in thread
From: Alexandru Elisei @ 2021-02-12 14:31 UTC (permalink / raw)
To: Anshuman Khandual, linux-arm-kernel
Cc: mark.rutland, Andre.Przywara, james.morse, Suzuki.Poulose
Hello Anshuman,
On 2/11/21 11:26 AM, Anshuman Khandual wrote:
> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
> buffer to use non-secure memory and to permit direct register accesses from
> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/aarch64/boot.S | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 37f4b98..e47cf59 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -71,6 +71,14 @@ _start:
> ldr x1, =(0x3 << 12)
> orr x0, x0, x1
>
> +1: mrs x1, id_aa64dfr0_el1
> + ubfx x1, x1, #44, #4
> + cbz x1, 1f
> +
> + // Enable TRBE for the non-secure world.
> + ldr x1, =(0x3 << 24)
> + orr x0, x0, x1
> +
> 1: msr mdcr_el3, x0 // Disable traps to EL3
>
> mrs x0, id_aa64pfr0_el1
That's strange, I'm looking at ARM DDI 0487G.a and bits [44:47] from
ID_AA64DFR0_EL1 are RES0 and there is no TraceBuffer field; bits [24:25] of
MDCR_EL3 are also RES0 and I searched the entire file for the NSTB field, could
not find it. Do I have an outdated version of the architecture?
Thanks,
Alex
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-12 14:31 ` Alexandru Elisei
@ 2021-02-12 15:44 ` Suzuki K Poulose
2021-02-12 17:28 ` Alexandru Elisei
0 siblings, 1 reply; 7+ messages in thread
From: Suzuki K Poulose @ 2021-02-12 15:44 UTC (permalink / raw)
To: Alexandru Elisei, Anshuman Khandual, linux-arm-kernel
Cc: mark.rutland, Andre.Przywara, james.morse
On 2/12/21 2:31 PM, Alexandru Elisei wrote:
> Hello Anshuman,
>
> On 2/11/21 11:26 AM, Anshuman Khandual wrote:
>> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
>> buffer to use non-secure memory and to permit direct register accesses from
>> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
>> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
>> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/aarch64/boot.S | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
>> index 37f4b98..e47cf59 100644
>> --- a/arch/aarch64/boot.S
>> +++ b/arch/aarch64/boot.S
>> @@ -71,6 +71,14 @@ _start:
>> ldr x1, =(0x3 << 12)
>> orr x0, x0, x1
>>
>> +1: mrs x1, id_aa64dfr0_el1
>> + ubfx x1, x1, #44, #4
>> + cbz x1, 1f
>> +
>> + // Enable TRBE for the non-secure world.
>> + ldr x1, =(0x3 << 24)
>> + orr x0, x0, x1
>> +
>> 1: msr mdcr_el3, x0 // Disable traps to EL3
>>
>> mrs x0, id_aa64pfr0_el1
>
> That's strange, I'm looking at ARM DDI 0487G.a and bits [44:47] from
> ID_AA64DFR0_EL1 are RES0 and there is no TraceBuffer field; bits [24:25] of
> MDCR_EL3 are also RES0 and I searched the entire file for the NSTB field, could
> not find it. Do I have an outdated version of the architecture?
They are not in the Arm ARM. These are part of the Future Architecture
technology changes, for which the register defintions are available here :
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/
Cheers
Suzuki
>
> Thanks,
>
> Alex
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-12 15:44 ` Suzuki K Poulose
@ 2021-02-12 17:28 ` Alexandru Elisei
0 siblings, 0 replies; 7+ messages in thread
From: Alexandru Elisei @ 2021-02-12 17:28 UTC (permalink / raw)
To: Suzuki K Poulose, Anshuman Khandual, linux-arm-kernel
Cc: mark.rutland, Andre.Przywara, james.morse
Hi,
On 2/12/21 3:44 PM, Suzuki K Poulose wrote:
> On 2/12/21 2:31 PM, Alexandru Elisei wrote:
>> Hello Anshuman,
>>
>> On 2/11/21 11:26 AM, Anshuman Khandual wrote:
>>> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
>>> buffer to use non-secure memory and to permit direct register accesses from
>>> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
>>> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
>>> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>>>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>> ---
>>> arch/aarch64/boot.S | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
>>> index 37f4b98..e47cf59 100644
>>> --- a/arch/aarch64/boot.S
>>> +++ b/arch/aarch64/boot.S
>>> @@ -71,6 +71,14 @@ _start:
>>> ldr x1, =(0x3 << 12)
>>> orr x0, x0, x1
>>> +1: mrs x1, id_aa64dfr0_el1
>>> + ubfx x1, x1, #44, #4
>>> + cbz x1, 1f
>>> +
>>> + // Enable TRBE for the non-secure world.
>>> + ldr x1, =(0x3 << 24)
>>> + orr x0, x0, x1
>>> +
>>> 1: msr mdcr_el3, x0 // Disable traps to EL3
>>> mrs x0, id_aa64pfr0_el1
>>
>> That's strange, I'm looking at ARM DDI 0487G.a and bits [44:47] from
>> ID_AA64DFR0_EL1 are RES0 and there is no TraceBuffer field; bits [24:25] of
>> MDCR_EL3 are also RES0 and I searched the entire file for the NSTB field, could
>> not find it. Do I have an outdated version of the architecture?
>
> They are not in the Arm ARM. These are part of the Future Architecture
> technology changes, for which the register defintions are available here :
>
> https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/
That worked, thanks!
Thanks,
Alex
>
> Cheers
> Suzuki
>
>>
>> Thanks,
>>
>> Alex
>>
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-11 11:26 [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world Anshuman Khandual
2021-02-12 14:31 ` Alexandru Elisei
@ 2021-02-12 17:33 ` Alexandru Elisei
2021-02-25 18:33 ` Mark Rutland
2021-02-25 18:30 ` Mark Rutland
2 siblings, 1 reply; 7+ messages in thread
From: Alexandru Elisei @ 2021-02-12 17:33 UTC (permalink / raw)
To: Anshuman Khandual, linux-arm-kernel
Cc: mark.rutland, Andre.Przywara, james.morse, Suzuki.Poulose
Hello,
On 2/11/21 11:26 AM, Anshuman Khandual wrote:
> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
> buffer to use non-secure memory and to permit direct register accesses from
> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/aarch64/boot.S | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 37f4b98..e47cf59 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -71,6 +71,14 @@ _start:
> ldr x1, =(0x3 << 12)
> orr x0, x0, x1
>
> +1: mrs x1, id_aa64dfr0_el1
Nitpick: we could change the first read of ID_AA64DFR0_EL1 to use x2 as the
destination register, to avoid this second read.
> + ubfx x1, x1, #44, #4
> + cbz x1, 1f
> +
> + // Enable TRBE for the non-secure world.
> + ldr x1, =(0x3 << 24)
> + orr x0, x0, x1
> +
> 1: msr mdcr_el3, x0 // Disable traps to EL3
Looked at [1] for the field definitions, and the patch indeed does what it says.
0b11 for MDCR_EL3.NSTB means that the buffer owning regime is the non-secure
state, and accesses to the buffer control registers from the *secure state* are
trapped to EL3, which is what we want.
With or without the destination register change:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
[1] https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/
Thanks,
Alex
>
> mrs x0, id_aa64pfr0_el1
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-12 17:33 ` Alexandru Elisei
@ 2021-02-25 18:33 ` Mark Rutland
0 siblings, 0 replies; 7+ messages in thread
From: Mark Rutland @ 2021-02-25 18:33 UTC (permalink / raw)
To: Alexandru Elisei
Cc: Andre.Przywara, Suzuki.Poulose, james.morse, linux-arm-kernel,
Anshuman Khandual
On Fri, Feb 12, 2021 at 05:33:08PM +0000, Alexandru Elisei wrote:
> Hello,
>
> On 2/11/21 11:26 AM, Anshuman Khandual wrote:
> > MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
> > buffer to use non-secure memory and to permit direct register accesses from
> > the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
> > make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
> > to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
> >
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > ---
> > arch/aarch64/boot.S | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> > index 37f4b98..e47cf59 100644
> > --- a/arch/aarch64/boot.S
> > +++ b/arch/aarch64/boot.S
> > @@ -71,6 +71,14 @@ _start:
> > ldr x1, =(0x3 << 12)
> > orr x0, x0, x1
> >
> > +1: mrs x1, id_aa64dfr0_el1
>
> Nitpick: we could change the first read of ID_AA64DFR0_EL1 to use x2 as the
> destination register, to avoid this second read.
I've kept this as-is for now; my general preference is to keep things
such that each of the feature enables can be read indepdendently, even
if that requires some redundant work.
> > + ubfx x1, x1, #44, #4
> > + cbz x1, 1f
> > +
> > + // Enable TRBE for the non-secure world.
> > + ldr x1, =(0x3 << 24)
> > + orr x0, x0, x1
> > +
> > 1: msr mdcr_el3, x0 // Disable traps to EL3
>
> Looked at [1] for the field definitions, and the patch indeed does what it says.
> 0b11 for MDCR_EL3.NSTB means that the buffer owning regime is the non-secure
> state, and accesses to the buffer control registers from the *secure state* are
> trapped to EL3, which is what we want.
>
> With or without the destination register change:
>
> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks for the review -- I folded your tag in.
Mark.
>
> [1] https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/
>
> Thanks,
>
> Alex
>
> >
> > mrs x0, id_aa64pfr0_el1
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
2021-02-11 11:26 [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world Anshuman Khandual
2021-02-12 14:31 ` Alexandru Elisei
2021-02-12 17:33 ` Alexandru Elisei
@ 2021-02-25 18:30 ` Mark Rutland
2 siblings, 0 replies; 7+ messages in thread
From: Mark Rutland @ 2021-02-25 18:30 UTC (permalink / raw)
To: Anshuman Khandual
Cc: Andre.Przywara, james.morse, linux-arm-kernel, Suzuki.Poulose
On Thu, Feb 11, 2021 at 04:56:37PM +0530, Anshuman Khandual wrote:
> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
> buffer to use non-secure memory and to permit direct register accesses from
> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Applied, thanks!
Mark.
> ---
> arch/aarch64/boot.S | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 37f4b98..e47cf59 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -71,6 +71,14 @@ _start:
> ldr x1, =(0x3 << 12)
> orr x0, x0, x1
>
> +1: mrs x1, id_aa64dfr0_el1
> + ubfx x1, x1, #44, #4
> + cbz x1, 1f
> +
> + // Enable TRBE for the non-secure world.
> + ldr x1, =(0x3 << 24)
> + orr x0, x0, x1
> +
> 1: msr mdcr_el3, x0 // Disable traps to EL3
>
> mrs x0, id_aa64pfr0_el1
> --
> 2.7.4
>
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