* Re: [PATCH 31/34] spi: remove incorrect of_match_ptr annotations
From: Mark Brown @ 2024-04-03 9:56 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, Neil Armstrong, Kevin Hilman, Heiko Stuebner,
Andi Shyti, Krzysztof Kozlowski, Arnd Bergmann, Jerome Brunet,
Martin Blumenstingl, Alim Akhtar, Li Zetao, Jonathan Cameron,
Rob Herring, Yang Yingliang, Andy Shevchenko, Luis de Arquer,
Tudor Ambarus, Sam Protsenko, Peter Griffin, Jaewon Kim,
linux-spi, linux-arm-kernel, linux-amlogic, linux-rockchip,
linux-samsung-soc
In-Reply-To: <20240403080702.3509288-32-arnd@kernel.org>
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On Wed, Apr 03, 2024 at 10:06:49AM +0200, Arnd Bergmann wrote:
> These appear to all be copied from the same original driver, so fix them at the
> same time by removing the unnecessary of_match_ptr() annotation. As far as I
> can tell, all these drivers are only actually used on configurations that
> have CONFIG_OF enabled.
Why are we not fixing of_match_ptr() here, or at least adding the ifdefs
in case someone does end up wanting to run without OF?
Just as a general thing for something like this where the patches aren't
expected to get merged together it makes life much easier to not send as
a series - pulling individual patches out of a series causes issues with
things like b4, especially if you have to apply them to multiple places,
and there's limited benefit.
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^ permalink raw reply
* Re: [PATCH] arm64: remove redundant 'extern'
From: Steven Price @ 2024-04-03 9:58 UTC (permalink / raw)
To: Mark Rutland; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel, linux-kernel
In-Reply-To: <ZgvXljt6vdlVc1sF@FVFF77S0Q05N>
On 02/04/2024 11:01, Mark Rutland wrote:
> On Wed, Mar 27, 2024 at 11:24:39AM +0000, Steven Price wrote:
>> It isn't necessary to mark function definitions extern and goes against
>> the kernel coding style. Remove the redundant extern keyword.
>>
>> Signed-off-by: Steven Price <steven.price@arm.com>
>
> We (unfortunately) have extern misused in a number of places:
>
> | [mark@lakrids:~/src/linux]% git grep 'extern.*(' -- arch/arm64/include | cut -d: -f 1 | uniq -c
> | 11 arch/arm64/include/asm/cacheflush.h
> | 1 arch/arm64/include/asm/checksum.h
> | 1 arch/arm64/include/asm/cpu_ops.h
> | 4 arch/arm64/include/asm/cpufeature.h
> | 2 arch/arm64/include/asm/efi.h
> | 2 arch/arm64/include/asm/elf.h
> | 1 arch/arm64/include/asm/exec.h
> | 1 arch/arm64/include/asm/fixmap.h
> | 48 arch/arm64/include/asm/fpsimd.h
> | 3 arch/arm64/include/asm/ftrace.h
> | 10 arch/arm64/include/asm/hugetlb.h
> | 11 arch/arm64/include/asm/hw_breakpoint.h
> | 6 arch/arm64/include/asm/io.h
> | 4 arch/arm64/include/asm/kexec.h
> | 1 arch/arm64/include/asm/kgdb.h
> | 16 arch/arm64/include/asm/kvm_asm.h
> | 3 arch/arm64/include/asm/kvm_host.h
> | 11 arch/arm64/include/asm/kvm_hyp.h
> | 2 arch/arm64/include/asm/kvm_pkvm.h
> | 2 arch/arm64/include/asm/memory.h
> | 8 arch/arm64/include/asm/mmu.h
> | 2 arch/arm64/include/asm/page.h
> | 1 arch/arm64/include/asm/percpu.h
> | 2 arch/arm64/include/asm/perf_event.h
> | 2 arch/arm64/include/asm/pgalloc.h
> | 18 arch/arm64/include/asm/pgtable.h
> | 3 arch/arm64/include/asm/pointer_auth.h
> | 3 arch/arm64/include/asm/proc-fns.h
> | 2 arch/arm64/include/asm/processor.h
> | 3 arch/arm64/include/asm/ptrace.h
> | 12 arch/arm64/include/asm/smp.h
> | 1 arch/arm64/include/asm/stacktrace.h
> | 14 arch/arm64/include/asm/string.h
> | 2 arch/arm64/include/asm/suspend.h
> | 1 arch/arm64/include/asm/system_misc.h
> | 6 arch/arm64/include/asm/uaccess.h
>
> ... so it'd probably be best to make the commit title more specific to this
> instance, and maybe go clean those up in bulk as a series to avoid a steady
> stream of copycat patches.
Ah, I hadn't gone looking that closely - I'll do a series updating the
arch/arm64/include ones (thanks for the list ;) ), and I'll include an
updated version of this patch, with a clearly commit title, in the series.
Thanks,
Steve
> Mark.
>
>> ---
>> arch/arm64/include/asm/fixmap.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
>> index 87e307804b99..75b22b89db1a 100644
>> --- a/arch/arm64/include/asm/fixmap.h
>> +++ b/arch/arm64/include/asm/fixmap.h
>> @@ -107,7 +107,7 @@ void __init early_fixmap_init(void);
>> #define __late_set_fixmap __set_fixmap
>> #define __late_clear_fixmap(idx) __set_fixmap((idx), 0, FIXMAP_PAGE_CLEAR)
>>
>> -extern void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
>> +void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
>>
>> #include <asm-generic/fixmap.h>
>>
>> --
>> 2.34.1
>>
>>
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^ permalink raw reply
* [PATCH v7 0/5] Add Tegra Security Engine driver
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
Add support for Tegra Security Engine which can accelerates various
crypto algorithms. The Engine has two separate instances within for
AES and HASH algorithms respectively.
The driver registers two crypto engines - one for AES and another for
HASH algorithms and these operate independently and both uses the host1x
bus. Additionally, it provides hardware-assisted key protection for up to
15 symmetric keys which it can use for the cipher operations.
v6->v7:
* Move fallback_tfm and fallback_req to end of struct
* Set reqsize and statesize based on fallback_tfm
* Remove ofb(aes)
v5->v6:
* Move copy/pase of intermediate results in export()/import() to
'update()' callback for CMAC as well.
* Check for rctx size when using fallback alg.
* Updated blocksizes to align with generic implementation
* Combined GCM and CCM init into aead_cra_init
* Updates to handle invalid cases better
* Reduce log levels for invalid cases to dev_dbg
v4->v5:
* Move copy/paste of intermediate results in export()/import() to
'update()' callback
v3->v4:
* Remove unused header in bindings doc.
* Update commit message in host1x change.
* Fix test bot warning.
v2->v3:
* Update compatible in driver and device trees.
* Remove extra new lines and symbols in binding doc.
v1->v2:
* Update probe errors with 'dev_err_probe'.
* Clean up function prototypes and redundant prints.
* Remove readl/writel wrappers.
* Fix test bot warnings.
Akhil R (5):
dt-bindings: crypto: Add Tegra Security Engine
gpu: host1x: Add Tegra SE to SID table
crypto: tegra: Add Tegra Security Engine driver
arm64: defconfig: Enable Tegra Security Engine
arm64: tegra: Add Tegra Security Engine DT nodes
.../crypto/nvidia,tegra234-se-aes.yaml | 52 +
.../crypto/nvidia,tegra234-se-hash.yaml | 52 +
MAINTAINERS | 5 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 +
arch/arm64/configs/defconfig | 1 +
drivers/crypto/Kconfig | 8 +
drivers/crypto/Makefile | 1 +
drivers/crypto/tegra/Makefile | 9 +
drivers/crypto/tegra/tegra-se-aes.c | 1933 +++++++++++++++++
drivers/crypto/tegra/tegra-se-hash.c | 1060 +++++++++
drivers/crypto/tegra/tegra-se-key.c | 156 ++
drivers/crypto/tegra/tegra-se-main.c | 439 ++++
drivers/crypto/tegra/tegra-se.h | 560 +++++
drivers/gpu/host1x/dev.c | 24 +
14 files changed, 4316 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
create mode 100644 drivers/crypto/tegra/Makefile
create mode 100644 drivers/crypto/tegra/tegra-se-aes.c
create mode 100644 drivers/crypto/tegra/tegra-se-hash.c
create mode 100644 drivers/crypto/tegra/tegra-se-key.c
create mode 100644 drivers/crypto/tegra/tegra-se-main.c
create mode 100644 drivers/crypto/tegra/tegra-se.h
--
2.43.2
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^ permalink raw reply
* [PATCH v7 1/5] dt-bindings: crypto: Add Tegra Security Engine
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R, Krzysztof Kozlowski
In-Reply-To: <20240403100039.33146-1-akhilrajeev@nvidia.com>
Add DT binding document for Tegra Security Engine.
The AES and HASH algorithms are handled independently by separate
engines within the Security Engine. These engines are registered
as two separate crypto engine drivers.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../crypto/nvidia,tegra234-se-aes.yaml | 52 +++++++++++++++++++
.../crypto/nvidia,tegra234-se-hash.yaml | 52 +++++++++++++++++++
2 files changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
diff --git a/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
new file mode 100644
index 000000000000..cb47ae2889b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Security Engine for AES algorithms
+
+description:
+ The Tegra Security Engine accelerates the following AES encryption/decryption
+ algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
+ AES-CMAC
+
+maintainers:
+ - Akhil R <akhilrajeev@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra234-se-aes
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/clock/tegra234-clock.h>
+
+ crypto@15820000 {
+ compatible = "nvidia,tegra234-se-aes";
+ reg = <0x15820000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu TEGRA234_SID_SES_SE1>;
+ dma-coherent;
+ };
+...
diff --git a/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
new file mode 100644
index 000000000000..f57ef10645e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Security Engine for HASH algorithms
+
+description:
+ The Tegra Security HASH Engine accelerates the following HASH functions -
+ SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
+ HMAC(SHA224), HMAC(SHA256), HMAC(SHA384), HMAC(SHA512)
+
+maintainers:
+ - Akhil R <akhilrajeev@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra234-se-hash
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/clock/tegra234-clock.h>
+
+ crypto@15840000 {
+ compatible = "nvidia,tegra234-se-hash";
+ reg = <0x15840000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu TEGRA234_SID_SES_SE2>;
+ dma-coherent;
+ };
+...
--
2.43.2
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^ permalink raw reply related
* Re: [PATCH v2] arm64: Fix double TCR_T0SZ_OFFSET shift
From: Mark Rutland @ 2024-04-03 10:01 UTC (permalink / raw)
To: Seongsu Park
Cc: will, catalin.marinas, ardb, linux-arm-kernel, linux-kernel,
Leem ChaeHoon, Gyeonggeon Choi, Soomin Cho, DaeRo Lee, kmasta
In-Reply-To: <20240403024236.193428-1-sgsu.park@samsung.com>
On Wed, Apr 03, 2024 at 11:42:36AM +0900, Seongsu Park wrote:
> We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET.
> So, the TCR_T0SZ_OFFSET shift here should be removed.
Can we please write a better commit message?
This doesn't explain:
* Where we have already shifted the value of t0sz, nor why it makes sense to do
that there.
* That the value of TCR_T0SZ_OFFSET is 0, and hence shifting this repeatedly is
beningn, and this patch is a cleanup rather than a fix.
Mark.
> Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
> Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
> Co-developed-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
> Signed-off-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
> Co-developed-by: Soomin Cho <to.soomin@gmail.com>
> Signed-off-by: Soomin Cho <to.soomin@gmail.com>
> Co-developed-by: DaeRo Lee <skseofh@gmail.com>
> Signed-off-by: DaeRo Lee <skseofh@gmail.com>
> Co-developed-by: kmasta <kmasta.study@gmail.com>
> Signed-off-by: kmasta <kmasta.study@gmail.com>
> Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
> ---
>
> Changes in v2:
> - Condition is updated
>
> ---
> arch/arm64/include/asm/mmu_context.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
> index c768d16b81a4..bd19f4c758b7 100644
> --- a/arch/arm64/include/asm/mmu_context.h
> +++ b/arch/arm64/include/asm/mmu_context.h
> @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
> {
> unsigned long tcr = read_sysreg(tcr_el1);
>
> - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
> + if ((tcr & TCR_T0SZ_MASK) == t0sz)
> return;
>
> tcr &= ~TCR_T0SZ_MASK;
> - tcr |= t0sz << TCR_T0SZ_OFFSET;
> + tcr |= t0sz;
> write_sysreg(tcr, tcr_el1);
> isb();
> }
> --
> 2.34.1
>
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* [PATCH v7 4/5] arm64: defconfig: Enable Tegra Security Engine
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
In-Reply-To: <20240403100039.33146-1-akhilrajeev@nvidia.com>
Enable Tegra Security Engine which can accelerate various
AES and HASH algorithms on supported hardware.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2c30d617e180..af6f247c497c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1647,6 +1647,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCOM_RNG=m
+CONFIG_CRYPTO_DEV_TEGRA=m
CONFIG_CRYPTO_DEV_CCREE=m
CONFIG_CRYPTO_DEV_HISI_SEC2=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
--
2.43.2
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^ permalink raw reply related
* [PATCH v7 5/5] arm64: tegra: Add Tegra Security Engine DT nodes
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
In-Reply-To: <20240403100039.33146-1-akhilrajeev@nvidia.com>
Add device tree nodes for Tegra AES and HASH engines.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 78cbfdd98dd1..f2e2d8d6845b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4406,6 +4406,22 @@ nvdec@15480000 {
*/
status = "disabled";
};
+
+ crypto@15820000 {
+ compatible = "nvidia,tegra234-se-aes";
+ reg = <0x00 0x15820000 0x00 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>;
+ dma-coherent;
+ };
+
+ crypto@15840000 {
+ compatible = "nvidia,tegra234-se-hash";
+ reg = <0x00 0x15840000 0x00 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>;
+ dma-coherent;
+ };
};
pcie@140a0000 {
--
2.43.2
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* Re: [PATCH 07/34] Input: stmpe-ts - mark OF related data as maybe unused
From: Andy Shevchenko @ 2024-04-03 10:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, linux-kernel, Dmitry Torokhov, Maxime Coquelin,
Alexandre Torgue, Arnd Bergmann, Uwe Kleine-König,
linux-input, linux-stm32, linux-arm-kernel
In-Reply-To: <614fc80a-5d2a-43a1-b8d4-48bdb2cc7dc7@linaro.org>
On Wed, Apr 03, 2024 at 11:52:12AM +0200, Krzysztof Kozlowski wrote:
> On 03/04/2024 11:40, Andy Shevchenko wrote:
> > On Wed, Apr 03, 2024 at 10:06:25AM +0200, Arnd Bergmann wrote:
...
> >> -static const struct of_device_id stmpe_ts_ids[] = {
> >> +static const struct of_device_id stmpe_ts_ids[] __maybe_unused = {
> >
> > __maybe_unused?
> >
> > Why not adding it into .driver as you have done in another patch in this series?
>
> Because there is no benefit in this. This is instantiated by MFD, so the
> only thing you need is entry for module loading.
Hmm... Seems to me rather a good candidate for MODULE_ALIAS in this case. No?
--
With Best Regards,
Andy Shevchenko
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* [PATCH v6 0/1] Add StarFive JH8100 dwmac support
From: Tan Chun Hau @ 2024-04-03 10:05 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Simon Horman, Bartosz Golaszewski,
Andrew Halaney, Jisheng Zhang, Uwe Kleine-König,
Russell King
Cc: Ley Foon Tan, Jee Heng Sia, netdev, devicetree, linux-kernel,
linux-stm32, linux-arm-kernel, linux-riscv
Add StarFive JH8100 dwmac support.
The JH8100 dwmac shares the same driver code as the JH7110 dwmac
and has only one reset signal.
Please refer to below:
JH8100: reset-names = "stmmaceth";
JH7110: reset-names = "stmmaceth", "ahb";
JH7100: reset-names = "ahb";
Example usage of JH8100 in the device tree:
gmac0: ethernet@16030000 {
compatible = "starfive,jh8100-dwmac",
"starfive,jh7110-dwmac",
"snps,dwmac-5.20";
...
};
Changes in v6:
- Removed unnecessary enum "starfive,jh8100-dwmac".
Tan Chun Hau (1):
dt-bindings: net: starfive,jh7110-dwmac: Add StarFive JH8100 support
.../bindings/net/starfive,jh7110-dwmac.yaml | 28 +++++++++++++++----
1 file changed, 23 insertions(+), 5 deletions(-)
--
2.25.1
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* [PATCH v6 1/1] dt-bindings: net: starfive,jh7110-dwmac: Add StarFive JH8100 support
From: Tan Chun Hau @ 2024-04-03 10:05 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Simon Horman, Bartosz Golaszewski,
Andrew Halaney, Jisheng Zhang, Uwe Kleine-König,
Russell King
Cc: Ley Foon Tan, Jee Heng Sia, netdev, devicetree, linux-kernel,
linux-stm32, linux-arm-kernel, linux-riscv
In-Reply-To: <20240403100549.78719-1-chunhau.tan@starfivetech.com>
Add StarFive JH8100 dwmac support.
The JH8100 dwmac shares the same driver code as the JH7110 dwmac
and has only one reset signal.
Please refer to below:
JH8100: reset-names = "stmmaceth";
JH7110: reset-names = "stmmaceth", "ahb";
JH7100: reset-names = "ahb";
Example usage of JH8100 in the device tree:
gmac0: ethernet@16030000 {
compatible = "starfive,jh8100-dwmac",
"starfive,jh7110-dwmac",
"snps,dwmac-5.20";
...
};
Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
---
.../bindings/net/starfive,jh7110-dwmac.yaml | 28 +++++++++++++++----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
index 0d1962980f57..313a15331661 100644
--- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
@@ -30,6 +30,10 @@ properties:
- items:
- const: starfive,jh7110-dwmac
- const: snps,dwmac-5.20
+ - items:
+ - const: starfive,jh8100-dwmac
+ - const: starfive,jh7110-dwmac
+ - const: snps,dwmac-5.20
reg:
maxItems: 1
@@ -116,11 +120,25 @@ allOf:
minItems: 3
maxItems: 3
- resets:
- minItems: 2
-
- reset-names:
- minItems: 2
+ if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh8100-dwmac
+ then:
+ properties:
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: stmmaceth
+ else:
+ properties:
+ resets:
+ minItems: 2
+
+ reset-names:
+ minItems: 2
unevaluatedProperties: false
--
2.25.1
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^ permalink raw reply related
* Re: [RESPIN PATCH] irqchip/gic-v3-its:Fix GICv4.1 needless VSYNC after unmap VPE
From: Marc Zyngier @ 2024-04-03 10:09 UTC (permalink / raw)
To: t00849498; +Cc: tglx, linux-arm-kernel, linux-kernel, guoyang2, wangwudi
In-Reply-To: <20240403083556.3862236-1-tangnianyao@huawei.com>
Thanks for respinning this.
A few remarks:
The subject line could be improved. Something like:
"irqchip/gic-v4: Don't issue a VSYNC after VMAPP with V=0"
On Wed, 03 Apr 2024 09:35:56 +0100,
t00849498 <tangnianyao@huawei.com> wrote:
>
> From: Nianyao Tang <tangnianyao@huawei.com>
>
> Quote from GIC spec 5.3.19, a VMAPP with {V, Alloc}=={0, x}
> is self-synchronizing, This means the ITS command queue does not
> show the command as consumed until all of its effects are completed.
Since this is a direct quote, make it clear that it is so.
>
> We don't need VSYNC to guarantee unmap finish. And VSYNC after unmap VPE
> will reach an invalid vpe table entry, which may trigger exception
> like SError or RAS. Let's fix it.
This should be much stronger. It's not that we don't need VSYNC. It is
that VSYNC is actively wrong. I suggest that you rewrite the commit
message along these lines:
<msg>
As per the GICv4.1 spec (Arm IHI 0069H, 5.3.19):
"A VMAPP with {V, Alloc}=={0, x} is self-synchronizing. This means the
ITS command queue does not show the command as consumed until all of
its effects are completed."
Furthermore, VSYNC is allowed to deliver an SError when referencing a
non existent VPE.
By these definitions, a VMAPP followed by a VSYNC is a bug, as the
later references a VPE that has been unmapped by the former.
Fix it by eliding the VSYNC in this scenario.
</msg>
>
> Signed-off-by: Nianyao Tang <tangnianyao@huawei.com>
Please also add:
Fixes: 64edfaa9a234 ("irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP")
With the above fixed:
Reviewed-by: Marc Zyngier <maz@kernel.org>
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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^ permalink raw reply
* RE: About upstreaming ArmChina NPU driver
From: Dejia Shang @ 2024-04-03 10:09 UTC (permalink / raw)
To: Oded Gabbay
Cc: ogabbay@kernel.org, airlied@redhat.com, daniel@ffwll.ch,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org, Toby Huang, Chengkun Sun
In-Reply-To: <CAFCwf12ou8zNgr-_Ru8xT+Q1RWyxywwqJmx9w1spo_MdaEPr1Q@mail.gmail.com>
> -----Original Message-----
> From: Oded Gabbay <oded.gabbay@gmail.com>
> Sent: 2024年4月3日 14:26
> To: Dejia Shang <Dejia.Shang@armchina.com>
> Cc: ogabbay@kernel.org; airlied@redhat.com; daniel@ffwll.ch;
> linux-kernel@vger.kernel.org; dri-devel@lists.freedesktop.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: About upstreaming ArmChina NPU driver
>
> On Thu, Mar 28, 2024 at 10:01 AM Dejia Shang <Dejia.Shang@armchina.com>
> wrote:
> >
> > Dear Kernel Maintainers,
> >
> > I am a driver developer and would like to upstream the ArmChina Zhouyi
> NPU driver ("Zhouyi" is the brand) to accel subsystem.
> >
> > The driver is already open sourced (both UMD and KMD) and anyone can
> find the code from https://github.com/Arm-China/Compass_NPU_Driver.git.
> >
> > This driver is responsible for scheduling AI inference tasks to the NPU cores
> (V1/V2/V3). Specifically, a simplified end-to-end flow is:
> >
> > 1. A TFLite/ONNX model is transformed to an executable binary
> file in ELF format by the NN graph compiler (designed by ArmChina)
> > 2. An application loads the executable binary file to UMD and
> provides the input data.
> > 3. UMD parses the binary and sends ioctls to KMD (open device,
> do memory allocation/mmap/free, submit the job descriptor).
> > 4. KMD dispatches the job to NPU h/w, handles interrupts and
> updates the execution status.
> > 5. UMD polls the status of the pre-scheduled job.
> > 6. The application gets the output results.
> >
> > So...for the upstreaming,
> >
> > Q1: do you think our NPU driver is suitable for accel? If the answer is yes,
> which tree & branch should the patches be based on?
> Hi Dejia,
> Yes, it definitely sounds as a good fit to the accel subsystem.
> Please base your patches on "drm-misc-next" branch in drm-misc repo:
> https://anongit.freedesktop.org/git/drm/drm-misc.git
>
Hi Oded,
Got it.
> >
> > Q2: in thread
> https://lore.kernel.org/lkml/ec547d33-214f-4952-aa33-c271e9edad63@kern
> el.org/ showing a similar case, Oded mentioned that:
> >
> > "If we would have upstreamed a new driver, the expectation
> would have been that we would use some drm mechanisms.", and
> > "the minimal requirement is to use GEM/BOs for memory
> management operations".
> >
> > I guess those requirements are also applicable for the Zhouyi NPU KMD?
> Currently, the memory management (MM) in KMD is based on dma-mapping
> APIs, which handles both reserved CMA region(s) and SMMU mapped buffers,
> and supports the dma-buf framework. Maybe I should replace the
> implementations with DRM APIs.
> Yes, those requirements definitely apply here.
> >
> > Q3: if you have looked at the KMD code, do you think I should make any
> other major change before submitting the first patch series? Thank you!
> I took a quick glance. In general, it seems to be ok, but I noticed two things
> related to the integration with drm/accel:
>
> 1. You us a scheduler for the job submission, which provides the ability to
> defer jobs. In that case, I suggest to check if you can use drm_sched instead of
> your own implementation. No point in re-inventing the wheel.
> 2. You provide several memory zones for allocation of memory. I would
> suggest here to look at using ttm as the memory manager instead of
> re-implementing your own.
Thanks for your time! I will try to refactor the code as suggested and then send the first patch series.
>
> And please remove the IMPORTANT NOTICE at the end of your emails. I
> would have to refrain from answering to further emails if that notice remains.
Now fixed. I did not realize that because the server auto appended the notice. Sorry for the inconvenience.
Best Regards,
Dejia
>
> Thanks,
> Oded
>
> >
> > Thanks for your time and look forward to your reply~ 😊
> >
> > Best Regards,
> > Dejia
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^ permalink raw reply
* Re: [PATCH 07/34] Input: stmpe-ts - mark OF related data as maybe unused
From: Krzysztof Kozlowski @ 2024-04-03 10:10 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Arnd Bergmann, linux-kernel, Dmitry Torokhov, Maxime Coquelin,
Alexandre Torgue, Arnd Bergmann, Uwe Kleine-König,
linux-input, linux-stm32, linux-arm-kernel
In-Reply-To: <Zg0pei7ut5lC9yVC@smile.fi.intel.com>
On 03/04/2024 12:03, Andy Shevchenko wrote:
> On Wed, Apr 03, 2024 at 11:52:12AM +0200, Krzysztof Kozlowski wrote:
>> On 03/04/2024 11:40, Andy Shevchenko wrote:
>>> On Wed, Apr 03, 2024 at 10:06:25AM +0200, Arnd Bergmann wrote:
>
> ...
>
>>>> -static const struct of_device_id stmpe_ts_ids[] = {
>>>> +static const struct of_device_id stmpe_ts_ids[] __maybe_unused = {
>>>
>>> __maybe_unused?
>>>
>>> Why not adding it into .driver as you have done in another patch in this series?
>>
>> Because there is no benefit in this. This is instantiated by MFD, so the
>> only thing you need is entry for module loading.
>
> Hmm... Seems to me rather a good candidate for MODULE_ALIAS in this case. No?
No, I do not think module alias is for that purpose. This is a valid
compatible, documented and provided by DT so it is expected to be in
of_device_id.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2] arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default
From: Michael Walle @ 2024-04-03 10:15 UTC (permalink / raw)
To: Francesco Dolcini, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Michael Walle
Device tree best practice is to disable any external interface in the
dtsi and just enable them if needed in the device tree. Thus, disable
the ethernet switch and its ports by default and just enable the ones
used by the EVMs in their device trees.
There is no functional change.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
v2:
- move the status propert into k3-am62p5-main.dtsi, thus also update
the k3-am62p5-sk.dts
- put "status" last
---
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 3 +++
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 5 +----
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 7337a9e13535..88bc64111234 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -673,6 +673,7 @@ cpsw3g: ethernet@8000000 {
assigned-clock-parents = <&k3_clks 13 11>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
dmas = <&main_pktdma 0xc600 15>,
<&main_pktdma 0xc601 15>,
@@ -696,6 +697,7 @@ cpsw_port1: port@1 {
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
+ status = "disabled";
};
cpsw_port2: port@2 {
@@ -704,6 +706,7 @@ cpsw_port2: port@2 {
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index 6694087b3665..6a9c99c5fb2a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -431,16 +431,19 @@ &cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>,
<&main_rgmii2_pins_default>;
+ status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
+ status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
+ status = "okay";
};
&cpsw3g_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index 6b148da2bcdc..8a38e5ae7d4f 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -226,10 +226,7 @@ cpsw3g_phy0: ethernet-phy@0 {
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- status = "disabled";
+ status = "okay";
};
&main_gpio1 {
--
2.39.2
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* Re: [PATCH v4 2/5] tee: optee: Move pool_op helper functions
From: Balint Dobszay @ 2024-04-03 10:18 UTC (permalink / raw)
To: Jens Wiklander
Cc: op-tee, linux-doc, linux-kernel, linux-arm-kernel, sumit.garg,
corbet, sudeep.holla, rdunlap, krzk, gyorgy.szing
In-Reply-To: <CAHUa44HHikgA2R_nZw9+f6ug1nKBZgwVEYvqPgKo6dx=iijAqA@mail.gmail.com>
Hi Jens,
On 3 Apr 2024, at 11:43, Jens Wiklander wrote:
> Hi Balint,
>
> On Mon, Mar 25, 2024 at 4:11 PM Balint Dobszay <balint.dobszay@arm.com> wrote:
>>
>> Move the pool alloc and free helper functions from the OP-TEE driver to
>> the TEE subsystem, since these could be reused in other TEE drivers.
>> This patch is not supposed to change behavior, it's only reorganizing
>> the code.
>>
>> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
>> Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
>> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
>> ---
>> drivers/tee/optee/core.c | 64 -------------------------------
>> drivers/tee/optee/ffa_abi.c | 6 +--
>> drivers/tee/optee/optee_private.h | 12 ------
>> drivers/tee/optee/smc_abi.c | 9 ++---
>> drivers/tee/tee_shm.c | 64 +++++++++++++++++++++++++++++++
>> include/linux/tee_core.h | 10 +++++
>> 6 files changed, 81 insertions(+), 84 deletions(-)
>
> This patch fails to build on x86_64:
> CC [M] drivers/tee/tee_shm.o
> drivers/tee/tee_shm.c: In function ‘tee_dyn_shm_alloc_helper’:
> linux/drivers/tee/tee_shm.c:226:22: error: implicit declaration of
> function ‘virt_to_phys’; did you mean ‘virt_to_page’?
> [-Werror=implicit-function-declaration]
> 226 | shm->paddr = virt_to_phys(shm->kaddr);
> | ^~~~~~~~~~~~
> | virt_to_page
>
> It's fixed by adding
> #include <linux/io.h>
>
> I'll fix up the patch if you agree with the fix.
Thanks for catching this. I agree with the fix, please apply it.
Regards,
Balint
>>
>> diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
>> index f762e3a25119..39e688d4e974 100644
>> --- a/drivers/tee/optee/core.c
>> +++ b/drivers/tee/optee/core.c
>> @@ -9,7 +9,6 @@
>> #include <linux/crash_dump.h>
>> #include <linux/errno.h>
>> #include <linux/io.h>
>> -#include <linux/mm.h>
>> #include <linux/module.h>
>> #include <linux/slab.h>
>> #include <linux/string.h>
>> @@ -17,69 +16,6 @@
>> #include <linux/types.h>
>> #include "optee_private.h"
>>
>> -int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm,
>> - size_t size, size_t align,
>> - int (*shm_register)(struct tee_context *ctx,
>> - struct tee_shm *shm,
>> - struct page **pages,
>> - size_t num_pages,
>> - unsigned long start))
>> -{
>> - size_t nr_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE;
>> - struct page **pages;
>> - unsigned int i;
>> - int rc = 0;
>> -
>> - /*
>> - * Ignore alignment since this is already going to be page aligned
>> - * and there's no need for any larger alignment.
>> - */
>> - shm->kaddr = alloc_pages_exact(nr_pages * PAGE_SIZE,
>> - GFP_KERNEL | __GFP_ZERO);
>> - if (!shm->kaddr)
>> - return -ENOMEM;
>> -
>> - shm->paddr = virt_to_phys(shm->kaddr);
>> - shm->size = nr_pages * PAGE_SIZE;
>> -
>> - pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL);
>> - if (!pages) {
>> - rc = -ENOMEM;
>> - goto err;
>> - }
>> -
>> - for (i = 0; i < nr_pages; i++)
>> - pages[i] = virt_to_page((u8 *)shm->kaddr + i * PAGE_SIZE);
>> -
>> - shm->pages = pages;
>> - shm->num_pages = nr_pages;
>> -
>> - if (shm_register) {
>> - rc = shm_register(shm->ctx, shm, pages, nr_pages,
>> - (unsigned long)shm->kaddr);
>> - if (rc)
>> - goto err;
>> - }
>> -
>> - return 0;
>> -err:
>> - free_pages_exact(shm->kaddr, shm->size);
>> - shm->kaddr = NULL;
>> - return rc;
>> -}
>> -
>> -void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm,
>> - int (*shm_unregister)(struct tee_context *ctx,
>> - struct tee_shm *shm))
>> -{
>> - if (shm_unregister)
>> - shm_unregister(shm->ctx, shm);
>> - free_pages_exact(shm->kaddr, shm->size);
>> - shm->kaddr = NULL;
>> - kfree(shm->pages);
>> - shm->pages = NULL;
>> -}
>> -
>> static void optee_bus_scan(struct work_struct *work)
>> {
>> WARN_ON(optee_enumerate_devices(PTA_CMD_GET_DEVICES_SUPP));
>> diff --git a/drivers/tee/optee/ffa_abi.c b/drivers/tee/optee/ffa_abi.c
>> index cee8ccb84cb8..3235e1c719e8 100644
>> --- a/drivers/tee/optee/ffa_abi.c
>> +++ b/drivers/tee/optee/ffa_abi.c
>> @@ -374,14 +374,14 @@ static int optee_ffa_shm_unregister_supp(struct tee_context *ctx,
>> static int pool_ffa_op_alloc(struct tee_shm_pool *pool,
>> struct tee_shm *shm, size_t size, size_t align)
>> {
>> - return optee_pool_op_alloc_helper(pool, shm, size, align,
>> - optee_ffa_shm_register);
>> + return tee_dyn_shm_alloc_helper(shm, size, align,
>> + optee_ffa_shm_register);
>> }
>>
>> static void pool_ffa_op_free(struct tee_shm_pool *pool,
>> struct tee_shm *shm)
>> {
>> - optee_pool_op_free_helper(pool, shm, optee_ffa_shm_unregister);
>> + tee_dyn_shm_free_helper(shm, optee_ffa_shm_unregister);
>> }
>>
>> static void pool_ffa_op_destroy_pool(struct tee_shm_pool *pool)
>> diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h
>> index a0698ac18993..429cc20be5cc 100644
>> --- a/drivers/tee/optee/optee_private.h
>> +++ b/drivers/tee/optee/optee_private.h
>> @@ -283,18 +283,6 @@ int optee_cancel_req(struct tee_context *ctx, u32 cancel_id, u32 session);
>> int optee_enumerate_devices(u32 func);
>> void optee_unregister_devices(void);
>>
>> -int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm,
>> - size_t size, size_t align,
>> - int (*shm_register)(struct tee_context *ctx,
>> - struct tee_shm *shm,
>> - struct page **pages,
>> - size_t num_pages,
>> - unsigned long start));
>> -void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm,
>> - int (*shm_unregister)(struct tee_context *ctx,
>> - struct tee_shm *shm));
>> -
>> -
>> void optee_remove_common(struct optee *optee);
>> int optee_open(struct tee_context *ctx, bool cap_memref_null);
>> void optee_release(struct tee_context *ctx);
>> diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c
>> index 9c296b887dc1..734c484ed0f6 100644
>> --- a/drivers/tee/optee/smc_abi.c
>> +++ b/drivers/tee/optee/smc_abi.c
>> @@ -592,19 +592,18 @@ static int pool_op_alloc(struct tee_shm_pool *pool,
>> * to be registered with OP-TEE.
>> */
>> if (shm->flags & TEE_SHM_PRIV)
>> - return optee_pool_op_alloc_helper(pool, shm, size, align, NULL);
>> + return tee_dyn_shm_alloc_helper(shm, size, align, NULL);
>>
>> - return optee_pool_op_alloc_helper(pool, shm, size, align,
>> - optee_shm_register);
>> + return tee_dyn_shm_alloc_helper(shm, size, align, optee_shm_register);
>> }
>>
>> static void pool_op_free(struct tee_shm_pool *pool,
>> struct tee_shm *shm)
>> {
>> if (!(shm->flags & TEE_SHM_PRIV))
>> - optee_pool_op_free_helper(pool, shm, optee_shm_unregister);
>> + tee_dyn_shm_free_helper(shm, optee_shm_unregister);
>> else
>> - optee_pool_op_free_helper(pool, shm, NULL);
>> + tee_dyn_shm_free_helper(shm, NULL);
>> }
>>
>> static void pool_op_destroy_pool(struct tee_shm_pool *pool)
>> diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c
>> index 96a45c817427..5bf76c35cd9e 100644
>> --- a/drivers/tee/tee_shm.c
>> +++ b/drivers/tee/tee_shm.c
>> @@ -202,6 +202,70 @@ struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size)
>> }
>> EXPORT_SYMBOL_GPL(tee_shm_alloc_priv_buf);
>>
>> +int tee_dyn_shm_alloc_helper(struct tee_shm *shm, size_t size, size_t align,
>> + int (*shm_register)(struct tee_context *ctx,
>> + struct tee_shm *shm,
>> + struct page **pages,
>> + size_t num_pages,
>> + unsigned long start))
>> +{
>> + size_t nr_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE;
>> + struct page **pages;
>> + unsigned int i;
>> + int rc = 0;
>> +
>> + /*
>> + * Ignore alignment since this is already going to be page aligned
>> + * and there's no need for any larger alignment.
>> + */
>> + shm->kaddr = alloc_pages_exact(nr_pages * PAGE_SIZE,
>> + GFP_KERNEL | __GFP_ZERO);
>> + if (!shm->kaddr)
>> + return -ENOMEM;
>> +
>> + shm->paddr = virt_to_phys(shm->kaddr);
>> + shm->size = nr_pages * PAGE_SIZE;
>> +
>> + pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL);
>> + if (!pages) {
>> + rc = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + for (i = 0; i < nr_pages; i++)
>> + pages[i] = virt_to_page((u8 *)shm->kaddr + i * PAGE_SIZE);
>> +
>> + shm->pages = pages;
>> + shm->num_pages = nr_pages;
>> +
>> + if (shm_register) {
>> + rc = shm_register(shm->ctx, shm, pages, nr_pages,
>> + (unsigned long)shm->kaddr);
>> + if (rc)
>> + goto err;
>> + }
>> +
>> + return 0;
>> +err:
>> + free_pages_exact(shm->kaddr, shm->size);
>> + shm->kaddr = NULL;
>> + return rc;
>> +}
>> +EXPORT_SYMBOL_GPL(tee_dyn_shm_alloc_helper);
>> +
>> +void tee_dyn_shm_free_helper(struct tee_shm *shm,
>> + int (*shm_unregister)(struct tee_context *ctx,
>> + struct tee_shm *shm))
>> +{
>> + if (shm_unregister)
>> + shm_unregister(shm->ctx, shm);
>> + free_pages_exact(shm->kaddr, shm->size);
>> + shm->kaddr = NULL;
>> + kfree(shm->pages);
>> + shm->pages = NULL;
>> +}
>> +EXPORT_SYMBOL_GPL(tee_dyn_shm_free_helper);
>> +
>> static struct tee_shm *
>> register_shm_helper(struct tee_context *ctx, struct iov_iter *iter, u32 flags,
>> int id)
>> diff --git a/include/linux/tee_core.h b/include/linux/tee_core.h
>> index d9b3ba8e8fa9..efd16ed52315 100644
>> --- a/include/linux/tee_core.h
>> +++ b/include/linux/tee_core.h
>> @@ -232,6 +232,16 @@ void *tee_get_drvdata(struct tee_device *teedev);
>> */
>> struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size);
>>
>> +int tee_dyn_shm_alloc_helper(struct tee_shm *shm, size_t size, size_t align,
>> + int (*shm_register)(struct tee_context *ctx,
>> + struct tee_shm *shm,
>> + struct page **pages,
>> + size_t num_pages,
>> + unsigned long start));
>> +void tee_dyn_shm_free_helper(struct tee_shm *shm,
>> + int (*shm_unregister)(struct tee_context *ctx,
>> + struct tee_shm *shm));
>> +
>> /**
>> * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind
>> * @shm: Shared memory handle
>> --
>> 2.34.1
>>
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^ permalink raw reply
* [PATCH v11 7/7] arm64: dts: imx8mm/n remove clock-names property from usb controller node
From: Xu Yang @ 2024-04-03 9:04 UTC (permalink / raw)
To: gregkh, robh+dt, krzysztof.kozlowski+dt, shawnguo, conor+dt
Cc: s.hauer, kernel, festevam, linux-imx, jun.li, linux-usb,
devicetree, linux-arm-kernel, imx, linux-kernel
In-Reply-To: <20240403090438.583326-1-xu.yang_2@nxp.com>
The clock-names property is not needed by usb controller node on imx8mm/n.
This will remove it.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v9:
- new patch
Changes in v10:
- no changes
Changes in v11:
- no changes
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 --
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 -
2 files changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 8a1b42b94dce..696e96b15585 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1253,7 +1253,6 @@ usbotg1: usb@32e40000 {
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
- clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
@@ -1274,7 +1273,6 @@ usbotg2: usb@32e50000 {
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
- clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 932c8b05c75f..f017faf87ecd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1213,7 +1213,6 @@ usbotg1: usb@32e40000 {
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
- clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH v3 0/6] Add Synopsys DesignWare HDMI RX Controller
From: Krzysztof Kozlowski @ 2024-04-03 10:21 UTC (permalink / raw)
To: Shreeya Patel, mchehab, hverkuil, hverkuil-cisco
Cc: heiko, robh, krzysztof.kozlowski+dt, conor+dt, mturquette, sboyd,
p.zabel, shawn.wen, kernel, linux-kernel, linux-media, devicetree,
linux-arm-kernel, linux-rockchip, linux-clk, linux-arm
In-Reply-To: <35e566-660d2080-1-7eb9eb00@16488675>
On 03/04/2024 11:24, Shreeya Patel wrote:
> On Thursday, March 28, 2024 04:20 IST, Shreeya Patel <shreeya.patel@collabora.com> wrote:
>
>> This series implements support for the Synopsys DesignWare
>> HDMI RX Controller, being compliant with standard HDMI 1.4b
>> and HDMI 2.0.
>>
>
> Hi Mauro and Hans,
>
> I haven't received any reviews so far. Hence, this is just a gentle reminder to review this patch series.
Why did you put clk changes here? These go via different subsystem. That
might be one of obstacles for your patchset.
Also, you sent it just a week ago and you already ping. Please relax,
and help out by reviewing other patches on the mailing lists in order to
relieve the burden of maintainers and move your patches higher up the list.
Best regards,
Krzysztof
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* Re: [PATCH v3 4/6] arm64: dts: rockchip: Add device tree support for HDMI RX Controller
From: Krzysztof Kozlowski @ 2024-04-03 10:22 UTC (permalink / raw)
To: Shreeya Patel, heiko, mchehab, robh, krzysztof.kozlowski+dt,
conor+dt, mturquette, sboyd, p.zabel, jose.abreu, nelson.costa,
dmitry.osipenko, sebastian.reichel, shawn.wen, nicolas.dufresne,
hverkuil, hverkuil-cisco
Cc: kernel, linux-kernel, linux-media, devicetree, linux-arm-kernel,
linux-rockchip, linux-clk, linux-arm
In-Reply-To: <20240327225057.672304-5-shreeya.patel@collabora.com>
On 27/03/2024 23:50, Shreeya Patel wrote:
> Add device tree support for Synopsys DesignWare HDMI RX
> Controller.
>
> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
> Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
> ---
> Changes in v3 :-
> - Rename cma node and phandle names
> - Elaborate the comment to explain 160MiB calculation
> - Move &hdmi_receiver_cma to the rock5b dts file
>
> Changes in v2 :-
> - Fix some of the checkpatch errors and warnings
> - Rename resets, vo1-grf and HPD
> - Move hdmirx_cma node to the rk3588.dtsi file
>
> .../boot/dts/rockchip/rk3588-pinctrl.dtsi | 41 ++++++++++++++
> .../boot/dts/rockchip/rk3588-rock-5b.dts | 19 +++++++
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 56 +++++++++++++++++++
Please do not engage multiple subsystems in one patchset, if not
necessary. Especially do not mix DTS into media or USB subsystems. And
do not put DTS in the middle!
This is not a correct way to upstream DTS. DTS is independent of
drivers, so your drivers cannot be based on this.
Please reach to your experienced colleagues to explain you how
submission of patches should look like.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2] arm64: dts: ti: k3-j722s-evm: Enable eMMC support
From: Michael Walle @ 2024-04-03 10:23 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Michael Walle
The J722S EVM has an on-board eMMC. Enable the SDHC interface for it.
There is no pinmuxing required because the interface has dedicated pins.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
v2:
- move status="okay" last
---
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index cee3a8661d5e..6b148da2bcdc 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -369,6 +369,13 @@ partition@3fc0000 {
};
+&sdhci0 {
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ bootph-all;
+ status = "okay";
+};
+
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
--
2.39.2
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* [PATCH v5 10/10] drm/mediatek: Add interface to allocate MediaTek GEM buffer.
From: Shawn Sung @ 2024-04-03 10:26 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek, Hsiao Chien Sung
In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com>
From: CK Hu <ck.hu@mediatek.com>
Add an interface to allocate MediaTek GEM buffers, allow the IOCTLs
to be used by render nodes.
This patch also sets the RENDER driver feature.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 16 ++++++-
drivers/gpu/drm/mediatek/mtk_gem.c | 40 ++++++++++++++++
drivers/gpu/drm/mediatek/mtk_gem.h | 11 +++++
include/uapi/drm/mediatek_drm.h | 64 ++++++++++++++++++++++++++
4 files changed, 130 insertions(+), 1 deletion(-)
create mode 100644 include/uapi/drm/mediatek_drm.h
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b5f605751b0a1..41eed3f89316c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -23,6 +23,7 @@
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
+#include <drm/mediatek_drm.h>
#include "mtk_crtc.h"
#include "mtk_ddp_comp.h"
@@ -570,6 +571,14 @@ static void mtk_drm_kms_deinit(struct drm_device *drm)
component_unbind_all(drm->dev, drm);
}
+static const struct drm_ioctl_desc mtk_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(MTK_GEM_CREATE, mtk_gem_create_ioctl,
+ DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(MTK_GEM_MAP_OFFSET,
+ mtk_gem_map_offset_ioctl,
+ DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
+};
+
DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
/*
@@ -585,12 +594,17 @@ static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,
}
static const struct drm_driver mtk_drm_driver = {
- .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC |
+ DRIVER_RENDER,
.dumb_create = mtk_gem_dumb_create,
.gem_prime_import = mtk_gem_prime_import,
.gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
+
+ .ioctls = mtk_ioctls,
+ .num_ioctls = ARRAY_SIZE(mtk_ioctls),
+
.fops = &mtk_drm_fops,
.name = DRIVER_NAME,
diff --git a/drivers/gpu/drm/mediatek/mtk_gem.c b/drivers/gpu/drm/mediatek/mtk_gem.c
index 5a82d7cf3ed0d..e59e0727717b7 100644
--- a/drivers/gpu/drm/mediatek/mtk_gem.c
+++ b/drivers/gpu/drm/mediatek/mtk_gem.c
@@ -4,9 +4,11 @@
*/
#include <linux/dma-buf.h>
+#include <drm/mediatek_drm.h>
#include <drm/drm.h>
#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
#include <drm/drm_gem.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_prime.h>
@@ -285,3 +287,41 @@ void mtk_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
mtk_gem->kvaddr = NULL;
kfree(mtk_gem->pages);
}
+
+int mtk_gem_map_offset_ioctl(struct drm_device *drm, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_mtk_gem_map_off *args = data;
+
+ return drm_gem_dumb_map_offset(file_priv, drm, args->handle,
+ &args->offset);
+}
+
+int mtk_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct mtk_gem_obj *mtk_gem;
+ struct drm_mtk_gem_create *args = data;
+ int ret;
+
+ mtk_gem = mtk_gem_create(dev, args->size, false);
+ if (IS_ERR(mtk_gem))
+ return PTR_ERR(mtk_gem);
+
+ /*
+ * allocate a id of idr table where the obj is registered
+ * and handle has the id what user can see.
+ */
+ ret = drm_gem_handle_create(file_priv, &mtk_gem->base, &args->handle);
+ if (ret)
+ goto err_handle_create;
+
+ /* drop reference from allocate - handle holds it now. */
+ drm_gem_object_put(&mtk_gem->base);
+
+ return 0;
+
+err_handle_create:
+ mtk_gem_free_object(&mtk_gem->base);
+ return ret;
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_gem.h b/drivers/gpu/drm/mediatek/mtk_gem.h
index 66e5f154f6980..4d7598220ca8f 100644
--- a/drivers/gpu/drm/mediatek/mtk_gem.h
+++ b/drivers/gpu/drm/mediatek/mtk_gem.h
@@ -45,4 +45,15 @@ struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev,
int mtk_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
void mtk_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
+/*
+ * request gem object creation and buffer allocation as the size
+ * that it is calculated with framebuffer information such as width,
+ * height and bpp.
+ */
+int mtk_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+/* get buffer offset to map to user space. */
+int mtk_gem_map_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
#endif
diff --git a/include/uapi/drm/mediatek_drm.h b/include/uapi/drm/mediatek_drm.h
new file mode 100644
index 0000000000000..b0dea00bacbc4
--- /dev/null
+++ b/include/uapi/drm/mediatek_drm.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _UAPI_MEDIATEK_DRM_H
+#define _UAPI_MEDIATEK_DRM_H
+
+#include <drm/drm.h>
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+/**
+ * User-desired buffer creation information structure.
+ *
+ * @size: user-desired memory allocation size.
+ * - this size value would be page-aligned internally.
+ * @flags: user request for setting memory type or cache attributes.
+ * @handle: returned a handle to created gem object.
+ * - this handle will be set by gem module of kernel side.
+ */
+struct drm_mtk_gem_create {
+ uint64_t size;
+ uint32_t flags;
+ uint32_t handle;
+};
+
+/**
+ * A structure for getting buffer offset.
+ *
+ * @handle: a pointer to gem object created.
+ * @pad: just padding to be 64-bit aligned.
+ * @offset: relatived offset value of the memory region allocated.
+ * - this value should be set by user.
+ */
+struct drm_mtk_gem_map_off {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+};
+
+#define DRM_MTK_GEM_CREATE 0x00
+#define DRM_MTK_GEM_MAP_OFFSET 0x01
+
+#define DRM_IOCTL_MTK_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_MTK_GEM_CREATE, struct drm_mtk_gem_create)
+
+#define DRM_IOCTL_MTK_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_MTK_GEM_MAP_OFFSET, struct drm_mtk_gem_map_off)
+
+#endif /* _UAPI_MEDIATEK_DRM_H */
--
2.18.0
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* [PATCH v5 04/10] soc: mediatek: cmdq: Add cmdq_pkt_write_s_reg_value to support write value to reg
From: Shawn Sung @ 2024-04-03 10:25 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com>
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add cmdq_pkt_write_s_reg_value to support write a value to a register.
It appends write_s command to the command buffer in a CMDQ packet,
ask GCE to excute a write instruction to write a value to a register
with low 16 bits physical address offset.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 72350138591c3..42a0194198d5b 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -292,6 +292,19 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
}
EXPORT_SYMBOL(cmdq_pkt_write_s_value);
+int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value)
+{
+ struct cmdq_instruction inst = {};
+
+ inst.op = CMDQ_CODE_WRITE_S;
+ inst.dst_t = CMDQ_REG_TYPE;
+ inst.reg_dst = high_addr_reg_idx;
+ inst.value = value;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_s_reg_value);
+
int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
u16 addr_low, u32 value, u32 mask)
{
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 1edb391ec604a..7bd77d40a5720 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -207,6 +207,17 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
u16 addr_low, u32 value, u32 mask);
+/**
+ * cmdq_pkt_write_s_reg_value() - append write_s command to the CMDQ packet which
+ * write value to a register with low address pa
+ * @pkt: the CMDQ packet
+ * @high_addr_reg_idx: internal register ID which contains high address of pa
+ * @value: the specified target value
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value);
+
/**
* cmdq_pkt_mem_move() - append memory move command to the CMDQ packet
* @pkt: the CMDQ packet
--
2.18.0
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* [PATCH v5 06/10] soc: mediatek: cmdq: Add cmdq_pkt_finalize_loop for looping cmd with irq
From: Shawn Sung @ 2024-04-03 10:25 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com>
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add cmdq_pkt_finalize_loop to CMDQ driver.
cmdq_pkt_finalize_loop appends end of command(EOC) instruction and
jump to start of command buffer instruction to make the command
buffer loopable.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 23 +++++++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 8 ++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 42a0194198d5b..3e5a9c4592fd0 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -568,6 +568,29 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
}
EXPORT_SYMBOL(cmdq_pkt_finalize);
+int cmdq_pkt_finalize_loop(struct cmdq_pkt *pkt)
+{
+ struct cmdq_instruction inst = { {0} };
+ int err;
+
+ /* insert EOC and generate IRQ for each command iteration */
+ inst.op = CMDQ_CODE_EOC;
+ inst.value = CMDQ_EOC_IRQ_EN;
+ err = cmdq_pkt_append_command(pkt, inst);
+ if (err < 0)
+ return err;
+
+ /* JUMP to start of pkt */
+ err = cmdq_pkt_jump(pkt, pkt->pa_base);
+ if (err < 0)
+ return err;
+
+ pkt->loop = true;
+
+ return err;
+}
+EXPORT_SYMBOL(cmdq_pkt_finalize_loop);
+
int cmdq_pkt_flush_async(struct cmdq_pkt *pkt)
{
int err;
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 7bd77d40a5720..f986117d930c0 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -371,6 +371,14 @@ int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
*/
int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
+/**
+ * cmdq_pkt_finalize_loop() - Append EOC and jump to start command.
+ * @pkt: the CMDQ packet
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_finalize_loop(struct cmdq_pkt *pkt);
+
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
* packet and call back at the end of done packet
--
2.18.0
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^ permalink raw reply related
* [PATCH v5 05/10] mailbox: mtk-cmdq: Support GCE loop packets in interrupt handler
From: Shawn Sung @ 2024-04-03 10:25 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com>
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
1. Add a loop flag for CMDQ packet struct.
CMDQ helper will use a loop flag to mark CMDQ packet as lopping command
and make current command buffer jumps to the beginning when GCE executes
to the end of command buffer.
2. Add a looping task handle flow in irq handler.
GCE irq occurs when GCE executes to the end of command(EOC) instruction.
If the CMDQ packet is a loopping command, GCE irq handler can not
delete the CMDQ task and disable the GCE thread.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 11 +++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index ead2200f39ba0..5906e0343d1fc 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -267,6 +267,17 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift;
+ task = list_first_entry_or_null(&thread->task_busy_list,
+ struct cmdq_task, list_entry);
+ if (task && task->pkt->loop) {
+ struct cmdq_cb_data data;
+
+ data.sta = err;
+ data.pkt = task->pkt;
+ mbox_chan_received_data(task->thread->chan, &data);
+ return;
+ }
+
list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
list_entry) {
task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index a8f0070c7aa98..f78a08e7c6ede 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -76,6 +76,7 @@ struct cmdq_pkt {
size_t cmd_buf_size; /* command occupied size */
size_t buf_size; /* real buffer size */
void *cl;
+ bool loop;
};
u8 cmdq_get_shift_pa(struct mbox_chan *chan);
--
2.18.0
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^ permalink raw reply related
* [PATCH v5 07/10] mailbox: mediatek: Move reuseable definition to header for secure driver
From: Shawn Sung @ 2024-04-03 10:25 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com>
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
To support CMDQ secure driver, move some reuseable definition to header.
- define: e.g. CMDQ_GCE_NUM_MAX, CMDQ_THR_BASE, CMDQ_THR_SIZE.
- struct: e.g. cmdq_thread, cmdq, cmdq_task.
- include: e.g. <linux/clk.h>.
Add "#include <linux/mailbox_controller.h>" for the function that takes
"struct mbox_chan * chan" as a parameter. That may occur a build error
if secure driver header includes the mtk-cmdq-mailbox.h.
- function: e.g. cmdq_get_shift_pa(struct mbox_chan *chan).
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 30 ---------------------
include/linux/mailbox/mtk-cmdq-mailbox.h | 34 ++++++++++++++++++++++++
2 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 5906e0343d1fc..e04302ca6ec03 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -3,7 +3,6 @@
// Copyright (c) 2018 MediaTek Inc.
#include <linux/bitops.h>
-#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
@@ -22,13 +21,10 @@
#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
-#define CMDQ_GCE_NUM_MAX (2)
#define CMDQ_CURR_IRQ_STATUS 0x10
#define CMDQ_SYNC_TOKEN_UPDATE 0x68
#define CMDQ_THR_SLOT_CYCLES 0x30
-#define CMDQ_THR_BASE 0x100
-#define CMDQ_THR_SIZE 0x80
#define CMDQ_THR_WARM_RESET 0x00
#define CMDQ_THR_ENABLE_TASK 0x04
#define CMDQ_THR_SUSPEND_TASK 0x08
@@ -59,32 +55,6 @@
#define CMDQ_JUMP_BY_OFFSET 0x10000000
#define CMDQ_JUMP_BY_PA 0x10000001
-struct cmdq_thread {
- struct mbox_chan *chan;
- void __iomem *base;
- struct list_head task_busy_list;
- u32 priority;
-};
-
-struct cmdq_task {
- struct cmdq *cmdq;
- struct list_head list_entry;
- dma_addr_t pa_base;
- struct cmdq_thread *thread;
- struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
-};
-
-struct cmdq {
- struct mbox_controller mbox;
- void __iomem *base;
- int irq;
- u32 irq_mask;
- const struct gce_plat *pdata;
- struct cmdq_thread *thread;
- struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX];
- bool suspended;
-};
-
struct gce_plat {
u32 thread_nr;
u8 shift;
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index f78a08e7c6ede..092dcadea0d8a 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -7,10 +7,17 @@
#ifndef __MTK_CMDQ_MAILBOX_H__
#define __MTK_CMDQ_MAILBOX_H__
+#include <linux/clk.h>
+#include <linux/mailbox_controller.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
+#define CMDQ_GCE_NUM_MAX 2
+
+#define CMDQ_THR_BASE 0x100
+#define CMDQ_THR_SIZE 0x80
+
#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
#define CMDQ_SUBSYS_SHIFT 16
#define CMDQ_OP_CODE_SHIFT 24
@@ -79,6 +86,33 @@ struct cmdq_pkt {
bool loop;
};
+struct cmdq_thread {
+ struct mbox_chan *chan;
+ void __iomem *base;
+ struct list_head task_busy_list;
+ u32 priority;
+ u32 idx;
+};
+
+struct cmdq {
+ struct mbox_controller mbox;
+ void __iomem *base;
+ int irq;
+ u32 irq_mask;
+ const struct gce_plat *pdata;
+ struct cmdq_thread *thread;
+ struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX];
+ bool suspended;
+};
+
+struct cmdq_task {
+ struct cmdq *cmdq;
+ struct list_head list_entry;
+ dma_addr_t pa_base;
+ struct cmdq_thread *thread;
+ struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
+};
+
u8 cmdq_get_shift_pa(struct mbox_chan *chan);
#endif /* __MTK_CMDQ_MAILBOX_H__ */
--
2.18.0
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* [PATCH v5 00/10] Add CMDQ secure driver for SVP
From: Shawn Sung @ 2024-04-03 10:25 UTC (permalink / raw)
To: CK Hu, Jassi Brar, AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Hsiao Chien Sung, Jason-JH . Lin, Houlong Wei, linux-kernel,
devicetree, linux-arm-kernel, linux-mediatek, Hsiao Chien Sung
From: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
For the Secure Video Path (SVP) feature, inculding the memory stored
secure video content, the registers of display HW pipeline and the
HW configure operations are required to execute in the secure world.
So using a CMDQ secure driver to make all display HW registers
configuration secure DRAM access permision settings execute by GCE
secure thread in the secure world.
We are landing this feature on mt8188 and mt8195 currently.
---
Based on 2 series and 1 patch:
[1] Add CMDQ driver support for mt8188
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=810382
[2] Add mediatek,gce-events definition to mediatek,gce-mailbox bindings
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=810938
[3] soc: mediatek: Add register definitions for GCE
- https://patchwork.kernel.org/project/linux-mediatek/patch/20231017064717.21616-2-shawn.sung@mediatek.com/
---
Changes in v5:
1. Sync the local changes
Changes in v4:
1. Rebase on mediatek-drm-next(278640d4d74cd) and fix the conflicts
2. This series is based on 20240307013458.23550-1-jason-jh.lin@mediatek.com
Changes in v3:
1. separate mt8188 driver porting patches to another series
2. separate adding 'mediatek,gce-events' event prop to another series
3. sepatate mailbox helper and controller driver modification to a
single patch for adding looping thread
4. add kerneldoc for secure mailbox related definition
5. add moving reuseable definition patch before adding secure mailbox
driver patch
6. adjust redundant logic in mtk-cmdq-sec-mailbox
Changes in v2:
1. adjust dt-binding SW event define patch before the dt-binding patch using it
2. adjust dt-binding patch for secure cmdq driver
3. remove the redundant patches or merge the patches of modification for the same API
CK Hu (1):
drm/mediatek: Add interface to allocate MediaTek GEM buffer.
Jason-JH.Lin (9):
dt-bindings: gce: mt8195: Add CMDQ_SYNC_TOKEN_SECURE_THR_EOF event id
dt-bindings: mailbox: Add mboxes property for CMDQ secure driver
soc: mediatek: cmdq: Add cmdq_pkt_logic_command to support math
operation
soc: mediatek: cmdq: Add cmdq_pkt_write_s_reg_value to support write
value to reg
mailbox: mtk-cmdq: Support GCE loop packets in interrupt handler
soc: mediatek: cmdq: Add cmdq_pkt_finalize_loop for looping cmd with
irq
mailbox: mediatek: Move reuseable definition to header for secure
driver
mailbox: mediatek: Add CMDQ secure mailbox driver
mailbox: mediatek: Add secure CMDQ driver support for CMDQ driver
.../mailbox/mediatek,gce-mailbox.yaml | 10 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 16 +-
drivers/gpu/drm/mediatek/mtk_gem.c | 40 +
drivers/gpu/drm/mediatek/mtk_gem.h | 11 +
drivers/mailbox/Makefile | 2 +-
drivers/mailbox/mtk-cmdq-mailbox.c | 108 +-
drivers/mailbox/mtk-cmdq-sec-mailbox.c | 1045 +++++++++++++++++
drivers/mailbox/mtk-cmdq-sec-tee.c | 165 +++
drivers/soc/mediatek/mtk-cmdq-helper.c | 75 ++
include/dt-bindings/gce/mt8195-gce.h | 6 +
include/linux/mailbox/mtk-cmdq-mailbox.h | 37 +
.../linux/mailbox/mtk-cmdq-sec-iwc-common.h | 385 ++++++
include/linux/mailbox/mtk-cmdq-sec-mailbox.h | 159 +++
include/linux/mailbox/mtk-cmdq-sec-tee.h | 105 ++
include/linux/soc/mediatek/mtk-cmdq.h | 61 +
include/uapi/drm/mediatek_drm.h | 64 +
16 files changed, 2257 insertions(+), 32 deletions(-)
create mode 100644 drivers/mailbox/mtk-cmdq-sec-mailbox.c
create mode 100644 drivers/mailbox/mtk-cmdq-sec-tee.c
create mode 100644 include/linux/mailbox/mtk-cmdq-sec-iwc-common.h
create mode 100644 include/linux/mailbox/mtk-cmdq-sec-mailbox.h
create mode 100644 include/linux/mailbox/mtk-cmdq-sec-tee.h
create mode 100644 include/uapi/drm/mediatek_drm.h
--
2.18.0
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