* [PATCH v3 1/9] dt-bindings: display/msm: Add SM6150 DSI phy
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-23 16:27 ` Krzysztof Kozlowski
2024-11-22 9:56 ` [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150 Fange Zhang
` (9 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add new compatible for SM6150 with dsi_phy_14nm_36mA_regulators
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
index 52bbe132e6dae57246200757767edcd1c8ec2d77..29bbc2f1c766e69a161cf3c8f97b8dd91dc87961 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -20,6 +20,7 @@ properties:
- qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953
- qcom,sm6125-dsi-phy-14nm
+ - qcom,sm6150-dsi-phy-14nm
reg:
items:
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 1/9] dt-bindings: display/msm: Add SM6150 DSI phy
2024-11-22 9:56 ` [PATCH v3 1/9] dt-bindings: display/msm: Add SM6150 DSI phy Fange Zhang
@ 2024-11-23 16:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 31+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-23 16:27 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:44PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add new compatible for SM6150 with dsi_phy_14nm_36mA_regulators
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
2024-11-22 9:56 ` [PATCH v3 1/9] dt-bindings: display/msm: Add SM6150 DSI phy Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-23 16:28 ` Krzysztof Kozlowski
2024-11-22 9:56 ` [PATCH v3 3/9] dt-bindings: display/msm: Add SM6150 MDSS & DPU Fange Zhang
` (8 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Document general compatibility of the DSI controller on SM6150.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..a7fbb5af4b0583e88ebcad07dd004046c38f95ee 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6125-dsi-ctrl
+ - qcom,sm6150-dsi-ctrl
- qcom,sm6350-dsi-ctrl
- qcom,sm6375-dsi-ctrl
- qcom,sm7150-dsi-ctrl
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150
2024-11-22 9:56 ` [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150 Fange Zhang
@ 2024-11-23 16:28 ` Krzysztof Kozlowski
2024-11-25 3:13 ` fange zhang
0 siblings, 1 reply; 31+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-23 16:28 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:45PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Document general compatibility of the DSI controller on SM6150.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..a7fbb5af4b0583e88ebcad07dd004046c38f95ee 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> @@ -30,6 +30,7 @@ properties:
> - qcom,sdm845-dsi-ctrl
> - qcom,sm6115-dsi-ctrl
> - qcom,sm6125-dsi-ctrl
> + - qcom,sm6150-dsi-ctrl
This is incomplete change. Where is the rest for clocks? See entire
file.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150
2024-11-23 16:28 ` Krzysztof Kozlowski
@ 2024-11-25 3:13 ` fange zhang
0 siblings, 0 replies; 31+ messages in thread
From: fange zhang @ 2024-11-25 3:13 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel
On 2024/11/24 0:28, Krzysztof Kozlowski wrote:
> On Fri, Nov 22, 2024 at 05:56:45PM +0800, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Document general compatibility of the DSI controller on SM6150.
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..a7fbb5af4b0583e88ebcad07dd004046c38f95ee 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> @@ -30,6 +30,7 @@ properties:
>> - qcom,sdm845-dsi-ctrl
>> - qcom,sm6115-dsi-ctrl
>> - qcom,sm6125-dsi-ctrl
>> + - qcom,sm6150-dsi-ctrl
>
> This is incomplete change. Where is the rest for clocks? See entire
> file.
Got it. will add the clock part in the next patch as shown below
- qcom,sc7280-dsi-ctrl
+ - qcom,sm6150-dsi-ctrl
- qcom,sm7150-dsi-ctrl
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 3/9] dt-bindings: display/msm: Add SM6150 MDSS & DPU
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
2024-11-22 9:56 ` [PATCH v3 1/9] dt-bindings: display/msm: Add SM6150 DSI phy Fange Zhang
2024-11-22 9:56 ` [PATCH v3 2/9] dt-bindings: display/msm: dsi-controller-main: Document SM6150 Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-23 16:15 ` Krzysztof Kozlowski
2024-11-22 9:56 ` [PATCH v3 4/9] drm/msm: mdss: Add SM6150 support Fange Zhang
` (7 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Document the MDSS and DPU hardware found on the Qualcomm SM6150 platform.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
.../bindings/display/msm/qcom,sm6150-dpu.yaml | 113 ++++++++++
.../bindings/display/msm/qcom,sm6150-mdss.yaml | 250 +++++++++++++++++++++
2 files changed, 363 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b9783ebb047ed19858928bb035e61a550feecea9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display DPU
+
+maintainers:
+ - Abhinav Kumar <quic_abhinavk@quicinc.com>
+ - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm6150-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display ahb clock
+ - description: Display hf axi clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6150-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdss_mdp_clk>,
+ <&dispcc_mdss_vsync_clk>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f750567fe1918d815e4af4ca214f817ca3f1c1fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
@@ -0,0 +1,250 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display MDSS
+
+maintainers:
+ - Abhinav Kumar <quic_abhinavk@quicinc.com>
+ - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS are mentioned for SM6150 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6150-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,sm6150-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6150-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,sm6150-dsi-phy-14nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,sm6150-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem", "cpu-cfg";
+
+ power-domains = <&dispcc_mdss_gdsc>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdss_mdp_clk>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x0>;
+
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6150-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdss_mdp_clk>,
+ <&dispcc_mdss_vsync_clk>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6150-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc_mdss_byte0_clk>,
+ <&dispcc_mdss_byte0_intf_clk>,
+ <&dispcc_mdss_pclk0_clk>,
+ <&dispcc_mdss_esc0_clk>,
+ <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
+ <&dispcc_mdss_pclk0_clk_src>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm6150-dsi-phy-14nm";
+ reg = <0x0ae94400 0x100>,
+ <0x0ae94500 0x300>,
+ <0x0ae94800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 3/9] dt-bindings: display/msm: Add SM6150 MDSS & DPU
2024-11-22 9:56 ` [PATCH v3 3/9] dt-bindings: display/msm: Add SM6150 MDSS & DPU Fange Zhang
@ 2024-11-23 16:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 31+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-23 16:15 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:46PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Document the MDSS and DPU hardware found on the Qualcomm SM6150 platform.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
This has a build failure, but nothing here explains dependency.
This cannot be merged and due to build failure cannot be tested by
automation.
Sorry, no review from me, please wait till dependencies come in or
decouple series. Anyway otherwise this *CANNOT* be applied by
maintainers...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 4/9] drm/msm: mdss: Add SM6150 support
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (2 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 3/9] dt-bindings: display/msm: Add SM6150 MDSS & DPU Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:03 ` Dmitry Baryshkov
2024-11-22 9:56 ` [PATCH v3 5/9] drm/msm/dpu: " Fange Zhang
` (6 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add support for MDSS on SM6150.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index b7bd899ead44bf86998e7295bccb31a334fa6811..b9661312bbdab2473f0a7b54b09fb5480cc2589c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -667,6 +667,13 @@ static const struct msm_mdss_data sm6125_data = {
.highest_bank_bit = 1,
};
+static const struct msm_mdss_data sm6150_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 1,
+ .reg_bus_bw = 76800,
+};
+
static const struct msm_mdss_data sm8250_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
@@ -724,6 +731,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
+ { .compatible = "qcom,sm6150-mdss", .data = &sm6150_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 4/9] drm/msm: mdss: Add SM6150 support
2024-11-22 9:56 ` [PATCH v3 4/9] drm/msm: mdss: Add SM6150 support Fange Zhang
@ 2024-11-22 10:03 ` Dmitry Baryshkov
0 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:03 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:47PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add support for MDSS on SM6150.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (3 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 4/9] drm/msm: mdss: Add SM6150 support Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:07 ` Dmitry Baryshkov
2024-12-06 20:17 ` Abhinav Kumar
2024-11-22 9:56 ` [PATCH v3 6/9] drm/msm/dsi: Add dsi phy support for SM6150 Fange Zhang
` (5 subsequent siblings)
10 siblings, 2 replies; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add definitions for the display hardware used on the Qualcomm SM6150
platform.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 266 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
new file mode 100644
index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_5_3_SM6150_H
+#define _DPU_5_3_SM6150_H
+
+static const struct dpu_caps sm6150_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x9,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg sm6150_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x45c,
+ .features = 0,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6150_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6150_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &dpu_vig_sblk_qseed3_2_4,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
+};
+
+static const struct dpu_lm_cfg sm6150_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ .lm_pair = LM_1,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_1,
+ .lm_pair = LM_0,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_2,
+ },
+};
+
+static const struct dpu_dspp_cfg sm6150_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg sm6150_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ },
+};
+
+static const struct dpu_intf_cfg sm6150_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_NONE,
+ .controller_id = 0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ },
+};
+
+static const struct dpu_perf_cfg sm6150_perf_data = {
+ .max_bw_low = 4800000,
+ .max_bw_high = 4800000,
+ .min_core_ib = 2400000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
+ .entries = sm8150_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sm6150_mdss_ver = {
+ .core_major_ver = 5,
+ .core_minor_ver = 3,
+};
+
+const struct dpu_mdss_cfg dpu_sm6150_cfg = {
+ .mdss_ver = &sm6150_mdss_ver,
+ .caps = &sm6150_dpu_caps,
+ .mdp = &sm6150_mdp,
+ .ctl_count = ARRAY_SIZE(sm6150_ctl),
+ .ctl = sm6150_ctl,
+ .sspp_count = ARRAY_SIZE(sm6150_sspp),
+ .sspp = sm6150_sspp,
+ .mixer_count = ARRAY_SIZE(sm6150_lm),
+ .mixer = sm6150_lm,
+ .dspp_count = ARRAY_SIZE(sm6150_dspp),
+ .dspp = sm6150_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6150_pp),
+ .pingpong = sm6150_pp,
+ .intf_count = ARRAY_SIZE(sm6150_intf),
+ .intf = sm6150_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6150_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2cbf41f33cc034fd3e649d1168ed65937e811d11..0b342c043875f3329a9f71c5e751b2244f9f5ef7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -765,6 +765,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_5_0_sm8150.h"
#include "catalog/dpu_5_1_sc8180x.h"
#include "catalog/dpu_5_2_sm7150.h"
+#include "catalog/dpu_5_3_sm6150.h"
#include "catalog/dpu_5_4_sm6125.h"
#include "catalog/dpu_6_0_sm8250.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c701d18c3522393b7d18d085d6554119f27f737b..3ab79092a7f254b47b99fb4868064796cadf56fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -839,6 +839,7 @@ extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6150_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ca4847b2b73876c59dedff1e3ec4188ea70860a7..597ae11b0b109c008d2e84ff8838e7282d4fa8d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1478,6 +1478,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
+ { .compatible = "qcom,sm6150-dpu", .data = &dpu_sm6150_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support
2024-11-22 9:56 ` [PATCH v3 5/9] drm/msm/dpu: " Fange Zhang
@ 2024-11-22 10:07 ` Dmitry Baryshkov
2024-11-25 1:44 ` fange zhang
2024-12-06 20:17 ` Abhinav Kumar
1 sibling, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:07 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:48PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add definitions for the display hardware used on the Qualcomm SM6150
> platform.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 266 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -0,0 +1,263 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DPU_5_3_SM6150_H
> +#define _DPU_5_3_SM6150_H
> +
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_NONE,
> + .controller_id = 0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
Please drop. No need to declare missing blocks.
Other than that:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + },
> +};
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support
2024-11-22 10:07 ` Dmitry Baryshkov
@ 2024-11-25 1:44 ` fange zhang
0 siblings, 0 replies; 31+ messages in thread
From: fange zhang @ 2024-11-25 1:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On 2024/11/22 18:07, Dmitry Baryshkov wrote:
> On Fri, Nov 22, 2024 at 05:56:48PM +0800, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add definitions for the display hardware used on the Qualcomm SM6150
>> platform.
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 266 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> @@ -0,0 +1,263 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _DPU_5_3_SM6150_H
>> +#define _DPU_5_3_SM6150_H
>> +
>> + }, {
>> + .name = "intf_2", .id = INTF_2,
>> + .base = 0x6b000, .len = 0x2c0,
>> + .features = INTF_SC7180_MASK,
>> + .type = INTF_NONE,
>> + .controller_id = 0,
>> + .prog_fetch_lines_worst_case = 24,
>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
>
> Please drop. No need to declare missing blocks.
got it, will remove this block in the next patch
>
> Other than that:
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
>
>> + }, {
>> + .name = "intf_3", .id = INTF_3,
>> + .base = 0x6b800, .len = 0x280,
>> + .features = INTF_SC7180_MASK,
>> + .type = INTF_DP,
>> + .controller_id = MSM_DP_CONTROLLER_1,
>> + .prog_fetch_lines_worst_case = 24,
>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
>> + },
>> +};
>> +
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support
2024-11-22 9:56 ` [PATCH v3 5/9] drm/msm/dpu: " Fange Zhang
2024-11-22 10:07 ` Dmitry Baryshkov
@ 2024-12-06 20:17 ` Abhinav Kumar
2024-12-09 1:44 ` fange zhang
1 sibling, 1 reply; 31+ messages in thread
From: Abhinav Kumar @ 2024-12-06 20:17 UTC (permalink / raw)
To: Fange Zhang, Rob Clark, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
On 11/22/2024 1:56 AM, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add definitions for the display hardware used on the Qualcomm SM6150
> platform.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 266 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -0,0 +1,263 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DPU_5_3_SM6150_H
> +#define _DPU_5_3_SM6150_H
> +
> +
<snip>
> +static const struct dpu_sspp_cfg sm6150_sspp[] = {
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
This is not correct. Smartdma is supported on this chipset on both Vig
and DMA SSPPs.
Please use VIG_SDM845_MASK_SDMA and DMA_SDM845_MASK_SDMA respectively.
> + .sblk = &dpu_vig_sblk_qseed3_2_4,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &dpu_dma_sblk,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &dpu_dma_sblk,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &dpu_dma_sblk,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &dpu_dma_sblk,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> +};
> +
<snip>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support
2024-12-06 20:17 ` Abhinav Kumar
@ 2024-12-09 1:44 ` fange zhang
0 siblings, 0 replies; 31+ messages in thread
From: fange zhang @ 2024-12-09 1:44 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
On 2024/12/7 4:17, Abhinav Kumar wrote:
>
>
> On 11/22/2024 1:56 AM, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add definitions for the display hardware used on the Qualcomm SM6150
>> platform.
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++
>> ++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 266 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/
>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> @@ -0,0 +1,263 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +#ifndef _DPU_5_3_SM6150_H
>> +#define _DPU_5_3_SM6150_H
>> +
>> +
>
> <snip>
>
>> +static const struct dpu_sspp_cfg sm6150_sspp[] = {
>> + {
>> + .name = "sspp_0", .id = SSPP_VIG0,
>> + .base = 0x4000, .len = 0x1f0,
>> + .features = VIG_SDM845_MASK,
>
> This is not correct. Smartdma is supported on this chipset on both Vig
> and DMA SSPPs.
>
> Please use VIG_SDM845_MASK_SDMA and DMA_SDM845_MASK_SDMA respectively.
Got it, will replace them in next patch
>
>
>> + .sblk = &dpu_vig_sblk_qseed3_2_4,
>> + .xin_id = 0,
>> + .type = SSPP_TYPE_VIG,
>> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
>> + }, {
>> + .name = "sspp_8", .id = SSPP_DMA0,
>> + .base = 0x24000, .len = 0x1f0,
>> + .features = DMA_SDM845_MASK,
>> + .sblk = &dpu_dma_sblk,
>> + .xin_id = 1,
>> + .type = SSPP_TYPE_DMA,
>> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
>> + }, {
>> + .name = "sspp_9", .id = SSPP_DMA1,
>> + .base = 0x26000, .len = 0x1f0,
>> + .features = DMA_SDM845_MASK,
>> + .sblk = &dpu_dma_sblk,
>> + .xin_id = 5,
>> + .type = SSPP_TYPE_DMA,
>> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
>> + }, {
>> + .name = "sspp_10", .id = SSPP_DMA2,
>> + .base = 0x28000, .len = 0x1f0,
>> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
>> + .sblk = &dpu_dma_sblk,
>> + .xin_id = 9,
>> + .type = SSPP_TYPE_DMA,
>> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
>> + }, {
>> + .name = "sspp_11", .id = SSPP_DMA3,
>> + .base = 0x2a000, .len = 0x1f0,
>> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
>> + .sblk = &dpu_dma_sblk,
>> + .xin_id = 13,
>> + .type = SSPP_TYPE_DMA,
>> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
>> + },
>> +};
>> +
>
> <snip>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 6/9] drm/msm/dsi: Add dsi phy support for SM6150
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (4 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 5/9] drm/msm/dpu: " Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:08 ` Dmitry Baryshkov
2024-11-22 9:56 ` [PATCH v3 7/9] drm/msm/dsi: Add " Fange Zhang
` (4 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add phy configuration for SM6150
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index dd58bc0a49eb5ca96370f7832d9251609ac0c552..c0bcc68289633fd7506ce4f1f963655d862e8f08 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_14nm_8953_cfgs },
{ .compatible = "qcom,sm6125-dsi-phy-14nm",
.data = &dsi_phy_14nm_2290_cfgs },
+ { .compatible = "qcom,sm6150-dsi-phy-14nm",
+ .data = &dsi_phy_14nm_6150_cfgs },
#endif
#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
{ .compatible = "qcom,dsi-phy-10nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 4953459edd636363614ecad85654614fc95cfa1d..8985818bb2e0934e9084a420c90e2269c2e1c414 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -46,6 +46,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..2c3cbe0f2870e7d68b9563957de8621f7cd36b78 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
{ .supply = "vcca", .init_load_uA = 73400 },
};
+static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = {
+ { .supply = "vdda", .init_load_uA = 36000 },
+};
+
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_14nm_17mA_regulators,
@@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
.io_start = { 0x5e94400 },
.num_dsi_phy = 1,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_14nm_36mA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators),
+ .ops = {
+ .enable = dsi_14nm_phy_enable,
+ .disable = dsi_14nm_phy_disable,
+ .pll_init = dsi_pll_14nm_init,
+ .save_pll_state = dsi_14nm_pll_save_state,
+ .restore_pll_state = dsi_14nm_pll_restore_state,
+ },
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
+ .io_start = { 0xae94400 },
+ .num_dsi_phy = 1,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 6/9] drm/msm/dsi: Add dsi phy support for SM6150
2024-11-22 9:56 ` [PATCH v3 6/9] drm/msm/dsi: Add dsi phy support for SM6150 Fange Zhang
@ 2024-11-22 10:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:08 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:49PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add phy configuration for SM6150
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++
> 3 files changed, 24 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 7/9] drm/msm/dsi: Add support for SM6150
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (5 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 6/9] drm/msm/dsi: Add dsi phy support for SM6150 Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:10 ` Dmitry Baryshkov
2024-11-22 9:56 ` [PATCH v3 8/9] arm64: dts: qcom: Add display support for QCS615 Fange Zhang
` (3 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add support for DSI 2.3.1 (block used on SM6150).
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +++-
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 10ba7d153d1cfc9015f527c911c4658558f6e29e..fe02724bddf69c2e8d6816589f4ea410fa666e5b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -171,7 +171,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
.io_start = {
{ 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
- { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
+ { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6150 / SM6375 */
},
};
@@ -286,6 +286,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
+ &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -23,6 +23,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000
#define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
#define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000
+#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001
#define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
#define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 7/9] drm/msm/dsi: Add support for SM6150
2024-11-22 9:56 ` [PATCH v3 7/9] drm/msm/dsi: Add " Fange Zhang
@ 2024-11-22 10:10 ` Dmitry Baryshkov
2024-11-25 2:31 ` fange zhang
0 siblings, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:10 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:50PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add support for DSI 2.3.1 (block used on SM6150).
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +++-
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..fe02724bddf69c2e8d6816589f4ea410fa666e5b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -171,7 +171,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
> .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> .io_start = {
> { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
> - { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
> + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6150 / SM6375 */
Not true
> },
> };
>
> @@ -286,6 +286,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
> + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -23,6 +23,7 @@
> #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000
> #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
> #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000
> +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001
> #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
> #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
> #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 7/9] drm/msm/dsi: Add support for SM6150
2024-11-22 10:10 ` Dmitry Baryshkov
@ 2024-11-25 2:31 ` fange zhang
2024-11-25 22:11 ` Dmitry Baryshkov
0 siblings, 1 reply; 31+ messages in thread
From: fange zhang @ 2024-11-25 2:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On 2024/11/22 18:10, Dmitry Baryshkov wrote:
> On Fri, Nov 22, 2024 at 05:56:50PM +0800, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add support for DSI 2.3.1 (block used on SM6150).
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +++-
>> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
>> 2 files changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..fe02724bddf69c2e8d6816589f4ea410fa666e5b 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> @@ -171,7 +171,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
>> .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
>> .io_start = {
>> { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
>> - { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
>> + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6150 / SM6375 */
>
> Not true
Should I remove it or add it behind the SDM670?
>
>> },
>> };
>>
>> @@ -286,6 +286,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
>> + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> @@ -23,6 +23,7 @@
>> #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000
>> #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
>> #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000
>> +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001
>> #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
>> #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
>> #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
>>
>> --
>> 2.34.1
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 7/9] drm/msm/dsi: Add support for SM6150
2024-11-25 2:31 ` fange zhang
@ 2024-11-25 22:11 ` Dmitry Baryshkov
2024-11-26 1:41 ` fange zhang
0 siblings, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-25 22:11 UTC (permalink / raw)
To: fange zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Mon, 25 Nov 2024 at 04:31, fange zhang <quic_fangez@quicinc.com> wrote:
>
>
>
> On 2024/11/22 18:10, Dmitry Baryshkov wrote:
> > On Fri, Nov 22, 2024 at 05:56:50PM +0800, Fange Zhang wrote:
> >> From: Li Liu <quic_lliu6@quicinc.com>
> >>
> >> Add support for DSI 2.3.1 (block used on SM6150).
> >>
> >> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> >> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> >> ---
> >> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +++-
> >> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> >> 2 files changed, 4 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..fe02724bddf69c2e8d6816589f4ea410fa666e5b 100644
> >> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> @@ -171,7 +171,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
> >> .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> >> .io_start = {
> >> { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
> >> - { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
> >> + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6150 / SM6375 */
> >
> > Not true
> Should I remove it or add it behind the SDM670?
You should not be sending patches which provide false information. Why
did you add it to the wrong line in the first place?
> >
> >> },
> >> };
> >>
> >> @@ -286,6 +286,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
> >> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
> >> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
> >> + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
> >> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
> >> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> @@ -23,6 +23,7 @@
> >> #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000
> >> #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
> >> #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000
> >> +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001
> >> #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
> >> #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
> >> #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
> >>
> >> --
> >> 2.34.1
> >>
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 7/9] drm/msm/dsi: Add support for SM6150
2024-11-25 22:11 ` Dmitry Baryshkov
@ 2024-11-26 1:41 ` fange zhang
0 siblings, 0 replies; 31+ messages in thread
From: fange zhang @ 2024-11-26 1:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On 2024/11/26 6:11, Dmitry Baryshkov wrote:
> On Mon, 25 Nov 2024 at 04:31, fange zhang <quic_fangez@quicinc.com> wrote:
>>
>>
>>
>> On 2024/11/22 18:10, Dmitry Baryshkov wrote:
>>> On Fri, Nov 22, 2024 at 05:56:50PM +0800, Fange Zhang wrote:
>>>> From: Li Liu <quic_lliu6@quicinc.com>
>>>>
>>>> Add support for DSI 2.3.1 (block used on SM6150).
>>>>
>>>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>>>> ---
>>>> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +++-
>>>> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
>>>> 2 files changed, 4 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>>> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..fe02724bddf69c2e8d6816589f4ea410fa666e5b 100644
>>>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>>> @@ -171,7 +171,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
>>>> .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
>>>> .io_start = {
>>>> { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
>>>> - { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
>>>> + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6150 / SM6375 */
>>>
>>> Not true
>> Should I remove it or add it behind the SDM670?
>
> You should not be sending patches which provide false information. Why
> did you add it to the wrong line in the first place?
sorry i missed it, will remove it in next patch
>
>>>
>>>> },
>>>> };
>>>>
>>>> @@ -286,6 +286,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>>>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
>>>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>>> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
>>>> + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
>>>> &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>>> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
>>>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>>>> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
>>>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>>>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>>>> @@ -23,6 +23,7 @@
>>>> #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000
>>>> #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
>>>> #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000
>>>> +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001
>>>> #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
>>>> #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
>>>> #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 8/9] arm64: dts: qcom: Add display support for QCS615
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (6 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 7/9] drm/msm/dsi: Add " Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:27 ` Dmitry Baryshkov
2024-11-22 9:56 ` [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board Fange Zhang
` (2 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add display MDSS and DSI configuration for QCS615 platform.
QCS615 has a DP port, and DP support will be added in a later patch.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 186 ++++++++++++++++++++++++++++++++++-
1 file changed, 185 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 57de1188ca2a34079578816c0c10825431d032bb..a9fb26dd27a0eb1f863707caca007f539422fc42 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -1184,12 +1185,195 @@ camcc: clock-controller@ad00000 {
#power-domain-cells = <1>;
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,sm6150-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm6150-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x0ae94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm6150-dsi-phy-14nm";
+ reg = <0x0 0x0ae94400 0x0 0x100>,
+ <0x0 0x0ae94500 0x0 0x300>,
+ <0x0 0x0ae94800 0x0 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0 0xaf00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <0>,
+ <0>,
+ <0>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 8/9] arm64: dts: qcom: Add display support for QCS615
2024-11-22 9:56 ` [PATCH v3 8/9] arm64: dts: qcom: Add display support for QCS615 Fange Zhang
@ 2024-11-22 10:27 ` Dmitry Baryshkov
0 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:27 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:51PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add display MDSS and DSI configuration for QCS615 platform.
> QCS615 has a DP port, and DP support will be added in a later patch.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 186 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 185 insertions(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (7 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 8/9] arm64: dts: qcom: Add display support for QCS615 Fange Zhang
@ 2024-11-22 9:56 ` Fange Zhang
2024-11-22 10:22 ` Dmitry Baryshkov
2024-11-23 16:14 ` [PATCH v3 0/9] Add display support for QCS615 platform Krzysztof Kozlowski
2024-11-23 16:25 ` Dmitry Baryshkov
10 siblings, 1 reply; 31+ messages in thread
From: Fange Zhang @ 2024-11-22 9:56 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Fange Zhang, Xiangxu Yin
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel
From: Li Liu <quic_lliu6@quicinc.com>
Add display MDSS and DSI configuration for QCS615 RIDE board.
QCS615 has a DP port, and DP support will be added in a later patch.
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6d71f29934a8debba3a832882abdd..cc7dadc411ab79b9e60ccb15eaff84ea5f997c4c 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -202,6 +202,82 @@ &gcc {
<&sleep_clk>;
};
+&i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ ioexp: gpio@3e {
+ compatible = "semtech,sx1509q";
+ reg = <0x3e>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <58 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ semtech,probe-reset;
+ };
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9542";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ anx7625@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ interrupt-parent = <&ioexp>;
+ interrupts = <0 0>;
+ enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ anx_7625_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ anx_7625_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l11a>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&anx_7625_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l5a>;
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board
2024-11-22 9:56 ` [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board Fange Zhang
@ 2024-11-22 10:22 ` Dmitry Baryshkov
2024-11-25 7:38 ` fange zhang
0 siblings, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-22 10:22 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add display MDSS and DSI configuration for QCS615 RIDE board.
> QCS615 has a DP port, and DP support will be added in a later patch.
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> index ee6cab3924a6d71f29934a8debba3a832882abdd..cc7dadc411ab79b9e60ccb15eaff84ea5f997c4c 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -202,6 +202,82 @@ &gcc {
> <&sleep_clk>;
> };
>
> +&i2c2 {
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + ioexp: gpio@3e {
> + compatible = "semtech,sx1509q";
> + reg = <0x3e>;
> + interrupt-parent = <&tlmm>;
> + interrupts = <58 0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + semtech,probe-reset;
> + };
> +
> + i2c-mux@77 {
> + compatible = "nxp,pca9542";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + anx7625@58 {
> + compatible = "analogix,anx7625";
> + reg = <0x58>;
> + interrupt-parent = <&ioexp>;
> + interrupts = <0 0>;
> + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
> + wakeup-source;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + anx_7625_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + anx_7625_out: endpoint {
> + };
Where is it connected? Is it DP port? USB-C? eDP?
> + };
> + };
> + };
> + };
> + };
> +};
> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vreg_l11a>;
> + status = "okay";
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&anx_7625_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vreg_l5a>;
> + status = "okay";
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board
2024-11-22 10:22 ` Dmitry Baryshkov
@ 2024-11-25 7:38 ` fange zhang
2024-11-25 22:08 ` Dmitry Baryshkov
0 siblings, 1 reply; 31+ messages in thread
From: fange zhang @ 2024-11-25 7:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On 2024/11/22 18:22, Dmitry Baryshkov wrote:
> On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add display MDSS and DSI configuration for QCS615 RIDE board.
>> QCS615 has a DP port, and DP support will be added in a later patch.
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> index ee6cab3924a6d71f29934a8debba3a832882abdd..cc7dadc411ab79b9e60ccb15eaff84ea5f997c4c 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> @@ -202,6 +202,82 @@ &gcc {
>> <&sleep_clk>;
>> };
>>
>> +&i2c2 {
>> + clock-frequency = <400000>;
>> + status = "okay";
>> +
>> + ioexp: gpio@3e {
>> + compatible = "semtech,sx1509q";
>> + reg = <0x3e>;
>> + interrupt-parent = <&tlmm>;
>> + interrupts = <58 0>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + semtech,probe-reset;
>> + };
>> +
>> + i2c-mux@77 {
>> + compatible = "nxp,pca9542";
>> + reg = <0x77>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + i2c@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + anx7625@58 {
>> + compatible = "analogix,anx7625";
>> + reg = <0x58>;
>> + interrupt-parent = <&ioexp>;
>> + interrupts = <0 0>;
>> + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
>> + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
>> + wakeup-source;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + anx_7625_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + anx_7625_out: endpoint {
>> + };
>
> Where is it connected? Is it DP port? USB-C? eDP?
yes, it's DP port
>
>> + };
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vreg_l11a>;
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&anx_7625_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vreg_l5a>;
>> + status = "okay";
>> +};
>> +
>> &qupv3_id_0 {
>> status = "okay";
>> };
>>
>> --
>> 2.34.1
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board
2024-11-25 7:38 ` fange zhang
@ 2024-11-25 22:08 ` Dmitry Baryshkov
2024-11-29 4:55 ` fange zhang
0 siblings, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-25 22:08 UTC (permalink / raw)
To: fange zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Mon, 25 Nov 2024 at 09:39, fange zhang <quic_fangez@quicinc.com> wrote:
>
>
>
> On 2024/11/22 18:22, Dmitry Baryshkov wrote:
> > On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote:
> >> From: Li Liu <quic_lliu6@quicinc.com>
> >>
> >> Add display MDSS and DSI configuration for QCS615 RIDE board.
> >> QCS615 has a DP port, and DP support will be added in a later patch.
> >>
> >> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> >> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++++++++++++++++++++++++++++
> >> 1 file changed, 76 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> index ee6cab3924a6d71f29934a8debba3a832882abdd..cc7dadc411ab79b9e60ccb15eaff84ea5f997c4c 100644
> >> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> @@ -202,6 +202,82 @@ &gcc {
> >> <&sleep_clk>;
> >> };
> >>
> >> +&i2c2 {
> >> + clock-frequency = <400000>;
> >> + status = "okay";
> >> +
> >> + ioexp: gpio@3e {
> >> + compatible = "semtech,sx1509q";
> >> + reg = <0x3e>;
> >> + interrupt-parent = <&tlmm>;
> >> + interrupts = <58 0>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + semtech,probe-reset;
> >> + };
> >> +
> >> + i2c-mux@77 {
> >> + compatible = "nxp,pca9542";
> >> + reg = <0x77>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + i2c@0 {
> >> + reg = <0>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + anx7625@58 {
> >> + compatible = "analogix,anx7625";
> >> + reg = <0x58>;
> >> + interrupt-parent = <&ioexp>;
> >> + interrupts = <0 0>;
> >> + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
> >> + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
> >> + wakeup-source;
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> + anx_7625_in: endpoint {
> >> + remote-endpoint = <&mdss_dsi0_out>;
> >> + };
> >> + };
> >> +
> >> + port@1 {
> >> + reg = <1>;
> >> + anx_7625_out: endpoint {
> >> + };
> >
> > Where is it connected? Is it DP port? USB-C? eDP?
> yes, it's DP port
So, I'd expect to see a dp-connector node at the end, not the
unterminated anx7625.
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> + };
> >> +};
> >> +
> >> +&mdss {
> >> + status = "okay";
> >> +};
> >> +
> >> +&mdss_dsi0 {
> >> + vdda-supply = <&vreg_l11a>;
> >> + status = "okay";
> >> +};
> >> +
> >> +&mdss_dsi0_out {
> >> + remote-endpoint = <&anx_7625_in>;
> >> + data-lanes = <0 1 2 3>;
> >> +};
> >> +
> >> +&mdss_dsi0_phy {
> >> + vdds-supply = <&vreg_l5a>;
> >> + status = "okay";
> >> +};
> >> +
> >> &qupv3_id_0 {
> >> status = "okay";
> >> };
> >>
> >> --
> >> 2.34.1
> >>
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board
2024-11-25 22:08 ` Dmitry Baryshkov
@ 2024-11-29 4:55 ` fange zhang
0 siblings, 0 replies; 31+ messages in thread
From: fange zhang @ 2024-11-29 4:55 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On 2024/11/26 6:08, Dmitry Baryshkov wrote:
> On Mon, 25 Nov 2024 at 09:39, fange zhang <quic_fangez@quicinc.com> wrote:
>>
>>
>>
>> On 2024/11/22 18:22, Dmitry Baryshkov wrote:
>>> On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote:
>>>> From: Li Liu <quic_lliu6@quicinc.com>
>>>>
>>>> Add display MDSS and DSI configuration for QCS615 RIDE board.
>>>> QCS615 has a DP port, and DP support will be added in a later patch.
>>>>
>>>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++++++++++++++++++++++++++++
>>>> 1 file changed, 76 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> index ee6cab3924a6d71f29934a8debba3a832882abdd..cc7dadc411ab79b9e60ccb15eaff84ea5f997c4c 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> @@ -202,6 +202,82 @@ &gcc {
>>>> <&sleep_clk>;
>>>> };
>>>>
>>>> +&i2c2 {
>>>> + clock-frequency = <400000>;
>>>> + status = "okay";
>>>> +
>>>> + ioexp: gpio@3e {
>>>> + compatible = "semtech,sx1509q";
>>>> + reg = <0x3e>;
>>>> + interrupt-parent = <&tlmm>;
>>>> + interrupts = <58 0>;
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <2>;
>>>> + semtech,probe-reset;
>>>> + };
>>>> +
>>>> + i2c-mux@77 {
>>>> + compatible = "nxp,pca9542";
>>>> + reg = <0x77>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + i2c@0 {
>>>> + reg = <0>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + anx7625@58 {
>>>> + compatible = "analogix,anx7625";
>>>> + reg = <0x58>;
>>>> + interrupt-parent = <&ioexp>;
>>>> + interrupts = <0 0>;
>>>> + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
>>>> + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
>>>> + wakeup-source;
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@0 {
>>>> + reg = <0>;
>>>> + anx_7625_in: endpoint {
>>>> + remote-endpoint = <&mdss_dsi0_out>;
>>>> + };
>>>> + };
>>>> +
>>>> + port@1 {
>>>> + reg = <1>;
>>>> + anx_7625_out: endpoint {
+ remote-endpoint = <&dp_connector_out>;
>>>> + };
>>>
>>> Where is it connected? Is it DP port? USB-C? eDP?
>> yes, it's DP port
>
> So, I'd expect to see a dp-connector node at the end, not the
> unterminated anx7625.
got it, will add it in next patch
+ dp-connector {
+ compatible = "dp-connector";
+ label = "DP";
+ type = "mini";
+
+ port {
+ dp_connector_out: endpoint {
+ remote-endpoint = <&anx_7625_out>;
+ };
+ };
+ };
>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&mdss {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mdss_dsi0 {
>>>> + vdda-supply = <&vreg_l11a>;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mdss_dsi0_out {
>>>> + remote-endpoint = <&anx_7625_in>;
>>>> + data-lanes = <0 1 2 3>;
>>>> +};
>>>> +
>>>> +&mdss_dsi0_phy {
>>>> + vdds-supply = <&vreg_l5a>;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> &qupv3_id_0 {
>>>> status = "okay";
>>>> };
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 0/9] Add display support for QCS615 platform
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (8 preceding siblings ...)
2024-11-22 9:56 ` [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board Fange Zhang
@ 2024-11-23 16:14 ` Krzysztof Kozlowski
2024-11-23 16:25 ` Dmitry Baryshkov
10 siblings, 0 replies; 31+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-23 16:14 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Bjorn Andersson, Konrad Dybcio, Catalin Marinas, Will Deacon,
Li Liu, Xiangxu Yin, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:43PM +0800, Fange Zhang wrote:
> This series aims to enable display on the QCS615 platform
>
> 1.Add MDSS & DPU support for QCS615
> 2.Add DSI support for QCS615
>
> QCS615 platform supports DisplayPort, and this feature will be added in a future patch
>
> This patch series depends on below patch series:
> - rpmhcc
> https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-2-3d716ad0d987@quicinc.com/
> - gcc
> https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-4-3d716ad0d987@quicinc.com/
> - base
> https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/
> - Apps SMMU
> https://lore.kernel.org/all/20241105032107.9552-4-quic_qqzhou@quicinc.com/
> - I2C
> https://lore.kernel.org/all/20241111084331.2564643-1-quic_vdadhani@quicinc.com/
> - dispcc
> https://lore.kernel.org/all/20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com/
> - dispcc dts
> https://lore.kernel.org/lkml/20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com/
Which makes it unmergeable and untestable. I suggest decouple
dependencies.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 0/9] Add display support for QCS615 platform
2024-11-22 9:56 [PATCH v3 0/9] Add display support for QCS615 platform Fange Zhang
` (9 preceding siblings ...)
2024-11-23 16:14 ` [PATCH v3 0/9] Add display support for QCS615 platform Krzysztof Kozlowski
@ 2024-11-23 16:25 ` Dmitry Baryshkov
10 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2024-11-23 16:25 UTC (permalink / raw)
To: Fange Zhang
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
Catalin Marinas, Will Deacon, Li Liu, Xiangxu Yin, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel
On Fri, Nov 22, 2024 at 05:56:43PM +0800, Fange Zhang wrote:
> This series aims to enable display on the QCS615 platform
>
> 1.Add MDSS & DPU support for QCS615
> 2.Add DSI support for QCS615
>
> QCS615 platform supports DisplayPort, and this feature will be added in a future patch
>
> This patch series depends on below patch series:
> - rpmhcc
> https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-2-3d716ad0d987@quicinc.com/
> - gcc
> https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-4-3d716ad0d987@quicinc.com/
> - base
> https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/
> - Apps SMMU
> https://lore.kernel.org/all/20241105032107.9552-4-quic_qqzhou@quicinc.com/
> - I2C
> https://lore.kernel.org/all/20241111084331.2564643-1-quic_vdadhani@quicinc.com/
> - dispcc
> https://lore.kernel.org/all/20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com/
> - dispcc dts
> https://lore.kernel.org/lkml/20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com/
>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> ---
> Changes in v3:
> - Add reg_bus_bw for sm6150_data [Dmitry]
> - Remove patch for SX150X defconfig [Dmitry]
> - Remove dsi0_hpd_cfg_pins from ioexp [Dmitry]
> - Remove dsi0_cdet_cfg_pins from ioexpa [Dmitry]
> - Remove tlmm node for ioexp_intr_active and ioAexp_reset_active [Dmitry]
> - Remove qcs615_dsi_regulators and reuse sdm845_dsi_cfg [Dmitry, Konrad]
> - Rename qcs615/QCS615 to sm6150/SM6150 for whole patch [Dmitry]
> - Rename qcom,dsi-phy-14nm-615 to qcom,sm6150-dsi-phy-14nm [Dmitry]
> - Rename qcom,qcs615-dsi-ctrl to qcom,sm6150-dsi-ctrl [Dmitry]
> - Rename qcom,qcs615-dpu to qcom,sm6150-dpu [Dmitry]
> - Rename qcom,qcs615-mdss to qcom,sm6150-mdss [Dmitry]
> - Split drm dsi patch to dsi and dsi phy [Dmitry]
> - Update yaml clocks node with ephemeral nodes and remove unsed include [Dmitry, Rob]
So, it seems it was not a complete truth.
Fange, please make sure that dt-bindings and driver patches can be
applied on top of the msm/msm-next, otherwise I can not pick them.
The tree must build w/o warnigns with W=1 and pass dt_binding_check with
no additional errors / warnings.
> - Link to v2: https://lore.kernel.org/r/20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com
>
> Changes in v2:
> - Add QCS615 DP controller comment in commit message [Dmitry]
> - Add comments for dsi_dp_hpd_cfg_pins and dsi_dp_cdet_cfg_pins [Dmitry]
> - Add missing port@1 for connector for anx7625 [Dmitry]
> - Change 0 to QCOM_ICC_TAG_ALWAYS for mdss interconnects [Dmitry]
> - Change 0 to GPIO_ACTIVE_HIGH for GPIO flags [Dmitry]
> - Move anx_7625 to same node [Dmitry]
> - Move status to last in mdss_dsi0 [Dmitry]
> - Rename dsi0_hpd_cfg_pins to dsi_dp_hpd_cfg_pins in ioexp [Dmitry]
> - Rename dsi0_cdet_cfg_pins to dsi_dp_cdet_cfg_pins in ioexp [Dmitry]
> - Rename anx_7625_1 to dsi_anx_7625 in ioexp [Dmitry]
> - Remove absent block in qcs615_lm [Dmitry]
> - Remove merge_3d value in qcs615_pp [Dmitry]
> - Remove redundant annotation in qcs615_sspp [Dmitry]
> - Remove unsupported dsi clk from dsi0_opp_table [Dmitry]
> - Remove dp_hpd_cfg_pins node from ioexp [Dmitry]
> - Splite drm driver patches to mdss, dpu and dsi [Dmitry]
> - Link to v2: https://lore.kernel.org/r/20241014-add_display_support_for_qcs615-v1-0-4efa191dbdd4@quicinc.com
>
> ---
> Li Liu (9):
> dt-bindings: display/msm: Add SM6150 DSI phy
> dt-bindings: display/msm: dsi-controller-main: Document SM6150
> dt-bindings: display/msm: Add SM6150 MDSS & DPU
> drm/msm: mdss: Add SM6150 support
> drm/msm/dpu: Add SM6150 support
> drm/msm/dsi: Add dsi phy support for SM6150
> drm/msm/dsi: Add support for SM6150
> arm64: dts: qcom: Add display support for QCS615
> arm64: dts: qcom: Add display support for QCS615 RIDE board
>
> .../bindings/display/msm/dsi-controller-main.yaml | 1 +
> .../bindings/display/msm/dsi-phy-14nm.yaml | 1 +
> .../bindings/display/msm/qcom,sm6150-dpu.yaml | 113 +++++++++
> .../bindings/display/msm/qcom,sm6150-mdss.yaml | 250 ++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 76 ++++++
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 186 ++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +-
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 ++
> drivers/gpu/drm/msm/msm_mdss.c | 8 +
> 16 files changed, 928 insertions(+), 2 deletions(-)
> ---
> base-commit: 929beafbe7acce3267c06115e13e03ff6e50548a
> change-id: 20241112-add-display-support-for-qcs615-platform-674ed6c8e150
> prerequisite-message-id: <20241022-qcs615-clock-driver-v4-2-3d716ad0d987@quicinc.com>
> prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91
> prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b
> prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f
> prerequisite-patch-id: 5a8e9ea15a2c3d60b4dbdf11b4e2695742d6333c
> prerequisite-message-id: <20241022-qcs615-clock-driver-v4-4-3d716ad0d987@quicinc.com>
> prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91
> prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b
> prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f
> prerequisite-patch-id: 5a8e9ea15a2c3d60b4dbdf11b4e2695742d6333c
> prerequisite-message-id: <20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com>
> prerequisite-patch-id: 09782474af7eecf1013425fd34f9d2f082fb3616
> prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9
> prerequisite-patch-id: 82481c82a20345548e2cb292d3098ed51843b809
> prerequisite-patch-id: 3bd8edd83297815fcb1b81fcd891d3c14908442f
> prerequisite-patch-id: fc1cfec4ecd56e669c161c4d2c3797fc0abff0ae
> prerequisite-message-id: <20241105032107.9552-4-quic_qqzhou@quicinc.com>
> prerequisite-patch-id: aaa7214fe86fade46ae5c245e0a44625fae1bad3
> prerequisite-patch-id: 4db9f55207af45c6b64fff4f8929648a7fb44669
> prerequisite-patch-id: 89ce719a863bf5e909989877f15f82b51552e449
> prerequisite-message-id: <20241111084331.2564643-1-quic_vdadhani@quicinc.com>
> prerequisite-patch-id: 3f9489c89f3e632abfc5c3ca2e8eca2ce23093b0
> prerequisite-message-id: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com>
> prerequisite-patch-id: 748a4e51bbedae9c6ebdbd642b2fd1badf958788
> prerequisite-patch-id: 72a894a3b19fdbd431e1cec9397365bc5b27abfe
> prerequisite-patch-id: da2b7a74f1afd58833c6a9a4544a0e271720641f
> prerequisite-patch-id: 40b79fe0b9101f5db3bddad23551c1123572aee5
> prerequisite-patch-id: cb93e5798f6bfe8cc3044c4ce973e3ae5f20dc6b
> prerequisite-patch-id: 13b0dbf97ac1865d241791afb4b46a28ca499523
> prerequisite-patch-id: 807019bedabd47c04f7ac78e9461d0b5a6e9131b
> prerequisite-patch-id: 8e2e841401fefbd96d78dd4a7c47514058c83bf2
> prerequisite-patch-id: 125bb8cb367109ba22cededf6e78754579e1ed03
> prerequisite-patch-id: b3cc42570d5826a4704f7702e7b26af9a0fe57b0
> prerequisite-patch-id: df8e2fdd997cbf6c0a107f1871ed9e2caaa97582
> prerequisite-message-id: <20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com>
> prerequisite-patch-id: bcb1328b70868bb9c87c0e4c48e5c9d38853bc60
> prerequisite-patch-id: 8844a4661902eb44406639a3b7344416a0c88ed9
>
> Best regards,
> --
> fangez <quic_fangez@quicinc.com>
>
--
With best wishes
Dmitry
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