Linux clock framework development
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From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>
Cc: <matthias.bgg@gmail.com>, <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
	<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
	<allen-kh.cheng@mediatek.com>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V2 05/12] clk: mediatek: reset: Add reset.h
Date: Wed, 20 Apr 2022 21:05:20 +0800	[thread overview]
Message-ID: <20220420130527.23200-6-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com>

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h | 11 ++---------
 drivers/clk/mediatek/reset.h   | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+), 9 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 399f1b2dc7d0..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -178,12 +180,6 @@ struct mtk_clk_divider {
 		.div_width = _width,				\
 }
 
-enum mtk_reset_version {
-	MTK_RST_SIMPLE = 0,
-	MTK_RST_SET_CLR,
-	MTK_RST_MAX,
-};
-
 int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
 			      void __iomem *base, spinlock_t *lock,
 			      struct clk_onecell_data *clk_data);
@@ -196,9 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_clk_register_rst_ctrl(struct device_node *np,
-			       u32 reg_num, u16 reg_ofs, u8 version);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..e4081c7217e3
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/types.h>
+
+enum mtk_reset_version {
+	MTK_RST_SIMPLE = 0,
+	MTK_RST_SET_CLR,
+	MTK_RST_MAX,
+};
+
+void mtk_clk_register_rst_ctrl(struct device_node *np,
+			       u32 reg_num, u16 reg_ofs, u8 version);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


  parent reply	other threads:[~2022-04-20 13:05 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-20 13:05 [PATCH V2 00/12] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-21  9:08   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Rex-BC Chen
2022-04-21  7:52   ` Chen-Yu Tsai
2022-04-22  3:58     ` Rex-BC Chen
2022-04-21  9:08   ` AngeloGioacchino Del Regno
2022-04-22  4:57     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 03/12] clk: mediatek: reset: Refine functions of set_clr Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:00     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 04/12] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:01     ` Rex-BC Chen
2022-04-20 13:05 ` Rex-BC Chen [this message]
2022-04-21  9:07   ` [PATCH V2 05/12] clk: mediatek: reset: Add reset.h AngeloGioacchino Del Regno
2022-04-21  9:14     ` Chen-Yu Tsai
2022-04-21  9:41       ` Chen-Yu Tsai
2022-04-22  5:02     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 06/12] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:04     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:04     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 08/12] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:05     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-21  5:36   ` Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:06     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 10/12] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-21  6:53   ` Chen-Yu Tsai
2022-04-22  4:00     ` Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno

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