Linux clock framework development
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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>,
	mturquette@baylibre.com, sboyd@kernel.org
Cc: matthias.bgg@gmail.com, p.zabel@pengutronix.de,
	chun-jie.chen@mediatek.com, wenst@chromium.org,
	runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
	allen-kh.cheng@mediatek.com, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT
Date: Thu, 21 Apr 2022 11:07:42 +0200	[thread overview]
Message-ID: <b9839f51-fef1-c54a-3024-674209987f13@collabora.com> (raw)
In-Reply-To: <20220420130527.23200-10-rex-bc.chen@mediatek.com>

Il 20/04/22 15:05, Rex-BC Chen ha scritto:
> To use the clock reset function easier, we implement the of_xlate.
> This function is only adopted in version MTK_SET_CLR because of
> the method of id calculation.
> 
> There is no impact for original use. If the argument number is not
> larger than 1, it will return original id.
> 
> With this implementation if we want to set offset 0x120 and bit 16,
> we can just write something like "resets = <&infra_rst 0x120 16>;".
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>   drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++
>   drivers/clk/mediatek/reset.h |  1 +
>   2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
> index 1173111af3ab..dbe812062bf5 100644
> --- a/drivers/clk/mediatek/reset.c
> +++ b/drivers/clk/mediatek/reset.c
> @@ -59,6 +59,20 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
>   	.reset = mtk_reset_set_clr,
>   };
>   
> +static int reset_xlate(struct reset_controller_dev *rcdev,
> +		       const struct of_phandle_args *reset_spec)
> +{
> +	unsigned int offset, bit;
> +
> +	if (reset_spec->args_count <= 1)
> +		return reset_spec->args[0];
> +
> +	offset = reset_spec->args[0];
> +	bit = reset_spec->args[1];
> +
> +	return (offset >> 4) * 32 + bit;
> +}
> +
>   static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
>   	[MTK_RST_SIMPLE] = &reset_simple_ops,
>   	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
> @@ -98,6 +112,11 @@ int mtk_clk_register_rst_ctrl(struct device_node *np,
>   	data->rcdev.ops = rst_op[desc->version];
>   	data->rcdev.of_node = np;
>   
> +	if (desc->version == MTK_RST_SET_CLR) {

...following my previous advice to use switch(version), this would fit in
just fine :-)

Everything else looks ok.

Cheers,
Angelo

  parent reply	other threads:[~2022-04-21  9:07 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-20 13:05 [PATCH V2 00/12] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-21  9:08   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Rex-BC Chen
2022-04-21  7:52   ` Chen-Yu Tsai
2022-04-22  3:58     ` Rex-BC Chen
2022-04-21  9:08   ` AngeloGioacchino Del Regno
2022-04-22  4:57     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 03/12] clk: mediatek: reset: Refine functions of set_clr Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:00     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 04/12] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:01     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 05/12] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-21  9:14     ` Chen-Yu Tsai
2022-04-21  9:41       ` Chen-Yu Tsai
2022-04-22  5:02     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 06/12] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:04     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:04     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 08/12] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-22  5:05     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-21  5:36   ` Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno [this message]
2022-04-22  5:06     ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 10/12] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-21  6:53   ` Chen-Yu Tsai
2022-04-22  4:00     ` Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-21  9:07   ` AngeloGioacchino Del Regno

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