From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <runyang.chen@mediatek.com>,
<linux-kernel@vger.kernel.org>, <allen-kh.cheng@mediatek.com>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations
Date: Fri, 22 Apr 2022 11:58:36 +0800 [thread overview]
Message-ID: <496c00b0225e8e2ce567225b94e1ce0f3ab8096d.camel@mediatek.com> (raw)
In-Reply-To: <CAGXv+5FJBKYoEuazH9broYSM4uOy=e_3O-86tOOQrsp0xH=4wQ@mail.gmail.com>
Hello Cehn-Yu,
On Thu, 2022-04-21 at 15:52 +0800, Chen-Yu Tsai wrote:
> On Wed, Apr 20, 2022 at 9:05 PM Rex-BC Chen <rex-bc.chen@mediatek.com
> > wrote:
> >
> > There are two version for clock reset register control of MediaTek
> > SoCs.
> > The reset operations before MT8183 can use simple reset to cover.
>
> I would go slightly into more detail, i.e.
>
> The old hardware is one bit per reset control, and does not have
> separate registers for bit set, clear and read-back operations.
> This
> matches the scheme supported by the simple reset driver. ...
>
> > Therefore, we replace mtk_reset_ops with reset_simple_ops.
>
> ... to remove redundant code.
>
> The "why" is more important than "what" in commit logs. "What" you
> did
> is already visible in the diff.
>
Got it, I will modify this in next version.
> > In addition, we also rename mtk_register_reset_controller to
> > mtk_register_reset_controller_simple.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> > drivers/clk/mediatek/Kconfig | 1 +
> > drivers/clk/mediatek/clk-mt2701-eth.c | 2 +-
> > drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
> > drivers/clk/mediatek/clk-mt2701-hif.c | 2 +-
> > drivers/clk/mediatek/clk-mt2701.c | 4 +--
> > drivers/clk/mediatek/clk-mt2712.c | 4 +--
> > drivers/clk/mediatek/clk-mt7622-eth.c | 2 +-
> > drivers/clk/mediatek/clk-mt7622-hif.c | 4 +--
> > drivers/clk/mediatek/clk-mt7622.c | 4 +--
> > drivers/clk/mediatek/clk-mt7629-eth.c | 2 +-
> > drivers/clk/mediatek/clk-mt7629-hif.c | 4 +--
> > drivers/clk/mediatek/clk-mt8135.c | 4 +--
> > drivers/clk/mediatek/clk-mt8173.c | 4 +--
> > drivers/clk/mediatek/clk-mtk.h | 6 ++--
> > drivers/clk/mediatek/reset.c | 43 +++------------------
> > ------
> > 15 files changed, 27 insertions(+), 61 deletions(-)
>
> [...]
>
> > void mtk_register_reset_controller_set_clr(struct device_node *np,
> > unsigned int num_regs, int regofs)
> > {
> > mtk_register_reset_controller_common(np, num_regs, regofs,
> > - &mtk_reset_ops_set_clr);
> > + &mtk_reset_ops_set_clr
> > );
>
> This change is unrelated and should not be included.
>
> ChenYu
>
I add a refinement patch in next version, and I will move this to that
patch.
BRs,
Rex
>
> > }
> >
> > MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> >
next prev parent reply other threads:[~2022-04-22 3:58 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-20 13:05 [PATCH V2 00/12] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-21 9:08 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Rex-BC Chen
2022-04-21 7:52 ` Chen-Yu Tsai
2022-04-22 3:58 ` Rex-BC Chen [this message]
2022-04-21 9:08 ` AngeloGioacchino Del Regno
2022-04-22 4:57 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 03/12] clk: mediatek: reset: Refine functions of set_clr Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:00 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 04/12] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:01 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 05/12] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-21 9:14 ` Chen-Yu Tsai
2022-04-21 9:41 ` Chen-Yu Tsai
2022-04-22 5:02 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 06/12] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:04 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:04 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 08/12] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:05 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-21 5:36 ` Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:06 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 10/12] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-21 6:53 ` Chen-Yu Tsai
2022-04-22 4:00 ` Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
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