From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>
Cc: <matthias.bgg@gmail.com>, <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<allen-kh.cheng@mediatek.com>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function
Date: Wed, 20 Apr 2022 21:05:22 +0800 [thread overview]
Message-ID: <20220420130527.23200-8-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com>
To make error handling, we add return for mtk_clk_register_rst_ctrl().
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/clk/mediatek/reset.c | 14 ++++++++------
drivers/clk/mediatek/reset.h | 4 ++--
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index d67c13958458..b164b1da7dd3 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -64,8 +64,8 @@ static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
};
-void mtk_clk_register_rst_ctrl(struct device_node *np,
- const struct mtk_clk_rst_desc *desc)
+int mtk_clk_register_rst_ctrl(struct device_node *np,
+ const struct mtk_clk_rst_desc *desc)
{
struct regmap *regmap;
struct mtk_clk_rst_data *data;
@@ -73,23 +73,23 @@ void mtk_clk_register_rst_ctrl(struct device_node *np,
if (!desc) {
pr_err("mtk clock reset desc is NULL\n");
- return;
+ return -EINVAL;
}
if (desc->version >= MTK_RST_MAX) {
pr_err("Error version number: %d\n", desc->version);
- return;
+ return -EINVAL;
}
regmap = device_node_to_regmap(np);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
- return;
+ return -EINVAL;
}
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
- return;
+ return -ENOMEM;
data->desc = desc;
data->regmap = regmap;
@@ -103,6 +103,8 @@ void mtk_clk_register_rst_ctrl(struct device_node *np,
pr_err("could not register reset controller: %d\n", ret);
kfree(data);
}
+
+ return ret;
}
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 3a93f61e106e..d59f4b89384d 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -27,7 +27,7 @@ struct mtk_clk_rst_data {
const struct mtk_clk_rst_desc *desc;
};
-void mtk_clk_register_rst_ctrl(struct device_node *np,
- const struct mtk_clk_rst_desc *desc);
+int mtk_clk_register_rst_ctrl(struct device_node *np,
+ const struct mtk_clk_rst_desc *desc);
#endif /* __DRV_CLK_MTK_RESET_H */
--
2.18.0
next prev parent reply other threads:[~2022-04-20 13:05 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-20 13:05 [PATCH V2 00/12] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-21 9:08 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Rex-BC Chen
2022-04-21 7:52 ` Chen-Yu Tsai
2022-04-22 3:58 ` Rex-BC Chen
2022-04-21 9:08 ` AngeloGioacchino Del Regno
2022-04-22 4:57 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 03/12] clk: mediatek: reset: Refine functions of set_clr Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:00 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 04/12] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:01 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 05/12] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-21 9:14 ` Chen-Yu Tsai
2022-04-21 9:41 ` Chen-Yu Tsai
2022-04-22 5:02 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 06/12] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:04 ` Rex-BC Chen
2022-04-20 13:05 ` Rex-BC Chen [this message]
2022-04-21 9:07 ` [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function AngeloGioacchino Del Regno
2022-04-22 5:04 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 08/12] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:05 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-21 5:36 ` Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-22 5:06 ` Rex-BC Chen
2022-04-20 13:05 ` [PATCH V2 10/12] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-21 6:53 ` Chen-Yu Tsai
2022-04-22 4:00 ` Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
2022-04-20 13:05 ` [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-21 9:07 ` AngeloGioacchino Del Regno
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