Re: [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Mon, 08 May 2023 13:47:36 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> The CDAT information from the switch, Switch Scoped Latency and Bandwidth
> Information Strucutre (SSLBIS), is parsed and stored under a cxl_dport
> based on the correlated downstream port id from the SSLBIS entry. Walk
> the entire CXL port paths and collect all the performance data. Also
> pick up the link latency number that's stored under the dports. The
> entire path PCIe bandwidth can be retrieved using the
> pcie_bandwidth_available() call.
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Trivial comment inline. Otherwise LGTM

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/port.c |   69 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h       |    3 ++
>  2 files changed, 72 insertions(+)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index e4f75847b851..1111a3cebc8e 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -9,6 +9,7 @@
>  #include <linux/pci.h>
>  #include <linux/slab.h>
>  #include <linux/idr.h>
> +#include <linux/node.h>
>  #include <cxlmem.h>
>  #include <cxlpci.h>
>  #include <cxl.h>
> @@ -1950,6 +1951,74 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
>  }
>  EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);
>  
> +static void combine_coordinates(struct access_coordinate *c1,
> +				struct access_coordinate *c2)
> +{
> +		if (c2->write_bandwidth)
> +			c1->write_bandwidth = min_t(unsigned int,
> +						    c1->write_bandwidth,
> +						    c2->write_bandwidth);

min() fine here I think. All unsigned int already unless I'm missing something.

> +		c1->write_latency += c2->write_latency;
> +
> +		if (c2->read_bandwidth)
> +			c1->read_bandwidth = min_t(unsigned int,
> +						   c1->read_bandwidth,
> +						   c2->read_bandwidth);
same here.

> +		c1->read_latency += c2->read_latency;
> +}