From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>
Subject: Re: [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class
Date: Fri, 12 May 2023 16:33:14 +0100 [thread overview]
Message-ID: <20230512163314.00002782@Huawei.com> (raw)
In-Reply-To: <168357889098.2756219.3746540473463747491.stgit@djiang5-mobl3>
On Mon, 08 May 2023 13:48:10 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Export qos_class sysfs attributes for the CXL memory device. The QoS clas
> should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile
> partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent
> partition. The QTG ID is retrieved via _DSM after supplying the
> calculated bandwidth and latency for the entire CXL path from device to
> the CPU. This ID is used to match up to the root decoder QoS class to
> determine which CFMWS the memory range of a hotplugged CXL mem device
> should be assigned under.
>
> While there may be multiple DSMAS exported by the device CDAT, the driver
> will only expose the first QTG ID per partition in sysfs for now. In the
> future when multiple QTG IDs are necessary, they can be exposed. [1]
>
> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
Reading this patch made me notice the whole issue of we may be exporting
a useless QTG for the device due to a missmatch of memory type and CFMWS
(as not using the full list provided by the _DSM)
> ---
> v5:
> - Change qtg_id to qos_class
> v4:
> - Change kernel version for documentation to v6.5
> v3:
> - Expand description of qtg_id. (Alison)
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 32 +++++++++++++++++++++++++++++++
> drivers/cxl/core/memdev.c | 26 +++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 2f24e42ef36d..c13ae49dd9aa 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -28,6 +28,22 @@ Description:
> Payload in the CXL-2.0 specification.
>
>
> +What: /sys/bus/cxl/devices/memX/ram/qos_class
> +Date: May, 2023
> +KernelVersion: v6.5
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) For CXL host platforms that support "QoS Telemmetry"
> + this attribute conveys a platform specific cookie that
> + identifies a QoS performance class for the volatile
> + partition of the CXL mem device. This class-id can be
> + compared against a similar "qos_class" published for
> + a root decoder. While it is not required that the endpoints
> + map their local memory-class to a matching platform class,
> + mismatches are not recommended and there are platform specific
> + side-effects that may result.
I think this needs to be the full ordered list from the _DSM with text suggesting
that a compatible CFMWS matching the earliest entry possible should be used.
next prev parent reply other threads:[~2023-05-12 15:34 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41 ` Jonathan Cameron
2023-05-16 17:49 ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59 ` Jonathan Cameron
2023-05-16 20:58 ` Dave Jiang
2023-05-16 21:13 ` Dan Williams
2023-05-16 21:52 ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33 ` Jonathan Cameron [this message]
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36 ` Jonathan Cameron
2023-05-17 22:28 ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49 ` Dan Williams
2023-05-17 8:50 ` Jonathan Cameron
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